1/* $NetBSD: omap5912_intr.c,v 1.4 2010/12/20 00:25:29 matt Exp $ */ 2 3/* 4 * IRQ data specific to the Texas Instruments OMAP5912 processor. 5 */ 6 7/* 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain this list of conditions 12 * and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce this list of conditions 14 * and the following disclaimer in the documentation and/or other materials 15 * provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 19 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANY 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__KERNEL_RCSID(0, "$NetBSD: omap5912_intr.c,v 1.4 2010/12/20 00:25:29 matt Exp $"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/device.h> 35#include <sys/malloc.h> 36#include <sys/device.h> 37 38#include <sys/bus.h> 39#include <machine/intr.h> 40#include <machine/lock.h> 41 42#include <arm/omap/omap_reg.h> 43#include <arm/omap/omap_tipb.h> 44 45/* 46 * INTC autoconf glue 47 */ 48CFATTACH_DECL_NEW(omap5912intc, 0, 49 omapintc_match, omapintc_attach, NULL, NULL); 50 51#define IRQ_TO_BANK_BASE(irq) \ 52 (((irq) < OMAP_INT_L1_NIRQ) \ 53 ? OMAP_INT_L1_BASE \ 54 : OMAP_INT_L2_BASE \ 55 + (irq-OMAP_INT_L1_NIRQ)/OMAP_BANK_WIDTH*OMAP_INTL2_BANK_OFF) 56#define IRQ_TO_BANK_NUM(irq) \ 57 ((irq)/OMAP_BANK_WIDTH) 58#define IRQ_TO_ILR(irq) \ 59 (IRQ_TO_BANK_BASE(irq) + \ 60 OMAP_INTB_ILR_BASE + \ 61 (irq) % OMAP_BANK_WIDTH * 4) 62#define IRQ_TO_MASK(irq) \ 63 (1 << (irq) % OMAP_BANK_WIDTH) 64 65#define INTR_INFO(irq,t) \ 66 [irq] = { \ 67 .trig = (t), \ 68 .bank_base = IRQ_TO_BANK_BASE(irq), \ 69 .bank_num = IRQ_TO_BANK_NUM(irq), \ 70 .ILR = IRQ_TO_ILR(irq), \ 71 .mask = IRQ_TO_MASK(irq) \ 72 } 73 74const omap_intr_info_t omap_intr_info[OMAP_NIRQ] = { 75 INTR_INFO( 0, TRIG_LEVEL), /* Level 2 IRQ */ 76 INTR_INFO( 1, TRIG_LEVEL), /* Camera IF */ 77 INTR_INFO( 2, TRIG_LEVEL), /* Level 2 FIQ */ 78 INTR_INFO( 3, TRIG_LEVEL_OR_EDGE), /* External FIQ */ 79 INTR_INFO( 4, TRIG_EDGE), /* McBSP2 TX */ 80 INTR_INFO( 5, TRIG_EDGE), /* McBSP2 RX */ 81 INTR_INFO( 6, TRIG_EDGE), /* IRQ_RTDX */ 82 INTR_INFO( 7, TRIG_LEVEL), /* IRQ_DSP_MMU_ABORT */ 83 INTR_INFO( 8, TRIG_EDGE), /* IRQ_HOST_INT */ 84 INTR_INFO( 9, TRIG_LEVEL), /* IRQ_ABORT */ 85 INTR_INFO( 10, TRIG_LEVEL), /* IRQ_DSP_MAILBOX1 */ 86 INTR_INFO( 11, TRIG_LEVEL), /* IRQ_DSP_MAILBOX2 */ 87 INTR_INFO( 12, TRIG_LEVEL), /* IRQ_LCD_LINE */ 88 INTR_INFO( 13, TRIG_LEVEL), /* Private TIPB Abort */ 89 INTR_INFO( 14, TRIG_LEVEL), /* IRQ1_GPIO1 */ 90 INTR_INFO( 15, TRIG_LEVEL), /* UART3 */ 91 INTR_INFO( 16, TRIG_EDGE), /* IRQ_TIMER3 */ 92 INTR_INFO( 17, TRIG_LEVEL), /* GPTIMER1 */ 93 INTR_INFO( 18, TRIG_LEVEL), /* GPTIMER2 */ 94 INTR_INFO( 19, TRIG_LEVEL), /* IRQ_DMA_CH0 */ 95 INTR_INFO( 20, TRIG_LEVEL), /* IRQ_DMA_CH1 */ 96 INTR_INFO( 21, TRIG_LEVEL), /* IRQ_DMA_CH2 */ 97 INTR_INFO( 22, TRIG_LEVEL), /* IRQ_DMA_CH3 */ 98 INTR_INFO( 23, TRIG_LEVEL), /* IRQ_DMA_CH4 */ 99 INTR_INFO( 24, TRIG_LEVEL), /* IRQ_DMA_CH5 */ 100 INTR_INFO( 25, TRIG_LEVEL), /* IRQ_DMA_CH_LCD */ 101 INTR_INFO( 26, TRIG_EDGE), /* IRQ_TIMER1 */ 102 INTR_INFO( 27, TRIG_EDGE), /* IRQ_WD_TIMER */ 103 INTR_INFO( 28, TRIG_LEVEL), /* Public TIPB Abort */ 104 INTR_INFO( 30, TRIG_EDGE), /* IRQ_TIMER2 */ 105 INTR_INFO( 31, TRIG_EDGE), /* IRQ_LCD_CTRL */ 106 INTR_INFO(OMAP_INT_L1_NIRQ+ 0, TRIG_LEVEL), /* FAC */ 107 INTR_INFO(OMAP_INT_L1_NIRQ+ 1, TRIG_EDGE), /* Keyboard */ 108 INTR_INFO(OMAP_INT_L1_NIRQ+ 2, TRIG_LEVEL), /* uWIRE TX */ 109 INTR_INFO(OMAP_INT_L1_NIRQ+ 3, TRIG_LEVEL), /* uWIRE RX */ 110 INTR_INFO(OMAP_INT_L1_NIRQ+ 4, TRIG_LEVEL), /* I2C */ 111 INTR_INFO(OMAP_INT_L1_NIRQ+ 5, TRIG_LEVEL), /* MPUIO */ 112 INTR_INFO(OMAP_INT_L1_NIRQ+ 6, TRIG_LEVEL), /* USB HHC 1 */ 113 INTR_INFO(OMAP_INT_L1_NIRQ+ 7, TRIG_LEVEL), /* USB HHC 2 */ 114 INTR_INFO(OMAP_INT_L1_NIRQ+ 8, TRIG_LEVEL), /* USB_OTG */ 115 INTR_INFO(OMAP_INT_L1_NIRQ+ 10, TRIG_EDGE), /* McBSP3 TX */ 116 INTR_INFO(OMAP_INT_L1_NIRQ+ 11, TRIG_EDGE), /* McBSP3 RX */ 117 INTR_INFO(OMAP_INT_L1_NIRQ+ 12, TRIG_EDGE), /* McBSP1 TX */ 118 INTR_INFO(OMAP_INT_L1_NIRQ+ 13, TRIG_EDGE), /* McBSP1 RX */ 119 INTR_INFO(OMAP_INT_L1_NIRQ+ 14, TRIG_LEVEL), /* UART1 */ 120 INTR_INFO(OMAP_INT_L1_NIRQ+ 15, TRIG_LEVEL), /* UART2 */ 121 INTR_INFO(OMAP_INT_L1_NIRQ+ 16, TRIG_LEVEL), /* MCSI1 */ 122 INTR_INFO(OMAP_INT_L1_NIRQ+ 17, TRIG_LEVEL), /* MCSI2 */ 123 INTR_INFO(OMAP_INT_L1_NIRQ+ 18, TRIG_EDGE), /* Free 1 */ 124 INTR_INFO(OMAP_INT_L1_NIRQ+ 20, TRIG_LEVEL), /* USB Geni IT */ 125 INTR_INFO(OMAP_INT_L1_NIRQ+ 21, TRIG_LEVEL), /* 1-Wire */ 126 INTR_INFO(OMAP_INT_L1_NIRQ+ 22, TRIG_EDGE), /* OS timer */ 127 INTR_INFO(OMAP_INT_L1_NIRQ+ 23, TRIG_LEVEL), /* MMC/SDIO1 */ 128 INTR_INFO(OMAP_INT_L1_NIRQ+ 24, TRIG_EDGE), /* USB client wakeup */ 129 INTR_INFO(OMAP_INT_L1_NIRQ+ 25, TRIG_EDGE), /* RTC periodic */ 130 INTR_INFO(OMAP_INT_L1_NIRQ+ 26, TRIG_LEVEL), /* RTC alarm */ 131 INTR_INFO(OMAP_INT_L1_NIRQ+ 28, TRIG_LEVEL), /* DSP_MMU_IRQ */ 132 INTR_INFO(OMAP_INT_L1_NIRQ+ 29, TRIG_LEVEL), /* USB IRQ_ISO_ON */ 133 INTR_INFO(OMAP_INT_L1_NIRQ+ 30, TRIG_LEVEL), /* USB IRQ_NON_ISO_ON */ 134 INTR_INFO(OMAP_INT_L1_NIRQ+ 34, TRIG_LEVEL), /* GPTIMER3 */ 135 INTR_INFO(OMAP_INT_L1_NIRQ+ 35, TRIG_LEVEL), /* GPTIMER4 */ 136 INTR_INFO(OMAP_INT_L1_NIRQ+ 36, TRIG_LEVEL), /* GPTIMER5 */ 137 INTR_INFO(OMAP_INT_L1_NIRQ+ 37, TRIG_LEVEL), /* GPTIMER6 */ 138 INTR_INFO(OMAP_INT_L1_NIRQ+ 38, TRIG_LEVEL), /* GPTIMER7 */ 139 INTR_INFO(OMAP_INT_L1_NIRQ+ 39, TRIG_LEVEL), /* GPTIMER8 */ 140 INTR_INFO(OMAP_INT_L1_NIRQ+ 40, TRIG_LEVEL), /* IRQ1_GPIO2 */ 141 INTR_INFO(OMAP_INT_L1_NIRQ+ 41, TRIG_LEVEL), /* IRQ1_GPIO3 */ 142 INTR_INFO(OMAP_INT_L1_NIRQ+ 42, TRIG_LEVEL), /* MMC/SDIO2 */ 143 INTR_INFO(OMAP_INT_L1_NIRQ+ 43, TRIG_EDGE), /* CompactFlash */ 144 INTR_INFO(OMAP_INT_L1_NIRQ+ 44, TRIG_LEVEL), /* COMMRX */ 145 INTR_INFO(OMAP_INT_L1_NIRQ+ 45, TRIG_LEVEL), /* COMMTX */ 146 INTR_INFO(OMAP_INT_L1_NIRQ+ 46, TRIG_EDGE), /* Peripheral wake up */ 147 INTR_INFO(OMAP_INT_L1_NIRQ+ 47, TRIG_EDGE), /* Free 2 */ 148 INTR_INFO(OMAP_INT_L1_NIRQ+ 48, TRIG_LEVEL), /* IRQ1_GPIO4 */ 149 INTR_INFO(OMAP_INT_L1_NIRQ+ 49, TRIG_LEVEL), /* SPI */ 150 INTR_INFO(OMAP_INT_L1_NIRQ+ 53, TRIG_LEVEL), /* IRQ_DMA_CH6 */ 151 INTR_INFO(OMAP_INT_L1_NIRQ+ 54, TRIG_LEVEL), /* IRQ_DMA_CH7 */ 152 INTR_INFO(OMAP_INT_L1_NIRQ+ 55, TRIG_LEVEL), /* IRQ_DMA_CH8 */ 153 INTR_INFO(OMAP_INT_L1_NIRQ+ 56, TRIG_LEVEL), /* IRQ_DMA_CH9 */ 154 INTR_INFO(OMAP_INT_L1_NIRQ+ 57, TRIG_LEVEL), /* IRQ_DMA_CH10 */ 155 INTR_INFO(OMAP_INT_L1_NIRQ+ 58, TRIG_LEVEL), /* IRQ_DMA_CH11 */ 156 INTR_INFO(OMAP_INT_L1_NIRQ+ 59, TRIG_LEVEL), /* IRQ_DMA_CH12 */ 157 INTR_INFO(OMAP_INT_L1_NIRQ+ 60, TRIG_LEVEL), /* IRQ_DMA_CH13 */ 158 INTR_INFO(OMAP_INT_L1_NIRQ+ 61, TRIG_LEVEL), /* IRQ_DMA_CH14 */ 159 INTR_INFO(OMAP_INT_L1_NIRQ+ 62, TRIG_LEVEL), /* IRQ_DMA_CH15 */ 160 INTR_INFO(OMAP_INT_L1_NIRQ+ 66, TRIG_EDGE), /* Free 3 */ 161 INTR_INFO(OMAP_INT_L1_NIRQ+ 91, TRIG_LEVEL), /* SHA1/MD5 */ 162 INTR_INFO(OMAP_INT_L1_NIRQ+ 92, TRIG_LEVEL), /* RNG */ 163 INTR_INFO(OMAP_INT_L1_NIRQ+ 93, TRIG_LEVEL), /* RNGIDLE */ 164 INTR_INFO(OMAP_INT_L1_NIRQ+103, TRIG_EDGE), /* Free 4 */ 165 INTR_INFO(OMAP_INT_L1_NIRQ+104, TRIG_EDGE), /* Free 5 */ 166 INTR_INFO(OMAP_INT_L1_NIRQ+105, TRIG_EDGE), /* Free 6 */ 167 INTR_INFO(OMAP_INT_L1_NIRQ+106, TRIG_EDGE), /* Free 7 */ 168 INTR_INFO(OMAP_INT_L1_NIRQ+107, TRIG_EDGE), /* Free 8 */ 169 INTR_INFO(OMAP_INT_L1_NIRQ+108, TRIG_EDGE), /* Free 9 */ 170 INTR_INFO(OMAP_INT_L1_NIRQ+109, TRIG_EDGE), /* Free 10 */ 171 INTR_INFO(OMAP_INT_L1_NIRQ+110, TRIG_EDGE), /* Free 11 */ 172 INTR_INFO(OMAP_INT_L1_NIRQ+111, TRIG_EDGE), /* Free 12 */ 173 INTR_INFO(OMAP_INT_L1_NIRQ+112, TRIG_EDGE), /* Free 13 */ 174 INTR_INFO(OMAP_INT_L1_NIRQ+113, TRIG_EDGE), /* Free 14 */ 175 INTR_INFO(OMAP_INT_L1_NIRQ+114, TRIG_EDGE), /* Free 15 */ 176 INTR_INFO(OMAP_INT_L1_NIRQ+115, TRIG_EDGE), /* Free 16 */ 177 INTR_INFO(OMAP_INT_L1_NIRQ+116, TRIG_EDGE), /* Free 17 */ 178 INTR_INFO(OMAP_INT_L1_NIRQ+117, TRIG_EDGE), /* Free 18 */ 179 INTR_INFO(OMAP_INT_L1_NIRQ+118, TRIG_EDGE), /* Free 19 */ 180 INTR_INFO(OMAP_INT_L1_NIRQ+119, TRIG_EDGE), /* Free 20 */ 181 INTR_INFO(OMAP_INT_L1_NIRQ+120, TRIG_EDGE), /* Free 21 */ 182 INTR_INFO(OMAP_INT_L1_NIRQ+121, TRIG_EDGE), /* Free 22 */ 183 INTR_INFO(OMAP_INT_L1_NIRQ+122, TRIG_EDGE), /* Free 23 */ 184 INTR_INFO(OMAP_INT_L1_NIRQ+123, TRIG_EDGE), /* Free 24 */ 185 INTR_INFO(OMAP_INT_L1_NIRQ+124, TRIG_EDGE), /* Free 25 */ 186 INTR_INFO(OMAP_INT_L1_NIRQ+125, TRIG_EDGE), /* Free 26 */ 187 INTR_INFO(OMAP_INT_L1_NIRQ+126, TRIG_EDGE), /* Free 27 */ 188 INTR_INFO(OMAP_INT_L1_NIRQ+127, TRIG_EDGE), /* Free 28 */ 189}; 190 191/* Array of pointers to each bank's base. */ 192vaddr_t omap_intr_bank_bases[OMAP_NBANKS] = { 193 OMAP_INT_L1_BASE, 194 OMAP_INT_L2_BASE + 0*OMAP_INTL2_BANK_OFF, 195 OMAP_INT_L2_BASE + 1*OMAP_INTL2_BANK_OFF, 196 OMAP_INT_L2_BASE + 2*OMAP_INTL2_BANK_OFF, 197 OMAP_INT_L2_BASE + 3*OMAP_INTL2_BANK_OFF, 198}; 199 200/* Array to translate from software interrupt numbers to an irq number. */ 201int omap_si_to_irq[OMAP_FREE_IRQ_NUM] = { 202 OMAP_INT_L1_NIRQ+ 18, /* Free 1 */ 203 OMAP_INT_L1_NIRQ+ 47, /* Free 2 */ 204 OMAP_INT_L1_NIRQ+ 66, /* Free 3 */ 205 OMAP_INT_L1_NIRQ+103, /* Free 4 */ 206 OMAP_INT_L1_NIRQ+104, /* Free 5 */ 207 OMAP_INT_L1_NIRQ+105, /* Free 6 */ 208 OMAP_INT_L1_NIRQ+106, /* Free 7 */ 209 OMAP_INT_L1_NIRQ+107, /* Free 8 */ 210 OMAP_INT_L1_NIRQ+108, /* Free 9 */ 211 OMAP_INT_L1_NIRQ+109, /* Free 10 */ 212 OMAP_INT_L1_NIRQ+110, /* Free 11 */ 213 OMAP_INT_L1_NIRQ+111, /* Free 12 */ 214 OMAP_INT_L1_NIRQ+112, /* Free 13 */ 215 OMAP_INT_L1_NIRQ+113, /* Free 14 */ 216 OMAP_INT_L1_NIRQ+114, /* Free 15 */ 217 OMAP_INT_L1_NIRQ+115, /* Free 16 */ 218 OMAP_INT_L1_NIRQ+116, /* Free 17 */ 219 OMAP_INT_L1_NIRQ+117, /* Free 18 */ 220 OMAP_INT_L1_NIRQ+118, /* Free 19 */ 221 OMAP_INT_L1_NIRQ+119, /* Free 20 */ 222 OMAP_INT_L1_NIRQ+120, /* Free 21 */ 223 OMAP_INT_L1_NIRQ+121, /* Free 22 */ 224 OMAP_INT_L1_NIRQ+122, /* Free 23 */ 225 OMAP_INT_L1_NIRQ+123, /* Free 24 */ 226 OMAP_INT_L1_NIRQ+124, /* Free 25 */ 227 OMAP_INT_L1_NIRQ+125, /* Free 26 */ 228 OMAP_INT_L1_NIRQ+126, /* Free 27 */ 229 OMAP_INT_L1_NIRQ+127, /* Free 28 */ 230}; 231