1/* $NetBSD: ofw_irq.S,v 1.11 2008/04/27 18:58:45 matt Exp $ */ 2 3/* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Low level irq and fiq handlers 38 * 39 * Created : 27/09/94 40 */ 41 42#include "assym.h" 43#include <machine/asm.h> 44#include <machine/cpu.h> 45#include <machine/frame.h> 46#include <machine/irqhandler.h> 47 48 .text 49 .align 0 50 51/* 52 * 53 * irq_entry 54 * 55 * Main entry point for the IRQ vector 56 * 57 * This function is called only on timer ticks, passed on to the 58 * kernel from the OFW tick handler. 59 * 60 * For now, I am trying to re-use as much of the code from the 61 * IOMD interrupt-handler as possible. In time, I will strip this 62 * down to something OFW-specific. 63 * 64 * Here's the original, IOMD-specific description: 65 * This function reads the irq request bits in the IOMD registers 66 * IRQRQA, IRQRQB and DMARQ 67 * It then calls an installed handler for each bit that is set. 68 * The function stray_irqhandler is called if a handler is not defined 69 * for a particular interrupt. 70 * If a interrupt handler is found then it is called with r0 containing 71 * the argument defined in the handler structure. If the field ih_arg 72 * is zero then a pointer to the IRQ frame on the stack is passed instead. 73 */ 74 75Ldisabled_mask: 76 .word _C_LABEL(disabled_mask) 77 78Lspl_masks: 79 .word _C_LABEL(spl_masks) 80 81Lofw_ticktmp: 82 .word _C_LABEL(ofw_ticktmp) 83 84Lirq_entry: 85 .word irq_entry 86 87Lofwirqstk: /* hack */ 88 .word ofwirqstk + 4096 89 90LOCK_CAS_CHECK_LOCALS 91 92AST_ALIGNMENT_FAULT_LOCALS 93 94/* 95 * Regsister usage 96 * 97 * r4 - Address of cpu_info 98 * r6 - Address of current handler 99 * r7 - Pointer to handler pointer list 100 * r8 - Current IRQ requests. 101 * r9 - Used to count through possible IRQ bits. 102 * r10 - Base address of IOMD 103 */ 104 105ASENTRY_NP(irq_entry) 106 /* 107 * We come here following an OFW-handled timer tick. 108 * 109 * We are in the SVC frame, and interrupts are disabled. 110 * The state of the interrupted context is partially in 111 * the registers and partially in the global storage area 112 * labeled ofw_ticktmp. ofw_ticktmp is filled-in by the 113 * tick callback that is invoked by OFW on the way out of 114 * its interrupt handler. ofw_ticktmp contains the following: 115 * 116 * pc // interrupted instruction 117 * lr_usr 118 * sp_usr 119 * r1 // makes r1 available for scratch 120 * r0 // makes r0 available for scratch 121 * spsr_svc // cpsr of interrupted context 122 * 123 * The prologue of this routine must re-construct the 124 * machine state that existed at the time OFW's interrupt- 125 * handler fielded the interrupt. That allows us to use 126 * the rest of the code in this routine, and have it all 127 * "just work." 128 */ 129 130 /* 131 * Switch to IRQ mode. 132 * First check the spsr in ofw_ticktmp to see what the FIQ bit should be. 133 * 134 * I need 2 scratch registers to do this. 135 * Fortunately, r0 and r1 are already saved in ofw_ticktmp. 136 * How convenient. 137 */ 138 ldr r0, Lofw_ticktmp 139 ldr r0, [r0] 140 and r0, r0, #F32_bit 141 mov r1, #(I32_bit | PSR_IRQ32_MODE) 142 orr r1, r1, r0 143 msr cpsr_all, r1 144 145 /* Now we're in IRQ mode. */ 146 /* Restore contents of ofw_ticktmp. */ 147 adr r0, Lofwirqstk /* Bummer! Mitch hasn't left me a stack. */ 148 ldr sp, [r0] /* I'll use my own for now... */ 149 ldr r0, Lofw_ticktmp /* r0 now points to ofw_ticktmp[0] */ 150 ldr r1, [r0], #(4*3) /* skip over saved {r0, r1} */ 151 msr spsr_all, r1 /* restore spsr */ 152 ldmia r0, {sp, lr}^ /* restore user sp and lr */ 153 add r0, r0, #(4*2) /* previous instruction can't writeback */ 154 /* this one can't use banked registers */ 155 ldr lr, [r0], #(-4*4) /* restore pc; point r0 at ofw_ticktmp[1] */ 156 add lr, lr, #4 /* pc += 4; will be decremented below */ 157 ldmia r0, {r0, r1} /* restore r0 and r1 */ 158 159 /* OK, the machine state should be identical now to that when */ 160 /* OFW fielded the interrupt. So just fall through... */ 161 162 sub lr, lr, #0x00000004 /* Adjust the lr */ 163 164 PUSHFRAMEINSVC /* Push an interrupt frame */ 165 166 /* 167 * Can't field this interrupt now if priority is IPL_CLOCK 168 * or higher. For now, we'll just ignore the interrupt. 169 * Soon, we will have to schedule it for later action. 170 */ 171 ldr r0, Lcurrent_spl_level 172 ldr r0, [r4, #CI_CPL] 173 cmp r0, #IPL_CLOCK 174 blt ofwtakeint 175 176 PULLFRAMEFROMSVCANDEXIT 177 movs pc, lr /* Exit */ 178 179 /* 180 * Stuff a bit-mask into r8 indicating which interrupts 181 * are pending. In our case, that is just the timer0 182 * interrupt: (1 << TIMER0). The existing code will take 183 * care of invoking that handler and the softint/ast stuff 184 * which follows it. 185 */ 186ofwtakeint: 187#ifdef EXEC_AOUT 188 ldr r0, [sp] /* Fetch SPSR */ 189#endif 190 ENABLE_ALIGNMENT_FAULTS 191 192 mov r8, #0x00000001 /* timer interrupt pending! */ 193 mov r8, r8, lsl #IRQ_TIMER0 194 195 /* 196 * Note that we have entered the IRQ handler. 197 * We are in SVC mode so we cannot use the processor mode 198 * to determine if we are in an IRQ. Instead we will count the 199 * each time the interrupt handler is nested. 200 */ 201 202 ldr r1, [r4, #CI_INTR_DEPTH] 203 add r1, r1, #1 204 str r1, [r4, #CI_INTR_DEPTH] 205 206 /* Block the current requested interrupts */ 207 ldr r1, Ldisabled_mask 208 ldr r0, [r1] 209 stmfd sp!, {r0} 210 orr r0, r0, r8 211 212 /* 213 * Need to block all interrupts at the IPL or lower for 214 * all asserted interrupts. 215 * This basically emulates hardware interrupt priority levels. 216 * Means we need to go through the interrupt mask and for 217 * every asserted interrupt we need to mask out all other 218 * interrupts at the same or lower IPL. 219 * If only we could wait until the main loop but we need to sort 220 * this out first so interrupts can be re-enabled. 221 * 222 * This would benefit from a special ffs type routine 223 */ 224 225 mov r9, #(NIPL - 1) 226 ldr r7, Lspl_masks 227 228Lfind_highest_ipl: 229 ldr r2, [r7, r9, lsl #2] 230 tst r8, r2 231 subeq r9, r9, #1 232 beq Lfind_highest_ipl 233 234 /* r9 = SPL level of highest priority interrupt */ 235 add r9, r9, #1 236 ldr r2, [r7, r9, lsl #2] 237 mvn r2, r2 238 orr r0, r0, r2 239 240 str r0, [r1] 241 242 ldr r0, Lcurrent_spl_level 243 ldr r1, [r4, #CI_CPL] 244 str r9, [r4, #CI_CPL] 245 stmfd sp!, {r1} 246 247 /* Update the irq masks */ 248 bl _C_LABEL(irq_setmasks) 249 250 mrs r0, cpsr_all /* Enable IRQ's */ 251 bic r0, r0, #I32_bit 252 msr cpsr_all, r0 253 254 ldr r7, Lirqhandlers 255 mov r9, #0x00000001 256 257irqloop: 258 /* This would benefit from a special ffs type routine */ 259 tst r8, r9 /* Is a bit set ? */ 260 beq nextirq /* No ? try next bit */ 261 262 ldr r6, [r7] /* Get address of first handler structure */ 263 264 teq r6, #0x00000000 /* Do we have a handler */ 265 moveq r0, r8 /* IRQ requests as arg 0 */ 266 beq _C_LABEL(stray_irqhandler) /* call special handler */ 267 268 ldr r1, [r4, #(CI_CC_NINTR)] 269 ldr r2, [r4, #(CI_CC_NINTR+4)] 270#ifdef _ARMEL 271 adds r1, r1, #0x00000001 272 adc r2, r2, #0x00000000 273#else 274 adds r2, r2, #0x00000001 275 adc r1, r1, #0x00000000 276#endif 277 str r1, [r4, #(CI_CC_NINTR)] 278 str r2, [r4, #(CI_CC_NINTR+4)] 279 280irqchainloop: 281 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 282 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 283 addeq r0, sp, #8 /* ... stack frame */ 284 mov lr, pc /* return address */ 285 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 286 287 teq r0, #0x00000001 /* Was the irq serviced ? */ 288 beq irqdone 289 290 ldr r6, [r6, #(IH_NEXT)] 291 teq r6, #0x00000000 292 bne irqchainloop 293 b nextirq 294 295irqdone: 296 add r3, r6, #IH_EV_COUNT /* get address of ih's ev_count */ 297 ldmia r3, {r1-r2} /* load ev_count */ 298 adds r1, r1, #0x00000001 /* 64bit incr (lo) */ 299 adc r2, r2, #0x00000000 /* 64bit incr (hi) */ 300 stmia r3, {r1-r2} /* store ev_count */ 301 302nextirq: 303 add r7, r7, #0x00000004 /* update pointer to handlers */ 304 mov r9, r9, lsl #1 /* move on to next bit */ 305 teq r9, #(1 << 24) /* done the last bit ? */ 306 bne irqloop /* no - loop back. */ 307 308 ldmfd sp!, {r2} 309 str r2, [r4, #CI_CPL] 310 311 /* Restore previous disabled mask */ 312 ldmfd sp!, {r2} 313 ldr r1, Ldisabled_mask 314 str r2, [r1] 315 bl _C_LABEL(irq_setmasks) 316 317 bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 318 319 /* Kill IRQ's in preparation for exit */ 320 mrs r0, cpsr_all 321 orr r0, r0, #(I32_bit) 322 msr cpsr_all, r0 323 324 /* Decrement the nest count */ 325 ldr r1, [r4, #CI_INTR_DEPTH] 326 sub r1, r1, #1 327 str r1, [r4, #CI_INTR_DEPTH] 328 329 LOCK_CAS_CHECK 330 331 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 332 PULLFRAMEFROMSVCANDEXIT 333 movs pc, lr /* Exit */ 334 335Lcurrent_mask: 336 .word _C_LABEL(current_mask) /* irq's that are usable */ 337 338 339ENTRY(irq_setmasks) 340 /* Do nothing */ 341 mov pc, lr 342 343 344Lirqhandlers: 345 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 346 347 .text 348 .global _C_LABEL(dotickgrovelling) 349 350/* 351 * Do magic to cause OFW to call our irq_entry 352 * routine when it returns from its tick-handling. 353 * 354 * This consists of two sub-tasks: 355 * - save some machine state in ofw_ticktmp 356 * - punch some new machine state into the 357 * OFW-supplied frame 358 * 359 * We are running in the IRQ frame, with 360 * interrupts disabled. 361 * 362 * r0 - base of saved OFW interrupt frame, which 363 * has the following format: 364 * 365 * pc // interrupted instruction 366 * lr // lr of interrupted context 367 * sp // sp of interrupted context 368 * r12 369 * ... // non-banked register values 370 * ... // of interrupted context 371 * r0 372 * spsr // psr of interrupted context 373 * 374 */ 375 376_C_LABEL(dotickgrovelling): 377 /*assert((cpsr & PSR_MODE) == PSR_IRQ32_MODE);*/ 378 379 stmfd sp!, {r1-r5} /* scratch registers r1-r5 */ 380 381 /* 382 * Sub-task 1: 383 * 384 * Our irq_entry routine needs to re-construct 385 * the state of the machine at the time OFW 386 * fielded the interrupt, so that we can use 387 * the rest of the standard interrupt-handling 388 * code. Specifically, irq_entry needs to get 389 * at the following machine state: 390 * 391 * pc // interrupted instruction 392 * lr_usr 393 * sp_usr 394 * r0-r12 // the non-banked registers 395 * // at the time of interruption 396 * spsr // cpsr of interrupted context 397 * 398 * The non-banked registers will be valid at the 399 * time irq_entry is called, but the other values 400 * will not be. We must save them here, in the 401 * ofw_ticktmp storage block. We also save r0 402 * and r1 so that we have some free registers 403 * when it's time to do the re-construction. 404 * 405 * Note that interrupts are not enabled before 406 * irq_entry is entered, so we don't have to 407 * worry about ofw_ticktmp getting clobbered. 408 */ 409 ldr r1, Lofw_ticktmp /* r1 points to ofw_ticktmp[0] */ 410 411 ldr r2, [r0, #0] /* ofwframe[0] is spsr */ 412 stmia r1!, {r2} /* put it in ofw_ticktmp[0] */ 413 414 ldr r2, [r0, #(4*1)] /* ofwframe[1] is saved r0 */ 415 stmia r1!, {r2} /* put it in ofw_ticktmp[1] */ 416 417 ldr r2, [r0, #(4*2)] /* ofwframe[2] is saved r1 */ 418 stmia r1!, {r2} /* put it in ofw_ticktmp[2] */ 419 420 stmia r1, {sp, lr}^ /* put {sp,lr}_usr in ofw_ticktmp[3,4]; */ 421 /* the user registers are still valid */ 422 /* because we haven't left IRQ mode */ 423 add r1, r1, #(4*2) /* previous instruction can't writeback */ 424 /* this one can't use banked registers */ 425 426 ldr r2, [r0, #(4*16)] /* ofwframe[16] is pc */ 427 stmia r1!, {r2} /* put it in ofw_ticktmp[5] */ 428 429 430 /* 431 * Sub-task 2: 432 * 433 * Diddle the OFW-supplied frame such that 434 * control passes to irq_entry when OFW does 435 * its return from interrupt. There are 4 436 * fields in that frame that we need to plug: 437 * 438 * pc // gets irq_entry 439 * lr // gets lr_svc 440 * sp // gets sp_svc 441 * spsr // gets (I32_bit | PSR_SVC32_MODE) 442 * 443 */ 444 mov r1, #(I32_bit | PSR_SVC32_MODE) 445 str r1, [r0, #0] /* plug spsr */ 446 447 /* Sneak into SVC mode to get sp and lr */ 448 mrs r3, cpsr_all 449 bic r3, r3, #(PSR_MODE) 450 orr r3, r3, #(PSR_SVC32_MODE) 451 msr cpsr_all, r3 452 mov r4, lr /* snarf lr_svc */ 453 mov r5, sp /* snarf sp_svc */ 454 bic r3, r3, #(PSR_MODE) 455 orr r3, r3, #(PSR_IRQ32_MODE) 456 msr cpsr_all, r3 457 str r5, [r0, #(4*14)] /* plug sp */ 458 str r4, [r0, #(4*15)] /* plug lr */ 459 460 ldr r1, Lirq_entry 461 str r1, [r0, #(4*16)] /* plug pc */ 462 463 ldmfd sp!, {r1-r5} 464 mov pc, lr 465 466 467 .bss 468 .align 0 469 470_C_LABEL(ofw_ticktmp): 471 .space 4 * 6 /* temporary storage for 6 words of machine state */ 472 473ofwirqstk: /* hack */ 474 .space 4096 475