1/* $NetBSD: armreg.h,v 1.48 2011/06/30 20:09:20 wiz Exp $ */ 2 3/* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39#ifndef _ARM_ARMREG_H 40#define _ARM_ARMREG_H 41 42/* 43 * ARM Process Status Register 44 * 45 * The picture in the ARM manuals looks like this: 46 * 3 3 2 2 2 2 47 * 1 0 9 8 7 6 8 7 6 5 4 0 48 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 49 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 50 * | | | | | | | | | |4 3 2 1 0| 51 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 52 */ 53 54#define PSR_FLAGS 0xf0000000 /* flags */ 55#define PSR_N_bit (1 << 31) /* negative */ 56#define PSR_Z_bit (1 << 30) /* zero */ 57#define PSR_C_bit (1 << 29) /* carry */ 58#define PSR_V_bit (1 << 28) /* overflow */ 59 60#define PSR_Q_bit (1 << 27) /* saturation */ 61 62#define I32_bit (1 << 7) /* IRQ disable */ 63#define F32_bit (1 << 6) /* FIQ disable */ 64#define IF32_bits (3 << 6) /* IRQ/FIQ disable */ 65 66#define PSR_T_bit (1 << 5) /* Thumb state */ 67#define PSR_J_bit (1 << 24) /* Java mode */ 68 69#define PSR_MODE 0x0000001f /* mode mask */ 70#define PSR_USR26_MODE 0x00000000 71#define PSR_FIQ26_MODE 0x00000001 72#define PSR_IRQ26_MODE 0x00000002 73#define PSR_SVC26_MODE 0x00000003 74#define PSR_USR32_MODE 0x00000010 75#define PSR_FIQ32_MODE 0x00000011 76#define PSR_IRQ32_MODE 0x00000012 77#define PSR_SVC32_MODE 0x00000013 78#define PSR_ABT32_MODE 0x00000017 79#define PSR_UND32_MODE 0x0000001b 80#define PSR_SYS32_MODE 0x0000001f 81#define PSR_32_MODE 0x00000010 82 83#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 84#define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) 85 86/* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ 87 88#define R15_MODE 0x00000003 89#define R15_MODE_USR 0x00000000 90#define R15_MODE_FIQ 0x00000001 91#define R15_MODE_IRQ 0x00000002 92#define R15_MODE_SVC 0x00000003 93 94#define R15_PC 0x03fffffc 95 96#define R15_FIQ_DISABLE 0x04000000 97#define R15_IRQ_DISABLE 0x08000000 98 99#define R15_FLAGS 0xf0000000 100#define R15_FLAG_N 0x80000000 101#define R15_FLAG_Z 0x40000000 102#define R15_FLAG_C 0x20000000 103#define R15_FLAG_V 0x10000000 104 105/* 106 * Co-processor 15: The system control co-processor. 107 */ 108 109#define ARM_CP15_CPU_ID 0 110 111/* 112 * The CPU ID register is theoretically structured, but the definitions of 113 * the fields keep changing. 114 */ 115 116/* The high-order byte is always the implementor */ 117#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 118#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 119#define CPU_ID_DEC 0x44000000 /* 'D' */ 120#define CPU_ID_INTEL 0x69000000 /* 'i' */ 121#define CPU_ID_TI 0x54000000 /* 'T' */ 122#define CPU_ID_MARVELL 0x56000000 /* 'V' */ 123#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 124 125/* How to decide what format the CPUID is in. */ 126#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 127#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 128#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 129 130/* On ARM3 and ARM6, this byte holds the foundry ID. */ 131#define CPU_ID_FOUNDRY_MASK 0x00ff0000 132#define CPU_ID_FOUNDRY_VLSI 0x00560000 133 134/* On ARM7 it holds the architecture and variant (sub-model) */ 135#define CPU_ID_7ARCH_MASK 0x00800000 136#define CPU_ID_7ARCH_V3 0x00000000 137#define CPU_ID_7ARCH_V4T 0x00800000 138#define CPU_ID_7VARIANT_MASK 0x007f0000 139 140/* On more recent ARMs, it does the same, but in a different format */ 141#define CPU_ID_ARCH_MASK 0x000f0000 142#define CPU_ID_ARCH_V3 0x00000000 143#define CPU_ID_ARCH_V4 0x00010000 144#define CPU_ID_ARCH_V4T 0x00020000 145#define CPU_ID_ARCH_V5 0x00030000 146#define CPU_ID_ARCH_V5T 0x00040000 147#define CPU_ID_ARCH_V5TE 0x00050000 148#define CPU_ID_ARCH_V5TEJ 0x00060000 149#define CPU_ID_ARCH_V6 0x00070000 150#define CPU_ID_VARIANT_MASK 0x00f00000 151 152/* Next three nybbles are part number */ 153#define CPU_ID_PARTNO_MASK 0x0000fff0 154 155/* Intel XScale has sub fields in part number */ 156#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 157#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 158#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 159 160/* And finally, the revision number. */ 161#define CPU_ID_REVISION_MASK 0x0000000f 162 163/* Individual CPUs are probably best IDed by everything but the revision. */ 164#define CPU_ID_CPU_MASK 0xfffffff0 165 166/* Fake CPU IDs for ARMs without CP15 */ 167#define CPU_ID_ARM2 0x41560200 168#define CPU_ID_ARM250 0x41560250 169 170/* Pre-ARM7 CPUs -- [15:12] == 0 */ 171#define CPU_ID_ARM3 0x41560300 172#define CPU_ID_ARM600 0x41560600 173#define CPU_ID_ARM610 0x41560610 174#define CPU_ID_ARM620 0x41560620 175 176/* ARM7 CPUs -- [15:12] == 7 */ 177#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 178#define CPU_ID_ARM710 0x41007100 179#define CPU_ID_ARM7500 0x41027100 180#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 181#define CPU_ID_ARM7500FE 0x41077100 182#define CPU_ID_ARM710T 0x41807100 183#define CPU_ID_ARM720T 0x41807200 184#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 185#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 186 187/* Post-ARM7 CPUs */ 188#define CPU_ID_ARM810 0x41018100 189#define CPU_ID_ARM920T 0x41129200 190#define CPU_ID_ARM922T 0x41029220 191#define CPU_ID_ARM926EJS 0x41069260 192#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 193#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 194#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 195#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 196#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 197#define CPU_ID_ARM1022ES 0x4105a220 198#define CPU_ID_ARM1026EJS 0x4106a260 199#define CPU_ID_ARM11MPCORE 0x410fb020 200#define CPU_ID_ARM1136JS 0x4107b360 201#define CPU_ID_ARM1136JSR1 0x4117b360 202#define CPU_ID_ARM1176JZS 0x410fb760 203#define CPU_ID_CORTEXA8R1 0x411fc080 204#define CPU_ID_CORTEXA8R2 0x412fc080 205#define CPU_ID_CORTEXA8R3 0x413fc080 206#define CPU_ID_CORTEXA9R1 0x411fc090 207#define CPU_ID_SA110 0x4401a100 208#define CPU_ID_SA1100 0x4401a110 209#define CPU_ID_TI925T 0x54029250 210#define CPU_ID_MV88FR571_VD 0x56155710 211#define CPU_ID_MV88SV131 0x56251310 212#define CPU_ID_FA526 0x66015260 213#define CPU_ID_SA1110 0x6901b110 214#define CPU_ID_IXP1200 0x6901c120 215#define CPU_ID_80200 0x69052000 216#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 217#define CPU_ID_PXA210 0x69052120 218#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 219#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 220#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 221#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 222#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 223#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 224#define CPU_ID_PXA27X 0x69054110 225#define CPU_ID_80321_400 0x69052420 226#define CPU_ID_80321_600 0x69052430 227#define CPU_ID_80321_400_B0 0x69052c20 228#define CPU_ID_80321_600_B0 0x69052c30 229#define CPU_ID_80219_400 0x69052e20 230#define CPU_ID_80219_600 0x69052e30 231#define CPU_ID_IXP425_533 0x690541c0 232#define CPU_ID_IXP425_400 0x690541d0 233#define CPU_ID_IXP425_266 0x690541f0 234 235/* ARM3-specific coprocessor 15 registers */ 236#define ARM3_CP15_FLUSH 1 237#define ARM3_CP15_CONTROL 2 238#define ARM3_CP15_CACHEABLE 3 239#define ARM3_CP15_UPDATEABLE 4 240#define ARM3_CP15_DISRUPTIVE 5 241 242/* ARM3 Control register bits */ 243#define ARM3_CTL_CACHE_ON 0x00000001 244#define ARM3_CTL_SHARED 0x00000002 245#define ARM3_CTL_MONITOR 0x00000004 246 247/* 248 * Post-ARM3 CP15 registers: 249 * 250 * 1 Control register 251 * 252 * 2 Translation Table Base 253 * 254 * 3 Domain Access Control 255 * 256 * 4 Reserved 257 * 258 * 5 Fault Status 259 * 260 * 6 Fault Address 261 * 262 * 7 Cache/write-buffer Control 263 * 264 * 8 TLB Control 265 * 266 * 9 Cache Lockdown 267 * 268 * 10 TLB Lockdown 269 * 270 * 11 Reserved 271 * 272 * 12 Reserved 273 * 274 * 13 Process ID (for FCSE) 275 * 276 * 14 Reserved 277 * 278 * 15 Implementation Dependent 279 */ 280 281/* Some of the definitions below need cleaning up for V3/V4 architectures */ 282 283/* CPU control register (CP15 register 1) */ 284#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 285#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 286#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 287#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 288#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 289#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 290#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 291#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 292#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 293#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 294#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 295#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 296#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 297#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 298#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 299#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 300#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 301#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 302#define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ 303#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 304#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 305#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 306#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ 307#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ 308#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 309 310#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 311 312/* ARM11r0 Auxillary Control Register (CP15 register 1, opcode2 1) */ 313#define ARM11R0_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 314 /* This is an undocumented flag 315 * used to work around a cache bug 316 * in r0 steppings. See errata 317 * 364296. 318 */ 319/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 320#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 321#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 322#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 323#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 324#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 325#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 326#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 327#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 328 329/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 330#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 331#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 332#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 333#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 334 335/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 336#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 337#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 338#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 339#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 340#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 341#define XSCALE_AUXCTL_MD_MASK 0x00000030 342 343/* ARM11 MPCore Auxillary Control Register (CP15 register 1, opcode2 1) */ 344#define MPCORE_AUXCTL_RS 0x00000001 /* return stack */ 345#define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 346#define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */ 347#define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */ 348#define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 349#define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */ 350 351/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ 352#define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ 353#define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ 354#define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ 355#define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ 356#define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 357#define FC_L2CACHE_EN 0x00400000 /* L2 enable */ 358#define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ 359#define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ 360#define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ 361#define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ 362 363/* Cache type register definitions 0 */ 364#define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */ 365#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 366#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 367#define CPU_CT_S (1U << 24) /* split cache */ 368#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 369 370#define CPU_CT_CTYPE_WT 0 /* write-through */ 371#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 372#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 373#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 374#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 375#define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */ 376 377#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 378#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 379#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 380#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 381#define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */ 382 383/* format 4 definitions */ 384#define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */ 385#define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */ 386#define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */ 387#define CPU_CT4_L1_VIPT 2 /* VIPT */ 388 389/* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */ 390#define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */ 391#define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */ 392#define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */ 393#define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */ 394#define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff) 395#define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) 396#define CPU_CSID_LEN(x) ((x) & 0x03) 397 398/* Cache size selection register definitions 2, Rd, c0, c0, 0 */ 399#define CPU_CSSR_L2 0x00000002 400#define CPU_CSSR_L1 0x00000000 401#define CPU_CSSR_InD 0x00000001 402 403/* Fault status register definitions */ 404 405#define FAULT_TYPE_MASK 0x0f 406#define FAULT_USER 0x10 407 408#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 409#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 410#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 411#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 412#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 413#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 414#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 415#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 416#define FAULT_ALIGN_0 0x01 /* Alignment */ 417#define FAULT_ALIGN_1 0x03 /* Alignment */ 418#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 419#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 420#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 421#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 422#define FAULT_PERM_S 0x0d /* Permission -- Section */ 423#define FAULT_PERM_P 0x0f /* Permission -- Page */ 424 425#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 426 427/* 428 * Address of the vector page, low and high versions. 429 */ 430#define ARM_VECTORS_LOW 0x00000000U 431#define ARM_VECTORS_HIGH 0xffff0000U 432 433/* 434 * ARM Instructions 435 * 436 * 3 3 2 2 2 437 * 1 0 9 8 7 0 438 * +-------+-------------------------------------------------------+ 439 * | cond | instruction dependent | 440 * |c c c c| | 441 * +-------+-------------------------------------------------------+ 442 */ 443 444#define INSN_SIZE 4 /* Always 4 bytes */ 445#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 446#define INSN_COND_AL 0xe0000000 /* Always condition */ 447 448#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 449 450/* 451 * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0) 452 */ 453#define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */ 454#define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */ 455#define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */ 456#define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */ 457#define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */ 458#define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */ 459#define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */ 460#define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */ 461#define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */ 462#define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */ 463#define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */ 464#define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */ 465#define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */ 466#define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */ 467#define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */ 468#define ARM11_PMCCTL_SBZ \ 469 (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb) 470 471#define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */ 472#define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */ 473#define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */ 474#define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */ 475#define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */ 476#define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */ 477#define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */ 478#define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */ 479#define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */ 480#define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */ 481#define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */ 482#define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */ 483#define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */ 484#define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */ 485#define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */ 486#define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */ 487#define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */ 488#define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */ 489#define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */ 490#define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */ 491#define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */ 492#define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */ 493#define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */ 494#define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */ 495 496/* Defines for ARM CORTEX performance counters */ 497#define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */ 498#define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ 499#define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ 500 501#endif /* _ARM_ARMREG_H */ 502