1/*	$NetBSD: vtpbc.c,v 1.7 2008/04/28 20:23:10 martin Exp $	*/
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Support for the V3 Semiconductor i960 PCI bus controller.  This appears
34 * on some MIPS boards (notably Algorithmics P-4032 and P-5064).
35 *
36 * Some help was provided by the Algorithmics PMON sources.
37 */
38
39#include <sys/cdefs.h>
40__KERNEL_RCSID(0, "$NetBSD: vtpbc.c,v 1.7 2008/04/28 20:23:10 martin Exp $");
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/device.h>
45
46#include <sys/bus.h>
47#include <machine/intr.h>
48#include <machine/locore.h>
49
50#include <dev/pci/pcireg.h>
51#include <dev/pci/pcivar.h>
52
53#include <algor/pci/vtpbcreg.h>
54#include <algor/pci/vtpbcvar.h>
55
56struct vtpbc_config vtpbc_configuration;
57
58#define	PCI_CONF_LOCK(s)	(s) = splhigh()
59#define	PCI_CONF_UNLOCK(s)	splx((s))
60
61const char *vtpbc_revs[] = {
62	"A",
63	"B0",
64	"B1",
65	"B2",
66	"C0",
67};
68const int vtpbc_nrevs = sizeof(vtpbc_revs) / sizeof(vtpbc_revs[0]);
69
70void	vtpbc_attach_hook(struct device *, struct device *,
71	    struct pcibus_attach_args *);
72int	vtpbc_bus_maxdevs(void *, int);
73pcitag_t vtpbc_make_tag(void *, int, int, int);
74void	vtpbc_decompose_tag(void *, pcitag_t, int *, int *, int *);
75pcireg_t vtpbc_conf_read(void *, pcitag_t, int);
76void	vtpbc_conf_write(void *, pcitag_t, int, pcireg_t);
77
78/*
79 * vtpbc_init:
80 *
81 *	Initialize the V3 PCI controller's software state.  We
82 *	simply use the existing windows that the firmware has
83 *	set up for us.
84 */
85void
86vtpbc_init(pci_chipset_tag_t pc, struct vtpbc_config *vt)
87{
88
89	pc->pc_conf_v = vt;
90	pc->pc_attach_hook = vtpbc_attach_hook;
91	pc->pc_bus_maxdevs = vtpbc_bus_maxdevs;
92	pc->pc_make_tag = vtpbc_make_tag;
93	pc->pc_decompose_tag = vtpbc_decompose_tag;
94	pc->pc_conf_read = vtpbc_conf_read;
95	pc->pc_conf_write = vtpbc_conf_write;
96
97	vt->vt_rev = V96X_PCI_CC_REV(vt) & V96X_PCI_CC_REV_VREV;
98
99	/*
100	 * Determine the PCI I/O space base that our PCI
101	 * I/O window maps to.  NOTE: We disable this on
102	 * PBC rev < B2.
103	 *
104	 * Also note that PMON has disabled the I/O space
105	 * if the old-style PCI address map is in-use.
106	 */
107	if (vt->vt_rev < V96X_VREV_B2)
108		vt->vt_pci_iobase = (bus_addr_t) -1;
109	else {
110		if ((V96X_LB_BASE2(vt) & V96X_LB_BASEx_ENABLE) == 0)
111			vt->vt_pci_iobase = (bus_addr_t) -1;
112		else
113			vt->vt_pci_iobase =
114			    (V96X_LB_MAP2(vt) & V96X_LB_MAPx_MAP_ADR) << 16;
115	}
116
117	/*
118	 * Determine the PCI memory space base that our PCI
119	 * memory window maps to.
120	 */
121	vt->vt_pci_membase = (V96X_LB_MAP1(vt) & V96X_LB_MAPx_MAP_ADR) << 16;
122
123	/*
124	 * Determine the PCI window base that maps host RAM for
125	 * DMA.
126	 */
127	vt->vt_dma_winbase = V96X_PCI_BASE1(vt) & 0xfffffff0;
128}
129
130void
131vtpbc_attach_hook(struct device *parent, struct device *self,
132    struct pcibus_attach_args *pba)
133{
134}
135
136int
137vtpbc_bus_maxdevs(void *v, int busno)
138{
139
140	return (32);
141}
142
143pcitag_t
144vtpbc_make_tag(void *v, int b, int d, int f)
145{
146
147	return ((b << 16) | (d << 11) | (f << 8));
148}
149
150void
151vtpbc_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
152{
153
154	if (bp != NULL)
155		*bp = (tag >> 16) & 0xff;
156	if (dp != NULL)
157		*dp = (tag >> 11) & 0x1f;
158	if (fp != NULL)
159		*fp = (tag >> 8) & 0x7;
160}
161
162static int
163vtpbc_conf_addr(struct vtpbc_config *vt, pcitag_t tag, int offset,
164    u_int32_t *cfgoff, u_int32_t *ad_low)
165{
166	int b, d, f;
167
168	vtpbc_decompose_tag(vt, tag, &b, &d, &f);
169
170	if (b == 0) {
171		if (d > (31 - vt->vt_adbase))
172			return (1);
173		*cfgoff = (1UL << (d + vt->vt_adbase)) | (f << 8) |
174		    offset;
175		*ad_low = 0;
176	} else if (vt->vt_rev >= V96X_VREV_C0) {
177		*cfgoff = tag | offset;
178		*ad_low = V96X_LB_MAPx_AD_LOW_EN;
179	} else
180		return (1);
181
182	return (0);
183}
184
185pcireg_t
186vtpbc_conf_read(void *v, pcitag_t tag, int offset)
187{
188	struct vtpbc_config *vt = v;
189	pcireg_t data;
190	u_int32_t cfgoff, ad_low;
191	int s;
192	u_int16_t errbits;
193
194	if (vtpbc_conf_addr(vt, tag, offset, &cfgoff, &ad_low))
195		return ((pcireg_t) -1);
196
197	PCI_CONF_LOCK(s);
198
199	/* high 12 bits of address go into map register */
200	V96X_LB_MAP0(vt) = ((cfgoff >> 16) & V96X_LB_MAPx_MAP_ADR) |
201	    ad_low | V96X_LB_TYPE_CONF;
202
203	/* clear aborts */
204	V96X_PCI_STAT(vt) |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
205
206	wbflush();
207
208	/* low 20 bits of address are offset into config space */
209	data = *(volatile u_int32_t *) (vt->vt_cfgbase + (cfgoff & 0xfffff));
210
211	errbits = V96X_PCI_STAT(vt) &
212	    (V96X_PCI_STAT_M_ABORT|V96X_PCI_STAT_T_ABORT);
213	if (errbits) {
214		V96X_PCI_STAT(vt) |= errbits;
215		data = (pcireg_t) -1;
216	}
217
218	PCI_CONF_UNLOCK(s);
219
220	return (data);
221}
222
223void
224vtpbc_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
225{
226	struct vtpbc_config *vt = v;
227	u_int32_t cfgoff, ad_low;
228	int s;
229
230	if (vtpbc_conf_addr(vt, tag, offset, &cfgoff, &ad_low))
231		panic("vtpbc_conf_write");
232
233	PCI_CONF_LOCK(s);
234
235	/* high 12 bits of address go into map register */
236	V96X_LB_MAP0(vt) = ((cfgoff >> 16) & V96X_LB_MAPx_MAP_ADR) |
237	    ad_low | V96X_LB_TYPE_CONF;
238
239	/* clear aborts */
240	V96X_PCI_STAT(vt) |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
241
242	wbflush();
243
244	/* low 20 bits of address are offset into config space */
245	*(volatile u_int32_t *) (vt->vt_cfgbase + (cfgoff & 0xfffff)) = data;
246
247	/* wait for FIFO to drain */
248	while (V96X_FIFO_STAT(vt) & V96X_FIFO_STAT_L2P_WR)
249		/* spin */ ;
250
251	PCI_CONF_UNLOCK(s);
252}
253