1/*	$NetBSD: interrupt.c,v 1.16 2011/02/20 07:51:21 matt Exp $	*/
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.16 2011/02/20 07:51:21 matt Exp $");
34
35#define	__INTR_PRIVATE
36#include "opt_algor_p4032.h"
37#include "opt_algor_p5064.h"
38#include "opt_algor_p6032.h"
39
40#include <sys/param.h>
41#include <sys/device.h>
42#include <sys/intr.h>
43#include <sys/cpu.h>
44
45#include <algor/autoconf.h>
46#include <mips/locore.h>
47#include <mips/mips3_clock.h>
48
49#ifdef ALGOR_P4032
50#include <algor/algor/algor_p4032var.h>
51#endif
52
53#ifdef ALGOR_P5064
54#include <algor/algor/algor_p5064var.h>
55#endif
56
57#ifdef ALGOR_P6032
58#include <algor/algor/algor_p6032var.h>
59#endif
60
61void	*(*algor_intr_establish)(int, int (*)(void *), void *);
62void	(*algor_intr_disestablish)(void *);
63
64void	(*algor_iointr)(int, vaddr_t, uint32_t);
65
66/*
67 * This is a mask of bits to clear in the SR when we go to a
68 * given interrupt priority level.
69 */
70static const struct ipl_sr_map algor_ipl_sr_map = {
71    .sr_bits = {
72	[IPL_NONE]	=	0,
73	[IPL_SOFTCLOCK]	=	MIPS_SOFT_INT_MASK_0,
74	[IPL_SOFTBIO]	=	MIPS_SOFT_INT_MASK_0,
75	[IPL_SOFTNET]	=	MIPS_SOFT_INT_MASK,
76	[IPL_SOFTSERIAL] =	MIPS_SOFT_INT_MASK,
77	[IPL_VM]	=	MIPS_SOFT_INT_MASK
78				|MIPS_INT_MASK_0|MIPS_INT_MASK_1
79				|MIPS_INT_MASK_2|MIPS_INT_MASK_3,
80	[IPL_SCHED]	=	MIPS_INT_MASK,
81	[IPL_HIGH]	=	MIPS_INT_MASK,
82    },
83};
84
85void
86#ifdef evbmips
87evbmips_intr_init(void)
88#else
89intr_init(void)
90#endif
91{
92	ipl_sr_map = algor_ipl_sr_map;
93
94#if defined(ALGOR_P4032)
95	algor_p4032_intr_init(&p4032_configuration);
96#elif defined(ALGOR_P5064)
97	algor_p5064_intr_init(&p5064_configuration);
98#elif defined(ALGOR_P6032)
99	algor_p6032_intr_init(&p6032_configuration);
100#endif
101}
102
103#ifdef evbmips
104void
105evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending)
106{
107	(*algor_iointr)(ipl, pc, pending);
108}
109
110void *
111evbmips_intr_establish(int irq, int (*func)(void *), void *arg)
112{
113	return (*algor_intr_establish)(irq, func, arg);
114}
115
116void
117evbmips_intr_disestablish(void *cookie)
118{
119	(*algor_intr_disestablish)(cookie);
120}
121#else
122void
123cpu_intr(int ppl, vaddr_t pc, uint32_t status)
124{
125	uint32_t pending;
126	int ipl;
127
128	curcpu()->ci_data.cpu_nintr++;
129
130	while (ppl < (ipl = splintr(&pending))) {
131		splx(ipl);
132		if (pending & MIPS_INT_MASK_5) {
133			struct clockframe cf;
134
135			cf.pc = pc;
136			cf.sr = status;
137			cf.intr = (curcpu()->ci_idepth > 1);
138			mips3_clockintr(&cf);
139		}
140
141		if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
142				MIPS_INT_MASK_3|MIPS_INT_MASK_4)) {
143			/* Process I/O and error interrupts. */
144			(*algor_iointr)(ipl, pc, pending);
145		}
146		(void)splhigh();
147	}
148}
149#endif
150