1/* This file contains the definitions and documentation for the 2 Register Transfer Expressions (rtx's) that make up the 3 Register Transfer Language (rtl) used in the Back End of the GNU compiler. 4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004, 5 2005 6 Free Software Foundation, Inc. 7 8This file is part of GCC. 9 10GCC is free software; you can redistribute it and/or modify it under 11the terms of the GNU General Public License as published by the Free 12Software Foundation; either version 2, or (at your option) any later 13version. 14 15GCC is distributed in the hope that it will be useful, but WITHOUT ANY 16WARRANTY; without even the implied warranty of MERCHANTABILITY or 17FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18for more details. 19 20You should have received a copy of the GNU General Public License 21along with GCC; see the file COPYING. If not, write to the Free 22Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 2302110-1301, USA. */ 24 25 26/* Expression definitions and descriptions for all targets are in this file. 27 Some will not be used for some targets. 28 29 The fields in the cpp macro call "DEF_RTL_EXPR()" 30 are used to create declarations in the C source of the compiler. 31 32 The fields are: 33 34 1. The internal name of the rtx used in the C source. 35 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". 36 By convention these are in UPPER_CASE. 37 38 2. The name of the rtx in the external ASCII format read by 39 read_rtx(), and printed by print_rtx(). 40 These names are stored in rtx_name[]. 41 By convention these are the internal (field 1) names in lower_case. 42 43 3. The print format, and type of each rtx->u.fld[] (field) in this rtx. 44 These formats are stored in rtx_format[]. 45 The meaning of the formats is documented in front of this array in rtl.c 46 47 4. The class of the rtx. These are stored in rtx_class and are accessed 48 via the GET_RTX_CLASS macro. They are defined as follows: 49 50 RTX_CONST_OBJ 51 an rtx code that can be used to represent a constant object 52 (e.g, CONST_INT) 53 RTX_OBJ 54 an rtx code that can be used to represent an object (e.g, REG, MEM) 55 RTX_COMPARE 56 an rtx code for a comparison (e.g, LT, GT) 57 RTX_COMM_COMPARE 58 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED) 59 RTX_UNARY 60 an rtx code for a unary arithmetic expression (e.g, NEG, NOT) 61 RTX_COMM_ARITH 62 an rtx code for a commutative binary operation (e.g,, PLUS, MULT) 63 RTX_TERNARY 64 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) 65 RTX_BIN_ARITH 66 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) 67 RTX_BITFIELD_OPS 68 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) 69 RTX_INSN 70 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) 71 RTX_MATCH 72 an rtx code for something that matches in insns (e.g, MATCH_DUP) 73 RTX_AUTOINC 74 an rtx code for autoincrement addressing modes (e.g. POST_DEC) 75 RTX_EXTRA 76 everything else 77 78 All of the expressions that appear only in machine descriptions, 79 not in RTL used by the compiler itself, are at the end of the file. */ 80 81/* Unknown, or no such operation; the enumeration constant should have 82 value zero. */ 83DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) 84 85/* --------------------------------------------------------------------- 86 Expressions used in constructing lists. 87 --------------------------------------------------------------------- */ 88 89/* a linked list of expressions */ 90DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA) 91 92/* a linked list of instructions. 93 The insns are represented in print by their uids. */ 94DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA) 95 96/* SEQUENCE appears in the result of a `gen_...' function 97 for a DEFINE_EXPAND that wants to make several insns. 98 Its elements are the bodies of the insns that should be made. 99 `emit_insn' takes the SEQUENCE apart and makes separate insns. */ 100DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA) 101 102/* Refers to the address of its argument. This is only used in alias.c. */ 103DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH) 104 105/* ---------------------------------------------------------------------- 106 Expression types used for things in the instruction chain. 107 108 All formats must start with "iuu" to handle the chain. 109 Each insn expression holds an rtl instruction and its semantics 110 during back-end processing. 111 See macros's in "rtl.h" for the meaning of each rtx->u.fld[]. 112 113 ---------------------------------------------------------------------- */ 114 115/* An instruction that cannot jump. */ 116DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN) 117 118/* An instruction that can possibly jump. 119 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 120DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN) 121 122/* An instruction that can possibly call a subroutine 123 but which will not change which instruction comes next 124 in the current function. 125 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE. 126 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 127DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN) 128 129/* A marker that indicates that control will not flow through. */ 130DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA) 131 132/* Holds a label that is followed by instructions. 133 Operand: 134 4: is used in jump.c for the use-count of the label. 135 5: is used in flow.c to point to the chain of label_ref's to this label. 136 6: is a number that is unique in the entire compilation. 137 7: is the user-given name of the label, if any. */ 138DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA) 139 140#ifdef USE_MAPPED_LOCATION 141/* Say where in the code a source line starts, for symbol table's sake. 142 Operand: 143 4: unused if line number > 0, note-specific data otherwise. 144 5: line number if > 0, enum note_insn otherwise. 145 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */ 146#else 147/* Say where in the code a source line starts, for symbol table's sake. 148 Operand: 149 4: filename, if line number > 0, note-specific data otherwise. 150 5: line number if > 0, enum note_insn otherwise. 151 6: unique number if line number == note_insn_deleted_label. */ 152#endif 153DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA) 154 155/* ---------------------------------------------------------------------- 156 Top level constituents of INSN, JUMP_INSN and CALL_INSN. 157 ---------------------------------------------------------------------- */ 158 159/* Conditionally execute code. 160 Operand 0 is the condition that if true, the code is executed. 161 Operand 1 is the code to be executed (typically a SET). 162 163 Semantics are that there are no side effects if the condition 164 is false. This pattern is created automatically by the if_convert 165 pass run after reload or by target-specific splitters. */ 166DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA) 167 168/* Several operations to be done in parallel (perhaps under COND_EXEC). */ 169DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA) 170 171/* A string that is passed through to the assembler as input. 172 One can obviously pass comments through by using the 173 assembler comment syntax. 174 These occur in an insn all by themselves as the PATTERN. 175 They also appear inside an ASM_OPERANDS 176 as a convenient way to hold a string. */ 177DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA) 178 179#ifdef USE_MAPPED_LOCATION 180/* An assembler instruction with operands. 181 1st operand is the instruction template. 182 2nd operand is the constraint for the output. 183 3rd operand is the number of the output this expression refers to. 184 When an insn stores more than one value, a separate ASM_OPERANDS 185 is made for each output; this integer distinguishes them. 186 4th is a vector of values of input operands. 187 5th is a vector of modes and constraints for the input operands. 188 Each element is an ASM_INPUT containing a constraint string 189 and whose mode indicates the mode of the input operand. 190 6th is the source line number. */ 191DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA) 192#else 193/* An assembler instruction with operands. 194 1st operand is the instruction template. 195 2nd operand is the constraint for the output. 196 3rd operand is the number of the output this expression refers to. 197 When an insn stores more than one value, a separate ASM_OPERANDS 198 is made for each output; this integer distinguishes them. 199 4th is a vector of values of input operands. 200 5th is a vector of modes and constraints for the input operands. 201 Each element is an ASM_INPUT containing a constraint string 202 and whose mode indicates the mode of the input operand. 203 6th is the name of the containing source file. 204 7th is the source line number. */ 205DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA) 206#endif 207 208/* A machine-specific operation. 209 1st operand is a vector of operands being used by the operation so that 210 any needed reloads can be done. 211 2nd operand is a unique value saying which of a number of machine-specific 212 operations is to be performed. 213 (Note that the vector must be the first operand because of the way that 214 genrecog.c record positions within an insn.) 215 This can occur all by itself in a PATTERN, as a component of a PARALLEL, 216 or inside an expression. */ 217DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA) 218 219/* Similar, but a volatile operation and one which may trap. */ 220DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA) 221 222/* Vector of addresses, stored as full words. */ 223/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ 224DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA) 225 226/* Vector of address differences X0 - BASE, X1 - BASE, ... 227 First operand is BASE; the vector contains the X's. 228 The machine mode of this rtx says how much space to leave 229 for each difference and is adjusted by branch shortening if 230 CASE_VECTOR_SHORTEN_MODE is defined. 231 The third and fourth operands store the target labels with the 232 minimum and maximum addresses respectively. 233 The fifth operand stores flags for use by branch shortening. 234 Set at the start of shorten_branches: 235 min_align: the minimum alignment for any of the target labels. 236 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. 237 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. 238 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. 239 min_after_base: true iff minimum address target label is after BASE. 240 max_after_base: true iff maximum address target label is after BASE. 241 Set by the actual branch shortening process: 242 offset_unsigned: true iff offsets have to be treated as unsigned. 243 scale: scaling that is necessary to make offsets fit into the mode. 244 245 The third, fourth and fifth operands are only valid when 246 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing 247 compilations. */ 248 249DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA) 250 251/* Memory prefetch, with attributes supported on some targets. 252 Operand 1 is the address of the memory to fetch. 253 Operand 2 is 1 for a write access, 0 otherwise. 254 Operand 3 is the level of temporal locality; 0 means there is no 255 temporal locality and 1, 2, and 3 are for increasing levels of temporal 256 locality. 257 258 The attributes specified by operands 2 and 3 are ignored for targets 259 whose prefetch instructions do not support them. */ 260DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA) 261 262/* ---------------------------------------------------------------------- 263 At the top level of an instruction (perhaps under PARALLEL). 264 ---------------------------------------------------------------------- */ 265 266/* Assignment. 267 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 268 Operand 2 is the value stored there. 269 ALL assignment must use SET. 270 Instructions that do multiple assignments must use multiple SET, 271 under PARALLEL. */ 272DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA) 273 274/* Indicate something is used in a way that we don't want to explain. 275 For example, subroutine calls will use the register 276 in which the static chain is passed. */ 277DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) 278 279/* Indicate something is clobbered in a way that we don't want to explain. 280 For example, subroutine calls will clobber some physical registers 281 (the ones that are by convention not saved). */ 282DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) 283 284/* Call a subroutine. 285 Operand 1 is the address to call. 286 Operand 2 is the number of arguments. */ 287 288DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA) 289 290/* Return from a subroutine. */ 291 292DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) 293 294/* Conditional trap. 295 Operand 1 is the condition. 296 Operand 2 is the trap code. 297 For an unconditional trap, make the condition (const_int 1). */ 298DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA) 299 300/* Placeholder for _Unwind_Resume before we know if a function call 301 or a branch is needed. Operand 1 is the exception region from 302 which control is flowing. */ 303DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA) 304 305/* ---------------------------------------------------------------------- 306 Primitive values for use in expressions. 307 ---------------------------------------------------------------------- */ 308 309/* numeric integer constant */ 310DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) 311 312/* numeric floating point constant. 313 Operands hold the value. They are all 'w' and there may be from 2 to 6; 314 see real.h. */ 315DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ) 316 317/* Describes a vector constant. */ 318DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ) 319 320/* String constant. Used for attributes in machine descriptions and 321 for special cases in DWARF2 debug output. NOT used for source- 322 language string constants. */ 323DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ) 324 325/* This is used to encapsulate an expression whose value is constant 326 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be 327 recognized as a constant operand rather than by arithmetic instructions. */ 328 329DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ) 330 331/* program counter. Ordinary jumps are represented 332 by a SET whose first operand is (PC). */ 333DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ) 334 335/* Used in the cselib routines to describe a value. Objects of this 336 kind are only allocated in cselib.c, in an alloc pool instead of 337 in GC memory. The only operand of a VALUE is a cselib_val_struct. */ 338DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ) 339 340/* A register. The "operand" is the register number, accessed with 341 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 342 than a hardware register is being referred to. The second operand 343 holds the original register number - this will be different for a 344 pseudo register that got turned into a hard register. The third 345 operand points to a reg_attrs structure. 346 This rtx needs to have as many (or more) fields as a MEM, since we 347 can change REG rtx's into MEMs during reload. */ 348DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ) 349 350/* A scratch register. This represents a register used only within a 351 single insn. It will be turned into a REG during register allocation 352 or reload unless the constraint indicates that the register won't be 353 needed, in which case it can remain a SCRATCH. This code is 354 marked as having one operand so it can be turned into a REG. */ 355DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ) 356 357/* One word of a multi-word value. 358 The first operand is the complete value; the second says which word. 359 The WORDS_BIG_ENDIAN flag controls whether word number 0 360 (as numbered in a SUBREG) is the most or least significant word. 361 362 This is also used to refer to a value in a different machine mode. 363 For example, it can be used to refer to a SImode value as if it were 364 Qimode, or vice versa. Then the word number is always 0. */ 365DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA) 366 367/* This one-argument rtx is used for move instructions 368 that are guaranteed to alter only the low part of a destination. 369 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 370 has an unspecified effect on the high part of REG, 371 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) 372 is guaranteed to alter only the bits of REG that are in HImode. 373 374 The actual instruction used is probably the same in both cases, 375 but the register constraints may be tighter when STRICT_LOW_PART 376 is in use. */ 377 378DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA) 379 380/* (CONCAT a b) represents the virtual concatenation of a and b 381 to make a value that has as many bits as a and b put together. 382 This is used for complex values. Normally it appears only 383 in DECL_RTLs and during RTL generation, but not in the insn chain. */ 384DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ) 385 386/* A memory location; operand is the address. The second operand is the 387 alias set to which this MEM belongs. We use `0' instead of `w' for this 388 field so that the field need not be specified in machine descriptions. */ 389DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ) 390 391/* Reference to an assembler label in the code for this function. 392 The operand is a CODE_LABEL found in the insn chain. 393 The unprinted field 1 is used in flow.c for the LABEL_NEXTREF. */ 394DEF_RTL_EXPR(LABEL_REF, "label_ref", "u0", RTX_CONST_OBJ) 395 396/* Reference to a named label: 397 Operand 0: label name 398 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h) 399 Operand 2: tree from which this symbol is derived, or null. 400 This is either a DECL node, or some kind of constant. */ 401DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ) 402 403/* The condition code register is represented, in our imagination, 404 as a register holding a value that can be compared to zero. 405 In fact, the machine has already compared them and recorded the 406 results; but instructions that look at the condition code 407 pretend to be looking at the entire value and comparing it. */ 408DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ) 409 410/* ---------------------------------------------------------------------- 411 Expressions for operators in an rtl pattern 412 ---------------------------------------------------------------------- */ 413 414/* if_then_else. This is used in representing ordinary 415 conditional jump instructions. 416 Operand: 417 0: condition 418 1: then expr 419 2: else expr */ 420DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY) 421 422/* Comparison, produces a condition code result. */ 423DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH) 424 425/* plus */ 426DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH) 427 428/* Operand 0 minus operand 1. */ 429DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH) 430 431/* Minus operand 0. */ 432DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY) 433 434DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH) 435 436/* Operand 0 divided by operand 1. */ 437DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH) 438/* Remainder of operand 0 divided by operand 1. */ 439DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH) 440 441/* Unsigned divide and remainder. */ 442DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH) 443DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) 444 445/* Bitwise operations. */ 446DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) 447DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) 448DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) 449DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) 450 451/* Operand: 452 0: value to be shifted. 453 1: number of bits. */ 454DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */ 455DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */ 456DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */ 457DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */ 458DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ 459 460/* Minimum and maximum values of two operands. We need both signed and 461 unsigned forms. (We cannot use MIN for SMIN because it conflicts 462 with a macro of the same name.) The signed variants should be used 463 with floating point. Further, if both operands are zeros, or if either 464 operand is NaN, then it is unspecified which of the two operands is 465 returned as the result. */ 466 467DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) 468DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) 469DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH) 470DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH) 471 472/* These unary operations are used to represent incrementation 473 and decrementation as they occur in memory addresses. 474 The amount of increment or decrement are not represented 475 because they can be understood from the machine-mode of the 476 containing MEM. These operations exist in only two cases: 477 1. pushes onto the stack. 478 2. created automatically by the life_analysis pass in flow.c. */ 479DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC) 480DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC) 481DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC) 482DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC) 483 484/* These binary operations are used to represent generic address 485 side-effects in memory addresses, except for simple incrementation 486 or decrementation which use the above operations. They are 487 created automatically by the life_analysis pass in flow.c. 488 The first operand is a REG which is used as the address. 489 The second operand is an expression that is assigned to the 490 register, either before (PRE_MODIFY) or after (POST_MODIFY) 491 evaluating the address. 492 Currently, the compiler can only handle second operands of the 493 form (plus (reg) (reg)) and (plus (reg) (const_int)), where 494 the first operand of the PLUS has to be the same register as 495 the first operand of the *_MODIFY. */ 496DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC) 497DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC) 498 499/* Comparison operations. The ordered comparisons exist in two 500 flavors, signed and unsigned. */ 501DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE) 502DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE) 503DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE) 504DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE) 505DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE) 506DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE) 507DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE) 508DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE) 509DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE) 510DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE) 511 512/* Additional floating point unordered comparison flavors. */ 513DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE) 514DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE) 515 516/* These are equivalent to unordered or ... */ 517DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE) 518DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE) 519DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE) 520DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE) 521DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE) 522 523/* This is an ordered NE, ie !UNEQ, ie false for NaN. */ 524DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE) 525 526/* Represents the result of sign-extending the sole operand. 527 The machine modes of the operand and of the SIGN_EXTEND expression 528 determine how much sign-extension is going on. */ 529DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY) 530 531/* Similar for zero-extension (such as unsigned short to int). */ 532DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY) 533 534/* Similar but here the operand has a wider mode. */ 535DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY) 536 537/* Similar for extending floating-point values (such as SFmode to DFmode). */ 538DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY) 539DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY) 540 541/* Conversion of fixed point operand to floating point value. */ 542DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY) 543 544/* With fixed-point machine mode: 545 Conversion of floating point operand to fixed point value. 546 Value is defined only when the operand's value is an integer. 547 With floating-point machine mode (and operand with same mode): 548 Operand is rounded toward zero to produce an integer value 549 represented in floating point. */ 550DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY) 551 552/* Conversion of unsigned fixed point operand to floating point value. */ 553DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY) 554 555/* With fixed-point machine mode: 556 Conversion of floating point operand to *unsigned* fixed point value. 557 Value is defined only when the operand's value is an integer. */ 558DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY) 559 560/* Absolute value */ 561DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY) 562 563/* Square root */ 564DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY) 565 566/* Find first bit that is set. 567 Value is 1 + number of trailing zeros in the arg., 568 or 0 if arg is 0. */ 569DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY) 570 571/* Count leading zeros. */ 572DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY) 573 574/* Count trailing zeros. */ 575DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY) 576 577/* Population count (number of 1 bits). */ 578DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY) 579 580/* Population parity (number of 1 bits modulo 2). */ 581DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY) 582 583/* Reference to a signed bit-field of specified size and position. 584 Operand 0 is the memory unit (usually SImode or QImode) which 585 contains the field's first bit. Operand 1 is the width, in bits. 586 Operand 2 is the number of bits in the memory unit before the 587 first bit of this field. 588 If BITS_BIG_ENDIAN is defined, the first bit is the msb and 589 operand 2 counts from the msb of the memory unit. 590 Otherwise, the first bit is the lsb and operand 2 counts from 591 the lsb of the memory unit. 592 This kind of expression can not appear as an lvalue in RTL. */ 593DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS) 594 595/* Similar for unsigned bit-field. 596 But note! This kind of expression _can_ appear as an lvalue. */ 597DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS) 598 599/* For RISC machines. These save memory when splitting insns. */ 600 601/* HIGH are the high-order bits of a constant expression. */ 602DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ) 603 604/* LO_SUM is the sum of a register and the low-order bits 605 of a constant expression. */ 606DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ) 607 608/* Describes a merge operation between two vector values. 609 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask 610 that specifies where the parts of the result are taken from. Set bits 611 indicate operand 0, clear bits indicate operand 1. The parts are defined 612 by the mode of the vectors. */ 613DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY) 614 615/* Describes an operation that selects parts of a vector. 616 Operands 0 is the source vector, operand 1 is a PARALLEL that contains 617 a CONST_INT for each of the subparts of the result vector, giving the 618 number of the source subpart that should be stored into it. */ 619DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH) 620 621/* Describes a vector concat operation. Operands 0 and 1 are the source 622 vectors, the result is a vector that is as long as operands 0 and 1 623 combined and is the concatenation of the two source vectors. */ 624DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH) 625 626/* Describes an operation that converts a small vector into a larger one by 627 duplicating the input values. The output vector mode must have the same 628 submodes as the input vector mode, and the number of output parts must be 629 an integer multiple of the number of input parts. */ 630DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY) 631 632/* Addition with signed saturation */ 633DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH) 634 635/* Addition with unsigned saturation */ 636DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH) 637 638/* Operand 0 minus operand 1, with signed saturation. */ 639DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH) 640 641/* Operand 0 minus operand 1, with unsigned saturation. */ 642DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH) 643 644/* Signed saturating truncate. */ 645DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY) 646 647/* Unsigned saturating truncate. */ 648DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) 649 650/* Information about the variable and its location. */ 651DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA) 652 653/* All expressions from this point forward appear only in machine 654 descriptions. */ 655#ifdef GENERATOR_FILE 656 657/* Include a secondary machine-description file at this point. */ 658DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA) 659 660/* Pattern-matching operators: */ 661 662/* Use the function named by the second arg (the string) 663 as a predicate; if matched, store the structure that was matched 664 in the operand table at index specified by the first arg (the integer). 665 If the second arg is the null string, the structure is just stored. 666 667 A third string argument indicates to the register allocator restrictions 668 on where the operand can be allocated. 669 670 If the target needs no restriction on any instruction this field should 671 be the null string. 672 673 The string is prepended by: 674 '=' to indicate the operand is only written to. 675 '+' to indicate the operand is both read and written to. 676 677 Each character in the string represents an allocable class for an operand. 678 'g' indicates the operand can be any valid class. 679 'i' indicates the operand can be immediate (in the instruction) data. 680 'r' indicates the operand can be in a register. 681 'm' indicates the operand can be in memory. 682 'o' a subset of the 'm' class. Those memory addressing modes that 683 can be offset at compile time (have a constant added to them). 684 685 Other characters indicate target dependent operand classes and 686 are described in each target's machine description. 687 688 For instructions with more than one operand, sets of classes can be 689 separated by a comma to indicate the appropriate multi-operand constraints. 690 There must be a 1 to 1 correspondence between these sets of classes in 691 all operands for an instruction. 692 */ 693DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH) 694 695/* Match a SCRATCH or a register. When used to generate rtl, a 696 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies 697 the desired mode and the first argument is the operand number. 698 The second argument is the constraint. */ 699DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH) 700 701/* Apply a predicate, AND match recursively the operands of the rtx. 702 Operand 0 is the operand-number, as in match_operand. 703 Operand 1 is a predicate to apply (as a string, a function name). 704 Operand 2 is a vector of expressions, each of which must match 705 one subexpression of the rtx this construct is matching. */ 706DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH) 707 708/* Match a PARALLEL of arbitrary length. The predicate is applied 709 to the PARALLEL and the initial expressions in the PARALLEL are matched. 710 Operand 0 is the operand-number, as in match_operand. 711 Operand 1 is a predicate to apply to the PARALLEL. 712 Operand 2 is a vector of expressions, each of which must match the 713 corresponding element in the PARALLEL. */ 714DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH) 715 716/* Match only something equal to what is stored in the operand table 717 at the index specified by the argument. Use with MATCH_OPERAND. */ 718DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH) 719 720/* Match only something equal to what is stored in the operand table 721 at the index specified by the argument. Use with MATCH_OPERATOR. */ 722DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH) 723 724/* Match only something equal to what is stored in the operand table 725 at the index specified by the argument. Use with MATCH_PARALLEL. */ 726DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH) 727 728/* Appears only in define_predicate/define_special_predicate 729 expressions. Evaluates true only if the operand has an RTX code 730 from the set given by the argument (a comma-separated list). */ 731DEF_RTL_EXPR(MATCH_CODE, "match_code", "s", RTX_MATCH) 732 733/* Appears only in define_predicate/define_special_predicate 734 expressions. The argument is a C expression to be injected at this 735 point in the predicate formula. */ 736DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH) 737 738/* Insn (and related) definitions. */ 739 740/* Definition of the pattern for one kind of instruction. 741 Operand: 742 0: names this instruction. 743 If the name is the null string, the instruction is in the 744 machine description just to be recognized, and will never be emitted by 745 the tree to rtl expander. 746 1: is the pattern. 747 2: is a string which is a C expression 748 giving an additional condition for recognizing this pattern. 749 A null string means no extra condition. 750 3: is the action to execute if this pattern is matched. 751 If this assembler code template starts with a * then it is a fragment of 752 C code to run to decide on a template to use. Otherwise, it is the 753 template to use. 754 4: optionally, a vector of attributes for this insn. 755 */ 756DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA) 757 758/* Definition of a peephole optimization. 759 1st operand: vector of insn patterns to match 760 2nd operand: C expression that must be true 761 3rd operand: template or C code to produce assembler output. 762 4: optionally, a vector of attributes for this insn. 763 764 This form is deprecated; use define_peephole2 instead. */ 765DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA) 766 767/* Definition of a split operation. 768 1st operand: insn pattern to match 769 2nd operand: C expression that must be true 770 3rd operand: vector of insn patterns to place into a SEQUENCE 771 4th operand: optionally, some C code to execute before generating the 772 insns. This might, for example, create some RTX's and store them in 773 elements of `recog_data.operand' for use by the vector of 774 insn-patterns. 775 (`operands' is an alias here for `recog_data.operand'). */ 776DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA) 777 778/* Definition of an insn and associated split. 779 This is the concatenation, with a few modifications, of a define_insn 780 and a define_split which share the same pattern. 781 Operand: 782 0: names this instruction. 783 If the name is the null string, the instruction is in the 784 machine description just to be recognized, and will never be emitted by 785 the tree to rtl expander. 786 1: is the pattern. 787 2: is a string which is a C expression 788 giving an additional condition for recognizing this pattern. 789 A null string means no extra condition. 790 3: is the action to execute if this pattern is matched. 791 If this assembler code template starts with a * then it is a fragment of 792 C code to run to decide on a template to use. Otherwise, it is the 793 template to use. 794 4: C expression that must be true for split. This may start with "&&" 795 in which case the split condition is the logical and of the insn 796 condition and what follows the "&&" of this operand. 797 5: vector of insn patterns to place into a SEQUENCE 798 6: optionally, some C code to execute before generating the 799 insns. This might, for example, create some RTX's and store them in 800 elements of `recog_data.operand' for use by the vector of 801 insn-patterns. 802 (`operands' is an alias here for `recog_data.operand'). 803 7: optionally, a vector of attributes for this insn. */ 804DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA) 805 806/* Definition of an RTL peephole operation. 807 Follows the same arguments as define_split. */ 808DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) 809 810/* Define how to generate multiple insns for a standard insn name. 811 1st operand: the insn name. 812 2nd operand: vector of insn-patterns. 813 Use match_operand to substitute an element of `recog_data.operand'. 814 3rd operand: C expression that must be true for this to be available. 815 This may not test any operands. 816 4th operand: Extra C code to execute before generating the insns. 817 This might, for example, create some RTX's and store them in 818 elements of `recog_data.operand' for use by the vector of 819 insn-patterns. 820 (`operands' is an alias here for `recog_data.operand'). */ 821DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA) 822 823/* Define a requirement for delay slots. 824 1st operand: Condition involving insn attributes that, if true, 825 indicates that the insn requires the number of delay slots 826 shown. 827 2nd operand: Vector whose length is the three times the number of delay 828 slots required. 829 Each entry gives three conditions, each involving attributes. 830 The first must be true for an insn to occupy that delay slot 831 location. The second is true for all insns that can be 832 annulled if the branch is true and the third is true for all 833 insns that can be annulled if the branch is false. 834 835 Multiple DEFINE_DELAYs may be present. They indicate differing 836 requirements for delay slots. */ 837DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA) 838 839/* Define attribute computation for `asm' instructions. */ 840DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA) 841 842/* Definition of a conditional execution meta operation. Automatically 843 generates new instances of DEFINE_INSN, selected by having attribute 844 "predicable" true. The new pattern will contain a COND_EXEC and the 845 predicate at top-level. 846 847 Operand: 848 0: The predicate pattern. The top-level form should match a 849 relational operator. Operands should have only one alternative. 850 1: A C expression giving an additional condition for recognizing 851 the generated pattern. 852 2: A template or C code to produce assembler output. */ 853DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) 854 855/* Definition of an operand predicate. The difference between 856 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will 857 not warn about a match_operand with no mode if it has a predicate 858 defined with DEFINE_SPECIAL_PREDICATE. 859 860 Operand: 861 0: The name of the predicate. 862 1: A boolean expression which computes whether or not the predicate 863 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND, 864 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog 865 can calculate the set of RTX codes that can possibly match. 866 2: A C function body which must return true for the predicate to match. 867 Optional. Use this when the test is too complicated to fit into a 868 match_test expression. */ 869DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA) 870DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA) 871 872/* Constructions for CPU pipeline description described by NDFAs. */ 873 874/* (define_cpu_unit string [string]) describes cpu functional 875 units (separated by comma). 876 877 1st operand: Names of cpu functional units. 878 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). 879 880 All define_reservations, define_cpu_units, and 881 define_query_cpu_units should have unique names which may not be 882 "nothing". */ 883DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA) 884 885/* (define_query_cpu_unit string [string]) describes cpu functional 886 units analogously to define_cpu_unit. The reservation of such 887 units can be queried for automaton state. */ 888DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA) 889 890/* (exclusion_set string string) means that each CPU functional unit 891 in the first string can not be reserved simultaneously with any 892 unit whose name is in the second string and vise versa. CPU units 893 in the string are separated by commas. For example, it is useful 894 for description CPU with fully pipelined floating point functional 895 unit which can execute simultaneously only single floating point 896 insns or only double floating point insns. All CPU functional 897 units in a set should belong to the same automaton. */ 898DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA) 899 900/* (presence_set string string) means that each CPU functional unit in 901 the first string can not be reserved unless at least one of pattern 902 of units whose names are in the second string is reserved. This is 903 an asymmetric relation. CPU units or unit patterns in the strings 904 are separated by commas. Pattern is one unit name or unit names 905 separated by white-spaces. 906 907 For example, it is useful for description that slot1 is reserved 908 after slot0 reservation for a VLIW processor. We could describe it 909 by the following construction 910 911 (presence_set "slot1" "slot0") 912 913 Or slot1 is reserved only after slot0 and unit b0 reservation. In 914 this case we could write 915 916 (presence_set "slot1" "slot0 b0") 917 918 All CPU functional units in a set should belong to the same 919 automaton. */ 920DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA) 921 922/* (final_presence_set string string) is analogous to `presence_set'. 923 The difference between them is when checking is done. When an 924 instruction is issued in given automaton state reflecting all 925 current and planned unit reservations, the automaton state is 926 changed. The first state is a source state, the second one is a 927 result state. Checking for `presence_set' is done on the source 928 state reservation, checking for `final_presence_set' is done on the 929 result reservation. This construction is useful to describe a 930 reservation which is actually two subsequent reservations. For 931 example, if we use 932 933 (presence_set "slot1" "slot0") 934 935 the following insn will be never issued (because slot1 requires 936 slot0 which is absent in the source state). 937 938 (define_reservation "insn_and_nop" "slot0 + slot1") 939 940 but it can be issued if we use analogous `final_presence_set'. */ 941DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA) 942 943/* (absence_set string string) means that each CPU functional unit in 944 the first string can be reserved only if each pattern of units 945 whose names are in the second string is not reserved. This is an 946 asymmetric relation (actually exclusion set is analogous to this 947 one but it is symmetric). CPU units or unit patterns in the string 948 are separated by commas. Pattern is one unit name or unit names 949 separated by white-spaces. 950 951 For example, it is useful for description that slot0 can not be 952 reserved after slot1 or slot2 reservation for a VLIW processor. We 953 could describe it by the following construction 954 955 (absence_set "slot2" "slot0, slot1") 956 957 Or slot2 can not be reserved if slot0 and unit b0 are reserved or 958 slot1 and unit b1 are reserved . In this case we could write 959 960 (absence_set "slot2" "slot0 b0, slot1 b1") 961 962 All CPU functional units in a set should to belong the same 963 automaton. */ 964DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA) 965 966/* (final_absence_set string string) is analogous to `absence_set' but 967 checking is done on the result (state) reservation. See comments 968 for `final_presence_set'. */ 969DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA) 970 971/* (define_bypass number out_insn_names in_insn_names) names bypass 972 with given latency (the first number) from insns given by the first 973 string (see define_insn_reservation) into insns given by the second 974 string. Insn names in the strings are separated by commas. The 975 third operand is optional name of function which is additional 976 guard for the bypass. The function will get the two insns as 977 parameters. If the function returns zero the bypass will be 978 ignored for this case. Additional guard is necessary to recognize 979 complicated bypasses, e.g. when consumer is load address. */ 980DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA) 981 982/* (define_automaton string) describes names of automata generated and 983 used for pipeline hazards recognition. The names are separated by 984 comma. Actually it is possibly to generate the single automaton 985 but unfortunately it can be very large. If we use more one 986 automata, the summary size of the automata usually is less than the 987 single one. The automaton name is used in define_cpu_unit and 988 define_query_cpu_unit. All automata should have unique names. */ 989DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA) 990 991/* (automata_option string) describes option for generation of 992 automata. Currently there are the following options: 993 994 o "no-minimization" which makes no minimization of automata. This 995 is only worth to do when we are debugging the description and 996 need to look more accurately at reservations of states. 997 998 o "time" which means printing additional time statistics about 999 generation of automata. 1000 1001 o "v" which means generation of file describing the result 1002 automata. The file has suffix `.dfa' and can be used for the 1003 description verification and debugging. 1004 1005 o "w" which means generation of warning instead of error for 1006 non-critical errors. 1007 1008 o "ndfa" which makes nondeterministic finite state automata. 1009 1010 o "progress" which means output of a progress bar showing how many 1011 states were generated so far for automaton being processed. */ 1012DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA) 1013 1014/* (define_reservation string string) names reservation (the first 1015 string) of cpu functional units (the 2nd string). Sometimes unit 1016 reservations for different insns contain common parts. In such 1017 case, you can describe common part and use its name (the 1st 1018 parameter) in regular expression in define_insn_reservation. All 1019 define_reservations, define_cpu_units, and define_query_cpu_units 1020 should have unique names which may not be "nothing". */ 1021DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA) 1022 1023/* (define_insn_reservation name default_latency condition regexpr) 1024 describes reservation of cpu functional units (the 3nd operand) for 1025 instruction which is selected by the condition (the 2nd parameter). 1026 The first parameter is used for output of debugging information. 1027 The reservations are described by a regular expression according 1028 the following syntax: 1029 1030 regexp = regexp "," oneof 1031 | oneof 1032 1033 oneof = oneof "|" allof 1034 | allof 1035 1036 allof = allof "+" repeat 1037 | repeat 1038 1039 repeat = element "*" number 1040 | element 1041 1042 element = cpu_function_unit_name 1043 | reservation_name 1044 | result_name 1045 | "nothing" 1046 | "(" regexp ")" 1047 1048 1. "," is used for describing start of the next cycle in 1049 reservation. 1050 1051 2. "|" is used for describing the reservation described by the 1052 first regular expression *or* the reservation described by the 1053 second regular expression *or* etc. 1054 1055 3. "+" is used for describing the reservation described by the 1056 first regular expression *and* the reservation described by the 1057 second regular expression *and* etc. 1058 1059 4. "*" is used for convenience and simply means sequence in 1060 which the regular expression are repeated NUMBER times with 1061 cycle advancing (see ","). 1062 1063 5. cpu functional unit name which means its reservation. 1064 1065 6. reservation name -- see define_reservation. 1066 1067 7. string "nothing" means no units reservation. */ 1068 1069DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA) 1070 1071/* Expressions used for insn attributes. */ 1072 1073/* Definition of an insn attribute. 1074 1st operand: name of the attribute 1075 2nd operand: comma-separated list of possible attribute values 1076 3rd operand: expression for the default value of the attribute. */ 1077DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA) 1078 1079/* Marker for the name of an attribute. */ 1080DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA) 1081 1082/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and 1083 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that 1084 pattern. 1085 1086 (set_attr "name" "value") is equivalent to 1087 (set (attr "name") (const_string "value")) */ 1088DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA) 1089 1090/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to 1091 specify that attribute values are to be assigned according to the 1092 alternative matched. 1093 1094 The following three expressions are equivalent: 1095 1096 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") 1097 (eq_attrq "alternative" "2") (const_string "a2")] 1098 (const_string "a3"))) 1099 (set_attr_alternative "att" [(const_string "a1") (const_string "a2") 1100 (const_string "a3")]) 1101 (set_attr "att" "a1,a2,a3") 1102 */ 1103DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA) 1104 1105/* A conditional expression true if the value of the specified attribute of 1106 the current insn equals the specified value. The first operand is the 1107 attribute name and the second is the comparison value. */ 1108DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA) 1109 1110/* A special case of the above representing a set of alternatives. The first 1111 operand is bitmap of the set, the second one is the default value. */ 1112DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA) 1113 1114/* A conditional expression which is true if the specified flag is 1115 true for the insn being scheduled in reorg. 1116 1117 genattr.c defines the following flags which can be tested by 1118 (attr_flag "foo") expressions in eligible_for_delay. 1119 1120 forward, backward, very_likely, likely, very_unlikely, and unlikely. */ 1121 1122DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA) 1123 1124/* General conditional. The first operand is a vector composed of pairs of 1125 expressions. The first element of each pair is evaluated, in turn. 1126 The value of the conditional is the second expression of the first pair 1127 whose first expression evaluates nonzero. If none of the expressions is 1128 true, the second operand will be used as the value of the conditional. */ 1129DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA) 1130 1131#endif /* GENERATOR_FILE */ 1132 1133/* 1134Local variables: 1135mode:c 1136End: 1137*/ 1138