1/* Subroutines used for code generation on IBM S/390 and zSeries 2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 3 Free Software Foundation, Inc. 4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and 5 Ulrich Weigand (uweigand@de.ibm.com). 6 7This file is part of GCC. 8 9GCC is free software; you can redistribute it and/or modify it under 10the terms of the GNU General Public License as published by the Free 11Software Foundation; either version 2, or (at your option) any later 12version. 13 14GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15WARRANTY; without even the implied warranty of MERCHANTABILITY or 16FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17for more details. 18 19You should have received a copy of the GNU General Public License 20along with GCC; see the file COPYING. If not, write to the Free 21Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 2202110-1301, USA. */ 23 24#include "config.h" 25#include "system.h" 26#include "coretypes.h" 27#include "tm.h" 28#include "rtl.h" 29#include "tree.h" 30#include "tm_p.h" 31#include "regs.h" 32#include "hard-reg-set.h" 33#include "real.h" 34#include "insn-config.h" 35#include "conditions.h" 36#include "output.h" 37#include "insn-attr.h" 38#include "flags.h" 39#include "except.h" 40#include "function.h" 41#include "recog.h" 42#include "expr.h" 43#include "reload.h" 44#include "toplev.h" 45#include "basic-block.h" 46#include "integrate.h" 47#include "ggc.h" 48#include "target.h" 49#include "target-def.h" 50#include "debug.h" 51#include "langhooks.h" 52#include "optabs.h" 53#include "tree-gimple.h" 54 55 56/* Define the specific costs for a given cpu. */ 57 58struct processor_costs 59{ 60 /* multiplication */ 61 const int m; /* cost of an M instruction. */ 62 const int mghi; /* cost of an MGHI instruction. */ 63 const int mh; /* cost of an MH instruction. */ 64 const int mhi; /* cost of an MHI instruction. */ 65 const int ml; /* cost of an ML instruction. */ 66 const int mr; /* cost of an MR instruction. */ 67 const int ms; /* cost of an MS instruction. */ 68 const int msg; /* cost of an MSG instruction. */ 69 const int msgf; /* cost of an MSGF instruction. */ 70 const int msgfr; /* cost of an MSGFR instruction. */ 71 const int msgr; /* cost of an MSGR instruction. */ 72 const int msr; /* cost of an MSR instruction. */ 73 const int mult_df; /* cost of multiplication in DFmode. */ 74 const int mxbr; 75 /* square root */ 76 const int sqxbr; /* cost of square root in TFmode. */ 77 const int sqdbr; /* cost of square root in DFmode. */ 78 const int sqebr; /* cost of square root in SFmode. */ 79 /* multiply and add */ 80 const int madbr; /* cost of multiply and add in DFmode. */ 81 const int maebr; /* cost of multiply and add in SFmode. */ 82 /* division */ 83 const int dxbr; 84 const int dxr; 85 const int ddbr; 86 const int ddr; 87 const int debr; 88 const int der; 89 const int dlgr; 90 const int dlr; 91 const int dr; 92 const int dsgfr; 93 const int dsgr; 94}; 95 96const struct processor_costs *s390_cost; 97 98static const 99struct processor_costs z900_cost = 100{ 101 COSTS_N_INSNS (5), /* M */ 102 COSTS_N_INSNS (10), /* MGHI */ 103 COSTS_N_INSNS (5), /* MH */ 104 COSTS_N_INSNS (4), /* MHI */ 105 COSTS_N_INSNS (5), /* ML */ 106 COSTS_N_INSNS (5), /* MR */ 107 COSTS_N_INSNS (4), /* MS */ 108 COSTS_N_INSNS (15), /* MSG */ 109 COSTS_N_INSNS (7), /* MSGF */ 110 COSTS_N_INSNS (7), /* MSGFR */ 111 COSTS_N_INSNS (10), /* MSGR */ 112 COSTS_N_INSNS (4), /* MSR */ 113 COSTS_N_INSNS (7), /* multiplication in DFmode */ 114 COSTS_N_INSNS (13), /* MXBR */ 115 COSTS_N_INSNS (136), /* SQXBR */ 116 COSTS_N_INSNS (44), /* SQDBR */ 117 COSTS_N_INSNS (35), /* SQEBR */ 118 COSTS_N_INSNS (18), /* MADBR */ 119 COSTS_N_INSNS (13), /* MAEBR */ 120 COSTS_N_INSNS (134), /* DXBR */ 121 COSTS_N_INSNS (135), /* DXR */ 122 COSTS_N_INSNS (30), /* DDBR */ 123 COSTS_N_INSNS (30), /* DDR */ 124 COSTS_N_INSNS (27), /* DEBR */ 125 COSTS_N_INSNS (26), /* DER */ 126 COSTS_N_INSNS (220), /* DLGR */ 127 COSTS_N_INSNS (34), /* DLR */ 128 COSTS_N_INSNS (34), /* DR */ 129 COSTS_N_INSNS (32), /* DSGFR */ 130 COSTS_N_INSNS (32), /* DSGR */ 131}; 132 133static const 134struct processor_costs z990_cost = 135{ 136 COSTS_N_INSNS (4), /* M */ 137 COSTS_N_INSNS (2), /* MGHI */ 138 COSTS_N_INSNS (2), /* MH */ 139 COSTS_N_INSNS (2), /* MHI */ 140 COSTS_N_INSNS (4), /* ML */ 141 COSTS_N_INSNS (4), /* MR */ 142 COSTS_N_INSNS (5), /* MS */ 143 COSTS_N_INSNS (6), /* MSG */ 144 COSTS_N_INSNS (4), /* MSGF */ 145 COSTS_N_INSNS (4), /* MSGFR */ 146 COSTS_N_INSNS (4), /* MSGR */ 147 COSTS_N_INSNS (4), /* MSR */ 148 COSTS_N_INSNS (1), /* multiplication in DFmode */ 149 COSTS_N_INSNS (28), /* MXBR */ 150 COSTS_N_INSNS (130), /* SQXBR */ 151 COSTS_N_INSNS (66), /* SQDBR */ 152 COSTS_N_INSNS (38), /* SQEBR */ 153 COSTS_N_INSNS (1), /* MADBR */ 154 COSTS_N_INSNS (1), /* MAEBR */ 155 COSTS_N_INSNS (60), /* DXBR */ 156 COSTS_N_INSNS (72), /* DXR */ 157 COSTS_N_INSNS (40), /* DDBR */ 158 COSTS_N_INSNS (44), /* DDR */ 159 COSTS_N_INSNS (26), /* DDBR */ 160 COSTS_N_INSNS (28), /* DER */ 161 COSTS_N_INSNS (176), /* DLGR */ 162 COSTS_N_INSNS (31), /* DLR */ 163 COSTS_N_INSNS (31), /* DR */ 164 COSTS_N_INSNS (31), /* DSGFR */ 165 COSTS_N_INSNS (31), /* DSGR */ 166}; 167 168static const 169struct processor_costs z9_109_cost = 170{ 171 COSTS_N_INSNS (4), /* M */ 172 COSTS_N_INSNS (2), /* MGHI */ 173 COSTS_N_INSNS (2), /* MH */ 174 COSTS_N_INSNS (2), /* MHI */ 175 COSTS_N_INSNS (4), /* ML */ 176 COSTS_N_INSNS (4), /* MR */ 177 COSTS_N_INSNS (5), /* MS */ 178 COSTS_N_INSNS (6), /* MSG */ 179 COSTS_N_INSNS (4), /* MSGF */ 180 COSTS_N_INSNS (4), /* MSGFR */ 181 COSTS_N_INSNS (4), /* MSGR */ 182 COSTS_N_INSNS (4), /* MSR */ 183 COSTS_N_INSNS (1), /* multiplication in DFmode */ 184 COSTS_N_INSNS (28), /* MXBR */ 185 COSTS_N_INSNS (130), /* SQXBR */ 186 COSTS_N_INSNS (66), /* SQDBR */ 187 COSTS_N_INSNS (38), /* SQEBR */ 188 COSTS_N_INSNS (1), /* MADBR */ 189 COSTS_N_INSNS (1), /* MAEBR */ 190 COSTS_N_INSNS (60), /* DXBR */ 191 COSTS_N_INSNS (72), /* DXR */ 192 COSTS_N_INSNS (40), /* DDBR */ 193 COSTS_N_INSNS (37), /* DDR */ 194 COSTS_N_INSNS (26), /* DDBR */ 195 COSTS_N_INSNS (28), /* DER */ 196 COSTS_N_INSNS (30), /* DLGR */ 197 COSTS_N_INSNS (23), /* DLR */ 198 COSTS_N_INSNS (23), /* DR */ 199 COSTS_N_INSNS (24), /* DSGFR */ 200 COSTS_N_INSNS (24), /* DSGR */ 201}; 202 203extern int reload_completed; 204 205/* Save information from a "cmpxx" operation until the branch or scc is 206 emitted. */ 207rtx s390_compare_op0, s390_compare_op1; 208 209/* Save the result of a compare_and_swap until the branch or scc is 210 emitted. */ 211rtx s390_compare_emitted = NULL_RTX; 212 213/* Structure used to hold the components of a S/390 memory 214 address. A legitimate address on S/390 is of the general 215 form 216 base + index + displacement 217 where any of the components is optional. 218 219 base and index are registers of the class ADDR_REGS, 220 displacement is an unsigned 12-bit immediate constant. */ 221 222struct s390_address 223{ 224 rtx base; 225 rtx indx; 226 rtx disp; 227 bool pointer; 228 bool literal_pool; 229}; 230 231/* Which cpu are we tuning for. */ 232enum processor_type s390_tune = PROCESSOR_max; 233enum processor_flags s390_tune_flags; 234/* Which instruction set architecture to use. */ 235enum processor_type s390_arch; 236enum processor_flags s390_arch_flags; 237 238HOST_WIDE_INT s390_warn_framesize = 0; 239HOST_WIDE_INT s390_stack_size = 0; 240HOST_WIDE_INT s390_stack_guard = 0; 241 242/* The following structure is embedded in the machine 243 specific part of struct function. */ 244 245struct s390_frame_layout GTY (()) 246{ 247 /* Offset within stack frame. */ 248 HOST_WIDE_INT gprs_offset; 249 HOST_WIDE_INT f0_offset; 250 HOST_WIDE_INT f4_offset; 251 HOST_WIDE_INT f8_offset; 252 HOST_WIDE_INT backchain_offset; 253 254 /* Number of first and last gpr where slots in the register 255 save area are reserved for. */ 256 int first_save_gpr_slot; 257 int last_save_gpr_slot; 258 259 /* Number of first and last gpr to be saved, restored. */ 260 int first_save_gpr; 261 int first_restore_gpr; 262 int last_save_gpr; 263 int last_restore_gpr; 264 265 /* Bits standing for floating point registers. Set, if the 266 respective register has to be saved. Starting with reg 16 (f0) 267 at the rightmost bit. 268 Bit 15 - 8 7 6 5 4 3 2 1 0 269 fpr 15 - 8 7 5 3 1 6 4 2 0 270 reg 31 - 24 23 22 21 20 19 18 17 16 */ 271 unsigned int fpr_bitmap; 272 273 /* Number of floating point registers f8-f15 which must be saved. */ 274 int high_fprs; 275 276 /* Set if return address needs to be saved. 277 This flag is set by s390_return_addr_rtx if it could not use 278 the initial value of r14 and therefore depends on r14 saved 279 to the stack. */ 280 bool save_return_addr_p; 281 282 /* Size of stack frame. */ 283 HOST_WIDE_INT frame_size; 284}; 285 286/* Define the structure for the machine field in struct function. */ 287 288struct machine_function GTY(()) 289{ 290 struct s390_frame_layout frame_layout; 291 292 /* Literal pool base register. */ 293 rtx base_reg; 294 295 /* True if we may need to perform branch splitting. */ 296 bool split_branches_pending_p; 297 298 /* True during final stage of literal pool processing. */ 299 bool decomposed_literal_pool_addresses_ok_p; 300 301 /* Some local-dynamic TLS symbol name. */ 302 const char *some_ld_name; 303 304 bool has_landing_pad_p; 305}; 306 307/* Few accessor macros for struct cfun->machine->s390_frame_layout. */ 308 309#define cfun_frame_layout (cfun->machine->frame_layout) 310#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs) 311#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \ 312 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD) 313#define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \ 314 (1 << (BITNUM))) 315#define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \ 316 (1 << (BITNUM)))) 317 318/* Number of GPRs and FPRs used for argument passing. */ 319#define GP_ARG_NUM_REG 5 320#define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2) 321 322/* A couple of shortcuts. */ 323#define CONST_OK_FOR_J(x) \ 324 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J") 325#define CONST_OK_FOR_K(x) \ 326 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K") 327#define CONST_OK_FOR_Os(x) \ 328 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os") 329#define CONST_OK_FOR_Op(x) \ 330 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op") 331#define CONST_OK_FOR_On(x) \ 332 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On") 333 334/* Set the has_landing_pad_p flag in struct machine_function to VALUE. */ 335 336void 337s390_set_has_landing_pad_p (bool value) 338{ 339 cfun->machine->has_landing_pad_p = value; 340} 341 342/* If two condition code modes are compatible, return a condition code 343 mode which is compatible with both. Otherwise, return 344 VOIDmode. */ 345 346static enum machine_mode 347s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) 348{ 349 if (m1 == m2) 350 return m1; 351 352 switch (m1) 353 { 354 case CCZmode: 355 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode 356 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode) 357 return m2; 358 return VOIDmode; 359 360 case CCSmode: 361 case CCUmode: 362 case CCTmode: 363 case CCSRmode: 364 case CCURmode: 365 case CCZ1mode: 366 if (m2 == CCZmode) 367 return m1; 368 369 return VOIDmode; 370 371 default: 372 return VOIDmode; 373 } 374 return VOIDmode; 375} 376 377/* Return true if SET either doesn't set the CC register, or else 378 the source and destination have matching CC modes and that 379 CC mode is at least as constrained as REQ_MODE. */ 380 381static bool 382s390_match_ccmode_set (rtx set, enum machine_mode req_mode) 383{ 384 enum machine_mode set_mode; 385 386 gcc_assert (GET_CODE (set) == SET); 387 388 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set)))) 389 return 1; 390 391 set_mode = GET_MODE (SET_DEST (set)); 392 switch (set_mode) 393 { 394 case CCSmode: 395 case CCSRmode: 396 case CCUmode: 397 case CCURmode: 398 case CCLmode: 399 case CCL1mode: 400 case CCL2mode: 401 case CCL3mode: 402 case CCT1mode: 403 case CCT2mode: 404 case CCT3mode: 405 if (req_mode != set_mode) 406 return 0; 407 break; 408 409 case CCZmode: 410 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode 411 && req_mode != CCSRmode && req_mode != CCURmode) 412 return 0; 413 break; 414 415 case CCAPmode: 416 case CCANmode: 417 if (req_mode != CCAmode) 418 return 0; 419 break; 420 421 default: 422 gcc_unreachable (); 423 } 424 425 return (GET_MODE (SET_SRC (set)) == set_mode); 426} 427 428/* Return true if every SET in INSN that sets the CC register 429 has source and destination with matching CC modes and that 430 CC mode is at least as constrained as REQ_MODE. 431 If REQ_MODE is VOIDmode, always return false. */ 432 433bool 434s390_match_ccmode (rtx insn, enum machine_mode req_mode) 435{ 436 int i; 437 438 /* s390_tm_ccmode returns VOIDmode to indicate failure. */ 439 if (req_mode == VOIDmode) 440 return false; 441 442 if (GET_CODE (PATTERN (insn)) == SET) 443 return s390_match_ccmode_set (PATTERN (insn), req_mode); 444 445 if (GET_CODE (PATTERN (insn)) == PARALLEL) 446 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 447 { 448 rtx set = XVECEXP (PATTERN (insn), 0, i); 449 if (GET_CODE (set) == SET) 450 if (!s390_match_ccmode_set (set, req_mode)) 451 return false; 452 } 453 454 return true; 455} 456 457/* If a test-under-mask instruction can be used to implement 458 (compare (and ... OP1) OP2), return the CC mode required 459 to do that. Otherwise, return VOIDmode. 460 MIXED is true if the instruction can distinguish between 461 CC1 and CC2 for mixed selected bits (TMxx), it is false 462 if the instruction cannot (TM). */ 463 464enum machine_mode 465s390_tm_ccmode (rtx op1, rtx op2, bool mixed) 466{ 467 int bit0, bit1; 468 469 /* ??? Fixme: should work on CONST_DOUBLE as well. */ 470 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT) 471 return VOIDmode; 472 473 /* Selected bits all zero: CC0. 474 e.g.: int a; if ((a & (16 + 128)) == 0) */ 475 if (INTVAL (op2) == 0) 476 return CCTmode; 477 478 /* Selected bits all one: CC3. 479 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */ 480 if (INTVAL (op2) == INTVAL (op1)) 481 return CCT3mode; 482 483 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.: 484 int a; 485 if ((a & (16 + 128)) == 16) -> CCT1 486 if ((a & (16 + 128)) == 128) -> CCT2 */ 487 if (mixed) 488 { 489 bit1 = exact_log2 (INTVAL (op2)); 490 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2)); 491 if (bit0 != -1 && bit1 != -1) 492 return bit0 > bit1 ? CCT1mode : CCT2mode; 493 } 494 495 return VOIDmode; 496} 497 498/* Given a comparison code OP (EQ, NE, etc.) and the operands 499 OP0 and OP1 of a COMPARE, return the mode to be used for the 500 comparison. */ 501 502enum machine_mode 503s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) 504{ 505 switch (code) 506 { 507 case EQ: 508 case NE: 509 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS) 510 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) 511 return CCAPmode; 512 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT 513 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))) 514 return CCAPmode; 515 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS 516 || GET_CODE (op1) == NEG) 517 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) 518 return CCLmode; 519 520 if (GET_CODE (op0) == AND) 521 { 522 /* Check whether we can potentially do it via TM. */ 523 enum machine_mode ccmode; 524 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1); 525 if (ccmode != VOIDmode) 526 { 527 /* Relax CCTmode to CCZmode to allow fall-back to AND 528 if that turns out to be beneficial. */ 529 return ccmode == CCTmode ? CCZmode : ccmode; 530 } 531 } 532 533 if (register_operand (op0, HImode) 534 && GET_CODE (op1) == CONST_INT 535 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535)) 536 return CCT3mode; 537 if (register_operand (op0, QImode) 538 && GET_CODE (op1) == CONST_INT 539 && (INTVAL (op1) == -1 || INTVAL (op1) == 255)) 540 return CCT3mode; 541 542 return CCZmode; 543 544 case LE: 545 case LT: 546 case GE: 547 case GT: 548 /* The only overflow condition of NEG and ABS happens when 549 -INT_MAX is used as parameter, which stays negative. So 550 we have an overflow from a positive value to a negative. 551 Using CCAP mode the resulting cc can be used for comparisons. */ 552 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS) 553 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) 554 return CCAPmode; 555 556 /* If constants are involved in an add instruction it is possible to use 557 the resulting cc for comparisons with zero. Knowing the sign of the 558 constant the overflow behavior gets predictable. e.g.: 559 int a, b; if ((b = a + c) > 0) 560 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */ 561 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT 562 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))) 563 { 564 if (INTVAL (XEXP((op0), 1)) < 0) 565 return CCANmode; 566 else 567 return CCAPmode; 568 } 569 /* Fall through. */ 570 case UNORDERED: 571 case ORDERED: 572 case UNEQ: 573 case UNLE: 574 case UNLT: 575 case UNGE: 576 case UNGT: 577 case LTGT: 578 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) 579 && GET_CODE (op1) != CONST_INT) 580 return CCSRmode; 581 return CCSmode; 582 583 case LTU: 584 case GEU: 585 if (GET_CODE (op0) == PLUS 586 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) 587 return CCL1mode; 588 589 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) 590 && GET_CODE (op1) != CONST_INT) 591 return CCURmode; 592 return CCUmode; 593 594 case LEU: 595 case GTU: 596 if (GET_CODE (op0) == MINUS 597 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) 598 return CCL2mode; 599 600 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) 601 && GET_CODE (op1) != CONST_INT) 602 return CCURmode; 603 return CCUmode; 604 605 default: 606 gcc_unreachable (); 607 } 608} 609 610/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one 611 that we can implement more efficiently. */ 612 613void 614s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1) 615{ 616 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */ 617 if ((*code == EQ || *code == NE) 618 && *op1 == const0_rtx 619 && GET_CODE (*op0) == ZERO_EXTRACT 620 && GET_CODE (XEXP (*op0, 1)) == CONST_INT 621 && GET_CODE (XEXP (*op0, 2)) == CONST_INT 622 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0)))) 623 { 624 rtx inner = XEXP (*op0, 0); 625 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner)); 626 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1)); 627 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2)); 628 629 if (len > 0 && len < modesize 630 && pos >= 0 && pos + len <= modesize 631 && modesize <= HOST_BITS_PER_WIDE_INT) 632 { 633 unsigned HOST_WIDE_INT block; 634 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1; 635 block <<= modesize - pos - len; 636 637 *op0 = gen_rtx_AND (GET_MODE (inner), inner, 638 gen_int_mode (block, GET_MODE (inner))); 639 } 640 } 641 642 /* Narrow AND of memory against immediate to enable TM. */ 643 if ((*code == EQ || *code == NE) 644 && *op1 == const0_rtx 645 && GET_CODE (*op0) == AND 646 && GET_CODE (XEXP (*op0, 1)) == CONST_INT 647 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0)))) 648 { 649 rtx inner = XEXP (*op0, 0); 650 rtx mask = XEXP (*op0, 1); 651 652 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */ 653 if (GET_CODE (inner) == SUBREG 654 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner))) 655 && (GET_MODE_SIZE (GET_MODE (inner)) 656 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) 657 && ((INTVAL (mask) 658 & GET_MODE_MASK (GET_MODE (inner)) 659 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner)))) 660 == 0)) 661 inner = SUBREG_REG (inner); 662 663 /* Do not change volatile MEMs. */ 664 if (MEM_P (inner) && !MEM_VOLATILE_P (inner)) 665 { 666 int part = s390_single_part (XEXP (*op0, 1), 667 GET_MODE (inner), QImode, 0); 668 if (part >= 0) 669 { 670 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode); 671 inner = adjust_address_nv (inner, QImode, part); 672 *op0 = gen_rtx_AND (QImode, inner, mask); 673 } 674 } 675 } 676 677 /* Narrow comparisons against 0xffff to HImode if possible. */ 678 if ((*code == EQ || *code == NE) 679 && GET_CODE (*op1) == CONST_INT 680 && INTVAL (*op1) == 0xffff 681 && SCALAR_INT_MODE_P (GET_MODE (*op0)) 682 && (nonzero_bits (*op0, GET_MODE (*op0)) 683 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) 684 { 685 *op0 = gen_lowpart (HImode, *op0); 686 *op1 = constm1_rtx; 687 } 688 689 690 /* Remove redundant UNSPEC_CMPINT conversions if possible. */ 691 if (GET_CODE (*op0) == UNSPEC 692 && XINT (*op0, 1) == UNSPEC_CMPINT 693 && XVECLEN (*op0, 0) == 1 694 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode 695 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG 696 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM 697 && *op1 == const0_rtx) 698 { 699 enum rtx_code new_code = UNKNOWN; 700 switch (*code) 701 { 702 case EQ: new_code = EQ; break; 703 case NE: new_code = NE; break; 704 case LT: new_code = GTU; break; 705 case GT: new_code = LTU; break; 706 case LE: new_code = GEU; break; 707 case GE: new_code = LEU; break; 708 default: break; 709 } 710 711 if (new_code != UNKNOWN) 712 { 713 *op0 = XVECEXP (*op0, 0, 0); 714 *code = new_code; 715 } 716 } 717 718 /* Simplify cascaded EQ, NE with const0_rtx. */ 719 if ((*code == NE || *code == EQ) 720 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE) 721 && GET_MODE (*op0) == SImode 722 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode 723 && REG_P (XEXP (*op0, 0)) 724 && XEXP (*op0, 1) == const0_rtx 725 && *op1 == const0_rtx) 726 { 727 if ((*code == EQ && GET_CODE (*op0) == NE) 728 || (*code == NE && GET_CODE (*op0) == EQ)) 729 *code = EQ; 730 else 731 *code = NE; 732 *op0 = XEXP (*op0, 0); 733 } 734 735 /* Prefer register over memory as first operand. */ 736 if (MEM_P (*op0) && REG_P (*op1)) 737 { 738 rtx tem = *op0; *op0 = *op1; *op1 = tem; 739 *code = swap_condition (*code); 740 } 741} 742 743/* Emit a compare instruction suitable to implement the comparison 744 OP0 CODE OP1. Return the correct condition RTL to be placed in 745 the IF_THEN_ELSE of the conditional branch testing the result. */ 746 747rtx 748s390_emit_compare (enum rtx_code code, rtx op0, rtx op1) 749{ 750 enum machine_mode mode = s390_select_ccmode (code, op0, op1); 751 rtx ret = NULL_RTX; 752 753 /* Do not output a redundant compare instruction if a compare_and_swap 754 pattern already computed the result and the machine modes are compatible. */ 755 if (s390_compare_emitted 756 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode) 757 == GET_MODE (s390_compare_emitted))) 758 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx); 759 else 760 { 761 rtx cc = gen_rtx_REG (mode, CC_REGNUM); 762 763 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1))); 764 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx); 765 } 766 s390_compare_emitted = NULL_RTX; 767 return ret; 768} 769 770/* Emit a SImode compare and swap instruction setting MEM to NEW if OLD 771 matches CMP. 772 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the 773 conditional branch testing the result. */ 774 775static rtx 776s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new) 777{ 778 rtx ret; 779 780 emit_insn (gen_sync_compare_and_swap_ccsi (old, mem, cmp, new)); 781 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx); 782 783 s390_compare_emitted = NULL_RTX; 784 785 return ret; 786} 787 788/* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an 789 unconditional jump, else a conditional jump under condition COND. */ 790 791void 792s390_emit_jump (rtx target, rtx cond) 793{ 794 rtx insn; 795 796 target = gen_rtx_LABEL_REF (VOIDmode, target); 797 if (cond) 798 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx); 799 800 insn = gen_rtx_SET (VOIDmode, pc_rtx, target); 801 emit_jump_insn (insn); 802} 803 804/* Return branch condition mask to implement a branch 805 specified by CODE. Return -1 for invalid comparisons. */ 806 807int 808s390_branch_condition_mask (rtx code) 809{ 810 const int CC0 = 1 << 3; 811 const int CC1 = 1 << 2; 812 const int CC2 = 1 << 1; 813 const int CC3 = 1 << 0; 814 815 gcc_assert (GET_CODE (XEXP (code, 0)) == REG); 816 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM); 817 gcc_assert (XEXP (code, 1) == const0_rtx); 818 819 switch (GET_MODE (XEXP (code, 0))) 820 { 821 case CCZmode: 822 case CCZ1mode: 823 switch (GET_CODE (code)) 824 { 825 case EQ: return CC0; 826 case NE: return CC1 | CC2 | CC3; 827 default: return -1; 828 } 829 break; 830 831 case CCT1mode: 832 switch (GET_CODE (code)) 833 { 834 case EQ: return CC1; 835 case NE: return CC0 | CC2 | CC3; 836 default: return -1; 837 } 838 break; 839 840 case CCT2mode: 841 switch (GET_CODE (code)) 842 { 843 case EQ: return CC2; 844 case NE: return CC0 | CC1 | CC3; 845 default: return -1; 846 } 847 break; 848 849 case CCT3mode: 850 switch (GET_CODE (code)) 851 { 852 case EQ: return CC3; 853 case NE: return CC0 | CC1 | CC2; 854 default: return -1; 855 } 856 break; 857 858 case CCLmode: 859 switch (GET_CODE (code)) 860 { 861 case EQ: return CC0 | CC2; 862 case NE: return CC1 | CC3; 863 default: return -1; 864 } 865 break; 866 867 case CCL1mode: 868 switch (GET_CODE (code)) 869 { 870 case LTU: return CC2 | CC3; /* carry */ 871 case GEU: return CC0 | CC1; /* no carry */ 872 default: return -1; 873 } 874 break; 875 876 case CCL2mode: 877 switch (GET_CODE (code)) 878 { 879 case GTU: return CC0 | CC1; /* borrow */ 880 case LEU: return CC2 | CC3; /* no borrow */ 881 default: return -1; 882 } 883 break; 884 885 case CCL3mode: 886 switch (GET_CODE (code)) 887 { 888 case EQ: return CC0 | CC2; 889 case NE: return CC1 | CC3; 890 case LTU: return CC1; 891 case GTU: return CC3; 892 case LEU: return CC1 | CC2; 893 case GEU: return CC2 | CC3; 894 default: return -1; 895 } 896 897 case CCUmode: 898 switch (GET_CODE (code)) 899 { 900 case EQ: return CC0; 901 case NE: return CC1 | CC2 | CC3; 902 case LTU: return CC1; 903 case GTU: return CC2; 904 case LEU: return CC0 | CC1; 905 case GEU: return CC0 | CC2; 906 default: return -1; 907 } 908 break; 909 910 case CCURmode: 911 switch (GET_CODE (code)) 912 { 913 case EQ: return CC0; 914 case NE: return CC2 | CC1 | CC3; 915 case LTU: return CC2; 916 case GTU: return CC1; 917 case LEU: return CC0 | CC2; 918 case GEU: return CC0 | CC1; 919 default: return -1; 920 } 921 break; 922 923 case CCAPmode: 924 switch (GET_CODE (code)) 925 { 926 case EQ: return CC0; 927 case NE: return CC1 | CC2 | CC3; 928 case LT: return CC1 | CC3; 929 case GT: return CC2; 930 case LE: return CC0 | CC1 | CC3; 931 case GE: return CC0 | CC2; 932 default: return -1; 933 } 934 break; 935 936 case CCANmode: 937 switch (GET_CODE (code)) 938 { 939 case EQ: return CC0; 940 case NE: return CC1 | CC2 | CC3; 941 case LT: return CC1; 942 case GT: return CC2 | CC3; 943 case LE: return CC0 | CC1; 944 case GE: return CC0 | CC2 | CC3; 945 default: return -1; 946 } 947 break; 948 949 case CCSmode: 950 switch (GET_CODE (code)) 951 { 952 case EQ: return CC0; 953 case NE: return CC1 | CC2 | CC3; 954 case LT: return CC1; 955 case GT: return CC2; 956 case LE: return CC0 | CC1; 957 case GE: return CC0 | CC2; 958 case UNORDERED: return CC3; 959 case ORDERED: return CC0 | CC1 | CC2; 960 case UNEQ: return CC0 | CC3; 961 case UNLT: return CC1 | CC3; 962 case UNGT: return CC2 | CC3; 963 case UNLE: return CC0 | CC1 | CC3; 964 case UNGE: return CC0 | CC2 | CC3; 965 case LTGT: return CC1 | CC2; 966 default: return -1; 967 } 968 break; 969 970 case CCSRmode: 971 switch (GET_CODE (code)) 972 { 973 case EQ: return CC0; 974 case NE: return CC2 | CC1 | CC3; 975 case LT: return CC2; 976 case GT: return CC1; 977 case LE: return CC0 | CC2; 978 case GE: return CC0 | CC1; 979 case UNORDERED: return CC3; 980 case ORDERED: return CC0 | CC2 | CC1; 981 case UNEQ: return CC0 | CC3; 982 case UNLT: return CC2 | CC3; 983 case UNGT: return CC1 | CC3; 984 case UNLE: return CC0 | CC2 | CC3; 985 case UNGE: return CC0 | CC1 | CC3; 986 case LTGT: return CC2 | CC1; 987 default: return -1; 988 } 989 break; 990 991 default: 992 return -1; 993 } 994} 995 996/* If INV is false, return assembler mnemonic string to implement 997 a branch specified by CODE. If INV is true, return mnemonic 998 for the corresponding inverted branch. */ 999 1000static const char * 1001s390_branch_condition_mnemonic (rtx code, int inv) 1002{ 1003 static const char *const mnemonic[16] = 1004 { 1005 NULL, "o", "h", "nle", 1006 "l", "nhe", "lh", "ne", 1007 "e", "nlh", "he", "nl", 1008 "le", "nh", "no", NULL 1009 }; 1010 1011 int mask = s390_branch_condition_mask (code); 1012 gcc_assert (mask >= 0); 1013 1014 if (inv) 1015 mask ^= 15; 1016 1017 gcc_assert (mask >= 1 && mask <= 14); 1018 1019 return mnemonic[mask]; 1020} 1021 1022/* Return the part of op which has a value different from def. 1023 The size of the part is determined by mode. 1024 Use this function only if you already know that op really 1025 contains such a part. */ 1026 1027unsigned HOST_WIDE_INT 1028s390_extract_part (rtx op, enum machine_mode mode, int def) 1029{ 1030 unsigned HOST_WIDE_INT value = 0; 1031 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode); 1032 int part_bits = GET_MODE_BITSIZE (mode); 1033 unsigned HOST_WIDE_INT part_mask 1034 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1; 1035 int i; 1036 1037 for (i = 0; i < max_parts; i++) 1038 { 1039 if (i == 0) 1040 value = (unsigned HOST_WIDE_INT) INTVAL (op); 1041 else 1042 value >>= part_bits; 1043 1044 if ((value & part_mask) != (def & part_mask)) 1045 return value & part_mask; 1046 } 1047 1048 gcc_unreachable (); 1049} 1050 1051/* If OP is an integer constant of mode MODE with exactly one 1052 part of mode PART_MODE unequal to DEF, return the number of that 1053 part. Otherwise, return -1. */ 1054 1055int 1056s390_single_part (rtx op, 1057 enum machine_mode mode, 1058 enum machine_mode part_mode, 1059 int def) 1060{ 1061 unsigned HOST_WIDE_INT value = 0; 1062 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode); 1063 unsigned HOST_WIDE_INT part_mask 1064 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1; 1065 int i, part = -1; 1066 1067 if (GET_CODE (op) != CONST_INT) 1068 return -1; 1069 1070 for (i = 0; i < n_parts; i++) 1071 { 1072 if (i == 0) 1073 value = (unsigned HOST_WIDE_INT) INTVAL (op); 1074 else 1075 value >>= GET_MODE_BITSIZE (part_mode); 1076 1077 if ((value & part_mask) != (def & part_mask)) 1078 { 1079 if (part != -1) 1080 return -1; 1081 else 1082 part = i; 1083 } 1084 } 1085 return part == -1 ? -1 : n_parts - 1 - part; 1086} 1087 1088/* Check whether we can (and want to) split a double-word 1089 move in mode MODE from SRC to DST into two single-word 1090 moves, moving the subword FIRST_SUBWORD first. */ 1091 1092bool 1093s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword) 1094{ 1095 /* Floating point registers cannot be split. */ 1096 if (FP_REG_P (src) || FP_REG_P (dst)) 1097 return false; 1098 1099 /* We don't need to split if operands are directly accessible. */ 1100 if (s_operand (src, mode) || s_operand (dst, mode)) 1101 return false; 1102 1103 /* Non-offsettable memory references cannot be split. */ 1104 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src)) 1105 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst))) 1106 return false; 1107 1108 /* Moving the first subword must not clobber a register 1109 needed to move the second subword. */ 1110 if (register_operand (dst, mode)) 1111 { 1112 rtx subreg = operand_subword (dst, first_subword, 0, mode); 1113 if (reg_overlap_mentioned_p (subreg, src)) 1114 return false; 1115 } 1116 1117 return true; 1118} 1119 1120/* Return true if it can be proven that [MEM1, MEM1 + SIZE] 1121 and [MEM2, MEM2 + SIZE] do overlap and false 1122 otherwise. */ 1123 1124bool 1125s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size) 1126{ 1127 rtx addr1, addr2, addr_delta; 1128 HOST_WIDE_INT delta; 1129 1130 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM) 1131 return true; 1132 1133 if (size == 0) 1134 return false; 1135 1136 addr1 = XEXP (mem1, 0); 1137 addr2 = XEXP (mem2, 0); 1138 1139 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1); 1140 1141 /* This overlapping check is used by peepholes merging memory block operations. 1142 Overlapping operations would otherwise be recognized by the S/390 hardware 1143 and would fall back to a slower implementation. Allowing overlapping 1144 operations would lead to slow code but not to wrong code. Therefore we are 1145 somewhat optimistic if we cannot prove that the memory blocks are 1146 overlapping. 1147 That's why we return false here although this may accept operations on 1148 overlapping memory areas. */ 1149 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT) 1150 return false; 1151 1152 delta = INTVAL (addr_delta); 1153 1154 if (delta == 0 1155 || (delta > 0 && delta < size) 1156 || (delta < 0 && -delta < size)) 1157 return true; 1158 1159 return false; 1160} 1161 1162/* Check whether the address of memory reference MEM2 equals exactly 1163 the address of memory reference MEM1 plus DELTA. Return true if 1164 we can prove this to be the case, false otherwise. */ 1165 1166bool 1167s390_offset_p (rtx mem1, rtx mem2, rtx delta) 1168{ 1169 rtx addr1, addr2, addr_delta; 1170 1171 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM) 1172 return false; 1173 1174 addr1 = XEXP (mem1, 0); 1175 addr2 = XEXP (mem2, 0); 1176 1177 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1); 1178 if (!addr_delta || !rtx_equal_p (addr_delta, delta)) 1179 return false; 1180 1181 return true; 1182} 1183 1184/* Expand logical operator CODE in mode MODE with operands OPERANDS. */ 1185 1186void 1187s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode, 1188 rtx *operands) 1189{ 1190 enum machine_mode wmode = mode; 1191 rtx dst = operands[0]; 1192 rtx src1 = operands[1]; 1193 rtx src2 = operands[2]; 1194 rtx op, clob, tem; 1195 1196 /* If we cannot handle the operation directly, use a temp register. */ 1197 if (!s390_logical_operator_ok_p (operands)) 1198 dst = gen_reg_rtx (mode); 1199 1200 /* QImode and HImode patterns make sense only if we have a destination 1201 in memory. Otherwise perform the operation in SImode. */ 1202 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM) 1203 wmode = SImode; 1204 1205 /* Widen operands if required. */ 1206 if (mode != wmode) 1207 { 1208 if (GET_CODE (dst) == SUBREG 1209 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0) 1210 dst = tem; 1211 else if (REG_P (dst)) 1212 dst = gen_rtx_SUBREG (wmode, dst, 0); 1213 else 1214 dst = gen_reg_rtx (wmode); 1215 1216 if (GET_CODE (src1) == SUBREG 1217 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0) 1218 src1 = tem; 1219 else if (GET_MODE (src1) != VOIDmode) 1220 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0); 1221 1222 if (GET_CODE (src2) == SUBREG 1223 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0) 1224 src2 = tem; 1225 else if (GET_MODE (src2) != VOIDmode) 1226 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0); 1227 } 1228 1229 /* Emit the instruction. */ 1230 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2)); 1231 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); 1232 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); 1233 1234 /* Fix up the destination if needed. */ 1235 if (dst != operands[0]) 1236 emit_move_insn (operands[0], gen_lowpart (mode, dst)); 1237} 1238 1239/* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */ 1240 1241bool 1242s390_logical_operator_ok_p (rtx *operands) 1243{ 1244 /* If the destination operand is in memory, it needs to coincide 1245 with one of the source operands. After reload, it has to be 1246 the first source operand. */ 1247 if (GET_CODE (operands[0]) == MEM) 1248 return rtx_equal_p (operands[0], operands[1]) 1249 || (!reload_completed && rtx_equal_p (operands[0], operands[2])); 1250 1251 return true; 1252} 1253 1254/* Narrow logical operation CODE of memory operand MEMOP with immediate 1255 operand IMMOP to switch from SS to SI type instructions. */ 1256 1257void 1258s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop) 1259{ 1260 int def = code == AND ? -1 : 0; 1261 HOST_WIDE_INT mask; 1262 int part; 1263 1264 gcc_assert (GET_CODE (*memop) == MEM); 1265 gcc_assert (!MEM_VOLATILE_P (*memop)); 1266 1267 mask = s390_extract_part (*immop, QImode, def); 1268 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def); 1269 gcc_assert (part >= 0); 1270 1271 *memop = adjust_address (*memop, QImode, part); 1272 *immop = gen_int_mode (mask, QImode); 1273} 1274 1275 1276/* How to allocate a 'struct machine_function'. */ 1277 1278static struct machine_function * 1279s390_init_machine_status (void) 1280{ 1281 return ggc_alloc_cleared (sizeof (struct machine_function)); 1282} 1283 1284/* Change optimizations to be performed, depending on the 1285 optimization level. 1286 1287 LEVEL is the optimization level specified; 2 if `-O2' is 1288 specified, 1 if `-O' is specified, and 0 if neither is specified. 1289 1290 SIZE is nonzero if `-Os' is specified and zero otherwise. */ 1291 1292void 1293optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) 1294{ 1295 /* ??? There are apparently still problems with -fcaller-saves. */ 1296 flag_caller_saves = 0; 1297 1298 /* By default, always emit DWARF-2 unwind info. This allows debugging 1299 without maintaining a stack frame back-chain. */ 1300 flag_asynchronous_unwind_tables = 1; 1301 1302 /* Use MVCLE instructions to decrease code size if requested. */ 1303 if (size != 0) 1304 target_flags |= MASK_MVCLE; 1305} 1306 1307/* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS 1308 to the associated processor_type and processor_flags if so. */ 1309 1310static bool 1311s390_handle_arch_option (const char *arg, 1312 enum processor_type *type, 1313 enum processor_flags *flags) 1314{ 1315 static struct pta 1316 { 1317 const char *const name; /* processor name or nickname. */ 1318 const enum processor_type processor; 1319 const enum processor_flags flags; 1320 } 1321 const processor_alias_table[] = 1322 { 1323 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT}, 1324 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT}, 1325 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH}, 1326 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH 1327 | PF_LONG_DISPLACEMENT}, 1328 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH 1329 | PF_LONG_DISPLACEMENT | PF_EXTIMM}, 1330 }; 1331 size_t i; 1332 1333 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++) 1334 if (strcmp (arg, processor_alias_table[i].name) == 0) 1335 { 1336 *type = processor_alias_table[i].processor; 1337 *flags = processor_alias_table[i].flags; 1338 return true; 1339 } 1340 return false; 1341} 1342 1343/* Implement TARGET_HANDLE_OPTION. */ 1344 1345static bool 1346s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) 1347{ 1348 switch (code) 1349 { 1350 case OPT_march_: 1351 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags); 1352 1353 case OPT_mstack_guard_: 1354 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1) 1355 return false; 1356 if (exact_log2 (s390_stack_guard) == -1) 1357 error ("stack guard value must be an exact power of 2"); 1358 return true; 1359 1360 case OPT_mstack_size_: 1361 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1) 1362 return false; 1363 if (exact_log2 (s390_stack_size) == -1) 1364 error ("stack size must be an exact power of 2"); 1365 return true; 1366 1367 case OPT_mtune_: 1368 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags); 1369 1370 case OPT_mwarn_framesize_: 1371 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1; 1372 1373 default: 1374 return true; 1375 } 1376} 1377 1378void 1379override_options (void) 1380{ 1381 /* Set up function hooks. */ 1382 init_machine_status = s390_init_machine_status; 1383 1384 /* Architecture mode defaults according to ABI. */ 1385 if (!(target_flags_explicit & MASK_ZARCH)) 1386 { 1387 if (TARGET_64BIT) 1388 target_flags |= MASK_ZARCH; 1389 else 1390 target_flags &= ~MASK_ZARCH; 1391 } 1392 1393 /* Determine processor architectural level. */ 1394 if (!s390_arch_string) 1395 { 1396 s390_arch_string = TARGET_ZARCH? "z900" : "g5"; 1397 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags); 1398 } 1399 1400 /* Determine processor to tune for. */ 1401 if (s390_tune == PROCESSOR_max) 1402 { 1403 s390_tune = s390_arch; 1404 s390_tune_flags = s390_arch_flags; 1405 } 1406 1407 /* Sanity checks. */ 1408 if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH)) 1409 error ("z/Architecture mode not supported on %s", s390_arch_string); 1410 if (TARGET_64BIT && !TARGET_ZARCH) 1411 error ("64-bit ABI not supported in ESA/390 mode"); 1412 1413 /* Set processor cost function. */ 1414 if (s390_tune == PROCESSOR_2094_Z9_109) 1415 s390_cost = &z9_109_cost; 1416 else if (s390_tune == PROCESSOR_2084_Z990) 1417 s390_cost = &z990_cost; 1418 else 1419 s390_cost = &z900_cost; 1420 1421 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT) 1422 error ("-mbackchain -mpacked-stack -mhard-float are not supported " 1423 "in combination"); 1424 1425 if (s390_stack_size) 1426 { 1427 if (!s390_stack_guard) 1428 error ("-mstack-size implies use of -mstack-guard"); 1429 else if (s390_stack_guard >= s390_stack_size) 1430 error ("stack size must be greater than the stack guard value"); 1431 else if (s390_stack_size > 1 << 16) 1432 error ("stack size must not be greater than 64k"); 1433 } 1434 else if (s390_stack_guard) 1435 error ("-mstack-guard implies use of -mstack-size"); 1436} 1437 1438/* Map for smallest class containing reg regno. */ 1439 1440const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = 1441{ GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, 1442 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, 1443 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, 1444 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, 1445 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 1446 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 1447 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 1448 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 1449 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS, 1450 ACCESS_REGS, ACCESS_REGS 1451}; 1452 1453/* Return attribute type of insn. */ 1454 1455static enum attr_type 1456s390_safe_attr_type (rtx insn) 1457{ 1458 if (recog_memoized (insn) >= 0) 1459 return get_attr_type (insn); 1460 else 1461 return TYPE_NONE; 1462} 1463 1464/* Return true if DISP is a valid short displacement. */ 1465 1466static bool 1467s390_short_displacement (rtx disp) 1468{ 1469 /* No displacement is OK. */ 1470 if (!disp) 1471 return true; 1472 1473 /* Integer displacement in range. */ 1474 if (GET_CODE (disp) == CONST_INT) 1475 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096; 1476 1477 /* GOT offset is not OK, the GOT can be large. */ 1478 if (GET_CODE (disp) == CONST 1479 && GET_CODE (XEXP (disp, 0)) == UNSPEC 1480 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT 1481 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF)) 1482 return false; 1483 1484 /* All other symbolic constants are literal pool references, 1485 which are OK as the literal pool must be small. */ 1486 if (GET_CODE (disp) == CONST) 1487 return true; 1488 1489 return false; 1490} 1491 1492/* Decompose a RTL expression ADDR for a memory address into 1493 its components, returned in OUT. 1494 1495 Returns false if ADDR is not a valid memory address, true 1496 otherwise. If OUT is NULL, don't return the components, 1497 but check for validity only. 1498 1499 Note: Only addresses in canonical form are recognized. 1500 LEGITIMIZE_ADDRESS should convert non-canonical forms to the 1501 canonical form so that they will be recognized. */ 1502 1503static int 1504s390_decompose_address (rtx addr, struct s390_address *out) 1505{ 1506 HOST_WIDE_INT offset = 0; 1507 rtx base = NULL_RTX; 1508 rtx indx = NULL_RTX; 1509 rtx disp = NULL_RTX; 1510 rtx orig_disp; 1511 bool pointer = false; 1512 bool base_ptr = false; 1513 bool indx_ptr = false; 1514 bool literal_pool = false; 1515 1516 /* We may need to substitute the literal pool base register into the address 1517 below. However, at this point we do not know which register is going to 1518 be used as base, so we substitute the arg pointer register. This is going 1519 to be treated as holding a pointer below -- it shouldn't be used for any 1520 other purpose. */ 1521 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM); 1522 1523 /* Decompose address into base + index + displacement. */ 1524 1525 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC) 1526 base = addr; 1527 1528 else if (GET_CODE (addr) == PLUS) 1529 { 1530 rtx op0 = XEXP (addr, 0); 1531 rtx op1 = XEXP (addr, 1); 1532 enum rtx_code code0 = GET_CODE (op0); 1533 enum rtx_code code1 = GET_CODE (op1); 1534 1535 if (code0 == REG || code0 == UNSPEC) 1536 { 1537 if (code1 == REG || code1 == UNSPEC) 1538 { 1539 indx = op0; /* index + base */ 1540 base = op1; 1541 } 1542 1543 else 1544 { 1545 base = op0; /* base + displacement */ 1546 disp = op1; 1547 } 1548 } 1549 1550 else if (code0 == PLUS) 1551 { 1552 indx = XEXP (op0, 0); /* index + base + disp */ 1553 base = XEXP (op0, 1); 1554 disp = op1; 1555 } 1556 1557 else 1558 { 1559 return false; 1560 } 1561 } 1562 1563 else 1564 disp = addr; /* displacement */ 1565 1566 /* Extract integer part of displacement. */ 1567 orig_disp = disp; 1568 if (disp) 1569 { 1570 if (GET_CODE (disp) == CONST_INT) 1571 { 1572 offset = INTVAL (disp); 1573 disp = NULL_RTX; 1574 } 1575 else if (GET_CODE (disp) == CONST 1576 && GET_CODE (XEXP (disp, 0)) == PLUS 1577 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT) 1578 { 1579 offset = INTVAL (XEXP (XEXP (disp, 0), 1)); 1580 disp = XEXP (XEXP (disp, 0), 0); 1581 } 1582 } 1583 1584 /* Strip off CONST here to avoid special case tests later. */ 1585 if (disp && GET_CODE (disp) == CONST) 1586 disp = XEXP (disp, 0); 1587 1588 /* We can convert literal pool addresses to 1589 displacements by basing them off the base register. */ 1590 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp)) 1591 { 1592 /* Either base or index must be free to hold the base register. */ 1593 if (!base) 1594 base = fake_pool_base, literal_pool = true; 1595 else if (!indx) 1596 indx = fake_pool_base, literal_pool = true; 1597 else 1598 return false; 1599 1600 /* Mark up the displacement. */ 1601 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp), 1602 UNSPEC_LTREL_OFFSET); 1603 } 1604 1605 /* Validate base register. */ 1606 if (base) 1607 { 1608 if (GET_CODE (base) == UNSPEC) 1609 switch (XINT (base, 1)) 1610 { 1611 case UNSPEC_LTREF: 1612 if (!disp) 1613 disp = gen_rtx_UNSPEC (Pmode, 1614 gen_rtvec (1, XVECEXP (base, 0, 0)), 1615 UNSPEC_LTREL_OFFSET); 1616 else 1617 return false; 1618 1619 base = XVECEXP (base, 0, 1); 1620 break; 1621 1622 case UNSPEC_LTREL_BASE: 1623 if (XVECLEN (base, 0) == 1) 1624 base = fake_pool_base, literal_pool = true; 1625 else 1626 base = XVECEXP (base, 0, 1); 1627 break; 1628 1629 default: 1630 return false; 1631 } 1632 1633 if (GET_CODE (base) != REG || GET_MODE (base) != Pmode) 1634 return false; 1635 1636 if (REGNO (base) == STACK_POINTER_REGNUM 1637 || REGNO (base) == FRAME_POINTER_REGNUM 1638 || ((reload_completed || reload_in_progress) 1639 && frame_pointer_needed 1640 && REGNO (base) == HARD_FRAME_POINTER_REGNUM) 1641 || REGNO (base) == ARG_POINTER_REGNUM 1642 || (flag_pic 1643 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM)) 1644 pointer = base_ptr = true; 1645 1646 if ((reload_completed || reload_in_progress) 1647 && base == cfun->machine->base_reg) 1648 pointer = base_ptr = literal_pool = true; 1649 } 1650 1651 /* Validate index register. */ 1652 if (indx) 1653 { 1654 if (GET_CODE (indx) == UNSPEC) 1655 switch (XINT (indx, 1)) 1656 { 1657 case UNSPEC_LTREF: 1658 if (!disp) 1659 disp = gen_rtx_UNSPEC (Pmode, 1660 gen_rtvec (1, XVECEXP (indx, 0, 0)), 1661 UNSPEC_LTREL_OFFSET); 1662 else 1663 return false; 1664 1665 indx = XVECEXP (indx, 0, 1); 1666 break; 1667 1668 case UNSPEC_LTREL_BASE: 1669 if (XVECLEN (indx, 0) == 1) 1670 indx = fake_pool_base, literal_pool = true; 1671 else 1672 indx = XVECEXP (indx, 0, 1); 1673 break; 1674 1675 default: 1676 return false; 1677 } 1678 1679 if (GET_CODE (indx) != REG || GET_MODE (indx) != Pmode) 1680 return false; 1681 1682 if (REGNO (indx) == STACK_POINTER_REGNUM 1683 || REGNO (indx) == FRAME_POINTER_REGNUM 1684 || ((reload_completed || reload_in_progress) 1685 && frame_pointer_needed 1686 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM) 1687 || REGNO (indx) == ARG_POINTER_REGNUM 1688 || (flag_pic 1689 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM)) 1690 pointer = indx_ptr = true; 1691 1692 if ((reload_completed || reload_in_progress) 1693 && indx == cfun->machine->base_reg) 1694 pointer = indx_ptr = literal_pool = true; 1695 } 1696 1697 /* Prefer to use pointer as base, not index. */ 1698 if (base && indx && !base_ptr 1699 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx)))) 1700 { 1701 rtx tmp = base; 1702 base = indx; 1703 indx = tmp; 1704 } 1705 1706 /* Validate displacement. */ 1707 if (!disp) 1708 { 1709 /* If virtual registers are involved, the displacement will change later 1710 anyway as the virtual registers get eliminated. This could make a 1711 valid displacement invalid, but it is more likely to make an invalid 1712 displacement valid, because we sometimes access the register save area 1713 via negative offsets to one of those registers. 1714 Thus we don't check the displacement for validity here. If after 1715 elimination the displacement turns out to be invalid after all, 1716 this is fixed up by reload in any case. */ 1717 if (base != arg_pointer_rtx 1718 && indx != arg_pointer_rtx 1719 && base != return_address_pointer_rtx 1720 && indx != return_address_pointer_rtx 1721 && base != frame_pointer_rtx 1722 && indx != frame_pointer_rtx 1723 && base != virtual_stack_vars_rtx 1724 && indx != virtual_stack_vars_rtx) 1725 if (!DISP_IN_RANGE (offset)) 1726 return false; 1727 } 1728 else 1729 { 1730 /* All the special cases are pointers. */ 1731 pointer = true; 1732 1733 /* In the small-PIC case, the linker converts @GOT 1734 and @GOTNTPOFF offsets to possible displacements. */ 1735 if (GET_CODE (disp) == UNSPEC 1736 && (XINT (disp, 1) == UNSPEC_GOT 1737 || XINT (disp, 1) == UNSPEC_GOTNTPOFF) 1738 && offset == 0 1739 && flag_pic == 1) 1740 { 1741 ; 1742 } 1743 1744 /* Accept chunkified literal pool symbol references. */ 1745 else if (cfun && cfun->machine 1746 && cfun->machine->decomposed_literal_pool_addresses_ok_p 1747 && GET_CODE (disp) == MINUS 1748 && GET_CODE (XEXP (disp, 0)) == LABEL_REF 1749 && GET_CODE (XEXP (disp, 1)) == LABEL_REF) 1750 { 1751 ; 1752 } 1753 1754 /* Accept literal pool references. */ 1755 else if (GET_CODE (disp) == UNSPEC 1756 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET) 1757 { 1758 orig_disp = gen_rtx_CONST (Pmode, disp); 1759 if (offset) 1760 { 1761 /* If we have an offset, make sure it does not 1762 exceed the size of the constant pool entry. */ 1763 rtx sym = XVECEXP (disp, 0, 0); 1764 if (offset >= GET_MODE_SIZE (get_pool_mode (sym))) 1765 return false; 1766 1767 orig_disp = plus_constant (orig_disp, offset); 1768 } 1769 } 1770 1771 else 1772 return false; 1773 } 1774 1775 if (!base && !indx) 1776 pointer = true; 1777 1778 if (out) 1779 { 1780 out->base = base; 1781 out->indx = indx; 1782 out->disp = orig_disp; 1783 out->pointer = pointer; 1784 out->literal_pool = literal_pool; 1785 } 1786 1787 return true; 1788} 1789 1790/* Decompose a RTL expression OP for a shift count into its components, 1791 and return the base register in BASE and the offset in OFFSET. 1792 1793 Return true if OP is a valid shift count, false if not. */ 1794 1795bool 1796s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset) 1797{ 1798 HOST_WIDE_INT off = 0; 1799 1800 /* We can have an integer constant, an address register, 1801 or a sum of the two. */ 1802 if (GET_CODE (op) == CONST_INT) 1803 { 1804 off = INTVAL (op); 1805 op = NULL_RTX; 1806 } 1807 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT) 1808 { 1809 off = INTVAL (XEXP (op, 1)); 1810 op = XEXP (op, 0); 1811 } 1812 while (op && GET_CODE (op) == SUBREG) 1813 op = SUBREG_REG (op); 1814 1815 if (op && GET_CODE (op) != REG) 1816 return false; 1817 1818 if (offset) 1819 *offset = off; 1820 if (base) 1821 *base = op; 1822 1823 return true; 1824} 1825 1826 1827/* Return true if CODE is a valid address without index. */ 1828 1829bool 1830s390_legitimate_address_without_index_p (rtx op) 1831{ 1832 struct s390_address addr; 1833 1834 if (!s390_decompose_address (XEXP (op, 0), &addr)) 1835 return false; 1836 if (addr.indx) 1837 return false; 1838 1839 return true; 1840} 1841 1842/* Return 1 if OP is a valid operand for a C constraint, 0 else. */ 1843 1844int 1845s390_extra_constraint_str (rtx op, int c, const char * str) 1846{ 1847 struct s390_address addr; 1848 1849 gcc_assert (c == str[0]); 1850 1851 /* Check for offsettable variants of memory constraints. */ 1852 if (c == 'A') 1853 { 1854 /* Only accept non-volatile MEMs. */ 1855 if (!MEM_P (op) || MEM_VOLATILE_P (op)) 1856 return 0; 1857 1858 if ((reload_completed || reload_in_progress) 1859 ? !offsettable_memref_p (op) 1860 : !offsettable_nonstrict_memref_p (op)) 1861 return 0; 1862 1863 c = str[1]; 1864 } 1865 1866 /* Check for non-literal-pool variants of memory constraints. */ 1867 else if (c == 'B') 1868 { 1869 if (GET_CODE (op) != MEM) 1870 return 0; 1871 if (!s390_decompose_address (XEXP (op, 0), &addr)) 1872 return 0; 1873 if (addr.literal_pool) 1874 return 0; 1875 1876 c = str[1]; 1877 } 1878 1879 switch (c) 1880 { 1881 case 'Q': 1882 if (GET_CODE (op) != MEM) 1883 return 0; 1884 if (!s390_decompose_address (XEXP (op, 0), &addr)) 1885 return 0; 1886 if (addr.indx) 1887 return 0; 1888 1889 if (TARGET_LONG_DISPLACEMENT) 1890 { 1891 if (!s390_short_displacement (addr.disp)) 1892 return 0; 1893 } 1894 break; 1895 1896 case 'R': 1897 if (GET_CODE (op) != MEM) 1898 return 0; 1899 1900 if (TARGET_LONG_DISPLACEMENT) 1901 { 1902 if (!s390_decompose_address (XEXP (op, 0), &addr)) 1903 return 0; 1904 if (!s390_short_displacement (addr.disp)) 1905 return 0; 1906 } 1907 break; 1908 1909 case 'S': 1910 if (!TARGET_LONG_DISPLACEMENT) 1911 return 0; 1912 if (GET_CODE (op) != MEM) 1913 return 0; 1914 if (!s390_decompose_address (XEXP (op, 0), &addr)) 1915 return 0; 1916 if (addr.indx) 1917 return 0; 1918 if (s390_short_displacement (addr.disp)) 1919 return 0; 1920 break; 1921 1922 case 'T': 1923 if (!TARGET_LONG_DISPLACEMENT) 1924 return 0; 1925 if (GET_CODE (op) != MEM) 1926 return 0; 1927 /* Any invalid address here will be fixed up by reload, 1928 so accept it for the most generic constraint. */ 1929 if (s390_decompose_address (XEXP (op, 0), &addr) 1930 && s390_short_displacement (addr.disp)) 1931 return 0; 1932 break; 1933 1934 case 'U': 1935 if (TARGET_LONG_DISPLACEMENT) 1936 { 1937 if (!s390_decompose_address (op, &addr)) 1938 return 0; 1939 if (!s390_short_displacement (addr.disp)) 1940 return 0; 1941 } 1942 break; 1943 1944 case 'W': 1945 if (!TARGET_LONG_DISPLACEMENT) 1946 return 0; 1947 /* Any invalid address here will be fixed up by reload, 1948 so accept it for the most generic constraint. */ 1949 if (s390_decompose_address (op, &addr) 1950 && s390_short_displacement (addr.disp)) 1951 return 0; 1952 break; 1953 1954 case 'Y': 1955 /* Simply check for the basic form of a shift count. Reload will 1956 take care of making sure we have a proper base register. */ 1957 if (!s390_decompose_shift_count (op, NULL, NULL)) 1958 return 0; 1959 break; 1960 1961 default: 1962 return 0; 1963 } 1964 1965 return 1; 1966} 1967 1968/* Return true if VALUE matches the constraint STR. */ 1969 1970int 1971s390_const_double_ok_for_constraint_p (rtx value, 1972 int c, 1973 const char * str) 1974{ 1975 gcc_assert (c == str[0]); 1976 1977 switch (str[0]) 1978 { 1979 case 'G': 1980 /* The floating point zero constant. */ 1981 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT 1982 && value == CONST0_RTX (GET_MODE (value))); 1983 1984 default: 1985 return 0; 1986 } 1987} 1988 1989/* Return true if VALUE matches the constraint STR. */ 1990 1991int 1992s390_const_ok_for_constraint_p (HOST_WIDE_INT value, 1993 int c, 1994 const char * str) 1995{ 1996 enum machine_mode mode, part_mode; 1997 int def; 1998 int part, part_goal; 1999 2000 gcc_assert (c == str[0]); 2001 2002 switch (str[0]) 2003 { 2004 case 'I': 2005 return (unsigned int)value < 256; 2006 2007 case 'J': 2008 return (unsigned int)value < 4096; 2009 2010 case 'K': 2011 return value >= -32768 && value < 32768; 2012 2013 case 'L': 2014 return (TARGET_LONG_DISPLACEMENT ? 2015 (value >= -524288 && value <= 524287) 2016 : (value >= 0 && value <= 4095)); 2017 case 'M': 2018 return value == 2147483647; 2019 2020 case 'N': 2021 if (str[1] == 'x') 2022 part_goal = -1; 2023 else 2024 part_goal = str[1] - '0'; 2025 2026 switch (str[2]) 2027 { 2028 case 'Q': part_mode = QImode; break; 2029 case 'H': part_mode = HImode; break; 2030 case 'S': part_mode = SImode; break; 2031 default: return 0; 2032 } 2033 2034 switch (str[3]) 2035 { 2036 case 'H': mode = HImode; break; 2037 case 'S': mode = SImode; break; 2038 case 'D': mode = DImode; break; 2039 default: return 0; 2040 } 2041 2042 switch (str[4]) 2043 { 2044 case '0': def = 0; break; 2045 case 'F': def = -1; break; 2046 default: return 0; 2047 } 2048 2049 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode)) 2050 return 0; 2051 2052 part = s390_single_part (GEN_INT (value), mode, part_mode, def); 2053 if (part < 0) 2054 return 0; 2055 if (part_goal != -1 && part_goal != part) 2056 return 0; 2057 2058 break; 2059 2060 case 'O': 2061 if (!TARGET_EXTIMM) 2062 return 0; 2063 2064 switch (str[1]) 2065 { 2066 case 's': 2067 return trunc_int_for_mode (value, SImode) == value; 2068 2069 case 'p': 2070 return value == 0 2071 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1; 2072 2073 case 'n': 2074 return 2075 (value == -1 2076 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1) 2077 && value != -((HOST_WIDE_INT)1 << 32); 2078 2079 default: 2080 gcc_unreachable (); 2081 } 2082 break; 2083 2084 case 'P': 2085 return legitimate_reload_constant_p (GEN_INT (value)); 2086 2087 default: 2088 return 0; 2089 } 2090 2091 return 1; 2092} 2093 2094/* Compute a (partial) cost for rtx X. Return true if the complete 2095 cost has been computed, and false if subexpressions should be 2096 scanned. In either case, *TOTAL contains the cost result. 2097 CODE contains GET_CODE (x), OUTER_CODE contains the code 2098 of the superexpression of x. */ 2099 2100static bool 2101s390_rtx_costs (rtx x, int code, int outer_code, int *total) 2102{ 2103 switch (code) 2104 { 2105 case CONST: 2106 case CONST_INT: 2107 case LABEL_REF: 2108 case SYMBOL_REF: 2109 case CONST_DOUBLE: 2110 case MEM: 2111 *total = 0; 2112 return true; 2113 2114 case ASHIFT: 2115 case ASHIFTRT: 2116 case LSHIFTRT: 2117 case ROTATE: 2118 case ROTATERT: 2119 case AND: 2120 case IOR: 2121 case XOR: 2122 case NEG: 2123 case NOT: 2124 *total = COSTS_N_INSNS (1); 2125 return false; 2126 2127 case PLUS: 2128 case MINUS: 2129 /* Check for multiply and add. */ 2130 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode) 2131 && GET_CODE (XEXP (x, 0)) == MULT 2132 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD) 2133 { 2134 /* This is the multiply and add case. */ 2135 if (GET_MODE (x) == DFmode) 2136 *total = s390_cost->madbr; 2137 else 2138 *total = s390_cost->maebr; 2139 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT) 2140 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT) 2141 + rtx_cost (XEXP (x, 1), code); 2142 return true; /* Do not do an additional recursive descent. */ 2143 } 2144 *total = COSTS_N_INSNS (1); 2145 return false; 2146 2147 case MULT: 2148 switch (GET_MODE (x)) 2149 { 2150 case SImode: 2151 { 2152 rtx left = XEXP (x, 0); 2153 rtx right = XEXP (x, 1); 2154 if (GET_CODE (right) == CONST_INT 2155 && CONST_OK_FOR_K (INTVAL (right))) 2156 *total = s390_cost->mhi; 2157 else if (GET_CODE (left) == SIGN_EXTEND) 2158 *total = s390_cost->mh; 2159 else 2160 *total = s390_cost->ms; /* msr, ms, msy */ 2161 break; 2162 } 2163 case DImode: 2164 { 2165 rtx left = XEXP (x, 0); 2166 rtx right = XEXP (x, 1); 2167 if (TARGET_64BIT) 2168 { 2169 if (GET_CODE (right) == CONST_INT 2170 && CONST_OK_FOR_K (INTVAL (right))) 2171 *total = s390_cost->mghi; 2172 else if (GET_CODE (left) == SIGN_EXTEND) 2173 *total = s390_cost->msgf; 2174 else 2175 *total = s390_cost->msg; /* msgr, msg */ 2176 } 2177 else /* TARGET_31BIT */ 2178 { 2179 if (GET_CODE (left) == SIGN_EXTEND 2180 && GET_CODE (right) == SIGN_EXTEND) 2181 /* mulsidi case: mr, m */ 2182 *total = s390_cost->m; 2183 else if (GET_CODE (left) == ZERO_EXTEND 2184 && GET_CODE (right) == ZERO_EXTEND 2185 && TARGET_CPU_ZARCH) 2186 /* umulsidi case: ml, mlr */ 2187 *total = s390_cost->ml; 2188 else 2189 /* Complex calculation is required. */ 2190 *total = COSTS_N_INSNS (40); 2191 } 2192 break; 2193 } 2194 case SFmode: 2195 case DFmode: 2196 *total = s390_cost->mult_df; 2197 break; 2198 case TFmode: 2199 *total = s390_cost->mxbr; 2200 break; 2201 default: 2202 return false; 2203 } 2204 return false; 2205 2206 case UDIV: 2207 case UMOD: 2208 if (GET_MODE (x) == TImode) /* 128 bit division */ 2209 *total = s390_cost->dlgr; 2210 else if (GET_MODE (x) == DImode) 2211 { 2212 rtx right = XEXP (x, 1); 2213 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ 2214 *total = s390_cost->dlr; 2215 else /* 64 by 64 bit division */ 2216 *total = s390_cost->dlgr; 2217 } 2218 else if (GET_MODE (x) == SImode) /* 32 bit division */ 2219 *total = s390_cost->dlr; 2220 return false; 2221 2222 case DIV: 2223 case MOD: 2224 if (GET_MODE (x) == DImode) 2225 { 2226 rtx right = XEXP (x, 1); 2227 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ 2228 if (TARGET_64BIT) 2229 *total = s390_cost->dsgfr; 2230 else 2231 *total = s390_cost->dr; 2232 else /* 64 by 64 bit division */ 2233 *total = s390_cost->dsgr; 2234 } 2235 else if (GET_MODE (x) == SImode) /* 32 bit division */ 2236 *total = s390_cost->dlr; 2237 else if (GET_MODE (x) == SFmode) 2238 { 2239 if (TARGET_IEEE_FLOAT) 2240 *total = s390_cost->debr; 2241 else /* TARGET_IBM_FLOAT */ 2242 *total = s390_cost->der; 2243 } 2244 else if (GET_MODE (x) == DFmode) 2245 { 2246 if (TARGET_IEEE_FLOAT) 2247 *total = s390_cost->ddbr; 2248 else /* TARGET_IBM_FLOAT */ 2249 *total = s390_cost->ddr; 2250 } 2251 else if (GET_MODE (x) == TFmode) 2252 { 2253 if (TARGET_IEEE_FLOAT) 2254 *total = s390_cost->dxbr; 2255 else /* TARGET_IBM_FLOAT */ 2256 *total = s390_cost->dxr; 2257 } 2258 return false; 2259 2260 case SQRT: 2261 if (GET_MODE (x) == SFmode) 2262 *total = s390_cost->sqebr; 2263 else if (GET_MODE (x) == DFmode) 2264 *total = s390_cost->sqdbr; 2265 else /* TFmode */ 2266 *total = s390_cost->sqxbr; 2267 return false; 2268 2269 case SIGN_EXTEND: 2270 case ZERO_EXTEND: 2271 if (outer_code == MULT || outer_code == DIV || outer_code == MOD 2272 || outer_code == PLUS || outer_code == MINUS 2273 || outer_code == COMPARE) 2274 *total = 0; 2275 return false; 2276 2277 case COMPARE: 2278 *total = COSTS_N_INSNS (1); 2279 if (GET_CODE (XEXP (x, 0)) == AND 2280 && GET_CODE (XEXP (x, 1)) == CONST_INT 2281 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) 2282 { 2283 rtx op0 = XEXP (XEXP (x, 0), 0); 2284 rtx op1 = XEXP (XEXP (x, 0), 1); 2285 rtx op2 = XEXP (x, 1); 2286 2287 if (memory_operand (op0, GET_MODE (op0)) 2288 && s390_tm_ccmode (op1, op2, 0) != VOIDmode) 2289 return true; 2290 if (register_operand (op0, GET_MODE (op0)) 2291 && s390_tm_ccmode (op1, op2, 1) != VOIDmode) 2292 return true; 2293 } 2294 return false; 2295 2296 default: 2297 return false; 2298 } 2299} 2300 2301/* Return the cost of an address rtx ADDR. */ 2302 2303static int 2304s390_address_cost (rtx addr) 2305{ 2306 struct s390_address ad; 2307 if (!s390_decompose_address (addr, &ad)) 2308 return 1000; 2309 2310 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1); 2311} 2312 2313/* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode, 2314 otherwise return 0. */ 2315 2316int 2317tls_symbolic_operand (rtx op) 2318{ 2319 if (GET_CODE (op) != SYMBOL_REF) 2320 return 0; 2321 return SYMBOL_REF_TLS_MODEL (op); 2322} 2323 2324/* Split DImode access register reference REG (on 64-bit) into its constituent 2325 low and high parts, and store them into LO and HI. Note that gen_lowpart/ 2326 gen_highpart cannot be used as they assume all registers are word-sized, 2327 while our access registers have only half that size. */ 2328 2329void 2330s390_split_access_reg (rtx reg, rtx *lo, rtx *hi) 2331{ 2332 gcc_assert (TARGET_64BIT); 2333 gcc_assert (ACCESS_REG_P (reg)); 2334 gcc_assert (GET_MODE (reg) == DImode); 2335 gcc_assert (!(REGNO (reg) & 1)); 2336 2337 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1); 2338 *hi = gen_rtx_REG (SImode, REGNO (reg)); 2339} 2340 2341/* Return true if OP contains a symbol reference */ 2342 2343bool 2344symbolic_reference_mentioned_p (rtx op) 2345{ 2346 const char *fmt; 2347 int i; 2348 2349 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) 2350 return 1; 2351 2352 fmt = GET_RTX_FORMAT (GET_CODE (op)); 2353 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) 2354 { 2355 if (fmt[i] == 'E') 2356 { 2357 int j; 2358 2359 for (j = XVECLEN (op, i) - 1; j >= 0; j--) 2360 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) 2361 return 1; 2362 } 2363 2364 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) 2365 return 1; 2366 } 2367 2368 return 0; 2369} 2370 2371/* Return true if OP contains a reference to a thread-local symbol. */ 2372 2373bool 2374tls_symbolic_reference_mentioned_p (rtx op) 2375{ 2376 const char *fmt; 2377 int i; 2378 2379 if (GET_CODE (op) == SYMBOL_REF) 2380 return tls_symbolic_operand (op); 2381 2382 fmt = GET_RTX_FORMAT (GET_CODE (op)); 2383 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) 2384 { 2385 if (fmt[i] == 'E') 2386 { 2387 int j; 2388 2389 for (j = XVECLEN (op, i) - 1; j >= 0; j--) 2390 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j))) 2391 return true; 2392 } 2393 2394 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i))) 2395 return true; 2396 } 2397 2398 return false; 2399} 2400 2401 2402/* Return true if OP is a legitimate general operand when 2403 generating PIC code. It is given that flag_pic is on 2404 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2405 2406int 2407legitimate_pic_operand_p (rtx op) 2408{ 2409 /* Accept all non-symbolic constants. */ 2410 if (!SYMBOLIC_CONST (op)) 2411 return 1; 2412 2413 /* Reject everything else; must be handled 2414 via emit_symbolic_move. */ 2415 return 0; 2416} 2417 2418/* Returns true if the constant value OP is a legitimate general operand. 2419 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2420 2421int 2422legitimate_constant_p (rtx op) 2423{ 2424 /* Accept all non-symbolic constants. */ 2425 if (!SYMBOLIC_CONST (op)) 2426 return 1; 2427 2428 /* Accept immediate LARL operands. */ 2429 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode)) 2430 return 1; 2431 2432 /* Thread-local symbols are never legal constants. This is 2433 so that emit_call knows that computing such addresses 2434 might require a function call. */ 2435 if (TLS_SYMBOLIC_CONST (op)) 2436 return 0; 2437 2438 /* In the PIC case, symbolic constants must *not* be 2439 forced into the literal pool. We accept them here, 2440 so that they will be handled by emit_symbolic_move. */ 2441 if (flag_pic) 2442 return 1; 2443 2444 /* All remaining non-PIC symbolic constants are 2445 forced into the literal pool. */ 2446 return 0; 2447} 2448 2449/* Determine if it's legal to put X into the constant pool. This 2450 is not possible if X contains the address of a symbol that is 2451 not constant (TLS) or not known at final link time (PIC). */ 2452 2453static bool 2454s390_cannot_force_const_mem (rtx x) 2455{ 2456 switch (GET_CODE (x)) 2457 { 2458 case CONST_INT: 2459 case CONST_DOUBLE: 2460 /* Accept all non-symbolic constants. */ 2461 return false; 2462 2463 case LABEL_REF: 2464 /* Labels are OK iff we are non-PIC. */ 2465 return flag_pic != 0; 2466 2467 case SYMBOL_REF: 2468 /* 'Naked' TLS symbol references are never OK, 2469 non-TLS symbols are OK iff we are non-PIC. */ 2470 if (tls_symbolic_operand (x)) 2471 return true; 2472 else 2473 return flag_pic != 0; 2474 2475 case CONST: 2476 return s390_cannot_force_const_mem (XEXP (x, 0)); 2477 case PLUS: 2478 case MINUS: 2479 return s390_cannot_force_const_mem (XEXP (x, 0)) 2480 || s390_cannot_force_const_mem (XEXP (x, 1)); 2481 2482 case UNSPEC: 2483 switch (XINT (x, 1)) 2484 { 2485 /* Only lt-relative or GOT-relative UNSPECs are OK. */ 2486 case UNSPEC_LTREL_OFFSET: 2487 case UNSPEC_GOT: 2488 case UNSPEC_GOTOFF: 2489 case UNSPEC_PLTOFF: 2490 case UNSPEC_TLSGD: 2491 case UNSPEC_TLSLDM: 2492 case UNSPEC_NTPOFF: 2493 case UNSPEC_DTPOFF: 2494 case UNSPEC_GOTNTPOFF: 2495 case UNSPEC_INDNTPOFF: 2496 return false; 2497 2498 /* If the literal pool shares the code section, be put 2499 execute template placeholders into the pool as well. */ 2500 case UNSPEC_INSN: 2501 return TARGET_CPU_ZARCH; 2502 2503 default: 2504 return true; 2505 } 2506 break; 2507 2508 default: 2509 gcc_unreachable (); 2510 } 2511} 2512 2513/* Returns true if the constant value OP is a legitimate general 2514 operand during and after reload. The difference to 2515 legitimate_constant_p is that this function will not accept 2516 a constant that would need to be forced to the literal pool 2517 before it can be used as operand. */ 2518 2519bool 2520legitimate_reload_constant_p (rtx op) 2521{ 2522 /* Accept la(y) operands. */ 2523 if (GET_CODE (op) == CONST_INT 2524 && DISP_IN_RANGE (INTVAL (op))) 2525 return true; 2526 2527 /* Accept l(g)hi/l(g)fi operands. */ 2528 if (GET_CODE (op) == CONST_INT 2529 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op)))) 2530 return true; 2531 2532 /* Accept lliXX operands. */ 2533 if (TARGET_ZARCH 2534 && GET_CODE (op) == CONST_INT 2535 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) 2536 && s390_single_part (op, word_mode, HImode, 0) >= 0) 2537 return true; 2538 2539 if (TARGET_EXTIMM 2540 && GET_CODE (op) == CONST_INT 2541 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) 2542 && s390_single_part (op, word_mode, SImode, 0) >= 0) 2543 return true; 2544 2545 /* Accept larl operands. */ 2546 if (TARGET_CPU_ZARCH 2547 && larl_operand (op, VOIDmode)) 2548 return true; 2549 2550 /* Accept lzXX operands. */ 2551 if (GET_CODE (op) == CONST_DOUBLE 2552 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G")) 2553 return true; 2554 2555 /* Accept double-word operands that can be split. */ 2556 if (GET_CODE (op) == CONST_INT 2557 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op)) 2558 { 2559 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode; 2560 rtx hi = operand_subword (op, 0, 0, dword_mode); 2561 rtx lo = operand_subword (op, 1, 0, dword_mode); 2562 return legitimate_reload_constant_p (hi) 2563 && legitimate_reload_constant_p (lo); 2564 } 2565 2566 /* Everything else cannot be handled without reload. */ 2567 return false; 2568} 2569 2570/* Given an rtx OP being reloaded into a reg required to be in class CLASS, 2571 return the class of reg to actually use. */ 2572 2573enum reg_class 2574s390_preferred_reload_class (rtx op, enum reg_class class) 2575{ 2576 switch (GET_CODE (op)) 2577 { 2578 /* Constants we cannot reload must be forced into the 2579 literal pool. */ 2580 2581 case CONST_DOUBLE: 2582 case CONST_INT: 2583 if (legitimate_reload_constant_p (op)) 2584 return class; 2585 else 2586 return NO_REGS; 2587 2588 /* If a symbolic constant or a PLUS is reloaded, 2589 it is most likely being used as an address, so 2590 prefer ADDR_REGS. If 'class' is not a superset 2591 of ADDR_REGS, e.g. FP_REGS, reject this reload. */ 2592 case PLUS: 2593 case LABEL_REF: 2594 case SYMBOL_REF: 2595 case CONST: 2596 if (reg_class_subset_p (ADDR_REGS, class)) 2597 return ADDR_REGS; 2598 else 2599 return NO_REGS; 2600 2601 default: 2602 break; 2603 } 2604 2605 return class; 2606} 2607 2608/* Return the register class of a scratch register needed to 2609 load IN into a register of class CLASS in MODE. 2610 2611 We need a temporary when loading a PLUS expression which 2612 is not a legitimate operand of the LOAD ADDRESS instruction. */ 2613 2614enum reg_class 2615s390_secondary_input_reload_class (enum reg_class class, 2616 enum machine_mode mode, rtx in) 2617{ 2618 if (s390_plus_operand (in, mode)) 2619 return ADDR_REGS; 2620 2621 if (reg_classes_intersect_p (FP_REGS, class) 2622 && mode == TFmode 2623 && GET_CODE (in) == MEM 2624 && GET_CODE (XEXP (in, 0)) == PLUS 2625 && GET_CODE (XEXP (XEXP (in, 0), 1)) == CONST_INT 2626 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (in, 0), 1)) 2627 + GET_MODE_SIZE (mode) - 1)) 2628 return ADDR_REGS; 2629 2630 if (reg_classes_intersect_p (CC_REGS, class)) 2631 return GENERAL_REGS; 2632 2633 return NO_REGS; 2634} 2635 2636/* Return the register class of a scratch register needed to 2637 store a register of class CLASS in MODE into OUT: 2638 2639 We need a temporary when storing a double-word to a 2640 non-offsettable memory address. */ 2641 2642enum reg_class 2643s390_secondary_output_reload_class (enum reg_class class, 2644 enum machine_mode mode, rtx out) 2645{ 2646 if ((TARGET_64BIT ? (mode == TImode || mode == TFmode) 2647 : (mode == DImode || mode == DFmode)) 2648 && reg_classes_intersect_p (GENERAL_REGS, class) 2649 && GET_CODE (out) == MEM 2650 && GET_CODE (XEXP (out, 0)) == PLUS 2651 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS 2652 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT 2653 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1)) 2654 + GET_MODE_SIZE (mode) - 1)) 2655 return ADDR_REGS; 2656 2657 if (reg_classes_intersect_p (FP_REGS, class) 2658 && mode == TFmode 2659 && GET_CODE (out) == MEM 2660 && GET_CODE (XEXP (out, 0)) == PLUS 2661 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT 2662 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1)) 2663 + GET_MODE_SIZE (mode) - 1)) 2664 return ADDR_REGS; 2665 2666 if (reg_classes_intersect_p (CC_REGS, class)) 2667 return GENERAL_REGS; 2668 2669 return NO_REGS; 2670} 2671 2672/* Generate code to load SRC, which is PLUS that is not a 2673 legitimate operand for the LA instruction, into TARGET. 2674 SCRATCH may be used as scratch register. */ 2675 2676void 2677s390_expand_plus_operand (rtx target, rtx src, 2678 rtx scratch) 2679{ 2680 rtx sum1, sum2; 2681 struct s390_address ad; 2682 2683 /* src must be a PLUS; get its two operands. */ 2684 gcc_assert (GET_CODE (src) == PLUS); 2685 gcc_assert (GET_MODE (src) == Pmode); 2686 2687 /* Check if any of the two operands is already scheduled 2688 for replacement by reload. This can happen e.g. when 2689 float registers occur in an address. */ 2690 sum1 = find_replacement (&XEXP (src, 0)); 2691 sum2 = find_replacement (&XEXP (src, 1)); 2692 src = gen_rtx_PLUS (Pmode, sum1, sum2); 2693 2694 /* If the address is already strictly valid, there's nothing to do. */ 2695 if (!s390_decompose_address (src, &ad) 2696 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base)) 2697 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx))) 2698 { 2699 /* Otherwise, one of the operands cannot be an address register; 2700 we reload its value into the scratch register. */ 2701 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15) 2702 { 2703 emit_move_insn (scratch, sum1); 2704 sum1 = scratch; 2705 } 2706 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15) 2707 { 2708 emit_move_insn (scratch, sum2); 2709 sum2 = scratch; 2710 } 2711 2712 /* According to the way these invalid addresses are generated 2713 in reload.c, it should never happen (at least on s390) that 2714 *neither* of the PLUS components, after find_replacements 2715 was applied, is an address register. */ 2716 if (sum1 == scratch && sum2 == scratch) 2717 { 2718 debug_rtx (src); 2719 gcc_unreachable (); 2720 } 2721 2722 src = gen_rtx_PLUS (Pmode, sum1, sum2); 2723 } 2724 2725 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS 2726 is only ever performed on addresses, so we can mark the 2727 sum as legitimate for LA in any case. */ 2728 s390_load_address (target, src); 2729} 2730 2731 2732/* Return true if ADDR is a valid memory address. 2733 STRICT specifies whether strict register checking applies. */ 2734 2735bool 2736legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, 2737 rtx addr, int strict) 2738{ 2739 struct s390_address ad; 2740 if (!s390_decompose_address (addr, &ad)) 2741 return false; 2742 2743 if (strict) 2744 { 2745 if (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base)) 2746 return false; 2747 if (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)) 2748 return false; 2749 } 2750 else 2751 { 2752 if (ad.base && !REG_OK_FOR_BASE_NONSTRICT_P (ad.base)) 2753 return false; 2754 if (ad.indx && !REG_OK_FOR_INDEX_NONSTRICT_P (ad.indx)) 2755 return false; 2756 } 2757 2758 return true; 2759} 2760 2761/* Return true if OP is a valid operand for the LA instruction. 2762 In 31-bit, we need to prove that the result is used as an 2763 address, as LA performs only a 31-bit addition. */ 2764 2765bool 2766legitimate_la_operand_p (rtx op) 2767{ 2768 struct s390_address addr; 2769 if (!s390_decompose_address (op, &addr)) 2770 return false; 2771 2772 return (TARGET_64BIT || addr.pointer); 2773} 2774 2775/* Return true if it is valid *and* preferable to use LA to 2776 compute the sum of OP1 and OP2. */ 2777 2778bool 2779preferred_la_operand_p (rtx op1, rtx op2) 2780{ 2781 struct s390_address addr; 2782 2783 if (op2 != const0_rtx) 2784 op1 = gen_rtx_PLUS (Pmode, op1, op2); 2785 2786 if (!s390_decompose_address (op1, &addr)) 2787 return false; 2788 if (addr.base && !REG_OK_FOR_BASE_STRICT_P (addr.base)) 2789 return false; 2790 if (addr.indx && !REG_OK_FOR_INDEX_STRICT_P (addr.indx)) 2791 return false; 2792 2793 if (!TARGET_64BIT && !addr.pointer) 2794 return false; 2795 2796 if (addr.pointer) 2797 return true; 2798 2799 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base)) 2800 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx))) 2801 return true; 2802 2803 return false; 2804} 2805 2806/* Emit a forced load-address operation to load SRC into DST. 2807 This will use the LOAD ADDRESS instruction even in situations 2808 where legitimate_la_operand_p (SRC) returns false. */ 2809 2810void 2811s390_load_address (rtx dst, rtx src) 2812{ 2813 if (TARGET_64BIT) 2814 emit_move_insn (dst, src); 2815 else 2816 emit_insn (gen_force_la_31 (dst, src)); 2817} 2818 2819/* Return a legitimate reference for ORIG (an address) using the 2820 register REG. If REG is 0, a new pseudo is generated. 2821 2822 There are two types of references that must be handled: 2823 2824 1. Global data references must load the address from the GOT, via 2825 the PIC reg. An insn is emitted to do this load, and the reg is 2826 returned. 2827 2828 2. Static data references, constant pool addresses, and code labels 2829 compute the address as an offset from the GOT, whose base is in 2830 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to 2831 differentiate them from global data objects. The returned 2832 address is the PIC reg + an unspec constant. 2833 2834 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC 2835 reg also appears in the address. */ 2836 2837rtx 2838legitimize_pic_address (rtx orig, rtx reg) 2839{ 2840 rtx addr = orig; 2841 rtx new = orig; 2842 rtx base; 2843 2844 gcc_assert (!TLS_SYMBOLIC_CONST (addr)); 2845 2846 if (GET_CODE (addr) == LABEL_REF 2847 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr))) 2848 { 2849 /* This is a local symbol. */ 2850 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode)) 2851 { 2852 /* Access local symbols PC-relative via LARL. 2853 This is the same as in the non-PIC case, so it is 2854 handled automatically ... */ 2855 } 2856 else 2857 { 2858 /* Access local symbols relative to the GOT. */ 2859 2860 rtx temp = reg? reg : gen_reg_rtx (Pmode); 2861 2862 if (reload_in_progress || reload_completed) 2863 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; 2864 2865 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF); 2866 addr = gen_rtx_CONST (Pmode, addr); 2867 addr = force_const_mem (Pmode, addr); 2868 emit_move_insn (temp, addr); 2869 2870 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); 2871 if (reg != 0) 2872 { 2873 s390_load_address (reg, new); 2874 new = reg; 2875 } 2876 } 2877 } 2878 else if (GET_CODE (addr) == SYMBOL_REF) 2879 { 2880 if (reg == 0) 2881 reg = gen_reg_rtx (Pmode); 2882 2883 if (flag_pic == 1) 2884 { 2885 /* Assume GOT offset < 4k. This is handled the same way 2886 in both 31- and 64-bit code (@GOT). */ 2887 2888 if (reload_in_progress || reload_completed) 2889 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; 2890 2891 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT); 2892 new = gen_rtx_CONST (Pmode, new); 2893 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); 2894 new = gen_const_mem (Pmode, new); 2895 emit_move_insn (reg, new); 2896 new = reg; 2897 } 2898 else if (TARGET_CPU_ZARCH) 2899 { 2900 /* If the GOT offset might be >= 4k, we determine the position 2901 of the GOT entry via a PC-relative LARL (@GOTENT). */ 2902 2903 rtx temp = gen_reg_rtx (Pmode); 2904 2905 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT); 2906 new = gen_rtx_CONST (Pmode, new); 2907 emit_move_insn (temp, new); 2908 2909 new = gen_const_mem (Pmode, temp); 2910 emit_move_insn (reg, new); 2911 new = reg; 2912 } 2913 else 2914 { 2915 /* If the GOT offset might be >= 4k, we have to load it 2916 from the literal pool (@GOT). */ 2917 2918 rtx temp = gen_reg_rtx (Pmode); 2919 2920 if (reload_in_progress || reload_completed) 2921 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; 2922 2923 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT); 2924 addr = gen_rtx_CONST (Pmode, addr); 2925 addr = force_const_mem (Pmode, addr); 2926 emit_move_insn (temp, addr); 2927 2928 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); 2929 new = gen_const_mem (Pmode, new); 2930 emit_move_insn (reg, new); 2931 new = reg; 2932 } 2933 } 2934 else 2935 { 2936 if (GET_CODE (addr) == CONST) 2937 { 2938 addr = XEXP (addr, 0); 2939 if (GET_CODE (addr) == UNSPEC) 2940 { 2941 gcc_assert (XVECLEN (addr, 0) == 1); 2942 switch (XINT (addr, 1)) 2943 { 2944 /* If someone moved a GOT-relative UNSPEC 2945 out of the literal pool, force them back in. */ 2946 case UNSPEC_GOTOFF: 2947 case UNSPEC_PLTOFF: 2948 new = force_const_mem (Pmode, orig); 2949 break; 2950 2951 /* @GOT is OK as is if small. */ 2952 case UNSPEC_GOT: 2953 if (flag_pic == 2) 2954 new = force_const_mem (Pmode, orig); 2955 break; 2956 2957 /* @GOTENT is OK as is. */ 2958 case UNSPEC_GOTENT: 2959 break; 2960 2961 /* @PLT is OK as is on 64-bit, must be converted to 2962 GOT-relative @PLTOFF on 31-bit. */ 2963 case UNSPEC_PLT: 2964 if (!TARGET_CPU_ZARCH) 2965 { 2966 rtx temp = reg? reg : gen_reg_rtx (Pmode); 2967 2968 if (reload_in_progress || reload_completed) 2969 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; 2970 2971 addr = XVECEXP (addr, 0, 0); 2972 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 2973 UNSPEC_PLTOFF); 2974 addr = gen_rtx_CONST (Pmode, addr); 2975 addr = force_const_mem (Pmode, addr); 2976 emit_move_insn (temp, addr); 2977 2978 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); 2979 if (reg != 0) 2980 { 2981 s390_load_address (reg, new); 2982 new = reg; 2983 } 2984 } 2985 break; 2986 2987 /* Everything else cannot happen. */ 2988 default: 2989 gcc_unreachable (); 2990 } 2991 } 2992 else 2993 gcc_assert (GET_CODE (addr) == PLUS); 2994 } 2995 if (GET_CODE (addr) == PLUS) 2996 { 2997 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1); 2998 2999 gcc_assert (!TLS_SYMBOLIC_CONST (op0)); 3000 gcc_assert (!TLS_SYMBOLIC_CONST (op1)); 3001 3002 /* Check first to see if this is a constant offset 3003 from a local symbol reference. */ 3004 if ((GET_CODE (op0) == LABEL_REF 3005 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0))) 3006 && GET_CODE (op1) == CONST_INT) 3007 { 3008 if (TARGET_CPU_ZARCH 3009 && larl_operand (op0, VOIDmode) 3010 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31 3011 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31)) 3012 { 3013 if (INTVAL (op1) & 1) 3014 { 3015 /* LARL can't handle odd offsets, so emit a 3016 pair of LARL and LA. */ 3017 rtx temp = reg? reg : gen_reg_rtx (Pmode); 3018 3019 if (!DISP_IN_RANGE (INTVAL (op1))) 3020 { 3021 HOST_WIDE_INT even = INTVAL (op1) - 1; 3022 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even)); 3023 op0 = gen_rtx_CONST (Pmode, op0); 3024 op1 = const1_rtx; 3025 } 3026 3027 emit_move_insn (temp, op0); 3028 new = gen_rtx_PLUS (Pmode, temp, op1); 3029 3030 if (reg != 0) 3031 { 3032 s390_load_address (reg, new); 3033 new = reg; 3034 } 3035 } 3036 else 3037 { 3038 /* If the offset is even, we can just use LARL. 3039 This will happen automatically. */ 3040 } 3041 } 3042 else 3043 { 3044 /* Access local symbols relative to the GOT. */ 3045 3046 rtx temp = reg? reg : gen_reg_rtx (Pmode); 3047 3048 if (reload_in_progress || reload_completed) 3049 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; 3050 3051 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), 3052 UNSPEC_GOTOFF); 3053 addr = gen_rtx_PLUS (Pmode, addr, op1); 3054 addr = gen_rtx_CONST (Pmode, addr); 3055 addr = force_const_mem (Pmode, addr); 3056 emit_move_insn (temp, addr); 3057 3058 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); 3059 if (reg != 0) 3060 { 3061 s390_load_address (reg, new); 3062 new = reg; 3063 } 3064 } 3065 } 3066 3067 /* Now, check whether it is a GOT relative symbol plus offset 3068 that was pulled out of the literal pool. Force it back in. */ 3069 3070 else if (GET_CODE (op0) == UNSPEC 3071 && GET_CODE (op1) == CONST_INT 3072 && XINT (op0, 1) == UNSPEC_GOTOFF) 3073 { 3074 gcc_assert (XVECLEN (op0, 0) == 1); 3075 3076 new = force_const_mem (Pmode, orig); 3077 } 3078 3079 /* Otherwise, compute the sum. */ 3080 else 3081 { 3082 base = legitimize_pic_address (XEXP (addr, 0), reg); 3083 new = legitimize_pic_address (XEXP (addr, 1), 3084 base == reg ? NULL_RTX : reg); 3085 if (GET_CODE (new) == CONST_INT) 3086 new = plus_constant (base, INTVAL (new)); 3087 else 3088 { 3089 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1))) 3090 { 3091 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0)); 3092 new = XEXP (new, 1); 3093 } 3094 new = gen_rtx_PLUS (Pmode, base, new); 3095 } 3096 3097 if (GET_CODE (new) == CONST) 3098 new = XEXP (new, 0); 3099 new = force_operand (new, 0); 3100 } 3101 } 3102 } 3103 return new; 3104} 3105 3106/* Load the thread pointer into a register. */ 3107 3108rtx 3109s390_get_thread_pointer (void) 3110{ 3111 rtx tp = gen_reg_rtx (Pmode); 3112 3113 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM)); 3114 mark_reg_pointer (tp, BITS_PER_WORD); 3115 3116 return tp; 3117} 3118 3119/* Emit a tls call insn. The call target is the SYMBOL_REF stored 3120 in s390_tls_symbol which always refers to __tls_get_offset. 3121 The returned offset is written to RESULT_REG and an USE rtx is 3122 generated for TLS_CALL. */ 3123 3124static GTY(()) rtx s390_tls_symbol; 3125 3126static void 3127s390_emit_tls_call_insn (rtx result_reg, rtx tls_call) 3128{ 3129 rtx insn; 3130 3131 gcc_assert (flag_pic); 3132 3133 if (!s390_tls_symbol) 3134 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset"); 3135 3136 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg, 3137 gen_rtx_REG (Pmode, RETURN_REGNUM)); 3138 3139 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg); 3140 CONST_OR_PURE_CALL_P (insn) = 1; 3141} 3142 3143/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute 3144 this (thread-local) address. REG may be used as temporary. */ 3145 3146static rtx 3147legitimize_tls_address (rtx addr, rtx reg) 3148{ 3149 rtx new, tls_call, temp, base, r2, insn; 3150 3151 if (GET_CODE (addr) == SYMBOL_REF) 3152 switch (tls_symbolic_operand (addr)) 3153 { 3154 case TLS_MODEL_GLOBAL_DYNAMIC: 3155 start_sequence (); 3156 r2 = gen_rtx_REG (Pmode, 2); 3157 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD); 3158 new = gen_rtx_CONST (Pmode, tls_call); 3159 new = force_const_mem (Pmode, new); 3160 emit_move_insn (r2, new); 3161 s390_emit_tls_call_insn (r2, tls_call); 3162 insn = get_insns (); 3163 end_sequence (); 3164 3165 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF); 3166 temp = gen_reg_rtx (Pmode); 3167 emit_libcall_block (insn, temp, r2, new); 3168 3169 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); 3170 if (reg != 0) 3171 { 3172 s390_load_address (reg, new); 3173 new = reg; 3174 } 3175 break; 3176 3177 case TLS_MODEL_LOCAL_DYNAMIC: 3178 start_sequence (); 3179 r2 = gen_rtx_REG (Pmode, 2); 3180 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM); 3181 new = gen_rtx_CONST (Pmode, tls_call); 3182 new = force_const_mem (Pmode, new); 3183 emit_move_insn (r2, new); 3184 s390_emit_tls_call_insn (r2, tls_call); 3185 insn = get_insns (); 3186 end_sequence (); 3187 3188 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF); 3189 temp = gen_reg_rtx (Pmode); 3190 emit_libcall_block (insn, temp, r2, new); 3191 3192 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); 3193 base = gen_reg_rtx (Pmode); 3194 s390_load_address (base, new); 3195 3196 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF); 3197 new = gen_rtx_CONST (Pmode, new); 3198 new = force_const_mem (Pmode, new); 3199 temp = gen_reg_rtx (Pmode); 3200 emit_move_insn (temp, new); 3201 3202 new = gen_rtx_PLUS (Pmode, base, temp); 3203 if (reg != 0) 3204 { 3205 s390_load_address (reg, new); 3206 new = reg; 3207 } 3208 break; 3209 3210 case TLS_MODEL_INITIAL_EXEC: 3211 if (flag_pic == 1) 3212 { 3213 /* Assume GOT offset < 4k. This is handled the same way 3214 in both 31- and 64-bit code. */ 3215 3216 if (reload_in_progress || reload_completed) 3217 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; 3218 3219 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF); 3220 new = gen_rtx_CONST (Pmode, new); 3221 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); 3222 new = gen_const_mem (Pmode, new); 3223 temp = gen_reg_rtx (Pmode); 3224 emit_move_insn (temp, new); 3225 } 3226 else if (TARGET_CPU_ZARCH) 3227 { 3228 /* If the GOT offset might be >= 4k, we determine the position 3229 of the GOT entry via a PC-relative LARL. */ 3230 3231 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF); 3232 new = gen_rtx_CONST (Pmode, new); 3233 temp = gen_reg_rtx (Pmode); 3234 emit_move_insn (temp, new); 3235 3236 new = gen_const_mem (Pmode, temp); 3237 temp = gen_reg_rtx (Pmode); 3238 emit_move_insn (temp, new); 3239 } 3240 else if (flag_pic) 3241 { 3242 /* If the GOT offset might be >= 4k, we have to load it 3243 from the literal pool. */ 3244 3245 if (reload_in_progress || reload_completed) 3246 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; 3247 3248 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF); 3249 new = gen_rtx_CONST (Pmode, new); 3250 new = force_const_mem (Pmode, new); 3251 temp = gen_reg_rtx (Pmode); 3252 emit_move_insn (temp, new); 3253 3254 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); 3255 new = gen_const_mem (Pmode, new); 3256 3257 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD); 3258 temp = gen_reg_rtx (Pmode); 3259 emit_insn (gen_rtx_SET (Pmode, temp, new)); 3260 } 3261 else 3262 { 3263 /* In position-dependent code, load the absolute address of 3264 the GOT entry from the literal pool. */ 3265 3266 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF); 3267 new = gen_rtx_CONST (Pmode, new); 3268 new = force_const_mem (Pmode, new); 3269 temp = gen_reg_rtx (Pmode); 3270 emit_move_insn (temp, new); 3271 3272 new = temp; 3273 new = gen_const_mem (Pmode, new); 3274 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD); 3275 temp = gen_reg_rtx (Pmode); 3276 emit_insn (gen_rtx_SET (Pmode, temp, new)); 3277 } 3278 3279 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); 3280 if (reg != 0) 3281 { 3282 s390_load_address (reg, new); 3283 new = reg; 3284 } 3285 break; 3286 3287 case TLS_MODEL_LOCAL_EXEC: 3288 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF); 3289 new = gen_rtx_CONST (Pmode, new); 3290 new = force_const_mem (Pmode, new); 3291 temp = gen_reg_rtx (Pmode); 3292 emit_move_insn (temp, new); 3293 3294 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); 3295 if (reg != 0) 3296 { 3297 s390_load_address (reg, new); 3298 new = reg; 3299 } 3300 break; 3301 3302 default: 3303 gcc_unreachable (); 3304 } 3305 3306 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC) 3307 { 3308 switch (XINT (XEXP (addr, 0), 1)) 3309 { 3310 case UNSPEC_INDNTPOFF: 3311 gcc_assert (TARGET_CPU_ZARCH); 3312 new = addr; 3313 break; 3314 3315 default: 3316 gcc_unreachable (); 3317 } 3318 } 3319 3320 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS 3321 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT) 3322 { 3323 new = XEXP (XEXP (addr, 0), 0); 3324 if (GET_CODE (new) != SYMBOL_REF) 3325 new = gen_rtx_CONST (Pmode, new); 3326 3327 new = legitimize_tls_address (new, reg); 3328 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1))); 3329 new = force_operand (new, 0); 3330 } 3331 3332 else 3333 gcc_unreachable (); /* for now ... */ 3334 3335 return new; 3336} 3337 3338/* Emit insns to move operands[1] into operands[0]. */ 3339 3340void 3341emit_symbolic_move (rtx *operands) 3342{ 3343 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode); 3344 3345 if (GET_CODE (operands[0]) == MEM) 3346 operands[1] = force_reg (Pmode, operands[1]); 3347 else if (TLS_SYMBOLIC_CONST (operands[1])) 3348 operands[1] = legitimize_tls_address (operands[1], temp); 3349 else if (flag_pic) 3350 operands[1] = legitimize_pic_address (operands[1], temp); 3351} 3352 3353/* Try machine-dependent ways of modifying an illegitimate address X 3354 to be legitimate. If we find one, return the new, valid address. 3355 3356 OLDX is the address as it was before break_out_memory_refs was called. 3357 In some cases it is useful to look at this to decide what needs to be done. 3358 3359 MODE is the mode of the operand pointed to by X. 3360 3361 When -fpic is used, special handling is needed for symbolic references. 3362 See comments by legitimize_pic_address for details. */ 3363 3364rtx 3365legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, 3366 enum machine_mode mode ATTRIBUTE_UNUSED) 3367{ 3368 rtx constant_term = const0_rtx; 3369 3370 if (TLS_SYMBOLIC_CONST (x)) 3371 { 3372 x = legitimize_tls_address (x, 0); 3373 3374 if (legitimate_address_p (mode, x, FALSE)) 3375 return x; 3376 } 3377 else if (GET_CODE (x) == PLUS 3378 && (TLS_SYMBOLIC_CONST (XEXP (x, 0)) 3379 || TLS_SYMBOLIC_CONST (XEXP (x, 1)))) 3380 { 3381 return x; 3382 } 3383 else if (flag_pic) 3384 { 3385 if (SYMBOLIC_CONST (x) 3386 || (GET_CODE (x) == PLUS 3387 && (SYMBOLIC_CONST (XEXP (x, 0)) 3388 || SYMBOLIC_CONST (XEXP (x, 1))))) 3389 x = legitimize_pic_address (x, 0); 3390 3391 if (legitimate_address_p (mode, x, FALSE)) 3392 return x; 3393 } 3394 3395 x = eliminate_constant_term (x, &constant_term); 3396 3397 /* Optimize loading of large displacements by splitting them 3398 into the multiple of 4K and the rest; this allows the 3399 former to be CSE'd if possible. 3400 3401 Don't do this if the displacement is added to a register 3402 pointing into the stack frame, as the offsets will 3403 change later anyway. */ 3404 3405 if (GET_CODE (constant_term) == CONST_INT 3406 && !TARGET_LONG_DISPLACEMENT 3407 && !DISP_IN_RANGE (INTVAL (constant_term)) 3408 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x)))) 3409 { 3410 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff; 3411 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower; 3412 3413 rtx temp = gen_reg_rtx (Pmode); 3414 rtx val = force_operand (GEN_INT (upper), temp); 3415 if (val != temp) 3416 emit_move_insn (temp, val); 3417 3418 x = gen_rtx_PLUS (Pmode, x, temp); 3419 constant_term = GEN_INT (lower); 3420 } 3421 3422 if (GET_CODE (x) == PLUS) 3423 { 3424 if (GET_CODE (XEXP (x, 0)) == REG) 3425 { 3426 rtx temp = gen_reg_rtx (Pmode); 3427 rtx val = force_operand (XEXP (x, 1), temp); 3428 if (val != temp) 3429 emit_move_insn (temp, val); 3430 3431 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp); 3432 } 3433 3434 else if (GET_CODE (XEXP (x, 1)) == REG) 3435 { 3436 rtx temp = gen_reg_rtx (Pmode); 3437 rtx val = force_operand (XEXP (x, 0), temp); 3438 if (val != temp) 3439 emit_move_insn (temp, val); 3440 3441 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1)); 3442 } 3443 } 3444 3445 if (constant_term != const0_rtx) 3446 x = gen_rtx_PLUS (Pmode, x, constant_term); 3447 3448 return x; 3449} 3450 3451/* Try a machine-dependent way of reloading an illegitimate address AD 3452 operand. If we find one, push the reload and and return the new address. 3453 3454 MODE is the mode of the enclosing MEM. OPNUM is the operand number 3455 and TYPE is the reload type of the current reload. */ 3456 3457rtx 3458legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED, 3459 int opnum, int type) 3460{ 3461 if (!optimize || TARGET_LONG_DISPLACEMENT) 3462 return NULL_RTX; 3463 3464 if (GET_CODE (ad) == PLUS) 3465 { 3466 rtx tem = simplify_binary_operation (PLUS, Pmode, 3467 XEXP (ad, 0), XEXP (ad, 1)); 3468 if (tem) 3469 ad = tem; 3470 } 3471 3472 if (GET_CODE (ad) == PLUS 3473 && GET_CODE (XEXP (ad, 0)) == REG 3474 && GET_CODE (XEXP (ad, 1)) == CONST_INT 3475 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1)))) 3476 { 3477 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff; 3478 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower; 3479 rtx cst, tem, new; 3480 3481 cst = GEN_INT (upper); 3482 if (!legitimate_reload_constant_p (cst)) 3483 cst = force_const_mem (Pmode, cst); 3484 3485 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst); 3486 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower)); 3487 3488 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0, 3489 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, 3490 opnum, (enum reload_type) type); 3491 return new; 3492 } 3493 3494 return NULL_RTX; 3495} 3496 3497/* Emit code to move LEN bytes from DST to SRC. */ 3498 3499void 3500s390_expand_movmem (rtx dst, rtx src, rtx len) 3501{ 3502 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256) 3503 { 3504 if (INTVAL (len) > 0) 3505 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1))); 3506 } 3507 3508 else if (TARGET_MVCLE) 3509 { 3510 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1))); 3511 } 3512 3513 else 3514 { 3515 rtx dst_addr, src_addr, count, blocks, temp; 3516 rtx loop_start_label = gen_label_rtx (); 3517 rtx loop_end_label = gen_label_rtx (); 3518 rtx end_label = gen_label_rtx (); 3519 enum machine_mode mode; 3520 3521 mode = GET_MODE (len); 3522 if (mode == VOIDmode) 3523 mode = Pmode; 3524 3525 dst_addr = gen_reg_rtx (Pmode); 3526 src_addr = gen_reg_rtx (Pmode); 3527 count = gen_reg_rtx (mode); 3528 blocks = gen_reg_rtx (mode); 3529 3530 convert_move (count, len, 1); 3531 emit_cmp_and_jump_insns (count, const0_rtx, 3532 EQ, NULL_RTX, mode, 1, end_label); 3533 3534 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); 3535 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX)); 3536 dst = change_address (dst, VOIDmode, dst_addr); 3537 src = change_address (src, VOIDmode, src_addr); 3538 3539 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0); 3540 if (temp != count) 3541 emit_move_insn (count, temp); 3542 3543 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, 0); 3544 if (temp != blocks) 3545 emit_move_insn (blocks, temp); 3546 3547 emit_cmp_and_jump_insns (blocks, const0_rtx, 3548 EQ, NULL_RTX, mode, 1, loop_end_label); 3549 3550 emit_label (loop_start_label); 3551 3552 emit_insn (gen_movmem_short (dst, src, GEN_INT (255))); 3553 s390_load_address (dst_addr, 3554 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); 3555 s390_load_address (src_addr, 3556 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256))); 3557 3558 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0); 3559 if (temp != blocks) 3560 emit_move_insn (blocks, temp); 3561 3562 emit_cmp_and_jump_insns (blocks, const0_rtx, 3563 EQ, NULL_RTX, mode, 1, loop_end_label); 3564 3565 emit_jump (loop_start_label); 3566 emit_label (loop_end_label); 3567 3568 emit_insn (gen_movmem_short (dst, src, 3569 convert_to_mode (Pmode, count, 1))); 3570 emit_label (end_label); 3571 } 3572} 3573 3574/* Emit code to set LEN bytes at DST to VAL. 3575 Make use of clrmem if VAL is zero. */ 3576 3577void 3578s390_expand_setmem (rtx dst, rtx len, rtx val) 3579{ 3580 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0) 3581 return; 3582 3583 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode); 3584 3585 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257) 3586 { 3587 if (val == const0_rtx && INTVAL (len) <= 256) 3588 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1))); 3589 else 3590 { 3591 /* Initialize memory by storing the first byte. */ 3592 emit_move_insn (adjust_address (dst, QImode, 0), val); 3593 3594 if (INTVAL (len) > 1) 3595 { 3596 /* Initiate 1 byte overlap move. 3597 The first byte of DST is propagated through DSTP1. 3598 Prepare a movmem for: DST+1 = DST (length = LEN - 1). 3599 DST is set to size 1 so the rest of the memory location 3600 does not count as source operand. */ 3601 rtx dstp1 = adjust_address (dst, VOIDmode, 1); 3602 set_mem_size (dst, const1_rtx); 3603 3604 emit_insn (gen_movmem_short (dstp1, dst, 3605 GEN_INT (INTVAL (len) - 2))); 3606 } 3607 } 3608 } 3609 3610 else if (TARGET_MVCLE) 3611 { 3612 val = force_not_mem (convert_modes (Pmode, QImode, val, 1)); 3613 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val)); 3614 } 3615 3616 else 3617 { 3618 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX; 3619 rtx loop_start_label = gen_label_rtx (); 3620 rtx loop_end_label = gen_label_rtx (); 3621 rtx end_label = gen_label_rtx (); 3622 enum machine_mode mode; 3623 3624 mode = GET_MODE (len); 3625 if (mode == VOIDmode) 3626 mode = Pmode; 3627 3628 dst_addr = gen_reg_rtx (Pmode); 3629 src_addr = gen_reg_rtx (Pmode); 3630 count = gen_reg_rtx (mode); 3631 blocks = gen_reg_rtx (mode); 3632 3633 convert_move (count, len, 1); 3634 emit_cmp_and_jump_insns (count, const0_rtx, 3635 EQ, NULL_RTX, mode, 1, end_label); 3636 3637 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); 3638 dst = change_address (dst, VOIDmode, dst_addr); 3639 3640 if (val == const0_rtx) 3641 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0); 3642 else 3643 { 3644 dstp1 = adjust_address (dst, VOIDmode, 1); 3645 set_mem_size (dst, const1_rtx); 3646 3647 /* Initialize memory by storing the first byte. */ 3648 emit_move_insn (adjust_address (dst, QImode, 0), val); 3649 3650 /* If count is 1 we are done. */ 3651 emit_cmp_and_jump_insns (count, const1_rtx, 3652 EQ, NULL_RTX, mode, 1, end_label); 3653 3654 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0); 3655 } 3656 if (temp != count) 3657 emit_move_insn (count, temp); 3658 3659 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, 0); 3660 if (temp != blocks) 3661 emit_move_insn (blocks, temp); 3662 3663 emit_cmp_and_jump_insns (blocks, const0_rtx, 3664 EQ, NULL_RTX, mode, 1, loop_end_label); 3665 3666 emit_label (loop_start_label); 3667 3668 if (val == const0_rtx) 3669 emit_insn (gen_clrmem_short (dst, GEN_INT (255))); 3670 else 3671 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255))); 3672 s390_load_address (dst_addr, 3673 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); 3674 3675 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0); 3676 if (temp != blocks) 3677 emit_move_insn (blocks, temp); 3678 3679 emit_cmp_and_jump_insns (blocks, const0_rtx, 3680 EQ, NULL_RTX, mode, 1, loop_end_label); 3681 3682 emit_jump (loop_start_label); 3683 emit_label (loop_end_label); 3684 3685 if (val == const0_rtx) 3686 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1))); 3687 else 3688 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1))); 3689 emit_label (end_label); 3690 } 3691} 3692 3693/* Emit code to compare LEN bytes at OP0 with those at OP1, 3694 and return the result in TARGET. */ 3695 3696void 3697s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len) 3698{ 3699 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM); 3700 rtx tmp; 3701 3702 /* As the result of CMPINT is inverted compared to what we need, 3703 we have to swap the operands. */ 3704 tmp = op0; op0 = op1; op1 = tmp; 3705 3706 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256) 3707 { 3708 if (INTVAL (len) > 0) 3709 { 3710 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1))); 3711 emit_insn (gen_cmpint (target, ccreg)); 3712 } 3713 else 3714 emit_move_insn (target, const0_rtx); 3715 } 3716 else if (TARGET_MVCLE) 3717 { 3718 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1))); 3719 emit_insn (gen_cmpint (target, ccreg)); 3720 } 3721 else 3722 { 3723 rtx addr0, addr1, count, blocks, temp; 3724 rtx loop_start_label = gen_label_rtx (); 3725 rtx loop_end_label = gen_label_rtx (); 3726 rtx end_label = gen_label_rtx (); 3727 enum machine_mode mode; 3728 3729 mode = GET_MODE (len); 3730 if (mode == VOIDmode) 3731 mode = Pmode; 3732 3733 addr0 = gen_reg_rtx (Pmode); 3734 addr1 = gen_reg_rtx (Pmode); 3735 count = gen_reg_rtx (mode); 3736 blocks = gen_reg_rtx (mode); 3737 3738 convert_move (count, len, 1); 3739 emit_cmp_and_jump_insns (count, const0_rtx, 3740 EQ, NULL_RTX, mode, 1, end_label); 3741 3742 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX)); 3743 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); 3744 op0 = change_address (op0, VOIDmode, addr0); 3745 op1 = change_address (op1, VOIDmode, addr1); 3746 3747 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0); 3748 if (temp != count) 3749 emit_move_insn (count, temp); 3750 3751 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, 0); 3752 if (temp != blocks) 3753 emit_move_insn (blocks, temp); 3754 3755 emit_cmp_and_jump_insns (blocks, const0_rtx, 3756 EQ, NULL_RTX, mode, 1, loop_end_label); 3757 3758 emit_label (loop_start_label); 3759 3760 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255))); 3761 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx); 3762 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp, 3763 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx); 3764 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp); 3765 emit_jump_insn (temp); 3766 3767 s390_load_address (addr0, 3768 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256))); 3769 s390_load_address (addr1, 3770 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256))); 3771 3772 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0); 3773 if (temp != blocks) 3774 emit_move_insn (blocks, temp); 3775 3776 emit_cmp_and_jump_insns (blocks, const0_rtx, 3777 EQ, NULL_RTX, mode, 1, loop_end_label); 3778 3779 emit_jump (loop_start_label); 3780 emit_label (loop_end_label); 3781 3782 emit_insn (gen_cmpmem_short (op0, op1, 3783 convert_to_mode (Pmode, count, 1))); 3784 emit_label (end_label); 3785 3786 emit_insn (gen_cmpint (target, ccreg)); 3787 } 3788} 3789 3790 3791/* Expand conditional increment or decrement using alc/slb instructions. 3792 Should generate code setting DST to either SRC or SRC + INCREMENT, 3793 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1. 3794 Returns true if successful, false otherwise. 3795 3796 That makes it possible to implement some if-constructs without jumps e.g.: 3797 (borrow = CC0 | CC1 and carry = CC2 | CC3) 3798 unsigned int a, b, c; 3799 if (a < b) c++; -> CCU b > a -> CC2; c += carry; 3800 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow; 3801 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry; 3802 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow; 3803 3804 Checks for EQ and NE with a nonzero value need an additional xor e.g.: 3805 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry; 3806 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow; 3807 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry; 3808 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */ 3809 3810bool 3811s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1, 3812 rtx dst, rtx src, rtx increment) 3813{ 3814 enum machine_mode cmp_mode; 3815 enum machine_mode cc_mode; 3816 rtx op_res; 3817 rtx insn; 3818 rtvec p; 3819 int ret; 3820 3821 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode) 3822 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode)) 3823 cmp_mode = SImode; 3824 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode) 3825 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode)) 3826 cmp_mode = DImode; 3827 else 3828 return false; 3829 3830 /* Try ADD LOGICAL WITH CARRY. */ 3831 if (increment == const1_rtx) 3832 { 3833 /* Determine CC mode to use. */ 3834 if (cmp_code == EQ || cmp_code == NE) 3835 { 3836 if (cmp_op1 != const0_rtx) 3837 { 3838 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1, 3839 NULL_RTX, 0, OPTAB_WIDEN); 3840 cmp_op1 = const0_rtx; 3841 } 3842 3843 cmp_code = cmp_code == EQ ? LEU : GTU; 3844 } 3845 3846 if (cmp_code == LTU || cmp_code == LEU) 3847 { 3848 rtx tem = cmp_op0; 3849 cmp_op0 = cmp_op1; 3850 cmp_op1 = tem; 3851 cmp_code = swap_condition (cmp_code); 3852 } 3853 3854 switch (cmp_code) 3855 { 3856 case GTU: 3857 cc_mode = CCUmode; 3858 break; 3859 3860 case GEU: 3861 cc_mode = CCL3mode; 3862 break; 3863 3864 default: 3865 return false; 3866 } 3867 3868 /* Emit comparison instruction pattern. */ 3869 if (!register_operand (cmp_op0, cmp_mode)) 3870 cmp_op0 = force_reg (cmp_mode, cmp_op0); 3871 3872 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM), 3873 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1)); 3874 /* We use insn_invalid_p here to add clobbers if required. */ 3875 ret = insn_invalid_p (emit_insn (insn)); 3876 gcc_assert (!ret); 3877 3878 /* Emit ALC instruction pattern. */ 3879 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst), 3880 gen_rtx_REG (cc_mode, CC_REGNUM), 3881 const0_rtx); 3882 3883 if (src != const0_rtx) 3884 { 3885 if (!register_operand (src, GET_MODE (dst))) 3886 src = force_reg (GET_MODE (dst), src); 3887 3888 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx); 3889 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res); 3890 } 3891 3892 p = rtvec_alloc (2); 3893 RTVEC_ELT (p, 0) = 3894 gen_rtx_SET (VOIDmode, dst, op_res); 3895 RTVEC_ELT (p, 1) = 3896 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); 3897 emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); 3898 3899 return true; 3900 } 3901 3902 /* Try SUBTRACT LOGICAL WITH BORROW. */ 3903 if (increment == constm1_rtx) 3904 { 3905 /* Determine CC mode to use. */ 3906 if (cmp_code == EQ || cmp_code == NE) 3907 { 3908 if (cmp_op1 != const0_rtx) 3909 { 3910 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1, 3911 NULL_RTX, 0, OPTAB_WIDEN); 3912 cmp_op1 = const0_rtx; 3913 } 3914 3915 cmp_code = cmp_code == EQ ? LEU : GTU; 3916 } 3917 3918 if (cmp_code == GTU || cmp_code == GEU) 3919 { 3920 rtx tem = cmp_op0; 3921 cmp_op0 = cmp_op1; 3922 cmp_op1 = tem; 3923 cmp_code = swap_condition (cmp_code); 3924 } 3925 3926 switch (cmp_code) 3927 { 3928 case LEU: 3929 cc_mode = CCUmode; 3930 break; 3931 3932 case LTU: 3933 cc_mode = CCL3mode; 3934 break; 3935 3936 default: 3937 return false; 3938 } 3939 3940 /* Emit comparison instruction pattern. */ 3941 if (!register_operand (cmp_op0, cmp_mode)) 3942 cmp_op0 = force_reg (cmp_mode, cmp_op0); 3943 3944 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM), 3945 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1)); 3946 /* We use insn_invalid_p here to add clobbers if required. */ 3947 ret = insn_invalid_p (emit_insn (insn)); 3948 gcc_assert (!ret); 3949 3950 /* Emit SLB instruction pattern. */ 3951 if (!register_operand (src, GET_MODE (dst))) 3952 src = force_reg (GET_MODE (dst), src); 3953 3954 op_res = gen_rtx_MINUS (GET_MODE (dst), 3955 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx), 3956 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst), 3957 gen_rtx_REG (cc_mode, CC_REGNUM), 3958 const0_rtx)); 3959 p = rtvec_alloc (2); 3960 RTVEC_ELT (p, 0) = 3961 gen_rtx_SET (VOIDmode, dst, op_res); 3962 RTVEC_ELT (p, 1) = 3963 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); 3964 emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); 3965 3966 return true; 3967 } 3968 3969 return false; 3970} 3971 3972/* Expand code for the insv template. Return true if successful, false else. */ 3973 3974bool 3975s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) 3976{ 3977 int bitsize = INTVAL (op1); 3978 int bitpos = INTVAL (op2); 3979 3980 /* We need byte alignment. */ 3981 if (bitsize % BITS_PER_UNIT) 3982 return false; 3983 3984 if (bitpos == 0 3985 && memory_operand (dest, VOIDmode) 3986 && (register_operand (src, word_mode) 3987 || const_int_operand (src, VOIDmode))) 3988 { 3989 /* Emit standard pattern if possible. */ 3990 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT); 3991 if (GET_MODE_BITSIZE (mode) == bitsize) 3992 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src)); 3993 3994 /* (set (ze (mem)) (const_int)). */ 3995 else if (const_int_operand (src, VOIDmode)) 3996 { 3997 int size = bitsize / BITS_PER_UNIT; 3998 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode, 3999 GET_MODE_SIZE (word_mode) - size); 4000 4001 dest = adjust_address (dest, BLKmode, 0); 4002 set_mem_size (dest, GEN_INT (size)); 4003 s390_expand_movmem (dest, src_mem, GEN_INT (size)); 4004 } 4005 4006 /* (set (ze (mem)) (reg)). */ 4007 else if (register_operand (src, word_mode)) 4008 { 4009 if (bitsize <= GET_MODE_BITSIZE (SImode)) 4010 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1, 4011 const0_rtx), src); 4012 else 4013 { 4014 /* Emit st,stcmh sequence. */ 4015 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode); 4016 int size = stcmh_width / BITS_PER_UNIT; 4017 4018 emit_move_insn (adjust_address (dest, SImode, size), 4019 gen_lowpart (SImode, src)); 4020 set_mem_size (dest, GEN_INT (size)); 4021 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT 4022 (stcmh_width), const0_rtx), 4023 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT 4024 (GET_MODE_BITSIZE (SImode)))); 4025 } 4026 } 4027 else 4028 return false; 4029 4030 return true; 4031 } 4032 4033 /* (set (ze (reg)) (const_int)). */ 4034 if (TARGET_ZARCH 4035 && register_operand (dest, word_mode) 4036 && (bitpos % 16) == 0 4037 && (bitsize % 16) == 0 4038 && const_int_operand (src, VOIDmode)) 4039 { 4040 HOST_WIDE_INT val = INTVAL (src); 4041 int regpos = bitpos + bitsize; 4042 4043 while (regpos > bitpos) 4044 { 4045 enum machine_mode putmode; 4046 int putsize; 4047 4048 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32)) 4049 putmode = SImode; 4050 else 4051 putmode = HImode; 4052 4053 putsize = GET_MODE_BITSIZE (putmode); 4054 regpos -= putsize; 4055 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, 4056 GEN_INT (putsize), 4057 GEN_INT (regpos)), 4058 gen_int_mode (val, putmode)); 4059 val >>= putsize; 4060 } 4061 gcc_assert (regpos == bitpos); 4062 return true; 4063 } 4064 4065 return false; 4066} 4067 4068/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a 4069 register that holds VAL of mode MODE shifted by COUNT bits. */ 4070 4071static inline rtx 4072s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count) 4073{ 4074 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)), 4075 NULL_RTX, 1, OPTAB_DIRECT); 4076 return expand_simple_binop (SImode, ASHIFT, val, count, 4077 NULL_RTX, 1, OPTAB_DIRECT); 4078} 4079 4080/* Structure to hold the initial parameters for a compare_and_swap operation 4081 in HImode and QImode. */ 4082 4083struct alignment_context 4084{ 4085 rtx memsi; /* SI aligned memory location. */ 4086 rtx shift; /* Bit offset with regard to lsb. */ 4087 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */ 4088 rtx modemaski; /* ~modemask */ 4089 bool aligned; /* True if memory is aliged, false else. */ 4090}; 4091 4092/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize 4093 structure AC for transparent simplifying, if the memory alignment is known 4094 to be at least 32bit. MEM is the memory location for the actual operation 4095 and MODE its mode. */ 4096 4097static void 4098init_alignment_context (struct alignment_context *ac, rtx mem, 4099 enum machine_mode mode) 4100{ 4101 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode)); 4102 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode)); 4103 4104 if (ac->aligned) 4105 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */ 4106 else 4107 { 4108 /* Alignment is unknown. */ 4109 rtx byteoffset, addr, align; 4110 4111 /* Force the address into a register. */ 4112 addr = force_reg (Pmode, XEXP (mem, 0)); 4113 4114 /* Align it to SImode. */ 4115 align = expand_simple_binop (Pmode, AND, addr, 4116 GEN_INT (-GET_MODE_SIZE (SImode)), 4117 NULL_RTX, 1, OPTAB_DIRECT); 4118 /* Generate MEM. */ 4119 ac->memsi = gen_rtx_MEM (SImode, align); 4120 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem); 4121 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER); 4122 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode)); 4123 4124 /* Calculate shiftcount. */ 4125 byteoffset = expand_simple_binop (Pmode, AND, addr, 4126 GEN_INT (GET_MODE_SIZE (SImode) - 1), 4127 NULL_RTX, 1, OPTAB_DIRECT); 4128 /* As we already have some offset, evaluate the remaining distance. */ 4129 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset, 4130 NULL_RTX, 1, OPTAB_DIRECT); 4131 4132 } 4133 /* Shift is the byte count, but we need the bitcount. */ 4134 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT), 4135 NULL_RTX, 1, OPTAB_DIRECT); 4136 /* Calculate masks. */ 4137 ac->modemask = expand_simple_binop (SImode, ASHIFT, 4138 GEN_INT (GET_MODE_MASK (mode)), ac->shift, 4139 NULL_RTX, 1, OPTAB_DIRECT); 4140 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1); 4141} 4142 4143/* Expand an atomic compare and swap operation for HImode and QImode. MEM is 4144 the memory location, CMP the old value to compare MEM with and NEW the value 4145 to set if CMP == MEM. 4146 CMP is never in memory for compare_and_swap_cc because 4147 expand_bool_compare_and_swap puts it into a register for later compare. */ 4148 4149void 4150s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new) 4151{ 4152 struct alignment_context ac; 4153 rtx cmpv, newv, val, resv, cc; 4154 rtx res = gen_reg_rtx (SImode); 4155 rtx csloop = gen_label_rtx (); 4156 rtx csend = gen_label_rtx (); 4157 4158 gcc_assert (register_operand (target, VOIDmode)); 4159 gcc_assert (MEM_P (mem)); 4160 4161 init_alignment_context (&ac, mem, mode); 4162 4163 /* Shift the values to the correct bit positions. */ 4164 if (!(ac.aligned && MEM_P (cmp))) 4165 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift); 4166 if (!(ac.aligned && MEM_P (new))) 4167 new = s390_expand_mask_and_shift (new, mode, ac.shift); 4168 4169 /* Load full word. Subsequent loads are performed by CS. */ 4170 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski, 4171 NULL_RTX, 1, OPTAB_DIRECT); 4172 4173 /* Start CS loop. */ 4174 emit_label (csloop); 4175 /* val = "<mem>00..0<mem>" 4176 * cmp = "00..0<cmp>00..0" 4177 * new = "00..0<new>00..0" 4178 */ 4179 4180 /* Patch cmp and new with val at correct position. */ 4181 if (ac.aligned && MEM_P (cmp)) 4182 { 4183 cmpv = force_reg (SImode, val); 4184 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp); 4185 } 4186 else 4187 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val, 4188 NULL_RTX, 1, OPTAB_DIRECT)); 4189 if (ac.aligned && MEM_P (new)) 4190 { 4191 newv = force_reg (SImode, val); 4192 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new); 4193 } 4194 else 4195 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val, 4196 NULL_RTX, 1, OPTAB_DIRECT)); 4197 4198 /* Jump to end if we're done (likely?). */ 4199 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi, 4200 cmpv, newv)); 4201 4202 /* Check for changes outside mode. */ 4203 resv = expand_simple_binop (SImode, AND, res, ac.modemaski, 4204 NULL_RTX, 1, OPTAB_DIRECT); 4205 cc = s390_emit_compare (NE, resv, val); 4206 emit_move_insn (val, resv); 4207 /* Loop internal if so. */ 4208 s390_emit_jump (csloop, cc); 4209 4210 emit_label (csend); 4211 4212 /* Return the correct part of the bitfield. */ 4213 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift, 4214 NULL_RTX, 1, OPTAB_DIRECT), 1); 4215} 4216 4217/* Expand an atomic operation CODE of mode MODE. MEM is the memory location 4218 and VAL the value to play with. If AFTER is true then store the the value 4219 MEM holds after the operation, if AFTER is false then store the value MEM 4220 holds before the operation. If TARGET is zero then discard that value, else 4221 store it to TARGET. */ 4222 4223void 4224s390_expand_atomic (enum machine_mode mode, enum rtx_code code, 4225 rtx target, rtx mem, rtx val, bool after) 4226{ 4227 struct alignment_context ac; 4228 rtx cmp; 4229 rtx new = gen_reg_rtx (SImode); 4230 rtx orig = gen_reg_rtx (SImode); 4231 rtx csloop = gen_label_rtx (); 4232 4233 gcc_assert (!target || register_operand (target, VOIDmode)); 4234 gcc_assert (MEM_P (mem)); 4235 4236 init_alignment_context (&ac, mem, mode); 4237 4238 /* Shift val to the correct bit positions. 4239 Preserve "icm", but prevent "ex icm". */ 4240 if (!(ac.aligned && code == SET && MEM_P (val))) 4241 val = s390_expand_mask_and_shift (val, mode, ac.shift); 4242 4243 /* Further preparation insns. */ 4244 if (code == PLUS || code == MINUS) 4245 emit_move_insn (orig, val); 4246 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */ 4247 val = expand_simple_binop (SImode, XOR, val, ac.modemaski, 4248 NULL_RTX, 1, OPTAB_DIRECT); 4249 4250 /* Load full word. Subsequent loads are performed by CS. */ 4251 cmp = force_reg (SImode, ac.memsi); 4252 4253 /* Start CS loop. */ 4254 emit_label (csloop); 4255 emit_move_insn (new, cmp); 4256 4257 /* Patch new with val at correct position. */ 4258 switch (code) 4259 { 4260 case PLUS: 4261 case MINUS: 4262 val = expand_simple_binop (SImode, code, new, orig, 4263 NULL_RTX, 1, OPTAB_DIRECT); 4264 val = expand_simple_binop (SImode, AND, val, ac.modemask, 4265 NULL_RTX, 1, OPTAB_DIRECT); 4266 /* FALLTHRU */ 4267 case SET: 4268 if (ac.aligned && MEM_P (val)) 4269 store_bit_field (new, GET_MODE_BITSIZE (mode), 0, SImode, val); 4270 else 4271 { 4272 new = expand_simple_binop (SImode, AND, new, ac.modemaski, 4273 NULL_RTX, 1, OPTAB_DIRECT); 4274 new = expand_simple_binop (SImode, IOR, new, val, 4275 NULL_RTX, 1, OPTAB_DIRECT); 4276 } 4277 break; 4278 case AND: 4279 case IOR: 4280 case XOR: 4281 new = expand_simple_binop (SImode, code, new, val, 4282 NULL_RTX, 1, OPTAB_DIRECT); 4283 break; 4284 case MULT: /* NAND */ 4285 new = expand_simple_binop (SImode, XOR, new, ac.modemask, 4286 NULL_RTX, 1, OPTAB_DIRECT); 4287 new = expand_simple_binop (SImode, AND, new, val, 4288 NULL_RTX, 1, OPTAB_DIRECT); 4289 break; 4290 default: 4291 gcc_unreachable (); 4292 } 4293 4294 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp, 4295 ac.memsi, cmp, new)); 4296 4297 /* Return the correct part of the bitfield. */ 4298 if (target) 4299 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, 4300 after ? new : cmp, ac.shift, 4301 NULL_RTX, 1, OPTAB_DIRECT), 1); 4302} 4303 4304/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. 4305 We need to emit DTP-relative relocations. */ 4306 4307static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; 4308 4309static void 4310s390_output_dwarf_dtprel (FILE *file, int size, rtx x) 4311{ 4312 switch (size) 4313 { 4314 case 4: 4315 fputs ("\t.long\t", file); 4316 break; 4317 case 8: 4318 fputs ("\t.quad\t", file); 4319 break; 4320 default: 4321 gcc_unreachable (); 4322 } 4323 output_addr_const (file, x); 4324 fputs ("@DTPOFF", file); 4325} 4326 4327#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING 4328/* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE. */ 4329 4330static const char * 4331s390_mangle_fundamental_type (tree type) 4332{ 4333 if (TYPE_MAIN_VARIANT (type) == long_double_type_node 4334 && TARGET_LONG_DOUBLE_128) 4335 return "g"; 4336 4337 /* For all other types, use normal C++ mangling. */ 4338 return NULL; 4339} 4340#endif 4341 4342/* In the name of slightly smaller debug output, and to cater to 4343 general assembler lossage, recognize various UNSPEC sequences 4344 and turn them back into a direct symbol reference. */ 4345 4346static rtx 4347s390_delegitimize_address (rtx orig_x) 4348{ 4349 rtx x = orig_x, y; 4350 4351 if (GET_CODE (x) != MEM) 4352 return orig_x; 4353 4354 x = XEXP (x, 0); 4355 if (GET_CODE (x) == PLUS 4356 && GET_CODE (XEXP (x, 1)) == CONST 4357 && GET_CODE (XEXP (x, 0)) == REG 4358 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM) 4359 { 4360 y = XEXP (XEXP (x, 1), 0); 4361 if (GET_CODE (y) == UNSPEC 4362 && XINT (y, 1) == UNSPEC_GOT) 4363 return XVECEXP (y, 0, 0); 4364 return orig_x; 4365 } 4366 4367 if (GET_CODE (x) == CONST) 4368 { 4369 y = XEXP (x, 0); 4370 if (GET_CODE (y) == UNSPEC 4371 && XINT (y, 1) == UNSPEC_GOTENT) 4372 return XVECEXP (y, 0, 0); 4373 return orig_x; 4374 } 4375 4376 return orig_x; 4377} 4378 4379/* Output operand OP to stdio stream FILE. 4380 OP is an address (register + offset) which is not used to address data; 4381 instead the rightmost bits are interpreted as the value. */ 4382 4383static void 4384print_shift_count_operand (FILE *file, rtx op) 4385{ 4386 HOST_WIDE_INT offset; 4387 rtx base; 4388 4389 /* Extract base register and offset. */ 4390 if (!s390_decompose_shift_count (op, &base, &offset)) 4391 gcc_unreachable (); 4392 4393 /* Sanity check. */ 4394 if (base) 4395 { 4396 gcc_assert (GET_CODE (base) == REG); 4397 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER); 4398 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS); 4399 } 4400 4401 /* Offsets are constricted to twelve bits. */ 4402 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1)); 4403 if (base) 4404 fprintf (file, "(%s)", reg_names[REGNO (base)]); 4405} 4406 4407/* See 'get_some_local_dynamic_name'. */ 4408 4409static int 4410get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) 4411{ 4412 rtx x = *px; 4413 4414 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) 4415 { 4416 x = get_pool_constant (x); 4417 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0); 4418 } 4419 4420 if (GET_CODE (x) == SYMBOL_REF 4421 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC) 4422 { 4423 cfun->machine->some_ld_name = XSTR (x, 0); 4424 return 1; 4425 } 4426 4427 return 0; 4428} 4429 4430/* Locate some local-dynamic symbol still in use by this function 4431 so that we can print its name in local-dynamic base patterns. */ 4432 4433static const char * 4434get_some_local_dynamic_name (void) 4435{ 4436 rtx insn; 4437 4438 if (cfun->machine->some_ld_name) 4439 return cfun->machine->some_ld_name; 4440 4441 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) 4442 if (INSN_P (insn) 4443 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) 4444 return cfun->machine->some_ld_name; 4445 4446 gcc_unreachable (); 4447} 4448 4449/* Output machine-dependent UNSPECs occurring in address constant X 4450 in assembler syntax to stdio stream FILE. Returns true if the 4451 constant X could be recognized, false otherwise. */ 4452 4453bool 4454s390_output_addr_const_extra (FILE *file, rtx x) 4455{ 4456 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1) 4457 switch (XINT (x, 1)) 4458 { 4459 case UNSPEC_GOTENT: 4460 output_addr_const (file, XVECEXP (x, 0, 0)); 4461 fprintf (file, "@GOTENT"); 4462 return true; 4463 case UNSPEC_GOT: 4464 output_addr_const (file, XVECEXP (x, 0, 0)); 4465 fprintf (file, "@GOT"); 4466 return true; 4467 case UNSPEC_GOTOFF: 4468 output_addr_const (file, XVECEXP (x, 0, 0)); 4469 fprintf (file, "@GOTOFF"); 4470 return true; 4471 case UNSPEC_PLT: 4472 output_addr_const (file, XVECEXP (x, 0, 0)); 4473 fprintf (file, "@PLT"); 4474 return true; 4475 case UNSPEC_PLTOFF: 4476 output_addr_const (file, XVECEXP (x, 0, 0)); 4477 fprintf (file, "@PLTOFF"); 4478 return true; 4479 case UNSPEC_TLSGD: 4480 output_addr_const (file, XVECEXP (x, 0, 0)); 4481 fprintf (file, "@TLSGD"); 4482 return true; 4483 case UNSPEC_TLSLDM: 4484 assemble_name (file, get_some_local_dynamic_name ()); 4485 fprintf (file, "@TLSLDM"); 4486 return true; 4487 case UNSPEC_DTPOFF: 4488 output_addr_const (file, XVECEXP (x, 0, 0)); 4489 fprintf (file, "@DTPOFF"); 4490 return true; 4491 case UNSPEC_NTPOFF: 4492 output_addr_const (file, XVECEXP (x, 0, 0)); 4493 fprintf (file, "@NTPOFF"); 4494 return true; 4495 case UNSPEC_GOTNTPOFF: 4496 output_addr_const (file, XVECEXP (x, 0, 0)); 4497 fprintf (file, "@GOTNTPOFF"); 4498 return true; 4499 case UNSPEC_INDNTPOFF: 4500 output_addr_const (file, XVECEXP (x, 0, 0)); 4501 fprintf (file, "@INDNTPOFF"); 4502 return true; 4503 } 4504 4505 return false; 4506} 4507 4508/* Output address operand ADDR in assembler syntax to 4509 stdio stream FILE. */ 4510 4511void 4512print_operand_address (FILE *file, rtx addr) 4513{ 4514 struct s390_address ad; 4515 4516 if (!s390_decompose_address (addr, &ad) 4517 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base)) 4518 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx))) 4519 output_operand_lossage ("cannot decompose address"); 4520 4521 if (ad.disp) 4522 output_addr_const (file, ad.disp); 4523 else 4524 fprintf (file, "0"); 4525 4526 if (ad.base && ad.indx) 4527 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)], 4528 reg_names[REGNO (ad.base)]); 4529 else if (ad.base) 4530 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]); 4531} 4532 4533/* Output operand X in assembler syntax to stdio stream FILE. 4534 CODE specified the format flag. The following format flags 4535 are recognized: 4536 4537 'C': print opcode suffix for branch condition. 4538 'D': print opcode suffix for inverse branch condition. 4539 'J': print tls_load/tls_gdcall/tls_ldcall suffix 4540 'G': print the size of the operand in bytes. 4541 'O': print only the displacement of a memory reference. 4542 'R': print only the base register of a memory reference. 4543 'S': print S-type memory reference (base+displacement). 4544 'N': print the second word of a DImode operand. 4545 'M': print the second word of a TImode operand. 4546 'Y': print shift count operand. 4547 4548 'b': print integer X as if it's an unsigned byte. 4549 'x': print integer X as if it's an unsigned halfword. 4550 'h': print integer X as if it's a signed halfword. 4551 'i': print the first nonzero HImode part of X. 4552 'j': print the first HImode part unequal to -1 of X. 4553 'k': print the first nonzero SImode part of X. 4554 'm': print the first SImode part unequal to -1 of X. 4555 'o': print integer X as if it's an unsigned 32bit word. */ 4556 4557void 4558print_operand (FILE *file, rtx x, int code) 4559{ 4560 switch (code) 4561 { 4562 case 'C': 4563 fprintf (file, s390_branch_condition_mnemonic (x, FALSE)); 4564 return; 4565 4566 case 'D': 4567 fprintf (file, s390_branch_condition_mnemonic (x, TRUE)); 4568 return; 4569 4570 case 'J': 4571 if (GET_CODE (x) == SYMBOL_REF) 4572 { 4573 fprintf (file, "%s", ":tls_load:"); 4574 output_addr_const (file, x); 4575 } 4576 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD) 4577 { 4578 fprintf (file, "%s", ":tls_gdcall:"); 4579 output_addr_const (file, XVECEXP (x, 0, 0)); 4580 } 4581 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM) 4582 { 4583 fprintf (file, "%s", ":tls_ldcall:"); 4584 assemble_name (file, get_some_local_dynamic_name ()); 4585 } 4586 else 4587 gcc_unreachable (); 4588 return; 4589 4590 case 'G': 4591 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x))); 4592 return; 4593 4594 case 'O': 4595 { 4596 struct s390_address ad; 4597 int ret; 4598 4599 gcc_assert (GET_CODE (x) == MEM); 4600 ret = s390_decompose_address (XEXP (x, 0), &ad); 4601 gcc_assert (ret); 4602 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base)); 4603 gcc_assert (!ad.indx); 4604 4605 if (ad.disp) 4606 output_addr_const (file, ad.disp); 4607 else 4608 fprintf (file, "0"); 4609 } 4610 return; 4611 4612 case 'R': 4613 { 4614 struct s390_address ad; 4615 int ret; 4616 4617 gcc_assert (GET_CODE (x) == MEM); 4618 ret = s390_decompose_address (XEXP (x, 0), &ad); 4619 gcc_assert (ret); 4620 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base)); 4621 gcc_assert (!ad.indx); 4622 4623 if (ad.base) 4624 fprintf (file, "%s", reg_names[REGNO (ad.base)]); 4625 else 4626 fprintf (file, "0"); 4627 } 4628 return; 4629 4630 case 'S': 4631 { 4632 struct s390_address ad; 4633 int ret; 4634 4635 gcc_assert (GET_CODE (x) == MEM); 4636 ret = s390_decompose_address (XEXP (x, 0), &ad); 4637 gcc_assert (ret); 4638 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base)); 4639 gcc_assert (!ad.indx); 4640 4641 if (ad.disp) 4642 output_addr_const (file, ad.disp); 4643 else 4644 fprintf (file, "0"); 4645 4646 if (ad.base) 4647 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]); 4648 } 4649 return; 4650 4651 case 'N': 4652 if (GET_CODE (x) == REG) 4653 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1); 4654 else if (GET_CODE (x) == MEM) 4655 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4)); 4656 else 4657 gcc_unreachable (); 4658 break; 4659 4660 case 'M': 4661 if (GET_CODE (x) == REG) 4662 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1); 4663 else if (GET_CODE (x) == MEM) 4664 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8)); 4665 else 4666 gcc_unreachable (); 4667 break; 4668 4669 case 'Y': 4670 print_shift_count_operand (file, x); 4671 return; 4672 } 4673 4674 switch (GET_CODE (x)) 4675 { 4676 case REG: 4677 fprintf (file, "%s", reg_names[REGNO (x)]); 4678 break; 4679 4680 case MEM: 4681 output_address (XEXP (x, 0)); 4682 break; 4683 4684 case CONST: 4685 case CODE_LABEL: 4686 case LABEL_REF: 4687 case SYMBOL_REF: 4688 output_addr_const (file, x); 4689 break; 4690 4691 case CONST_INT: 4692 if (code == 'b') 4693 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff); 4694 else if (code == 'x') 4695 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff); 4696 else if (code == 'h') 4697 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000); 4698 else if (code == 'i') 4699 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 4700 s390_extract_part (x, HImode, 0)); 4701 else if (code == 'j') 4702 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 4703 s390_extract_part (x, HImode, -1)); 4704 else if (code == 'k') 4705 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 4706 s390_extract_part (x, SImode, 0)); 4707 else if (code == 'm') 4708 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 4709 s390_extract_part (x, SImode, -1)); 4710 else if (code == 'o') 4711 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff); 4712 else 4713 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); 4714 break; 4715 4716 case CONST_DOUBLE: 4717 gcc_assert (GET_MODE (x) == VOIDmode); 4718 if (code == 'b') 4719 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff); 4720 else if (code == 'x') 4721 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff); 4722 else if (code == 'h') 4723 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000); 4724 else 4725 gcc_unreachable (); 4726 break; 4727 4728 default: 4729 fatal_insn ("UNKNOWN in print_operand !?", x); 4730 break; 4731 } 4732} 4733 4734/* Target hook for assembling integer objects. We need to define it 4735 here to work a round a bug in some versions of GAS, which couldn't 4736 handle values smaller than INT_MIN when printed in decimal. */ 4737 4738static bool 4739s390_assemble_integer (rtx x, unsigned int size, int aligned_p) 4740{ 4741 if (size == 8 && aligned_p 4742 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN) 4743 { 4744 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", 4745 INTVAL (x)); 4746 return true; 4747 } 4748 return default_assemble_integer (x, size, aligned_p); 4749} 4750 4751/* Returns true if register REGNO is used for forming 4752 a memory address in expression X. */ 4753 4754static bool 4755reg_used_in_mem_p (int regno, rtx x) 4756{ 4757 enum rtx_code code = GET_CODE (x); 4758 int i, j; 4759 const char *fmt; 4760 4761 if (code == MEM) 4762 { 4763 if (refers_to_regno_p (regno, regno+1, 4764 XEXP (x, 0), 0)) 4765 return true; 4766 } 4767 else if (code == SET 4768 && GET_CODE (SET_DEST (x)) == PC) 4769 { 4770 if (refers_to_regno_p (regno, regno+1, 4771 SET_SRC (x), 0)) 4772 return true; 4773 } 4774 4775 fmt = GET_RTX_FORMAT (code); 4776 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4777 { 4778 if (fmt[i] == 'e' 4779 && reg_used_in_mem_p (regno, XEXP (x, i))) 4780 return true; 4781 4782 else if (fmt[i] == 'E') 4783 for (j = 0; j < XVECLEN (x, i); j++) 4784 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j))) 4785 return true; 4786 } 4787 return false; 4788} 4789 4790/* Returns true if expression DEP_RTX sets an address register 4791 used by instruction INSN to address memory. */ 4792 4793static bool 4794addr_generation_dependency_p (rtx dep_rtx, rtx insn) 4795{ 4796 rtx target, pat; 4797 4798 if (GET_CODE (dep_rtx) == INSN) 4799 dep_rtx = PATTERN (dep_rtx); 4800 4801 if (GET_CODE (dep_rtx) == SET) 4802 { 4803 target = SET_DEST (dep_rtx); 4804 if (GET_CODE (target) == STRICT_LOW_PART) 4805 target = XEXP (target, 0); 4806 while (GET_CODE (target) == SUBREG) 4807 target = SUBREG_REG (target); 4808 4809 if (GET_CODE (target) == REG) 4810 { 4811 int regno = REGNO (target); 4812 4813 if (s390_safe_attr_type (insn) == TYPE_LA) 4814 { 4815 pat = PATTERN (insn); 4816 if (GET_CODE (pat) == PARALLEL) 4817 { 4818 gcc_assert (XVECLEN (pat, 0) == 2); 4819 pat = XVECEXP (pat, 0, 0); 4820 } 4821 gcc_assert (GET_CODE (pat) == SET); 4822 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0); 4823 } 4824 else if (get_attr_atype (insn) == ATYPE_AGEN) 4825 return reg_used_in_mem_p (regno, PATTERN (insn)); 4826 } 4827 } 4828 return false; 4829} 4830 4831/* Return 1, if dep_insn sets register used in insn in the agen unit. */ 4832 4833int 4834s390_agen_dep_p (rtx dep_insn, rtx insn) 4835{ 4836 rtx dep_rtx = PATTERN (dep_insn); 4837 int i; 4838 4839 if (GET_CODE (dep_rtx) == SET 4840 && addr_generation_dependency_p (dep_rtx, insn)) 4841 return 1; 4842 else if (GET_CODE (dep_rtx) == PARALLEL) 4843 { 4844 for (i = 0; i < XVECLEN (dep_rtx, 0); i++) 4845 { 4846 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn)) 4847 return 1; 4848 } 4849 } 4850 return 0; 4851} 4852 4853/* A C statement (sans semicolon) to update the integer scheduling priority 4854 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier, 4855 reduce the priority to execute INSN later. Do not define this macro if 4856 you do not need to adjust the scheduling priorities of insns. 4857 4858 A STD instruction should be scheduled earlier, 4859 in order to use the bypass. */ 4860 4861static int 4862s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) 4863{ 4864 if (! INSN_P (insn)) 4865 return priority; 4866 4867 if (s390_tune != PROCESSOR_2084_Z990 4868 && s390_tune != PROCESSOR_2094_Z9_109) 4869 return priority; 4870 4871 switch (s390_safe_attr_type (insn)) 4872 { 4873 case TYPE_FSTOREDF: 4874 case TYPE_FSTORESF: 4875 priority = priority << 3; 4876 break; 4877 case TYPE_STORE: 4878 case TYPE_STM: 4879 priority = priority << 1; 4880 break; 4881 default: 4882 break; 4883 } 4884 return priority; 4885} 4886 4887/* The number of instructions that can be issued per cycle. */ 4888 4889static int 4890s390_issue_rate (void) 4891{ 4892 if (s390_tune == PROCESSOR_2084_Z990 4893 || s390_tune == PROCESSOR_2094_Z9_109) 4894 return 3; 4895 return 1; 4896} 4897 4898static int 4899s390_first_cycle_multipass_dfa_lookahead (void) 4900{ 4901 return 4; 4902} 4903 4904 4905/* Annotate every literal pool reference in X by an UNSPEC_LTREF expression. 4906 Fix up MEMs as required. */ 4907 4908static void 4909annotate_constant_pool_refs (rtx *x) 4910{ 4911 int i, j; 4912 const char *fmt; 4913 4914 gcc_assert (GET_CODE (*x) != SYMBOL_REF 4915 || !CONSTANT_POOL_ADDRESS_P (*x)); 4916 4917 /* Literal pool references can only occur inside a MEM ... */ 4918 if (GET_CODE (*x) == MEM) 4919 { 4920 rtx memref = XEXP (*x, 0); 4921 4922 if (GET_CODE (memref) == SYMBOL_REF 4923 && CONSTANT_POOL_ADDRESS_P (memref)) 4924 { 4925 rtx base = cfun->machine->base_reg; 4926 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base), 4927 UNSPEC_LTREF); 4928 4929 *x = replace_equiv_address (*x, addr); 4930 return; 4931 } 4932 4933 if (GET_CODE (memref) == CONST 4934 && GET_CODE (XEXP (memref, 0)) == PLUS 4935 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT 4936 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF 4937 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0))) 4938 { 4939 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1)); 4940 rtx sym = XEXP (XEXP (memref, 0), 0); 4941 rtx base = cfun->machine->base_reg; 4942 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base), 4943 UNSPEC_LTREF); 4944 4945 *x = replace_equiv_address (*x, plus_constant (addr, off)); 4946 return; 4947 } 4948 } 4949 4950 /* ... or a load-address type pattern. */ 4951 if (GET_CODE (*x) == SET) 4952 { 4953 rtx addrref = SET_SRC (*x); 4954 4955 if (GET_CODE (addrref) == SYMBOL_REF 4956 && CONSTANT_POOL_ADDRESS_P (addrref)) 4957 { 4958 rtx base = cfun->machine->base_reg; 4959 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base), 4960 UNSPEC_LTREF); 4961 4962 SET_SRC (*x) = addr; 4963 return; 4964 } 4965 4966 if (GET_CODE (addrref) == CONST 4967 && GET_CODE (XEXP (addrref, 0)) == PLUS 4968 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT 4969 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF 4970 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0))) 4971 { 4972 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1)); 4973 rtx sym = XEXP (XEXP (addrref, 0), 0); 4974 rtx base = cfun->machine->base_reg; 4975 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base), 4976 UNSPEC_LTREF); 4977 4978 SET_SRC (*x) = plus_constant (addr, off); 4979 return; 4980 } 4981 } 4982 4983 /* Annotate LTREL_BASE as well. */ 4984 if (GET_CODE (*x) == UNSPEC 4985 && XINT (*x, 1) == UNSPEC_LTREL_BASE) 4986 { 4987 rtx base = cfun->machine->base_reg; 4988 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base), 4989 UNSPEC_LTREL_BASE); 4990 return; 4991 } 4992 4993 fmt = GET_RTX_FORMAT (GET_CODE (*x)); 4994 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) 4995 { 4996 if (fmt[i] == 'e') 4997 { 4998 annotate_constant_pool_refs (&XEXP (*x, i)); 4999 } 5000 else if (fmt[i] == 'E') 5001 { 5002 for (j = 0; j < XVECLEN (*x, i); j++) 5003 annotate_constant_pool_refs (&XVECEXP (*x, i, j)); 5004 } 5005 } 5006} 5007 5008/* Split all branches that exceed the maximum distance. 5009 Returns true if this created a new literal pool entry. */ 5010 5011static int 5012s390_split_branches (void) 5013{ 5014 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); 5015 int new_literal = 0, ret; 5016 rtx insn, pat, tmp, target; 5017 rtx *label; 5018 5019 /* We need correct insn addresses. */ 5020 5021 shorten_branches (get_insns ()); 5022 5023 /* Find all branches that exceed 64KB, and split them. */ 5024 5025 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 5026 { 5027 if (GET_CODE (insn) != JUMP_INSN) 5028 continue; 5029 5030 pat = PATTERN (insn); 5031 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2) 5032 pat = XVECEXP (pat, 0, 0); 5033 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx) 5034 continue; 5035 5036 if (GET_CODE (SET_SRC (pat)) == LABEL_REF) 5037 { 5038 label = &SET_SRC (pat); 5039 } 5040 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE) 5041 { 5042 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF) 5043 label = &XEXP (SET_SRC (pat), 1); 5044 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF) 5045 label = &XEXP (SET_SRC (pat), 2); 5046 else 5047 continue; 5048 } 5049 else 5050 continue; 5051 5052 if (get_attr_length (insn) <= 4) 5053 continue; 5054 5055 /* We are going to use the return register as scratch register, 5056 make sure it will be saved/restored by the prologue/epilogue. */ 5057 cfun_frame_layout.save_return_addr_p = 1; 5058 5059 if (!flag_pic) 5060 { 5061 new_literal = 1; 5062 tmp = force_const_mem (Pmode, *label); 5063 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn); 5064 INSN_ADDRESSES_NEW (tmp, -1); 5065 annotate_constant_pool_refs (&PATTERN (tmp)); 5066 5067 target = temp_reg; 5068 } 5069 else 5070 { 5071 new_literal = 1; 5072 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label), 5073 UNSPEC_LTREL_OFFSET); 5074 target = gen_rtx_CONST (Pmode, target); 5075 target = force_const_mem (Pmode, target); 5076 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn); 5077 INSN_ADDRESSES_NEW (tmp, -1); 5078 annotate_constant_pool_refs (&PATTERN (tmp)); 5079 5080 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0), 5081 cfun->machine->base_reg), 5082 UNSPEC_LTREL_BASE); 5083 target = gen_rtx_PLUS (Pmode, temp_reg, target); 5084 } 5085 5086 ret = validate_change (insn, label, target, 0); 5087 gcc_assert (ret); 5088 } 5089 5090 return new_literal; 5091} 5092 5093 5094/* Find an annotated literal pool symbol referenced in RTX X, 5095 and store it at REF. Will abort if X contains references to 5096 more than one such pool symbol; multiple references to the same 5097 symbol are allowed, however. 5098 5099 The rtx pointed to by REF must be initialized to NULL_RTX 5100 by the caller before calling this routine. */ 5101 5102static void 5103find_constant_pool_ref (rtx x, rtx *ref) 5104{ 5105 int i, j; 5106 const char *fmt; 5107 5108 /* Ignore LTREL_BASE references. */ 5109 if (GET_CODE (x) == UNSPEC 5110 && XINT (x, 1) == UNSPEC_LTREL_BASE) 5111 return; 5112 /* Likewise POOL_ENTRY insns. */ 5113 if (GET_CODE (x) == UNSPEC_VOLATILE 5114 && XINT (x, 1) == UNSPECV_POOL_ENTRY) 5115 return; 5116 5117 gcc_assert (GET_CODE (x) != SYMBOL_REF 5118 || !CONSTANT_POOL_ADDRESS_P (x)); 5119 5120 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF) 5121 { 5122 rtx sym = XVECEXP (x, 0, 0); 5123 gcc_assert (GET_CODE (sym) == SYMBOL_REF 5124 && CONSTANT_POOL_ADDRESS_P (sym)); 5125 5126 if (*ref == NULL_RTX) 5127 *ref = sym; 5128 else 5129 gcc_assert (*ref == sym); 5130 5131 return; 5132 } 5133 5134 fmt = GET_RTX_FORMAT (GET_CODE (x)); 5135 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 5136 { 5137 if (fmt[i] == 'e') 5138 { 5139 find_constant_pool_ref (XEXP (x, i), ref); 5140 } 5141 else if (fmt[i] == 'E') 5142 { 5143 for (j = 0; j < XVECLEN (x, i); j++) 5144 find_constant_pool_ref (XVECEXP (x, i, j), ref); 5145 } 5146 } 5147} 5148 5149/* Replace every reference to the annotated literal pool 5150 symbol REF in X by its base plus OFFSET. */ 5151 5152static void 5153replace_constant_pool_ref (rtx *x, rtx ref, rtx offset) 5154{ 5155 int i, j; 5156 const char *fmt; 5157 5158 gcc_assert (*x != ref); 5159 5160 if (GET_CODE (*x) == UNSPEC 5161 && XINT (*x, 1) == UNSPEC_LTREF 5162 && XVECEXP (*x, 0, 0) == ref) 5163 { 5164 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset); 5165 return; 5166 } 5167 5168 if (GET_CODE (*x) == PLUS 5169 && GET_CODE (XEXP (*x, 1)) == CONST_INT 5170 && GET_CODE (XEXP (*x, 0)) == UNSPEC 5171 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF 5172 && XVECEXP (XEXP (*x, 0), 0, 0) == ref) 5173 { 5174 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset); 5175 *x = plus_constant (addr, INTVAL (XEXP (*x, 1))); 5176 return; 5177 } 5178 5179 fmt = GET_RTX_FORMAT (GET_CODE (*x)); 5180 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) 5181 { 5182 if (fmt[i] == 'e') 5183 { 5184 replace_constant_pool_ref (&XEXP (*x, i), ref, offset); 5185 } 5186 else if (fmt[i] == 'E') 5187 { 5188 for (j = 0; j < XVECLEN (*x, i); j++) 5189 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset); 5190 } 5191 } 5192} 5193 5194/* Check whether X contains an UNSPEC_LTREL_BASE. 5195 Return its constant pool symbol if found, NULL_RTX otherwise. */ 5196 5197static rtx 5198find_ltrel_base (rtx x) 5199{ 5200 int i, j; 5201 const char *fmt; 5202 5203 if (GET_CODE (x) == UNSPEC 5204 && XINT (x, 1) == UNSPEC_LTREL_BASE) 5205 return XVECEXP (x, 0, 0); 5206 5207 fmt = GET_RTX_FORMAT (GET_CODE (x)); 5208 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 5209 { 5210 if (fmt[i] == 'e') 5211 { 5212 rtx fnd = find_ltrel_base (XEXP (x, i)); 5213 if (fnd) 5214 return fnd; 5215 } 5216 else if (fmt[i] == 'E') 5217 { 5218 for (j = 0; j < XVECLEN (x, i); j++) 5219 { 5220 rtx fnd = find_ltrel_base (XVECEXP (x, i, j)); 5221 if (fnd) 5222 return fnd; 5223 } 5224 } 5225 } 5226 5227 return NULL_RTX; 5228} 5229 5230/* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */ 5231 5232static void 5233replace_ltrel_base (rtx *x) 5234{ 5235 int i, j; 5236 const char *fmt; 5237 5238 if (GET_CODE (*x) == UNSPEC 5239 && XINT (*x, 1) == UNSPEC_LTREL_BASE) 5240 { 5241 *x = XVECEXP (*x, 0, 1); 5242 return; 5243 } 5244 5245 fmt = GET_RTX_FORMAT (GET_CODE (*x)); 5246 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) 5247 { 5248 if (fmt[i] == 'e') 5249 { 5250 replace_ltrel_base (&XEXP (*x, i)); 5251 } 5252 else if (fmt[i] == 'E') 5253 { 5254 for (j = 0; j < XVECLEN (*x, i); j++) 5255 replace_ltrel_base (&XVECEXP (*x, i, j)); 5256 } 5257 } 5258} 5259 5260 5261/* We keep a list of constants which we have to add to internal 5262 constant tables in the middle of large functions. */ 5263 5264#define NR_C_MODES 8 5265enum machine_mode constant_modes[NR_C_MODES] = 5266{ 5267 TFmode, TImode, 5268 DFmode, DImode, 5269 SFmode, SImode, 5270 HImode, 5271 QImode 5272}; 5273 5274struct constant 5275{ 5276 struct constant *next; 5277 rtx value; 5278 rtx label; 5279}; 5280 5281struct constant_pool 5282{ 5283 struct constant_pool *next; 5284 rtx first_insn; 5285 rtx pool_insn; 5286 bitmap insns; 5287 5288 struct constant *constants[NR_C_MODES]; 5289 struct constant *execute; 5290 rtx label; 5291 int size; 5292}; 5293 5294/* Allocate new constant_pool structure. */ 5295 5296static struct constant_pool * 5297s390_alloc_pool (void) 5298{ 5299 struct constant_pool *pool; 5300 int i; 5301 5302 pool = (struct constant_pool *) xmalloc (sizeof *pool); 5303 pool->next = NULL; 5304 for (i = 0; i < NR_C_MODES; i++) 5305 pool->constants[i] = NULL; 5306 5307 pool->execute = NULL; 5308 pool->label = gen_label_rtx (); 5309 pool->first_insn = NULL_RTX; 5310 pool->pool_insn = NULL_RTX; 5311 pool->insns = BITMAP_ALLOC (NULL); 5312 pool->size = 0; 5313 5314 return pool; 5315} 5316 5317/* Create new constant pool covering instructions starting at INSN 5318 and chain it to the end of POOL_LIST. */ 5319 5320static struct constant_pool * 5321s390_start_pool (struct constant_pool **pool_list, rtx insn) 5322{ 5323 struct constant_pool *pool, **prev; 5324 5325 pool = s390_alloc_pool (); 5326 pool->first_insn = insn; 5327 5328 for (prev = pool_list; *prev; prev = &(*prev)->next) 5329 ; 5330 *prev = pool; 5331 5332 return pool; 5333} 5334 5335/* End range of instructions covered by POOL at INSN and emit 5336 placeholder insn representing the pool. */ 5337 5338static void 5339s390_end_pool (struct constant_pool *pool, rtx insn) 5340{ 5341 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */); 5342 5343 if (!insn) 5344 insn = get_last_insn (); 5345 5346 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn); 5347 INSN_ADDRESSES_NEW (pool->pool_insn, -1); 5348} 5349 5350/* Add INSN to the list of insns covered by POOL. */ 5351 5352static void 5353s390_add_pool_insn (struct constant_pool *pool, rtx insn) 5354{ 5355 bitmap_set_bit (pool->insns, INSN_UID (insn)); 5356} 5357 5358/* Return pool out of POOL_LIST that covers INSN. */ 5359 5360static struct constant_pool * 5361s390_find_pool (struct constant_pool *pool_list, rtx insn) 5362{ 5363 struct constant_pool *pool; 5364 5365 for (pool = pool_list; pool; pool = pool->next) 5366 if (bitmap_bit_p (pool->insns, INSN_UID (insn))) 5367 break; 5368 5369 return pool; 5370} 5371 5372/* Add constant VAL of mode MODE to the constant pool POOL. */ 5373 5374static void 5375s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode) 5376{ 5377 struct constant *c; 5378 int i; 5379 5380 for (i = 0; i < NR_C_MODES; i++) 5381 if (constant_modes[i] == mode) 5382 break; 5383 gcc_assert (i != NR_C_MODES); 5384 5385 for (c = pool->constants[i]; c != NULL; c = c->next) 5386 if (rtx_equal_p (val, c->value)) 5387 break; 5388 5389 if (c == NULL) 5390 { 5391 c = (struct constant *) xmalloc (sizeof *c); 5392 c->value = val; 5393 c->label = gen_label_rtx (); 5394 c->next = pool->constants[i]; 5395 pool->constants[i] = c; 5396 pool->size += GET_MODE_SIZE (mode); 5397 } 5398} 5399 5400/* Find constant VAL of mode MODE in the constant pool POOL. 5401 Return an RTX describing the distance from the start of 5402 the pool to the location of the new constant. */ 5403 5404static rtx 5405s390_find_constant (struct constant_pool *pool, rtx val, 5406 enum machine_mode mode) 5407{ 5408 struct constant *c; 5409 rtx offset; 5410 int i; 5411 5412 for (i = 0; i < NR_C_MODES; i++) 5413 if (constant_modes[i] == mode) 5414 break; 5415 gcc_assert (i != NR_C_MODES); 5416 5417 for (c = pool->constants[i]; c != NULL; c = c->next) 5418 if (rtx_equal_p (val, c->value)) 5419 break; 5420 5421 gcc_assert (c); 5422 5423 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label), 5424 gen_rtx_LABEL_REF (Pmode, pool->label)); 5425 offset = gen_rtx_CONST (Pmode, offset); 5426 return offset; 5427} 5428 5429/* Check whether INSN is an execute. Return the label_ref to its 5430 execute target template if so, NULL_RTX otherwise. */ 5431 5432static rtx 5433s390_execute_label (rtx insn) 5434{ 5435 if (GET_CODE (insn) == INSN 5436 && GET_CODE (PATTERN (insn)) == PARALLEL 5437 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC 5438 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE) 5439 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2); 5440 5441 return NULL_RTX; 5442} 5443 5444/* Add execute target for INSN to the constant pool POOL. */ 5445 5446static void 5447s390_add_execute (struct constant_pool *pool, rtx insn) 5448{ 5449 struct constant *c; 5450 5451 for (c = pool->execute; c != NULL; c = c->next) 5452 if (INSN_UID (insn) == INSN_UID (c->value)) 5453 break; 5454 5455 if (c == NULL) 5456 { 5457 c = (struct constant *) xmalloc (sizeof *c); 5458 c->value = insn; 5459 c->label = gen_label_rtx (); 5460 c->next = pool->execute; 5461 pool->execute = c; 5462 pool->size += 6; 5463 } 5464} 5465 5466/* Find execute target for INSN in the constant pool POOL. 5467 Return an RTX describing the distance from the start of 5468 the pool to the location of the execute target. */ 5469 5470static rtx 5471s390_find_execute (struct constant_pool *pool, rtx insn) 5472{ 5473 struct constant *c; 5474 rtx offset; 5475 5476 for (c = pool->execute; c != NULL; c = c->next) 5477 if (INSN_UID (insn) == INSN_UID (c->value)) 5478 break; 5479 5480 gcc_assert (c); 5481 5482 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label), 5483 gen_rtx_LABEL_REF (Pmode, pool->label)); 5484 offset = gen_rtx_CONST (Pmode, offset); 5485 return offset; 5486} 5487 5488/* For an execute INSN, extract the execute target template. */ 5489 5490static rtx 5491s390_execute_target (rtx insn) 5492{ 5493 rtx pattern = PATTERN (insn); 5494 gcc_assert (s390_execute_label (insn)); 5495 5496 if (XVECLEN (pattern, 0) == 2) 5497 { 5498 pattern = copy_rtx (XVECEXP (pattern, 0, 1)); 5499 } 5500 else 5501 { 5502 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1); 5503 int i; 5504 5505 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++) 5506 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1)); 5507 5508 pattern = gen_rtx_PARALLEL (VOIDmode, vec); 5509 } 5510 5511 return pattern; 5512} 5513 5514/* Indicate that INSN cannot be duplicated. This is the case for 5515 execute insns that carry a unique label. */ 5516 5517static bool 5518s390_cannot_copy_insn_p (rtx insn) 5519{ 5520 rtx label = s390_execute_label (insn); 5521 return label && label != const0_rtx; 5522} 5523 5524/* Dump out the constants in POOL. If REMOTE_LABEL is true, 5525 do not emit the pool base label. */ 5526 5527static void 5528s390_dump_pool (struct constant_pool *pool, bool remote_label) 5529{ 5530 struct constant *c; 5531 rtx insn = pool->pool_insn; 5532 int i; 5533 5534 /* Switch to rodata section. */ 5535 if (TARGET_CPU_ZARCH) 5536 { 5537 insn = emit_insn_after (gen_pool_section_start (), insn); 5538 INSN_ADDRESSES_NEW (insn, -1); 5539 } 5540 5541 /* Ensure minimum pool alignment. */ 5542 if (TARGET_CPU_ZARCH) 5543 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn); 5544 else 5545 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn); 5546 INSN_ADDRESSES_NEW (insn, -1); 5547 5548 /* Emit pool base label. */ 5549 if (!remote_label) 5550 { 5551 insn = emit_label_after (pool->label, insn); 5552 INSN_ADDRESSES_NEW (insn, -1); 5553 } 5554 5555 /* Dump constants in descending alignment requirement order, 5556 ensuring proper alignment for every constant. */ 5557 for (i = 0; i < NR_C_MODES; i++) 5558 for (c = pool->constants[i]; c; c = c->next) 5559 { 5560 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */ 5561 rtx value = c->value; 5562 if (GET_CODE (value) == CONST 5563 && GET_CODE (XEXP (value, 0)) == UNSPEC 5564 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET 5565 && XVECLEN (XEXP (value, 0), 0) == 1) 5566 { 5567 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0), 5568 gen_rtx_LABEL_REF (VOIDmode, pool->label)); 5569 value = gen_rtx_CONST (VOIDmode, value); 5570 } 5571 5572 insn = emit_label_after (c->label, insn); 5573 INSN_ADDRESSES_NEW (insn, -1); 5574 5575 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i], 5576 gen_rtvec (1, value), 5577 UNSPECV_POOL_ENTRY); 5578 insn = emit_insn_after (value, insn); 5579 INSN_ADDRESSES_NEW (insn, -1); 5580 } 5581 5582 /* Ensure minimum alignment for instructions. */ 5583 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn); 5584 INSN_ADDRESSES_NEW (insn, -1); 5585 5586 /* Output in-pool execute template insns. */ 5587 for (c = pool->execute; c; c = c->next) 5588 { 5589 insn = emit_label_after (c->label, insn); 5590 INSN_ADDRESSES_NEW (insn, -1); 5591 5592 insn = emit_insn_after (s390_execute_target (c->value), insn); 5593 INSN_ADDRESSES_NEW (insn, -1); 5594 } 5595 5596 /* Switch back to previous section. */ 5597 if (TARGET_CPU_ZARCH) 5598 { 5599 insn = emit_insn_after (gen_pool_section_end (), insn); 5600 INSN_ADDRESSES_NEW (insn, -1); 5601 } 5602 5603 insn = emit_barrier_after (insn); 5604 INSN_ADDRESSES_NEW (insn, -1); 5605 5606 /* Remove placeholder insn. */ 5607 remove_insn (pool->pool_insn); 5608} 5609 5610/* Free all memory used by POOL. */ 5611 5612static void 5613s390_free_pool (struct constant_pool *pool) 5614{ 5615 struct constant *c, *next; 5616 int i; 5617 5618 for (i = 0; i < NR_C_MODES; i++) 5619 for (c = pool->constants[i]; c; c = next) 5620 { 5621 next = c->next; 5622 free (c); 5623 } 5624 5625 for (c = pool->execute; c; c = next) 5626 { 5627 next = c->next; 5628 free (c); 5629 } 5630 5631 BITMAP_FREE (pool->insns); 5632 free (pool); 5633} 5634 5635 5636/* Collect main literal pool. Return NULL on overflow. */ 5637 5638static struct constant_pool * 5639s390_mainpool_start (void) 5640{ 5641 struct constant_pool *pool; 5642 rtx insn; 5643 5644 pool = s390_alloc_pool (); 5645 5646 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 5647 { 5648 if (GET_CODE (insn) == INSN 5649 && GET_CODE (PATTERN (insn)) == SET 5650 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE 5651 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL) 5652 { 5653 gcc_assert (!pool->pool_insn); 5654 pool->pool_insn = insn; 5655 } 5656 5657 if (!TARGET_CPU_ZARCH && s390_execute_label (insn)) 5658 { 5659 s390_add_execute (pool, insn); 5660 } 5661 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) 5662 { 5663 rtx pool_ref = NULL_RTX; 5664 find_constant_pool_ref (PATTERN (insn), &pool_ref); 5665 if (pool_ref) 5666 { 5667 rtx constant = get_pool_constant (pool_ref); 5668 enum machine_mode mode = get_pool_mode (pool_ref); 5669 s390_add_constant (pool, constant, mode); 5670 } 5671 } 5672 } 5673 5674 gcc_assert (pool->pool_insn || pool->size == 0); 5675 5676 if (pool->size >= 4096) 5677 { 5678 /* We're going to chunkify the pool, so remove the main 5679 pool placeholder insn. */ 5680 remove_insn (pool->pool_insn); 5681 5682 s390_free_pool (pool); 5683 pool = NULL; 5684 } 5685 5686 return pool; 5687} 5688 5689/* POOL holds the main literal pool as collected by s390_mainpool_start. 5690 Modify the current function to output the pool constants as well as 5691 the pool register setup instruction. */ 5692 5693static void 5694s390_mainpool_finish (struct constant_pool *pool) 5695{ 5696 rtx base_reg = cfun->machine->base_reg; 5697 rtx insn; 5698 5699 /* If the pool is empty, we're done. */ 5700 if (pool->size == 0) 5701 { 5702 /* We don't actually need a base register after all. */ 5703 cfun->machine->base_reg = NULL_RTX; 5704 5705 if (pool->pool_insn) 5706 remove_insn (pool->pool_insn); 5707 s390_free_pool (pool); 5708 return; 5709 } 5710 5711 /* We need correct insn addresses. */ 5712 shorten_branches (get_insns ()); 5713 5714 /* On zSeries, we use a LARL to load the pool register. The pool is 5715 located in the .rodata section, so we emit it after the function. */ 5716 if (TARGET_CPU_ZARCH) 5717 { 5718 insn = gen_main_base_64 (base_reg, pool->label); 5719 insn = emit_insn_after (insn, pool->pool_insn); 5720 INSN_ADDRESSES_NEW (insn, -1); 5721 remove_insn (pool->pool_insn); 5722 5723 insn = get_last_insn (); 5724 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); 5725 INSN_ADDRESSES_NEW (pool->pool_insn, -1); 5726 5727 s390_dump_pool (pool, 0); 5728 } 5729 5730 /* On S/390, if the total size of the function's code plus literal pool 5731 does not exceed 4096 bytes, we use BASR to set up a function base 5732 pointer, and emit the literal pool at the end of the function. */ 5733 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ())) 5734 + pool->size + 8 /* alignment slop */ < 4096) 5735 { 5736 insn = gen_main_base_31_small (base_reg, pool->label); 5737 insn = emit_insn_after (insn, pool->pool_insn); 5738 INSN_ADDRESSES_NEW (insn, -1); 5739 remove_insn (pool->pool_insn); 5740 5741 insn = emit_label_after (pool->label, insn); 5742 INSN_ADDRESSES_NEW (insn, -1); 5743 5744 insn = get_last_insn (); 5745 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); 5746 INSN_ADDRESSES_NEW (pool->pool_insn, -1); 5747 5748 s390_dump_pool (pool, 1); 5749 } 5750 5751 /* Otherwise, we emit an inline literal pool and use BASR to branch 5752 over it, setting up the pool register at the same time. */ 5753 else 5754 { 5755 rtx pool_end = gen_label_rtx (); 5756 5757 insn = gen_main_base_31_large (base_reg, pool->label, pool_end); 5758 insn = emit_insn_after (insn, pool->pool_insn); 5759 INSN_ADDRESSES_NEW (insn, -1); 5760 remove_insn (pool->pool_insn); 5761 5762 insn = emit_label_after (pool->label, insn); 5763 INSN_ADDRESSES_NEW (insn, -1); 5764 5765 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); 5766 INSN_ADDRESSES_NEW (pool->pool_insn, -1); 5767 5768 insn = emit_label_after (pool_end, pool->pool_insn); 5769 INSN_ADDRESSES_NEW (insn, -1); 5770 5771 s390_dump_pool (pool, 1); 5772 } 5773 5774 5775 /* Replace all literal pool references. */ 5776 5777 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 5778 { 5779 if (INSN_P (insn)) 5780 replace_ltrel_base (&PATTERN (insn)); 5781 5782 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) 5783 { 5784 rtx addr, pool_ref = NULL_RTX; 5785 find_constant_pool_ref (PATTERN (insn), &pool_ref); 5786 if (pool_ref) 5787 { 5788 if (s390_execute_label (insn)) 5789 addr = s390_find_execute (pool, insn); 5790 else 5791 addr = s390_find_constant (pool, get_pool_constant (pool_ref), 5792 get_pool_mode (pool_ref)); 5793 5794 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr); 5795 INSN_CODE (insn) = -1; 5796 } 5797 } 5798 } 5799 5800 5801 /* Free the pool. */ 5802 s390_free_pool (pool); 5803} 5804 5805/* POOL holds the main literal pool as collected by s390_mainpool_start. 5806 We have decided we cannot use this pool, so revert all changes 5807 to the current function that were done by s390_mainpool_start. */ 5808static void 5809s390_mainpool_cancel (struct constant_pool *pool) 5810{ 5811 /* We didn't actually change the instruction stream, so simply 5812 free the pool memory. */ 5813 s390_free_pool (pool); 5814} 5815 5816 5817/* Chunkify the literal pool. */ 5818 5819#define S390_POOL_CHUNK_MIN 0xc00 5820#define S390_POOL_CHUNK_MAX 0xe00 5821 5822static struct constant_pool * 5823s390_chunkify_start (void) 5824{ 5825 struct constant_pool *curr_pool = NULL, *pool_list = NULL; 5826 int extra_size = 0; 5827 bitmap far_labels; 5828 rtx pending_ltrel = NULL_RTX; 5829 rtx insn; 5830 5831 rtx (*gen_reload_base) (rtx, rtx) = 5832 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31; 5833 5834 5835 /* We need correct insn addresses. */ 5836 5837 shorten_branches (get_insns ()); 5838 5839 /* Scan all insns and move literals to pool chunks. */ 5840 5841 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 5842 { 5843 /* Check for pending LTREL_BASE. */ 5844 if (INSN_P (insn)) 5845 { 5846 rtx ltrel_base = find_ltrel_base (PATTERN (insn)); 5847 if (ltrel_base) 5848 { 5849 gcc_assert (ltrel_base == pending_ltrel); 5850 pending_ltrel = NULL_RTX; 5851 } 5852 } 5853 5854 if (!TARGET_CPU_ZARCH && s390_execute_label (insn)) 5855 { 5856 if (!curr_pool) 5857 curr_pool = s390_start_pool (&pool_list, insn); 5858 5859 s390_add_execute (curr_pool, insn); 5860 s390_add_pool_insn (curr_pool, insn); 5861 } 5862 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) 5863 { 5864 rtx pool_ref = NULL_RTX; 5865 find_constant_pool_ref (PATTERN (insn), &pool_ref); 5866 if (pool_ref) 5867 { 5868 rtx constant = get_pool_constant (pool_ref); 5869 enum machine_mode mode = get_pool_mode (pool_ref); 5870 5871 if (!curr_pool) 5872 curr_pool = s390_start_pool (&pool_list, insn); 5873 5874 s390_add_constant (curr_pool, constant, mode); 5875 s390_add_pool_insn (curr_pool, insn); 5876 5877 /* Don't split the pool chunk between a LTREL_OFFSET load 5878 and the corresponding LTREL_BASE. */ 5879 if (GET_CODE (constant) == CONST 5880 && GET_CODE (XEXP (constant, 0)) == UNSPEC 5881 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET) 5882 { 5883 gcc_assert (!pending_ltrel); 5884 pending_ltrel = pool_ref; 5885 } 5886 } 5887 } 5888 5889 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL) 5890 { 5891 if (curr_pool) 5892 s390_add_pool_insn (curr_pool, insn); 5893 /* An LTREL_BASE must follow within the same basic block. */ 5894 gcc_assert (!pending_ltrel); 5895 } 5896 5897 if (!curr_pool 5898 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn) 5899 || INSN_ADDRESSES (INSN_UID (insn)) == -1) 5900 continue; 5901 5902 if (TARGET_CPU_ZARCH) 5903 { 5904 if (curr_pool->size < S390_POOL_CHUNK_MAX) 5905 continue; 5906 5907 s390_end_pool (curr_pool, NULL_RTX); 5908 curr_pool = NULL; 5909 } 5910 else 5911 { 5912 int chunk_size = INSN_ADDRESSES (INSN_UID (insn)) 5913 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn)) 5914 + extra_size; 5915 5916 /* We will later have to insert base register reload insns. 5917 Those will have an effect on code size, which we need to 5918 consider here. This calculation makes rather pessimistic 5919 worst-case assumptions. */ 5920 if (GET_CODE (insn) == CODE_LABEL) 5921 extra_size += 6; 5922 5923 if (chunk_size < S390_POOL_CHUNK_MIN 5924 && curr_pool->size < S390_POOL_CHUNK_MIN) 5925 continue; 5926 5927 /* Pool chunks can only be inserted after BARRIERs ... */ 5928 if (GET_CODE (insn) == BARRIER) 5929 { 5930 s390_end_pool (curr_pool, insn); 5931 curr_pool = NULL; 5932 extra_size = 0; 5933 } 5934 5935 /* ... so if we don't find one in time, create one. */ 5936 else if ((chunk_size > S390_POOL_CHUNK_MAX 5937 || curr_pool->size > S390_POOL_CHUNK_MAX)) 5938 { 5939 rtx label, jump, barrier; 5940 5941 /* We can insert the barrier only after a 'real' insn. */ 5942 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN) 5943 continue; 5944 if (get_attr_length (insn) == 0) 5945 continue; 5946 5947 /* Don't separate LTREL_BASE from the corresponding 5948 LTREL_OFFSET load. */ 5949 if (pending_ltrel) 5950 continue; 5951 5952 label = gen_label_rtx (); 5953 jump = emit_jump_insn_after (gen_jump (label), insn); 5954 barrier = emit_barrier_after (jump); 5955 insn = emit_label_after (label, barrier); 5956 JUMP_LABEL (jump) = label; 5957 LABEL_NUSES (label) = 1; 5958 5959 INSN_ADDRESSES_NEW (jump, -1); 5960 INSN_ADDRESSES_NEW (barrier, -1); 5961 INSN_ADDRESSES_NEW (insn, -1); 5962 5963 s390_end_pool (curr_pool, barrier); 5964 curr_pool = NULL; 5965 extra_size = 0; 5966 } 5967 } 5968 } 5969 5970 if (curr_pool) 5971 s390_end_pool (curr_pool, NULL_RTX); 5972 gcc_assert (!pending_ltrel); 5973 5974 /* Find all labels that are branched into 5975 from an insn belonging to a different chunk. */ 5976 5977 far_labels = BITMAP_ALLOC (NULL); 5978 5979 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 5980 { 5981 /* Labels marked with LABEL_PRESERVE_P can be target 5982 of non-local jumps, so we have to mark them. 5983 The same holds for named labels. 5984 5985 Don't do that, however, if it is the label before 5986 a jump table. */ 5987 5988 if (GET_CODE (insn) == CODE_LABEL 5989 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn))) 5990 { 5991 rtx vec_insn = next_real_insn (insn); 5992 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ? 5993 PATTERN (vec_insn) : NULL_RTX; 5994 if (!vec_pat 5995 || !(GET_CODE (vec_pat) == ADDR_VEC 5996 || GET_CODE (vec_pat) == ADDR_DIFF_VEC)) 5997 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn)); 5998 } 5999 6000 /* If we have a direct jump (conditional or unconditional) 6001 or a casesi jump, check all potential targets. */ 6002 else if (GET_CODE (insn) == JUMP_INSN) 6003 { 6004 rtx pat = PATTERN (insn); 6005 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2) 6006 pat = XVECEXP (pat, 0, 0); 6007 6008 if (GET_CODE (pat) == SET) 6009 { 6010 rtx label = JUMP_LABEL (insn); 6011 if (label) 6012 { 6013 if (s390_find_pool (pool_list, label) 6014 != s390_find_pool (pool_list, insn)) 6015 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); 6016 } 6017 } 6018 else if (GET_CODE (pat) == PARALLEL 6019 && XVECLEN (pat, 0) == 2 6020 && GET_CODE (XVECEXP (pat, 0, 0)) == SET 6021 && GET_CODE (XVECEXP (pat, 0, 1)) == USE 6022 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF) 6023 { 6024 /* Find the jump table used by this casesi jump. */ 6025 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0); 6026 rtx vec_insn = next_real_insn (vec_label); 6027 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ? 6028 PATTERN (vec_insn) : NULL_RTX; 6029 if (vec_pat 6030 && (GET_CODE (vec_pat) == ADDR_VEC 6031 || GET_CODE (vec_pat) == ADDR_DIFF_VEC)) 6032 { 6033 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC; 6034 6035 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++) 6036 { 6037 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0); 6038 6039 if (s390_find_pool (pool_list, label) 6040 != s390_find_pool (pool_list, insn)) 6041 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); 6042 } 6043 } 6044 } 6045 } 6046 } 6047 6048 /* Insert base register reload insns before every pool. */ 6049 6050 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) 6051 { 6052 rtx new_insn = gen_reload_base (cfun->machine->base_reg, 6053 curr_pool->label); 6054 rtx insn = curr_pool->first_insn; 6055 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1); 6056 } 6057 6058 /* Insert base register reload insns at every far label. */ 6059 6060 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 6061 if (GET_CODE (insn) == CODE_LABEL 6062 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn))) 6063 { 6064 struct constant_pool *pool = s390_find_pool (pool_list, insn); 6065 if (pool) 6066 { 6067 rtx new_insn = gen_reload_base (cfun->machine->base_reg, 6068 pool->label); 6069 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1); 6070 } 6071 } 6072 6073 6074 BITMAP_FREE (far_labels); 6075 6076 6077 /* Recompute insn addresses. */ 6078 6079 init_insn_lengths (); 6080 shorten_branches (get_insns ()); 6081 6082 return pool_list; 6083} 6084 6085/* POOL_LIST is a chunk list as prepared by s390_chunkify_start. 6086 After we have decided to use this list, finish implementing 6087 all changes to the current function as required. */ 6088 6089static void 6090s390_chunkify_finish (struct constant_pool *pool_list) 6091{ 6092 struct constant_pool *curr_pool = NULL; 6093 rtx insn; 6094 6095 6096 /* Replace all literal pool references. */ 6097 6098 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 6099 { 6100 if (INSN_P (insn)) 6101 replace_ltrel_base (&PATTERN (insn)); 6102 6103 curr_pool = s390_find_pool (pool_list, insn); 6104 if (!curr_pool) 6105 continue; 6106 6107 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) 6108 { 6109 rtx addr, pool_ref = NULL_RTX; 6110 find_constant_pool_ref (PATTERN (insn), &pool_ref); 6111 if (pool_ref) 6112 { 6113 if (s390_execute_label (insn)) 6114 addr = s390_find_execute (curr_pool, insn); 6115 else 6116 addr = s390_find_constant (curr_pool, 6117 get_pool_constant (pool_ref), 6118 get_pool_mode (pool_ref)); 6119 6120 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr); 6121 INSN_CODE (insn) = -1; 6122 } 6123 } 6124 } 6125 6126 /* Dump out all literal pools. */ 6127 6128 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) 6129 s390_dump_pool (curr_pool, 0); 6130 6131 /* Free pool list. */ 6132 6133 while (pool_list) 6134 { 6135 struct constant_pool *next = pool_list->next; 6136 s390_free_pool (pool_list); 6137 pool_list = next; 6138 } 6139} 6140 6141/* POOL_LIST is a chunk list as prepared by s390_chunkify_start. 6142 We have decided we cannot use this list, so revert all changes 6143 to the current function that were done by s390_chunkify_start. */ 6144 6145static void 6146s390_chunkify_cancel (struct constant_pool *pool_list) 6147{ 6148 struct constant_pool *curr_pool = NULL; 6149 rtx insn; 6150 6151 /* Remove all pool placeholder insns. */ 6152 6153 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) 6154 { 6155 /* Did we insert an extra barrier? Remove it. */ 6156 rtx barrier = PREV_INSN (curr_pool->pool_insn); 6157 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX; 6158 rtx label = NEXT_INSN (curr_pool->pool_insn); 6159 6160 if (jump && GET_CODE (jump) == JUMP_INSN 6161 && barrier && GET_CODE (barrier) == BARRIER 6162 && label && GET_CODE (label) == CODE_LABEL 6163 && GET_CODE (PATTERN (jump)) == SET 6164 && SET_DEST (PATTERN (jump)) == pc_rtx 6165 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF 6166 && XEXP (SET_SRC (PATTERN (jump)), 0) == label) 6167 { 6168 remove_insn (jump); 6169 remove_insn (barrier); 6170 remove_insn (label); 6171 } 6172 6173 remove_insn (curr_pool->pool_insn); 6174 } 6175 6176 /* Remove all base register reload insns. */ 6177 6178 for (insn = get_insns (); insn; ) 6179 { 6180 rtx next_insn = NEXT_INSN (insn); 6181 6182 if (GET_CODE (insn) == INSN 6183 && GET_CODE (PATTERN (insn)) == SET 6184 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC 6185 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE) 6186 remove_insn (insn); 6187 6188 insn = next_insn; 6189 } 6190 6191 /* Free pool list. */ 6192 6193 while (pool_list) 6194 { 6195 struct constant_pool *next = pool_list->next; 6196 s390_free_pool (pool_list); 6197 pool_list = next; 6198 } 6199} 6200 6201 6202/* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */ 6203 6204void 6205s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align) 6206{ 6207 REAL_VALUE_TYPE r; 6208 6209 switch (GET_MODE_CLASS (mode)) 6210 { 6211 case MODE_FLOAT: 6212 gcc_assert (GET_CODE (exp) == CONST_DOUBLE); 6213 6214 REAL_VALUE_FROM_CONST_DOUBLE (r, exp); 6215 assemble_real (r, mode, align); 6216 break; 6217 6218 case MODE_INT: 6219 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1); 6220 break; 6221 6222 default: 6223 gcc_unreachable (); 6224 } 6225} 6226 6227 6228/* Return an RTL expression representing the value of the return address 6229 for the frame COUNT steps up from the current frame. FRAME is the 6230 frame pointer of that frame. */ 6231 6232rtx 6233s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) 6234{ 6235 int offset; 6236 rtx addr; 6237 6238 /* Without backchain, we fail for all but the current frame. */ 6239 6240 if (!TARGET_BACKCHAIN && count > 0) 6241 return NULL_RTX; 6242 6243 /* For the current frame, we need to make sure the initial 6244 value of RETURN_REGNUM is actually saved. */ 6245 6246 if (count == 0) 6247 { 6248 /* On non-z architectures branch splitting could overwrite r14. */ 6249 if (TARGET_CPU_ZARCH) 6250 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM); 6251 else 6252 { 6253 cfun_frame_layout.save_return_addr_p = true; 6254 return gen_rtx_MEM (Pmode, return_address_pointer_rtx); 6255 } 6256 } 6257 6258 if (TARGET_PACKED_STACK) 6259 offset = -2 * UNITS_PER_WORD; 6260 else 6261 offset = RETURN_REGNUM * UNITS_PER_WORD; 6262 6263 addr = plus_constant (frame, offset); 6264 addr = memory_address (Pmode, addr); 6265 return gen_rtx_MEM (Pmode, addr); 6266} 6267 6268/* Return an RTL expression representing the back chain stored in 6269 the current stack frame. */ 6270 6271rtx 6272s390_back_chain_rtx (void) 6273{ 6274 rtx chain; 6275 6276 gcc_assert (TARGET_BACKCHAIN); 6277 6278 if (TARGET_PACKED_STACK) 6279 chain = plus_constant (stack_pointer_rtx, 6280 STACK_POINTER_OFFSET - UNITS_PER_WORD); 6281 else 6282 chain = stack_pointer_rtx; 6283 6284 chain = gen_rtx_MEM (Pmode, chain); 6285 return chain; 6286} 6287 6288/* Find first call clobbered register unused in a function. 6289 This could be used as base register in a leaf function 6290 or for holding the return address before epilogue. */ 6291 6292static int 6293find_unused_clobbered_reg (void) 6294{ 6295 int i; 6296 for (i = 0; i < 6; i++) 6297 if (!regs_ever_live[i]) 6298 return i; 6299 return 0; 6300} 6301 6302 6303/* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all 6304 clobbered hard regs in SETREG. */ 6305 6306static void 6307s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data) 6308{ 6309 int *regs_ever_clobbered = (int *)data; 6310 unsigned int i, regno; 6311 enum machine_mode mode = GET_MODE (setreg); 6312 6313 if (GET_CODE (setreg) == SUBREG) 6314 { 6315 rtx inner = SUBREG_REG (setreg); 6316 if (!GENERAL_REG_P (inner)) 6317 return; 6318 regno = subreg_regno (setreg); 6319 } 6320 else if (GENERAL_REG_P (setreg)) 6321 regno = REGNO (setreg); 6322 else 6323 return; 6324 6325 for (i = regno; 6326 i < regno + HARD_REGNO_NREGS (regno, mode); 6327 i++) 6328 regs_ever_clobbered[i] = 1; 6329} 6330 6331/* Walks through all basic blocks of the current function looking 6332 for clobbered hard regs using s390_reg_clobbered_rtx. The fields 6333 of the passed integer array REGS_EVER_CLOBBERED are set to one for 6334 each of those regs. */ 6335 6336static void 6337s390_regs_ever_clobbered (int *regs_ever_clobbered) 6338{ 6339 basic_block cur_bb; 6340 rtx cur_insn; 6341 unsigned int i; 6342 6343 memset (regs_ever_clobbered, 0, 16 * sizeof (int)); 6344 6345 /* For non-leaf functions we have to consider all call clobbered regs to be 6346 clobbered. */ 6347 if (!current_function_is_leaf) 6348 { 6349 for (i = 0; i < 16; i++) 6350 regs_ever_clobbered[i] = call_really_used_regs[i]; 6351 } 6352 6353 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live 6354 this work is done by liveness analysis (mark_regs_live_at_end). 6355 Special care is needed for functions containing landing pads. Landing pads 6356 may use the eh registers, but the code which sets these registers is not 6357 contained in that function. Hence s390_regs_ever_clobbered is not able to 6358 deal with this automatically. */ 6359 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p) 6360 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++) 6361 if (current_function_calls_eh_return 6362 || (cfun->machine->has_landing_pad_p 6363 && regs_ever_live [EH_RETURN_DATA_REGNO (i)])) 6364 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1; 6365 6366 /* For nonlocal gotos all call-saved registers have to be saved. 6367 This flag is also set for the unwinding code in libgcc. 6368 See expand_builtin_unwind_init. For regs_ever_live this is done by 6369 reload. */ 6370 if (current_function_has_nonlocal_label) 6371 for (i = 0; i < 16; i++) 6372 if (!call_really_used_regs[i]) 6373 regs_ever_clobbered[i] = 1; 6374 6375 FOR_EACH_BB (cur_bb) 6376 { 6377 FOR_BB_INSNS (cur_bb, cur_insn) 6378 { 6379 if (INSN_P (cur_insn)) 6380 note_stores (PATTERN (cur_insn), 6381 s390_reg_clobbered_rtx, 6382 regs_ever_clobbered); 6383 } 6384 } 6385} 6386 6387/* Determine the frame area which actually has to be accessed 6388 in the function epilogue. The values are stored at the 6389 given pointers AREA_BOTTOM (address of the lowest used stack 6390 address) and AREA_TOP (address of the first item which does 6391 not belong to the stack frame). */ 6392 6393static void 6394s390_frame_area (int *area_bottom, int *area_top) 6395{ 6396 int b, t; 6397 int i; 6398 6399 b = INT_MAX; 6400 t = INT_MIN; 6401 6402 if (cfun_frame_layout.first_restore_gpr != -1) 6403 { 6404 b = (cfun_frame_layout.gprs_offset 6405 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD); 6406 t = b + (cfun_frame_layout.last_restore_gpr 6407 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD; 6408 } 6409 6410 if (TARGET_64BIT && cfun_save_high_fprs_p) 6411 { 6412 b = MIN (b, cfun_frame_layout.f8_offset); 6413 t = MAX (t, (cfun_frame_layout.f8_offset 6414 + cfun_frame_layout.high_fprs * 8)); 6415 } 6416 6417 if (!TARGET_64BIT) 6418 for (i = 2; i < 4; i++) 6419 if (cfun_fpr_bit_p (i)) 6420 { 6421 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8); 6422 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8); 6423 } 6424 6425 *area_bottom = b; 6426 *area_top = t; 6427} 6428 6429/* Fill cfun->machine with info about register usage of current function. 6430 Return in CLOBBERED_REGS which GPRs are currently considered set. */ 6431 6432static void 6433s390_register_info (int clobbered_regs[]) 6434{ 6435 int i, j; 6436 6437 /* fprs 8 - 15 are call saved for 64 Bit ABI. */ 6438 cfun_frame_layout.fpr_bitmap = 0; 6439 cfun_frame_layout.high_fprs = 0; 6440 if (TARGET_64BIT) 6441 for (i = 24; i < 32; i++) 6442 if (regs_ever_live[i] && !global_regs[i]) 6443 { 6444 cfun_set_fpr_bit (i - 16); 6445 cfun_frame_layout.high_fprs++; 6446 } 6447 6448 /* Find first and last gpr to be saved. We trust regs_ever_live 6449 data, except that we don't save and restore global registers. 6450 6451 Also, all registers with special meaning to the compiler need 6452 to be handled extra. */ 6453 6454 s390_regs_ever_clobbered (clobbered_regs); 6455 6456 for (i = 0; i < 16; i++) 6457 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i]; 6458 6459 if (frame_pointer_needed) 6460 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1; 6461 6462 if (flag_pic) 6463 clobbered_regs[PIC_OFFSET_TABLE_REGNUM] 6464 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM]; 6465 6466 clobbered_regs[BASE_REGNUM] 6467 |= (cfun->machine->base_reg 6468 && REGNO (cfun->machine->base_reg) == BASE_REGNUM); 6469 6470 clobbered_regs[RETURN_REGNUM] 6471 |= (!current_function_is_leaf 6472 || TARGET_TPF_PROFILING 6473 || cfun->machine->split_branches_pending_p 6474 || cfun_frame_layout.save_return_addr_p 6475 || current_function_calls_eh_return 6476 || current_function_stdarg); 6477 6478 clobbered_regs[STACK_POINTER_REGNUM] 6479 |= (!current_function_is_leaf 6480 || TARGET_TPF_PROFILING 6481 || cfun_save_high_fprs_p 6482 || get_frame_size () > 0 6483 || current_function_calls_alloca 6484 || current_function_stdarg); 6485 6486 for (i = 6; i < 16; i++) 6487 if (regs_ever_live[i] || clobbered_regs[i]) 6488 break; 6489 for (j = 15; j > i; j--) 6490 if (regs_ever_live[j] || clobbered_regs[j]) 6491 break; 6492 6493 if (i == 16) 6494 { 6495 /* Nothing to save/restore. */ 6496 cfun_frame_layout.first_save_gpr_slot = -1; 6497 cfun_frame_layout.last_save_gpr_slot = -1; 6498 cfun_frame_layout.first_save_gpr = -1; 6499 cfun_frame_layout.first_restore_gpr = -1; 6500 cfun_frame_layout.last_save_gpr = -1; 6501 cfun_frame_layout.last_restore_gpr = -1; 6502 } 6503 else 6504 { 6505 /* Save slots for gprs from i to j. */ 6506 cfun_frame_layout.first_save_gpr_slot = i; 6507 cfun_frame_layout.last_save_gpr_slot = j; 6508 6509 for (i = cfun_frame_layout.first_save_gpr_slot; 6510 i < cfun_frame_layout.last_save_gpr_slot + 1; 6511 i++) 6512 if (clobbered_regs[i]) 6513 break; 6514 6515 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--) 6516 if (clobbered_regs[j]) 6517 break; 6518 6519 if (i == cfun_frame_layout.last_save_gpr_slot + 1) 6520 { 6521 /* Nothing to save/restore. */ 6522 cfun_frame_layout.first_save_gpr = -1; 6523 cfun_frame_layout.first_restore_gpr = -1; 6524 cfun_frame_layout.last_save_gpr = -1; 6525 cfun_frame_layout.last_restore_gpr = -1; 6526 } 6527 else 6528 { 6529 /* Save / Restore from gpr i to j. */ 6530 cfun_frame_layout.first_save_gpr = i; 6531 cfun_frame_layout.first_restore_gpr = i; 6532 cfun_frame_layout.last_save_gpr = j; 6533 cfun_frame_layout.last_restore_gpr = j; 6534 } 6535 } 6536 6537 if (current_function_stdarg) 6538 { 6539 /* Varargs functions need to save gprs 2 to 6. */ 6540 if (cfun->va_list_gpr_size 6541 && current_function_args_info.gprs < GP_ARG_NUM_REG) 6542 { 6543 int min_gpr = current_function_args_info.gprs; 6544 int max_gpr = min_gpr + cfun->va_list_gpr_size; 6545 if (max_gpr > GP_ARG_NUM_REG) 6546 max_gpr = GP_ARG_NUM_REG; 6547 6548 if (cfun_frame_layout.first_save_gpr == -1 6549 || cfun_frame_layout.first_save_gpr > 2 + min_gpr) 6550 { 6551 cfun_frame_layout.first_save_gpr = 2 + min_gpr; 6552 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr; 6553 } 6554 6555 if (cfun_frame_layout.last_save_gpr == -1 6556 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1) 6557 { 6558 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1; 6559 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1; 6560 } 6561 } 6562 6563 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */ 6564 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size 6565 && current_function_args_info.fprs < FP_ARG_NUM_REG) 6566 { 6567 int min_fpr = current_function_args_info.fprs; 6568 int max_fpr = min_fpr + cfun->va_list_fpr_size; 6569 if (max_fpr > FP_ARG_NUM_REG) 6570 max_fpr = FP_ARG_NUM_REG; 6571 6572 /* ??? This is currently required to ensure proper location 6573 of the fpr save slots within the va_list save area. */ 6574 if (TARGET_PACKED_STACK) 6575 min_fpr = 0; 6576 6577 for (i = min_fpr; i < max_fpr; i++) 6578 cfun_set_fpr_bit (i); 6579 } 6580 } 6581 6582 if (!TARGET_64BIT) 6583 for (i = 2; i < 4; i++) 6584 if (regs_ever_live[i + 16] && !global_regs[i + 16]) 6585 cfun_set_fpr_bit (i); 6586} 6587 6588/* Fill cfun->machine with info about frame of current function. */ 6589 6590static void 6591s390_frame_info (void) 6592{ 6593 int i; 6594 6595 cfun_frame_layout.frame_size = get_frame_size (); 6596 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000) 6597 fatal_error ("total size of local variables exceeds architecture limit"); 6598 6599 if (!TARGET_PACKED_STACK) 6600 { 6601 cfun_frame_layout.backchain_offset = 0; 6602 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD; 6603 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8; 6604 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8; 6605 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot 6606 * UNITS_PER_WORD); 6607 } 6608 else if (TARGET_BACKCHAIN) /* kernel stack layout */ 6609 { 6610 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET 6611 - UNITS_PER_WORD); 6612 cfun_frame_layout.gprs_offset 6613 = (cfun_frame_layout.backchain_offset 6614 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1) 6615 * UNITS_PER_WORD); 6616 6617 if (TARGET_64BIT) 6618 { 6619 cfun_frame_layout.f4_offset 6620 = (cfun_frame_layout.gprs_offset 6621 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3))); 6622 6623 cfun_frame_layout.f0_offset 6624 = (cfun_frame_layout.f4_offset 6625 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1))); 6626 } 6627 else 6628 { 6629 /* On 31 bit we have to care about alignment of the 6630 floating point regs to provide fastest access. */ 6631 cfun_frame_layout.f0_offset 6632 = ((cfun_frame_layout.gprs_offset 6633 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)) 6634 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1))); 6635 6636 cfun_frame_layout.f4_offset 6637 = (cfun_frame_layout.f0_offset 6638 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3))); 6639 } 6640 } 6641 else /* no backchain */ 6642 { 6643 cfun_frame_layout.f4_offset 6644 = (STACK_POINTER_OFFSET 6645 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3))); 6646 6647 cfun_frame_layout.f0_offset 6648 = (cfun_frame_layout.f4_offset 6649 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1))); 6650 6651 cfun_frame_layout.gprs_offset 6652 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size; 6653 } 6654 6655 if (current_function_is_leaf 6656 && !TARGET_TPF_PROFILING 6657 && cfun_frame_layout.frame_size == 0 6658 && !cfun_save_high_fprs_p 6659 && !current_function_calls_alloca 6660 && !current_function_stdarg) 6661 return; 6662 6663 if (!TARGET_PACKED_STACK) 6664 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET 6665 + current_function_outgoing_args_size 6666 + cfun_frame_layout.high_fprs * 8); 6667 else 6668 { 6669 if (TARGET_BACKCHAIN) 6670 cfun_frame_layout.frame_size += UNITS_PER_WORD; 6671 6672 /* No alignment trouble here because f8-f15 are only saved under 6673 64 bit. */ 6674 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset, 6675 cfun_frame_layout.f4_offset), 6676 cfun_frame_layout.gprs_offset) 6677 - cfun_frame_layout.high_fprs * 8); 6678 6679 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8; 6680 6681 for (i = 0; i < 8; i++) 6682 if (cfun_fpr_bit_p (i)) 6683 cfun_frame_layout.frame_size += 8; 6684 6685 cfun_frame_layout.frame_size += cfun_gprs_save_area_size; 6686 6687 /* If under 31 bit an odd number of gprs has to be saved we have to adjust 6688 the frame size to sustain 8 byte alignment of stack frames. */ 6689 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size + 6690 STACK_BOUNDARY / BITS_PER_UNIT - 1) 6691 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)); 6692 6693 cfun_frame_layout.frame_size += current_function_outgoing_args_size; 6694 } 6695} 6696 6697/* Generate frame layout. Fills in register and frame data for the current 6698 function in cfun->machine. This routine can be called multiple times; 6699 it will re-do the complete frame layout every time. */ 6700 6701static void 6702s390_init_frame_layout (void) 6703{ 6704 HOST_WIDE_INT frame_size; 6705 int base_used; 6706 int clobbered_regs[16]; 6707 6708 /* On S/390 machines, we may need to perform branch splitting, which 6709 will require both base and return address register. We have no 6710 choice but to assume we're going to need them until right at the 6711 end of the machine dependent reorg phase. */ 6712 if (!TARGET_CPU_ZARCH) 6713 cfun->machine->split_branches_pending_p = true; 6714 6715 do 6716 { 6717 frame_size = cfun_frame_layout.frame_size; 6718 6719 /* Try to predict whether we'll need the base register. */ 6720 base_used = cfun->machine->split_branches_pending_p 6721 || current_function_uses_const_pool 6722 || (!DISP_IN_RANGE (frame_size) 6723 && !CONST_OK_FOR_K (frame_size)); 6724 6725 /* Decide which register to use as literal pool base. In small 6726 leaf functions, try to use an unused call-clobbered register 6727 as base register to avoid save/restore overhead. */ 6728 if (!base_used) 6729 cfun->machine->base_reg = NULL_RTX; 6730 else if (current_function_is_leaf && !regs_ever_live[5]) 6731 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5); 6732 else 6733 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM); 6734 6735 s390_register_info (clobbered_regs); 6736 s390_frame_info (); 6737 } 6738 while (frame_size != cfun_frame_layout.frame_size); 6739} 6740 6741/* Update frame layout. Recompute actual register save data based on 6742 current info and update regs_ever_live for the special registers. 6743 May be called multiple times, but may never cause *more* registers 6744 to be saved than s390_init_frame_layout allocated room for. */ 6745 6746static void 6747s390_update_frame_layout (void) 6748{ 6749 int clobbered_regs[16]; 6750 6751 s390_register_info (clobbered_regs); 6752 6753 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM]; 6754 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM]; 6755 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM]; 6756 6757 if (cfun->machine->base_reg) 6758 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1; 6759} 6760 6761/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ 6762 6763bool 6764s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg) 6765{ 6766 /* Once we've decided upon a register to use as base register, it must 6767 no longer be used for any other purpose. */ 6768 if (cfun->machine->base_reg) 6769 if (REGNO (cfun->machine->base_reg) == old_reg 6770 || REGNO (cfun->machine->base_reg) == new_reg) 6771 return false; 6772 6773 return true; 6774} 6775 6776/* Return true if register FROM can be eliminated via register TO. */ 6777 6778bool 6779s390_can_eliminate (int from, int to) 6780{ 6781 /* On zSeries machines, we have not marked the base register as fixed. 6782 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM. 6783 If a function requires the base register, we say here that this 6784 elimination cannot be performed. This will cause reload to free 6785 up the base register (as if it were fixed). On the other hand, 6786 if the current function does *not* require the base register, we 6787 say here the elimination succeeds, which in turn allows reload 6788 to allocate the base register for any other purpose. */ 6789 if (from == BASE_REGNUM && to == BASE_REGNUM) 6790 { 6791 if (TARGET_CPU_ZARCH) 6792 { 6793 s390_init_frame_layout (); 6794 return cfun->machine->base_reg == NULL_RTX; 6795 } 6796 6797 return false; 6798 } 6799 6800 /* Everything else must point into the stack frame. */ 6801 gcc_assert (to == STACK_POINTER_REGNUM 6802 || to == HARD_FRAME_POINTER_REGNUM); 6803 6804 gcc_assert (from == FRAME_POINTER_REGNUM 6805 || from == ARG_POINTER_REGNUM 6806 || from == RETURN_ADDRESS_POINTER_REGNUM); 6807 6808 /* Make sure we actually saved the return address. */ 6809 if (from == RETURN_ADDRESS_POINTER_REGNUM) 6810 if (!current_function_calls_eh_return 6811 && !current_function_stdarg 6812 && !cfun_frame_layout.save_return_addr_p) 6813 return false; 6814 6815 return true; 6816} 6817 6818/* Return offset between register FROM and TO initially after prolog. */ 6819 6820HOST_WIDE_INT 6821s390_initial_elimination_offset (int from, int to) 6822{ 6823 HOST_WIDE_INT offset; 6824 int index; 6825 6826 /* ??? Why are we called for non-eliminable pairs? */ 6827 if (!s390_can_eliminate (from, to)) 6828 return 0; 6829 6830 switch (from) 6831 { 6832 case FRAME_POINTER_REGNUM: 6833 offset = (get_frame_size() 6834 + STACK_POINTER_OFFSET 6835 + current_function_outgoing_args_size); 6836 break; 6837 6838 case ARG_POINTER_REGNUM: 6839 s390_init_frame_layout (); 6840 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET; 6841 break; 6842 6843 case RETURN_ADDRESS_POINTER_REGNUM: 6844 s390_init_frame_layout (); 6845 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot; 6846 gcc_assert (index >= 0); 6847 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset; 6848 offset += index * UNITS_PER_WORD; 6849 break; 6850 6851 case BASE_REGNUM: 6852 offset = 0; 6853 break; 6854 6855 default: 6856 gcc_unreachable (); 6857 } 6858 6859 return offset; 6860} 6861 6862/* Emit insn to save fpr REGNUM at offset OFFSET relative 6863 to register BASE. Return generated insn. */ 6864 6865static rtx 6866save_fpr (rtx base, int offset, int regnum) 6867{ 6868 rtx addr; 6869 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset)); 6870 6871 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG)) 6872 set_mem_alias_set (addr, get_varargs_alias_set ()); 6873 else 6874 set_mem_alias_set (addr, get_frame_alias_set ()); 6875 6876 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum)); 6877} 6878 6879/* Emit insn to restore fpr REGNUM from offset OFFSET relative 6880 to register BASE. Return generated insn. */ 6881 6882static rtx 6883restore_fpr (rtx base, int offset, int regnum) 6884{ 6885 rtx addr; 6886 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset)); 6887 set_mem_alias_set (addr, get_frame_alias_set ()); 6888 6889 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr); 6890} 6891 6892/* Generate insn to save registers FIRST to LAST into 6893 the register save area located at offset OFFSET 6894 relative to register BASE. */ 6895 6896static rtx 6897save_gprs (rtx base, int offset, int first, int last) 6898{ 6899 rtx addr, insn, note; 6900 int i; 6901 6902 addr = plus_constant (base, offset); 6903 addr = gen_rtx_MEM (Pmode, addr); 6904 6905 set_mem_alias_set (addr, get_frame_alias_set ()); 6906 6907 /* Special-case single register. */ 6908 if (first == last) 6909 { 6910 if (TARGET_64BIT) 6911 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first)); 6912 else 6913 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first)); 6914 6915 RTX_FRAME_RELATED_P (insn) = 1; 6916 return insn; 6917 } 6918 6919 6920 insn = gen_store_multiple (addr, 6921 gen_rtx_REG (Pmode, first), 6922 GEN_INT (last - first + 1)); 6923 6924 if (first <= 6 && current_function_stdarg) 6925 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 6926 { 6927 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0); 6928 6929 if (first + i <= 6) 6930 set_mem_alias_set (mem, get_varargs_alias_set ()); 6931 } 6932 6933 /* We need to set the FRAME_RELATED flag on all SETs 6934 inside the store-multiple pattern. 6935 6936 However, we must not emit DWARF records for registers 2..5 6937 if they are stored for use by variable arguments ... 6938 6939 ??? Unfortunately, it is not enough to simply not the 6940 FRAME_RELATED flags for those SETs, because the first SET 6941 of the PARALLEL is always treated as if it had the flag 6942 set, even if it does not. Therefore we emit a new pattern 6943 without those registers as REG_FRAME_RELATED_EXPR note. */ 6944 6945 if (first >= 6) 6946 { 6947 rtx pat = PATTERN (insn); 6948 6949 for (i = 0; i < XVECLEN (pat, 0); i++) 6950 if (GET_CODE (XVECEXP (pat, 0, i)) == SET) 6951 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1; 6952 6953 RTX_FRAME_RELATED_P (insn) = 1; 6954 } 6955 else if (last >= 6) 6956 { 6957 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD); 6958 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr), 6959 gen_rtx_REG (Pmode, 6), 6960 GEN_INT (last - 6 + 1)); 6961 note = PATTERN (note); 6962 6963 REG_NOTES (insn) = 6964 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 6965 note, REG_NOTES (insn)); 6966 6967 for (i = 0; i < XVECLEN (note, 0); i++) 6968 if (GET_CODE (XVECEXP (note, 0, i)) == SET) 6969 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1; 6970 6971 RTX_FRAME_RELATED_P (insn) = 1; 6972 } 6973 6974 return insn; 6975} 6976 6977/* Generate insn to restore registers FIRST to LAST from 6978 the register save area located at offset OFFSET 6979 relative to register BASE. */ 6980 6981static rtx 6982restore_gprs (rtx base, int offset, int first, int last) 6983{ 6984 rtx addr, insn; 6985 6986 addr = plus_constant (base, offset); 6987 addr = gen_rtx_MEM (Pmode, addr); 6988 set_mem_alias_set (addr, get_frame_alias_set ()); 6989 6990 /* Special-case single register. */ 6991 if (first == last) 6992 { 6993 if (TARGET_64BIT) 6994 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr); 6995 else 6996 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr); 6997 6998 return insn; 6999 } 7000 7001 insn = gen_load_multiple (gen_rtx_REG (Pmode, first), 7002 addr, 7003 GEN_INT (last - first + 1)); 7004 return insn; 7005} 7006 7007/* Return insn sequence to load the GOT register. */ 7008 7009static GTY(()) rtx got_symbol; 7010rtx 7011s390_load_got (void) 7012{ 7013 rtx insns; 7014 7015 if (!got_symbol) 7016 { 7017 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 7018 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL; 7019 } 7020 7021 start_sequence (); 7022 7023 if (TARGET_CPU_ZARCH) 7024 { 7025 emit_move_insn (pic_offset_table_rtx, got_symbol); 7026 } 7027 else 7028 { 7029 rtx offset; 7030 7031 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol), 7032 UNSPEC_LTREL_OFFSET); 7033 offset = gen_rtx_CONST (Pmode, offset); 7034 offset = force_const_mem (Pmode, offset); 7035 7036 emit_move_insn (pic_offset_table_rtx, offset); 7037 7038 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)), 7039 UNSPEC_LTREL_BASE); 7040 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset); 7041 7042 emit_move_insn (pic_offset_table_rtx, offset); 7043 } 7044 7045 insns = get_insns (); 7046 end_sequence (); 7047 return insns; 7048} 7049 7050/* Expand the prologue into a bunch of separate insns. */ 7051 7052void 7053s390_emit_prologue (void) 7054{ 7055 rtx insn, addr; 7056 rtx temp_reg; 7057 int i; 7058 int offset; 7059 int next_fpr = 0; 7060 7061 /* Complete frame layout. */ 7062 7063 s390_update_frame_layout (); 7064 7065 /* Annotate all constant pool references to let the scheduler know 7066 they implicitly use the base register. */ 7067 7068 push_topmost_sequence (); 7069 7070 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 7071 if (INSN_P (insn)) 7072 annotate_constant_pool_refs (&PATTERN (insn)); 7073 7074 pop_topmost_sequence (); 7075 7076 /* Choose best register to use for temp use within prologue. 7077 See below for why TPF must use the register 1. */ 7078 7079 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM) 7080 && !current_function_is_leaf 7081 && !TARGET_TPF_PROFILING) 7082 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); 7083 else 7084 temp_reg = gen_rtx_REG (Pmode, 1); 7085 7086 /* Save call saved gprs. */ 7087 if (cfun_frame_layout.first_save_gpr != -1) 7088 { 7089 insn = save_gprs (stack_pointer_rtx, 7090 cfun_frame_layout.gprs_offset + 7091 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr 7092 - cfun_frame_layout.first_save_gpr_slot), 7093 cfun_frame_layout.first_save_gpr, 7094 cfun_frame_layout.last_save_gpr); 7095 emit_insn (insn); 7096 } 7097 7098 /* Dummy insn to mark literal pool slot. */ 7099 7100 if (cfun->machine->base_reg) 7101 emit_insn (gen_main_pool (cfun->machine->base_reg)); 7102 7103 offset = cfun_frame_layout.f0_offset; 7104 7105 /* Save f0 and f2. */ 7106 for (i = 0; i < 2; i++) 7107 { 7108 if (cfun_fpr_bit_p (i)) 7109 { 7110 save_fpr (stack_pointer_rtx, offset, i + 16); 7111 offset += 8; 7112 } 7113 else if (!TARGET_PACKED_STACK) 7114 offset += 8; 7115 } 7116 7117 /* Save f4 and f6. */ 7118 offset = cfun_frame_layout.f4_offset; 7119 for (i = 2; i < 4; i++) 7120 { 7121 if (cfun_fpr_bit_p (i)) 7122 { 7123 insn = save_fpr (stack_pointer_rtx, offset, i + 16); 7124 offset += 8; 7125 7126 /* If f4 and f6 are call clobbered they are saved due to stdargs and 7127 therefore are not frame related. */ 7128 if (!call_really_used_regs[i + 16]) 7129 RTX_FRAME_RELATED_P (insn) = 1; 7130 } 7131 else if (!TARGET_PACKED_STACK) 7132 offset += 8; 7133 } 7134 7135 if (TARGET_PACKED_STACK 7136 && cfun_save_high_fprs_p 7137 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0) 7138 { 7139 offset = (cfun_frame_layout.f8_offset 7140 + (cfun_frame_layout.high_fprs - 1) * 8); 7141 7142 for (i = 15; i > 7 && offset >= 0; i--) 7143 if (cfun_fpr_bit_p (i)) 7144 { 7145 insn = save_fpr (stack_pointer_rtx, offset, i + 16); 7146 7147 RTX_FRAME_RELATED_P (insn) = 1; 7148 offset -= 8; 7149 } 7150 if (offset >= cfun_frame_layout.f8_offset) 7151 next_fpr = i + 16; 7152 } 7153 7154 if (!TARGET_PACKED_STACK) 7155 next_fpr = cfun_save_high_fprs_p ? 31 : 0; 7156 7157 /* Decrement stack pointer. */ 7158 7159 if (cfun_frame_layout.frame_size > 0) 7160 { 7161 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size); 7162 7163 if (s390_stack_size) 7164 { 7165 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1) 7166 & ~(s390_stack_guard - 1)); 7167 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx, 7168 GEN_INT (stack_check_mask)); 7169 7170 if (TARGET_64BIT) 7171 gen_cmpdi (t, const0_rtx); 7172 else 7173 gen_cmpsi (t, const0_rtx); 7174 7175 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode, 7176 gen_rtx_REG (CCmode, 7177 CC_REGNUM), 7178 const0_rtx), 7179 const0_rtx)); 7180 } 7181 7182 if (s390_warn_framesize > 0 7183 && cfun_frame_layout.frame_size >= s390_warn_framesize) 7184 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes", 7185 current_function_name (), cfun_frame_layout.frame_size); 7186 7187 if (s390_warn_dynamicstack_p && cfun->calls_alloca) 7188 warning (0, "%qs uses dynamic stack allocation", current_function_name ()); 7189 7190 /* Save incoming stack pointer into temp reg. */ 7191 if (TARGET_BACKCHAIN || next_fpr) 7192 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx)); 7193 7194 /* Subtract frame size from stack pointer. */ 7195 7196 if (DISP_IN_RANGE (INTVAL (frame_off))) 7197 { 7198 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx, 7199 gen_rtx_PLUS (Pmode, stack_pointer_rtx, 7200 frame_off)); 7201 insn = emit_insn (insn); 7202 } 7203 else 7204 { 7205 if (!CONST_OK_FOR_K (INTVAL (frame_off))) 7206 frame_off = force_const_mem (Pmode, frame_off); 7207 7208 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off)); 7209 annotate_constant_pool_refs (&PATTERN (insn)); 7210 } 7211 7212 RTX_FRAME_RELATED_P (insn) = 1; 7213 REG_NOTES (insn) = 7214 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 7215 gen_rtx_SET (VOIDmode, stack_pointer_rtx, 7216 gen_rtx_PLUS (Pmode, stack_pointer_rtx, 7217 GEN_INT (-cfun_frame_layout.frame_size))), 7218 REG_NOTES (insn)); 7219 7220 /* Set backchain. */ 7221 7222 if (TARGET_BACKCHAIN) 7223 { 7224 if (cfun_frame_layout.backchain_offset) 7225 addr = gen_rtx_MEM (Pmode, 7226 plus_constant (stack_pointer_rtx, 7227 cfun_frame_layout.backchain_offset)); 7228 else 7229 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx); 7230 set_mem_alias_set (addr, get_frame_alias_set ()); 7231 insn = emit_insn (gen_move_insn (addr, temp_reg)); 7232 } 7233 7234 /* If we support asynchronous exceptions (e.g. for Java), 7235 we need to make sure the backchain pointer is set up 7236 before any possibly trapping memory access. */ 7237 7238 if (TARGET_BACKCHAIN && flag_non_call_exceptions) 7239 { 7240 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)); 7241 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr)); 7242 } 7243 } 7244 7245 /* Save fprs 8 - 15 (64 bit ABI). */ 7246 7247 if (cfun_save_high_fprs_p && next_fpr) 7248 { 7249 insn = emit_insn (gen_add2_insn (temp_reg, 7250 GEN_INT (cfun_frame_layout.f8_offset))); 7251 7252 offset = 0; 7253 7254 for (i = 24; i <= next_fpr; i++) 7255 if (cfun_fpr_bit_p (i - 16)) 7256 { 7257 rtx addr = plus_constant (stack_pointer_rtx, 7258 cfun_frame_layout.frame_size 7259 + cfun_frame_layout.f8_offset 7260 + offset); 7261 7262 insn = save_fpr (temp_reg, offset, i); 7263 offset += 8; 7264 RTX_FRAME_RELATED_P (insn) = 1; 7265 REG_NOTES (insn) = 7266 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 7267 gen_rtx_SET (VOIDmode, 7268 gen_rtx_MEM (DFmode, addr), 7269 gen_rtx_REG (DFmode, i)), 7270 REG_NOTES (insn)); 7271 } 7272 } 7273 7274 /* Set frame pointer, if needed. */ 7275 7276 if (frame_pointer_needed) 7277 { 7278 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); 7279 RTX_FRAME_RELATED_P (insn) = 1; 7280 } 7281 7282 /* Set up got pointer, if needed. */ 7283 7284 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) 7285 { 7286 rtx insns = s390_load_got (); 7287 7288 for (insn = insns; insn; insn = NEXT_INSN (insn)) 7289 { 7290 annotate_constant_pool_refs (&PATTERN (insn)); 7291 7292 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX, 7293 REG_NOTES (insn)); 7294 } 7295 7296 emit_insn (insns); 7297 } 7298 7299 if (TARGET_TPF_PROFILING) 7300 { 7301 /* Generate a BAS instruction to serve as a function 7302 entry intercept to facilitate the use of tracing 7303 algorithms located at the branch target. */ 7304 emit_insn (gen_prologue_tpf ()); 7305 7306 /* Emit a blockage here so that all code 7307 lies between the profiling mechanisms. */ 7308 emit_insn (gen_blockage ()); 7309 } 7310} 7311 7312/* Expand the epilogue into a bunch of separate insns. */ 7313 7314void 7315s390_emit_epilogue (bool sibcall) 7316{ 7317 rtx frame_pointer, return_reg; 7318 int area_bottom, area_top, offset = 0; 7319 int next_offset; 7320 rtvec p; 7321 int i; 7322 7323 if (TARGET_TPF_PROFILING) 7324 { 7325 7326 /* Generate a BAS instruction to serve as a function 7327 entry intercept to facilitate the use of tracing 7328 algorithms located at the branch target. */ 7329 7330 /* Emit a blockage here so that all code 7331 lies between the profiling mechanisms. */ 7332 emit_insn (gen_blockage ()); 7333 7334 emit_insn (gen_epilogue_tpf ()); 7335 } 7336 7337 /* Check whether to use frame or stack pointer for restore. */ 7338 7339 frame_pointer = (frame_pointer_needed 7340 ? hard_frame_pointer_rtx : stack_pointer_rtx); 7341 7342 s390_frame_area (&area_bottom, &area_top); 7343 7344 /* Check whether we can access the register save area. 7345 If not, increment the frame pointer as required. */ 7346 7347 if (area_top <= area_bottom) 7348 { 7349 /* Nothing to restore. */ 7350 } 7351 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom) 7352 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1)) 7353 { 7354 /* Area is in range. */ 7355 offset = cfun_frame_layout.frame_size; 7356 } 7357 else 7358 { 7359 rtx insn, frame_off; 7360 7361 offset = area_bottom < 0 ? -area_bottom : 0; 7362 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset); 7363 7364 if (DISP_IN_RANGE (INTVAL (frame_off))) 7365 { 7366 insn = gen_rtx_SET (VOIDmode, frame_pointer, 7367 gen_rtx_PLUS (Pmode, frame_pointer, frame_off)); 7368 insn = emit_insn (insn); 7369 } 7370 else 7371 { 7372 if (!CONST_OK_FOR_K (INTVAL (frame_off))) 7373 frame_off = force_const_mem (Pmode, frame_off); 7374 7375 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off)); 7376 annotate_constant_pool_refs (&PATTERN (insn)); 7377 } 7378 } 7379 7380 /* Restore call saved fprs. */ 7381 7382 if (TARGET_64BIT) 7383 { 7384 if (cfun_save_high_fprs_p) 7385 { 7386 next_offset = cfun_frame_layout.f8_offset; 7387 for (i = 24; i < 32; i++) 7388 { 7389 if (cfun_fpr_bit_p (i - 16)) 7390 { 7391 restore_fpr (frame_pointer, 7392 offset + next_offset, i); 7393 next_offset += 8; 7394 } 7395 } 7396 } 7397 7398 } 7399 else 7400 { 7401 next_offset = cfun_frame_layout.f4_offset; 7402 for (i = 18; i < 20; i++) 7403 { 7404 if (cfun_fpr_bit_p (i - 16)) 7405 { 7406 restore_fpr (frame_pointer, 7407 offset + next_offset, i); 7408 next_offset += 8; 7409 } 7410 else if (!TARGET_PACKED_STACK) 7411 next_offset += 8; 7412 } 7413 7414 } 7415 7416 /* Return register. */ 7417 7418 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); 7419 7420 /* Restore call saved gprs. */ 7421 7422 if (cfun_frame_layout.first_restore_gpr != -1) 7423 { 7424 rtx insn, addr; 7425 int i; 7426 7427 /* Check for global register and save them 7428 to stack location from where they get restored. */ 7429 7430 for (i = cfun_frame_layout.first_restore_gpr; 7431 i <= cfun_frame_layout.last_restore_gpr; 7432 i++) 7433 { 7434 /* These registers are special and need to be 7435 restored in any case. */ 7436 if (i == STACK_POINTER_REGNUM 7437 || i == RETURN_REGNUM 7438 || i == BASE_REGNUM 7439 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM)) 7440 continue; 7441 7442 if (global_regs[i]) 7443 { 7444 addr = plus_constant (frame_pointer, 7445 offset + cfun_frame_layout.gprs_offset 7446 + (i - cfun_frame_layout.first_save_gpr_slot) 7447 * UNITS_PER_WORD); 7448 addr = gen_rtx_MEM (Pmode, addr); 7449 set_mem_alias_set (addr, get_frame_alias_set ()); 7450 emit_move_insn (addr, gen_rtx_REG (Pmode, i)); 7451 } 7452 } 7453 7454 if (! sibcall) 7455 { 7456 /* Fetch return address from stack before load multiple, 7457 this will do good for scheduling. */ 7458 7459 if (cfun_frame_layout.save_return_addr_p 7460 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM 7461 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM)) 7462 { 7463 int return_regnum = find_unused_clobbered_reg(); 7464 if (!return_regnum) 7465 return_regnum = 4; 7466 return_reg = gen_rtx_REG (Pmode, return_regnum); 7467 7468 addr = plus_constant (frame_pointer, 7469 offset + cfun_frame_layout.gprs_offset 7470 + (RETURN_REGNUM 7471 - cfun_frame_layout.first_save_gpr_slot) 7472 * UNITS_PER_WORD); 7473 addr = gen_rtx_MEM (Pmode, addr); 7474 set_mem_alias_set (addr, get_frame_alias_set ()); 7475 emit_move_insn (return_reg, addr); 7476 } 7477 } 7478 7479 insn = restore_gprs (frame_pointer, 7480 offset + cfun_frame_layout.gprs_offset 7481 + (cfun_frame_layout.first_restore_gpr 7482 - cfun_frame_layout.first_save_gpr_slot) 7483 * UNITS_PER_WORD, 7484 cfun_frame_layout.first_restore_gpr, 7485 cfun_frame_layout.last_restore_gpr); 7486 emit_insn (insn); 7487 } 7488 7489 if (! sibcall) 7490 { 7491 7492 /* Return to caller. */ 7493 7494 p = rtvec_alloc (2); 7495 7496 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); 7497 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg); 7498 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); 7499 } 7500} 7501 7502 7503/* Return the size in bytes of a function argument of 7504 type TYPE and/or mode MODE. At least one of TYPE or 7505 MODE must be specified. */ 7506 7507static int 7508s390_function_arg_size (enum machine_mode mode, tree type) 7509{ 7510 if (type) 7511 return int_size_in_bytes (type); 7512 7513 /* No type info available for some library calls ... */ 7514 if (mode != BLKmode) 7515 return GET_MODE_SIZE (mode); 7516 7517 /* If we have neither type nor mode, abort */ 7518 gcc_unreachable (); 7519} 7520 7521/* Return true if a function argument of type TYPE and mode MODE 7522 is to be passed in a floating-point register, if available. */ 7523 7524static bool 7525s390_function_arg_float (enum machine_mode mode, tree type) 7526{ 7527 int size = s390_function_arg_size (mode, type); 7528 if (size > 8) 7529 return false; 7530 7531 /* Soft-float changes the ABI: no floating-point registers are used. */ 7532 if (TARGET_SOFT_FLOAT) 7533 return false; 7534 7535 /* No type info available for some library calls ... */ 7536 if (!type) 7537 return mode == SFmode || mode == DFmode; 7538 7539 /* The ABI says that record types with a single member are treated 7540 just like that member would be. */ 7541 while (TREE_CODE (type) == RECORD_TYPE) 7542 { 7543 tree field, single = NULL_TREE; 7544 7545 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 7546 { 7547 if (TREE_CODE (field) != FIELD_DECL) 7548 continue; 7549 7550 if (single == NULL_TREE) 7551 single = TREE_TYPE (field); 7552 else 7553 return false; 7554 } 7555 7556 if (single == NULL_TREE) 7557 return false; 7558 else 7559 type = single; 7560 } 7561 7562 return TREE_CODE (type) == REAL_TYPE; 7563} 7564 7565/* Return true if a function argument of type TYPE and mode MODE 7566 is to be passed in an integer register, or a pair of integer 7567 registers, if available. */ 7568 7569static bool 7570s390_function_arg_integer (enum machine_mode mode, tree type) 7571{ 7572 int size = s390_function_arg_size (mode, type); 7573 if (size > 8) 7574 return false; 7575 7576 /* No type info available for some library calls ... */ 7577 if (!type) 7578 return GET_MODE_CLASS (mode) == MODE_INT 7579 || (TARGET_SOFT_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT); 7580 7581 /* We accept small integral (and similar) types. */ 7582 if (INTEGRAL_TYPE_P (type) 7583 || POINTER_TYPE_P (type) 7584 || TREE_CODE (type) == OFFSET_TYPE 7585 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE)) 7586 return true; 7587 7588 /* We also accept structs of size 1, 2, 4, 8 that are not 7589 passed in floating-point registers. */ 7590 if (AGGREGATE_TYPE_P (type) 7591 && exact_log2 (size) >= 0 7592 && !s390_function_arg_float (mode, type)) 7593 return true; 7594 7595 return false; 7596} 7597 7598/* Return 1 if a function argument of type TYPE and mode MODE 7599 is to be passed by reference. The ABI specifies that only 7600 structures of size 1, 2, 4, or 8 bytes are passed by value, 7601 all other structures (and complex numbers) are passed by 7602 reference. */ 7603 7604static bool 7605s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, 7606 enum machine_mode mode, tree type, 7607 bool named ATTRIBUTE_UNUSED) 7608{ 7609 int size = s390_function_arg_size (mode, type); 7610 if (size > 8) 7611 return true; 7612 7613 if (type) 7614 { 7615 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0) 7616 return 1; 7617 7618 if (TREE_CODE (type) == COMPLEX_TYPE 7619 || TREE_CODE (type) == VECTOR_TYPE) 7620 return 1; 7621 } 7622 7623 return 0; 7624} 7625 7626/* Update the data in CUM to advance over an argument of mode MODE and 7627 data type TYPE. (TYPE is null for libcalls where that information 7628 may not be available.). The boolean NAMED specifies whether the 7629 argument is a named argument (as opposed to an unnamed argument 7630 matching an ellipsis). */ 7631 7632void 7633s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, 7634 tree type, int named ATTRIBUTE_UNUSED) 7635{ 7636 if (s390_function_arg_float (mode, type)) 7637 { 7638 cum->fprs += 1; 7639 } 7640 else if (s390_function_arg_integer (mode, type)) 7641 { 7642 int size = s390_function_arg_size (mode, type); 7643 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD); 7644 } 7645 else 7646 gcc_unreachable (); 7647} 7648 7649/* Define where to put the arguments to a function. 7650 Value is zero to push the argument on the stack, 7651 or a hard register in which to store the argument. 7652 7653 MODE is the argument's machine mode. 7654 TYPE is the data type of the argument (as a tree). 7655 This is null for libcalls where that information may 7656 not be available. 7657 CUM is a variable of type CUMULATIVE_ARGS which gives info about 7658 the preceding args and about the function being called. 7659 NAMED is nonzero if this argument is a named parameter 7660 (otherwise it is an extra parameter matching an ellipsis). 7661 7662 On S/390, we use general purpose registers 2 through 6 to 7663 pass integer, pointer, and certain structure arguments, and 7664 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit) 7665 to pass floating point arguments. All remaining arguments 7666 are pushed to the stack. */ 7667 7668rtx 7669s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, 7670 int named ATTRIBUTE_UNUSED) 7671{ 7672 if (s390_function_arg_float (mode, type)) 7673 { 7674 if (cum->fprs + 1 > FP_ARG_NUM_REG) 7675 return 0; 7676 else 7677 return gen_rtx_REG (mode, cum->fprs + 16); 7678 } 7679 else if (s390_function_arg_integer (mode, type)) 7680 { 7681 int size = s390_function_arg_size (mode, type); 7682 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD; 7683 7684 if (cum->gprs + n_gprs > GP_ARG_NUM_REG) 7685 return 0; 7686 else 7687 return gen_rtx_REG (mode, cum->gprs + 2); 7688 } 7689 7690 /* After the real arguments, expand_call calls us once again 7691 with a void_type_node type. Whatever we return here is 7692 passed as operand 2 to the call expanders. 7693 7694 We don't need this feature ... */ 7695 else if (type == void_type_node) 7696 return const0_rtx; 7697 7698 gcc_unreachable (); 7699} 7700 7701/* Return true if return values of type TYPE should be returned 7702 in a memory buffer whose address is passed by the caller as 7703 hidden first argument. */ 7704 7705static bool 7706s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED) 7707{ 7708 /* We accept small integral (and similar) types. */ 7709 if (INTEGRAL_TYPE_P (type) 7710 || POINTER_TYPE_P (type) 7711 || TREE_CODE (type) == OFFSET_TYPE 7712 || TREE_CODE (type) == REAL_TYPE) 7713 return int_size_in_bytes (type) > 8; 7714 7715 /* Aggregates and similar constructs are always returned 7716 in memory. */ 7717 if (AGGREGATE_TYPE_P (type) 7718 || TREE_CODE (type) == COMPLEX_TYPE 7719 || TREE_CODE (type) == VECTOR_TYPE) 7720 return true; 7721 7722 /* ??? We get called on all sorts of random stuff from 7723 aggregate_value_p. We can't abort, but it's not clear 7724 what's safe to return. Pretend it's a struct I guess. */ 7725 return true; 7726} 7727 7728/* Define where to return a (scalar) value of type TYPE. 7729 If TYPE is null, define where to return a (scalar) 7730 value of mode MODE from a libcall. */ 7731 7732rtx 7733s390_function_value (tree type, enum machine_mode mode) 7734{ 7735 if (type) 7736 { 7737 int unsignedp = TYPE_UNSIGNED (type); 7738 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1); 7739 } 7740 7741 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT 7742 || GET_MODE_CLASS (mode) == MODE_FLOAT); 7743 gcc_assert (GET_MODE_SIZE (mode) <= 8); 7744 7745 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) 7746 return gen_rtx_REG (mode, 16); 7747 else 7748 return gen_rtx_REG (mode, 2); 7749} 7750 7751 7752/* Create and return the va_list datatype. 7753 7754 On S/390, va_list is an array type equivalent to 7755 7756 typedef struct __va_list_tag 7757 { 7758 long __gpr; 7759 long __fpr; 7760 void *__overflow_arg_area; 7761 void *__reg_save_area; 7762 } va_list[1]; 7763 7764 where __gpr and __fpr hold the number of general purpose 7765 or floating point arguments used up to now, respectively, 7766 __overflow_arg_area points to the stack location of the 7767 next argument passed on the stack, and __reg_save_area 7768 always points to the start of the register area in the 7769 call frame of the current function. The function prologue 7770 saves all registers used for argument passing into this 7771 area if the function uses variable arguments. */ 7772 7773static tree 7774s390_build_builtin_va_list (void) 7775{ 7776 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; 7777 7778 record = lang_hooks.types.make_type (RECORD_TYPE); 7779 7780 type_decl = 7781 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); 7782 7783 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"), 7784 long_integer_type_node); 7785 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"), 7786 long_integer_type_node); 7787 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"), 7788 ptr_type_node); 7789 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"), 7790 ptr_type_node); 7791 7792 va_list_gpr_counter_field = f_gpr; 7793 va_list_fpr_counter_field = f_fpr; 7794 7795 DECL_FIELD_CONTEXT (f_gpr) = record; 7796 DECL_FIELD_CONTEXT (f_fpr) = record; 7797 DECL_FIELD_CONTEXT (f_ovf) = record; 7798 DECL_FIELD_CONTEXT (f_sav) = record; 7799 7800 TREE_CHAIN (record) = type_decl; 7801 TYPE_NAME (record) = type_decl; 7802 TYPE_FIELDS (record) = f_gpr; 7803 TREE_CHAIN (f_gpr) = f_fpr; 7804 TREE_CHAIN (f_fpr) = f_ovf; 7805 TREE_CHAIN (f_ovf) = f_sav; 7806 7807 layout_type (record); 7808 7809 /* The correct type is an array type of one element. */ 7810 return build_array_type (record, build_index_type (size_zero_node)); 7811} 7812 7813/* Implement va_start by filling the va_list structure VALIST. 7814 STDARG_P is always true, and ignored. 7815 NEXTARG points to the first anonymous stack argument. 7816 7817 The following global variables are used to initialize 7818 the va_list structure: 7819 7820 current_function_args_info: 7821 holds number of gprs and fprs used for named arguments. 7822 current_function_arg_offset_rtx: 7823 holds the offset of the first anonymous stack argument 7824 (relative to the virtual arg pointer). */ 7825 7826void 7827s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) 7828{ 7829 HOST_WIDE_INT n_gpr, n_fpr; 7830 int off; 7831 tree f_gpr, f_fpr, f_ovf, f_sav; 7832 tree gpr, fpr, ovf, sav, t; 7833 7834 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); 7835 f_fpr = TREE_CHAIN (f_gpr); 7836 f_ovf = TREE_CHAIN (f_fpr); 7837 f_sav = TREE_CHAIN (f_ovf); 7838 7839 valist = build_va_arg_indirect_ref (valist); 7840 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); 7841 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); 7842 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); 7843 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); 7844 7845 /* Count number of gp and fp argument registers used. */ 7846 7847 n_gpr = current_function_args_info.gprs; 7848 n_fpr = current_function_args_info.fprs; 7849 7850 if (cfun->va_list_gpr_size) 7851 { 7852 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, 7853 build_int_cst (NULL_TREE, n_gpr)); 7854 TREE_SIDE_EFFECTS (t) = 1; 7855 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 7856 } 7857 7858 if (cfun->va_list_fpr_size) 7859 { 7860 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, 7861 build_int_cst (NULL_TREE, n_fpr)); 7862 TREE_SIDE_EFFECTS (t) = 1; 7863 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 7864 } 7865 7866 /* Find the overflow area. */ 7867 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG 7868 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG) 7869 { 7870 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); 7871 7872 off = INTVAL (current_function_arg_offset_rtx); 7873 off = off < 0 ? 0 : off; 7874 if (TARGET_DEBUG_ARG) 7875 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n", 7876 (int)n_gpr, (int)n_fpr, off); 7877 7878 t = build (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off)); 7879 7880 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); 7881 TREE_SIDE_EFFECTS (t) = 1; 7882 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 7883 } 7884 7885 /* Find the register save area. */ 7886 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG) 7887 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG)) 7888 { 7889 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx); 7890 t = build (PLUS_EXPR, TREE_TYPE (sav), t, 7891 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD)); 7892 7893 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); 7894 TREE_SIDE_EFFECTS (t) = 1; 7895 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 7896 } 7897} 7898 7899/* Implement va_arg by updating the va_list structure 7900 VALIST as required to retrieve an argument of type 7901 TYPE, and returning that argument. 7902 7903 Generates code equivalent to: 7904 7905 if (integral value) { 7906 if (size <= 4 && args.gpr < 5 || 7907 size > 4 && args.gpr < 4 ) 7908 ret = args.reg_save_area[args.gpr+8] 7909 else 7910 ret = *args.overflow_arg_area++; 7911 } else if (float value) { 7912 if (args.fgpr < 2) 7913 ret = args.reg_save_area[args.fpr+64] 7914 else 7915 ret = *args.overflow_arg_area++; 7916 } else if (aggregate value) { 7917 if (args.gpr < 5) 7918 ret = *args.reg_save_area[args.gpr] 7919 else 7920 ret = **args.overflow_arg_area++; 7921 } */ 7922 7923static tree 7924s390_gimplify_va_arg (tree valist, tree type, tree *pre_p, 7925 tree *post_p ATTRIBUTE_UNUSED) 7926{ 7927 tree f_gpr, f_fpr, f_ovf, f_sav; 7928 tree gpr, fpr, ovf, sav, reg, t, u; 7929 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg; 7930 tree lab_false, lab_over, addr; 7931 7932 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); 7933 f_fpr = TREE_CHAIN (f_gpr); 7934 f_ovf = TREE_CHAIN (f_fpr); 7935 f_sav = TREE_CHAIN (f_ovf); 7936 7937 valist = build_va_arg_indirect_ref (valist); 7938 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); 7939 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); 7940 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); 7941 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); 7942 7943 size = int_size_in_bytes (type); 7944 7945 if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) 7946 { 7947 if (TARGET_DEBUG_ARG) 7948 { 7949 fprintf (stderr, "va_arg: aggregate type"); 7950 debug_tree (type); 7951 } 7952 7953 /* Aggregates are passed by reference. */ 7954 indirect_p = 1; 7955 reg = gpr; 7956 n_reg = 1; 7957 7958 /* kernel stack layout on 31 bit: It is assumed here that no padding 7959 will be added by s390_frame_info because for va_args always an even 7960 number of gprs has to be saved r15-r2 = 14 regs. */ 7961 sav_ofs = 2 * UNITS_PER_WORD; 7962 sav_scale = UNITS_PER_WORD; 7963 size = UNITS_PER_WORD; 7964 max_reg = GP_ARG_NUM_REG - n_reg; 7965 } 7966 else if (s390_function_arg_float (TYPE_MODE (type), type)) 7967 { 7968 if (TARGET_DEBUG_ARG) 7969 { 7970 fprintf (stderr, "va_arg: float type"); 7971 debug_tree (type); 7972 } 7973 7974 /* FP args go in FP registers, if present. */ 7975 indirect_p = 0; 7976 reg = fpr; 7977 n_reg = 1; 7978 sav_ofs = 16 * UNITS_PER_WORD; 7979 sav_scale = 8; 7980 max_reg = FP_ARG_NUM_REG - n_reg; 7981 } 7982 else 7983 { 7984 if (TARGET_DEBUG_ARG) 7985 { 7986 fprintf (stderr, "va_arg: other type"); 7987 debug_tree (type); 7988 } 7989 7990 /* Otherwise into GP registers. */ 7991 indirect_p = 0; 7992 reg = gpr; 7993 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 7994 7995 /* kernel stack layout on 31 bit: It is assumed here that no padding 7996 will be added by s390_frame_info because for va_args always an even 7997 number of gprs has to be saved r15-r2 = 14 regs. */ 7998 sav_ofs = 2 * UNITS_PER_WORD; 7999 8000 if (size < UNITS_PER_WORD) 8001 sav_ofs += UNITS_PER_WORD - size; 8002 8003 sav_scale = UNITS_PER_WORD; 8004 max_reg = GP_ARG_NUM_REG - n_reg; 8005 } 8006 8007 /* Pull the value out of the saved registers ... */ 8008 8009 lab_false = create_artificial_label (); 8010 lab_over = create_artificial_label (); 8011 addr = create_tmp_var (ptr_type_node, "addr"); 8012 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); 8013 8014 t = fold_convert (TREE_TYPE (reg), size_int (max_reg)); 8015 t = build2 (GT_EXPR, boolean_type_node, reg, t); 8016 u = build1 (GOTO_EXPR, void_type_node, lab_false); 8017 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); 8018 gimplify_and_add (t, pre_p); 8019 8020 t = build2 (PLUS_EXPR, ptr_type_node, sav, 8021 fold_convert (ptr_type_node, size_int (sav_ofs))); 8022 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg, 8023 fold_convert (TREE_TYPE (reg), size_int (sav_scale))); 8024 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u)); 8025 8026 t = build2 (MODIFY_EXPR, void_type_node, addr, t); 8027 gimplify_and_add (t, pre_p); 8028 8029 t = build1 (GOTO_EXPR, void_type_node, lab_over); 8030 gimplify_and_add (t, pre_p); 8031 8032 t = build1 (LABEL_EXPR, void_type_node, lab_false); 8033 append_to_statement_list (t, pre_p); 8034 8035 8036 /* ... Otherwise out of the overflow area. */ 8037 8038 t = ovf; 8039 if (size < UNITS_PER_WORD) 8040 t = build2 (PLUS_EXPR, ptr_type_node, t, 8041 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size))); 8042 8043 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); 8044 8045 u = build2 (MODIFY_EXPR, void_type_node, addr, t); 8046 gimplify_and_add (u, pre_p); 8047 8048 t = build2 (PLUS_EXPR, ptr_type_node, t, 8049 fold_convert (ptr_type_node, size_int (size))); 8050 t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t); 8051 gimplify_and_add (t, pre_p); 8052 8053 t = build1 (LABEL_EXPR, void_type_node, lab_over); 8054 append_to_statement_list (t, pre_p); 8055 8056 8057 /* Increment register save count. */ 8058 8059 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg, 8060 fold_convert (TREE_TYPE (reg), size_int (n_reg))); 8061 gimplify_and_add (u, pre_p); 8062 8063 if (indirect_p) 8064 { 8065 t = build_pointer_type (build_pointer_type (type)); 8066 addr = fold_convert (t, addr); 8067 addr = build_va_arg_indirect_ref (addr); 8068 } 8069 else 8070 { 8071 t = build_pointer_type (type); 8072 addr = fold_convert (t, addr); 8073 } 8074 8075 return build_va_arg_indirect_ref (addr); 8076} 8077 8078 8079/* Builtins. */ 8080 8081enum s390_builtin 8082{ 8083 S390_BUILTIN_THREAD_POINTER, 8084 S390_BUILTIN_SET_THREAD_POINTER, 8085 8086 S390_BUILTIN_max 8087}; 8088 8089static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = { 8090 CODE_FOR_get_tp_64, 8091 CODE_FOR_set_tp_64 8092}; 8093 8094static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = { 8095 CODE_FOR_get_tp_31, 8096 CODE_FOR_set_tp_31 8097}; 8098 8099static void 8100s390_init_builtins (void) 8101{ 8102 tree ftype; 8103 8104 ftype = build_function_type (ptr_type_node, void_list_node); 8105 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype, 8106 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD, 8107 NULL, NULL_TREE); 8108 8109 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE); 8110 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype, 8111 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD, 8112 NULL, NULL_TREE); 8113} 8114 8115/* Expand an expression EXP that calls a built-in function, 8116 with result going to TARGET if that's convenient 8117 (and in mode MODE if that's convenient). 8118 SUBTARGET may be used as the target for computing one of EXP's operands. 8119 IGNORE is nonzero if the value is to be ignored. */ 8120 8121static rtx 8122s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, 8123 enum machine_mode mode ATTRIBUTE_UNUSED, 8124 int ignore ATTRIBUTE_UNUSED) 8125{ 8126#define MAX_ARGS 2 8127 8128 unsigned int const *code_for_builtin = 8129 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31; 8130 8131 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 8132 unsigned int fcode = DECL_FUNCTION_CODE (fndecl); 8133 tree arglist = TREE_OPERAND (exp, 1); 8134 enum insn_code icode; 8135 rtx op[MAX_ARGS], pat; 8136 int arity; 8137 bool nonvoid; 8138 8139 if (fcode >= S390_BUILTIN_max) 8140 internal_error ("bad builtin fcode"); 8141 icode = code_for_builtin[fcode]; 8142 if (icode == 0) 8143 internal_error ("bad builtin fcode"); 8144 8145 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; 8146 8147 for (arglist = TREE_OPERAND (exp, 1), arity = 0; 8148 arglist; 8149 arglist = TREE_CHAIN (arglist), arity++) 8150 { 8151 const struct insn_operand_data *insn_op; 8152 8153 tree arg = TREE_VALUE (arglist); 8154 if (arg == error_mark_node) 8155 return NULL_RTX; 8156 if (arity > MAX_ARGS) 8157 return NULL_RTX; 8158 8159 insn_op = &insn_data[icode].operand[arity + nonvoid]; 8160 8161 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0); 8162 8163 if (!(*insn_op->predicate) (op[arity], insn_op->mode)) 8164 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]); 8165 } 8166 8167 if (nonvoid) 8168 { 8169 enum machine_mode tmode = insn_data[icode].operand[0].mode; 8170 if (!target 8171 || GET_MODE (target) != tmode 8172 || !(*insn_data[icode].operand[0].predicate) (target, tmode)) 8173 target = gen_reg_rtx (tmode); 8174 } 8175 8176 switch (arity) 8177 { 8178 case 0: 8179 pat = GEN_FCN (icode) (target); 8180 break; 8181 case 1: 8182 if (nonvoid) 8183 pat = GEN_FCN (icode) (target, op[0]); 8184 else 8185 pat = GEN_FCN (icode) (op[0]); 8186 break; 8187 case 2: 8188 pat = GEN_FCN (icode) (target, op[0], op[1]); 8189 break; 8190 default: 8191 gcc_unreachable (); 8192 } 8193 if (!pat) 8194 return NULL_RTX; 8195 emit_insn (pat); 8196 8197 if (nonvoid) 8198 return target; 8199 else 8200 return const0_rtx; 8201} 8202 8203 8204/* Output assembly code for the trampoline template to 8205 stdio stream FILE. 8206 8207 On S/390, we use gpr 1 internally in the trampoline code; 8208 gpr 0 is used to hold the static chain. */ 8209 8210void 8211s390_trampoline_template (FILE *file) 8212{ 8213 rtx op[2]; 8214 op[0] = gen_rtx_REG (Pmode, 0); 8215 op[1] = gen_rtx_REG (Pmode, 1); 8216 8217 if (TARGET_64BIT) 8218 { 8219 output_asm_insn ("basr\t%1,0", op); 8220 output_asm_insn ("lmg\t%0,%1,14(%1)", op); 8221 output_asm_insn ("br\t%1", op); 8222 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10)); 8223 } 8224 else 8225 { 8226 output_asm_insn ("basr\t%1,0", op); 8227 output_asm_insn ("lm\t%0,%1,6(%1)", op); 8228 output_asm_insn ("br\t%1", op); 8229 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8)); 8230 } 8231} 8232 8233/* Emit RTL insns to initialize the variable parts of a trampoline. 8234 FNADDR is an RTX for the address of the function's pure code. 8235 CXT is an RTX for the static chain value for the function. */ 8236 8237void 8238s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) 8239{ 8240 emit_move_insn (gen_rtx_MEM (Pmode, 8241 memory_address (Pmode, 8242 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt); 8243 emit_move_insn (gen_rtx_MEM (Pmode, 8244 memory_address (Pmode, 8245 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr); 8246} 8247 8248/* Return rtx for 64-bit constant formed from the 32-bit subwords 8249 LOW and HIGH, independent of the host word size. */ 8250 8251rtx 8252s390_gen_rtx_const_DI (int high, int low) 8253{ 8254#if HOST_BITS_PER_WIDE_INT >= 64 8255 HOST_WIDE_INT val; 8256 val = (HOST_WIDE_INT)high; 8257 val <<= 32; 8258 val |= (HOST_WIDE_INT)low; 8259 8260 return GEN_INT (val); 8261#else 8262#if HOST_BITS_PER_WIDE_INT >= 32 8263 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode); 8264#else 8265 gcc_unreachable (); 8266#endif 8267#endif 8268} 8269 8270/* Output assembler code to FILE to increment profiler label # LABELNO 8271 for profiling a function entry. */ 8272 8273void 8274s390_function_profiler (FILE *file, int labelno) 8275{ 8276 rtx op[7]; 8277 8278 char label[128]; 8279 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno); 8280 8281 fprintf (file, "# function profiler \n"); 8282 8283 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM); 8284 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); 8285 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD)); 8286 8287 op[2] = gen_rtx_REG (Pmode, 1); 8288 op[3] = gen_rtx_SYMBOL_REF (Pmode, label); 8289 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL; 8290 8291 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); 8292 if (flag_pic) 8293 { 8294 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT); 8295 op[4] = gen_rtx_CONST (Pmode, op[4]); 8296 } 8297 8298 if (TARGET_64BIT) 8299 { 8300 output_asm_insn ("stg\t%0,%1", op); 8301 output_asm_insn ("larl\t%2,%3", op); 8302 output_asm_insn ("brasl\t%0,%4", op); 8303 output_asm_insn ("lg\t%0,%1", op); 8304 } 8305 else if (!flag_pic) 8306 { 8307 op[6] = gen_label_rtx (); 8308 8309 output_asm_insn ("st\t%0,%1", op); 8310 output_asm_insn ("bras\t%2,%l6", op); 8311 output_asm_insn (".long\t%4", op); 8312 output_asm_insn (".long\t%3", op); 8313 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6])); 8314 output_asm_insn ("l\t%0,0(%2)", op); 8315 output_asm_insn ("l\t%2,4(%2)", op); 8316 output_asm_insn ("basr\t%0,%0", op); 8317 output_asm_insn ("l\t%0,%1", op); 8318 } 8319 else 8320 { 8321 op[5] = gen_label_rtx (); 8322 op[6] = gen_label_rtx (); 8323 8324 output_asm_insn ("st\t%0,%1", op); 8325 output_asm_insn ("bras\t%2,%l6", op); 8326 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5])); 8327 output_asm_insn (".long\t%4-%l5", op); 8328 output_asm_insn (".long\t%3-%l5", op); 8329 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6])); 8330 output_asm_insn ("lr\t%0,%2", op); 8331 output_asm_insn ("a\t%0,0(%2)", op); 8332 output_asm_insn ("a\t%2,4(%2)", op); 8333 output_asm_insn ("basr\t%0,%0", op); 8334 output_asm_insn ("l\t%0,%1", op); 8335 } 8336} 8337 8338/* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF 8339 into its SYMBOL_REF_FLAGS. */ 8340 8341static void 8342s390_encode_section_info (tree decl, rtx rtl, int first) 8343{ 8344 default_encode_section_info (decl, rtl, first); 8345 8346 /* If a variable has a forced alignment to < 2 bytes, mark it with 8347 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */ 8348 if (TREE_CODE (decl) == VAR_DECL 8349 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16) 8350 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1; 8351} 8352 8353/* Output thunk to FILE that implements a C++ virtual function call (with 8354 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer 8355 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment 8356 stored at VCALL_OFFSET in the vtable whose address is located at offset 0 8357 relative to the resulting this pointer. */ 8358 8359static void 8360s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, 8361 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 8362 tree function) 8363{ 8364 rtx op[10]; 8365 int nonlocal = 0; 8366 8367 /* Operand 0 is the target function. */ 8368 op[0] = XEXP (DECL_RTL (function), 0); 8369 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0])) 8370 { 8371 nonlocal = 1; 8372 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]), 8373 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT); 8374 op[0] = gen_rtx_CONST (Pmode, op[0]); 8375 } 8376 8377 /* Operand 1 is the 'this' pointer. */ 8378 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 8379 op[1] = gen_rtx_REG (Pmode, 3); 8380 else 8381 op[1] = gen_rtx_REG (Pmode, 2); 8382 8383 /* Operand 2 is the delta. */ 8384 op[2] = GEN_INT (delta); 8385 8386 /* Operand 3 is the vcall_offset. */ 8387 op[3] = GEN_INT (vcall_offset); 8388 8389 /* Operand 4 is the temporary register. */ 8390 op[4] = gen_rtx_REG (Pmode, 1); 8391 8392 /* Operands 5 to 8 can be used as labels. */ 8393 op[5] = NULL_RTX; 8394 op[6] = NULL_RTX; 8395 op[7] = NULL_RTX; 8396 op[8] = NULL_RTX; 8397 8398 /* Operand 9 can be used for temporary register. */ 8399 op[9] = NULL_RTX; 8400 8401 /* Generate code. */ 8402 if (TARGET_64BIT) 8403 { 8404 /* Setup literal pool pointer if required. */ 8405 if ((!DISP_IN_RANGE (delta) 8406 && !CONST_OK_FOR_K (delta) 8407 && !CONST_OK_FOR_Os (delta)) 8408 || (!DISP_IN_RANGE (vcall_offset) 8409 && !CONST_OK_FOR_K (vcall_offset) 8410 && !CONST_OK_FOR_Os (vcall_offset))) 8411 { 8412 op[5] = gen_label_rtx (); 8413 output_asm_insn ("larl\t%4,%5", op); 8414 } 8415 8416 /* Add DELTA to this pointer. */ 8417 if (delta) 8418 { 8419 if (CONST_OK_FOR_J (delta)) 8420 output_asm_insn ("la\t%1,%2(%1)", op); 8421 else if (DISP_IN_RANGE (delta)) 8422 output_asm_insn ("lay\t%1,%2(%1)", op); 8423 else if (CONST_OK_FOR_K (delta)) 8424 output_asm_insn ("aghi\t%1,%2", op); 8425 else if (CONST_OK_FOR_Os (delta)) 8426 output_asm_insn ("agfi\t%1,%2", op); 8427 else 8428 { 8429 op[6] = gen_label_rtx (); 8430 output_asm_insn ("agf\t%1,%6-%5(%4)", op); 8431 } 8432 } 8433 8434 /* Perform vcall adjustment. */ 8435 if (vcall_offset) 8436 { 8437 if (DISP_IN_RANGE (vcall_offset)) 8438 { 8439 output_asm_insn ("lg\t%4,0(%1)", op); 8440 output_asm_insn ("ag\t%1,%3(%4)", op); 8441 } 8442 else if (CONST_OK_FOR_K (vcall_offset)) 8443 { 8444 output_asm_insn ("lghi\t%4,%3", op); 8445 output_asm_insn ("ag\t%4,0(%1)", op); 8446 output_asm_insn ("ag\t%1,0(%4)", op); 8447 } 8448 else if (CONST_OK_FOR_Os (vcall_offset)) 8449 { 8450 output_asm_insn ("lgfi\t%4,%3", op); 8451 output_asm_insn ("ag\t%4,0(%1)", op); 8452 output_asm_insn ("ag\t%1,0(%4)", op); 8453 } 8454 else 8455 { 8456 op[7] = gen_label_rtx (); 8457 output_asm_insn ("llgf\t%4,%7-%5(%4)", op); 8458 output_asm_insn ("ag\t%4,0(%1)", op); 8459 output_asm_insn ("ag\t%1,0(%4)", op); 8460 } 8461 } 8462 8463 /* Jump to target. */ 8464 output_asm_insn ("jg\t%0", op); 8465 8466 /* Output literal pool if required. */ 8467 if (op[5]) 8468 { 8469 output_asm_insn (".align\t4", op); 8470 targetm.asm_out.internal_label (file, "L", 8471 CODE_LABEL_NUMBER (op[5])); 8472 } 8473 if (op[6]) 8474 { 8475 targetm.asm_out.internal_label (file, "L", 8476 CODE_LABEL_NUMBER (op[6])); 8477 output_asm_insn (".long\t%2", op); 8478 } 8479 if (op[7]) 8480 { 8481 targetm.asm_out.internal_label (file, "L", 8482 CODE_LABEL_NUMBER (op[7])); 8483 output_asm_insn (".long\t%3", op); 8484 } 8485 } 8486 else 8487 { 8488 /* Setup base pointer if required. */ 8489 if (!vcall_offset 8490 || (!DISP_IN_RANGE (delta) 8491 && !CONST_OK_FOR_K (delta) 8492 && !CONST_OK_FOR_Os (delta)) 8493 || (!DISP_IN_RANGE (delta) 8494 && !CONST_OK_FOR_K (vcall_offset) 8495 && !CONST_OK_FOR_Os (vcall_offset))) 8496 { 8497 op[5] = gen_label_rtx (); 8498 output_asm_insn ("basr\t%4,0", op); 8499 targetm.asm_out.internal_label (file, "L", 8500 CODE_LABEL_NUMBER (op[5])); 8501 } 8502 8503 /* Add DELTA to this pointer. */ 8504 if (delta) 8505 { 8506 if (CONST_OK_FOR_J (delta)) 8507 output_asm_insn ("la\t%1,%2(%1)", op); 8508 else if (DISP_IN_RANGE (delta)) 8509 output_asm_insn ("lay\t%1,%2(%1)", op); 8510 else if (CONST_OK_FOR_K (delta)) 8511 output_asm_insn ("ahi\t%1,%2", op); 8512 else if (CONST_OK_FOR_Os (delta)) 8513 output_asm_insn ("afi\t%1,%2", op); 8514 else 8515 { 8516 op[6] = gen_label_rtx (); 8517 output_asm_insn ("a\t%1,%6-%5(%4)", op); 8518 } 8519 } 8520 8521 /* Perform vcall adjustment. */ 8522 if (vcall_offset) 8523 { 8524 if (CONST_OK_FOR_J (vcall_offset)) 8525 { 8526 output_asm_insn ("l\t%4,0(%1)", op); 8527 output_asm_insn ("a\t%1,%3(%4)", op); 8528 } 8529 else if (DISP_IN_RANGE (vcall_offset)) 8530 { 8531 output_asm_insn ("l\t%4,0(%1)", op); 8532 output_asm_insn ("ay\t%1,%3(%4)", op); 8533 } 8534 else if (CONST_OK_FOR_K (vcall_offset)) 8535 { 8536 output_asm_insn ("lhi\t%4,%3", op); 8537 output_asm_insn ("a\t%4,0(%1)", op); 8538 output_asm_insn ("a\t%1,0(%4)", op); 8539 } 8540 else if (CONST_OK_FOR_Os (vcall_offset)) 8541 { 8542 output_asm_insn ("iilf\t%4,%3", op); 8543 output_asm_insn ("a\t%4,0(%1)", op); 8544 output_asm_insn ("a\t%1,0(%4)", op); 8545 } 8546 else 8547 { 8548 op[7] = gen_label_rtx (); 8549 output_asm_insn ("l\t%4,%7-%5(%4)", op); 8550 output_asm_insn ("a\t%4,0(%1)", op); 8551 output_asm_insn ("a\t%1,0(%4)", op); 8552 } 8553 8554 /* We had to clobber the base pointer register. 8555 Re-setup the base pointer (with a different base). */ 8556 op[5] = gen_label_rtx (); 8557 output_asm_insn ("basr\t%4,0", op); 8558 targetm.asm_out.internal_label (file, "L", 8559 CODE_LABEL_NUMBER (op[5])); 8560 } 8561 8562 /* Jump to target. */ 8563 op[8] = gen_label_rtx (); 8564 8565 if (!flag_pic) 8566 output_asm_insn ("l\t%4,%8-%5(%4)", op); 8567 else if (!nonlocal) 8568 output_asm_insn ("a\t%4,%8-%5(%4)", op); 8569 /* We cannot call through .plt, since .plt requires %r12 loaded. */ 8570 else if (flag_pic == 1) 8571 { 8572 output_asm_insn ("a\t%4,%8-%5(%4)", op); 8573 output_asm_insn ("l\t%4,%0(%4)", op); 8574 } 8575 else if (flag_pic == 2) 8576 { 8577 op[9] = gen_rtx_REG (Pmode, 0); 8578 output_asm_insn ("l\t%9,%8-4-%5(%4)", op); 8579 output_asm_insn ("a\t%4,%8-%5(%4)", op); 8580 output_asm_insn ("ar\t%4,%9", op); 8581 output_asm_insn ("l\t%4,0(%4)", op); 8582 } 8583 8584 output_asm_insn ("br\t%4", op); 8585 8586 /* Output literal pool. */ 8587 output_asm_insn (".align\t4", op); 8588 8589 if (nonlocal && flag_pic == 2) 8590 output_asm_insn (".long\t%0", op); 8591 if (nonlocal) 8592 { 8593 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 8594 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL; 8595 } 8596 8597 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8])); 8598 if (!flag_pic) 8599 output_asm_insn (".long\t%0", op); 8600 else 8601 output_asm_insn (".long\t%0-%5", op); 8602 8603 if (op[6]) 8604 { 8605 targetm.asm_out.internal_label (file, "L", 8606 CODE_LABEL_NUMBER (op[6])); 8607 output_asm_insn (".long\t%2", op); 8608 } 8609 if (op[7]) 8610 { 8611 targetm.asm_out.internal_label (file, "L", 8612 CODE_LABEL_NUMBER (op[7])); 8613 output_asm_insn (".long\t%3", op); 8614 } 8615 } 8616} 8617 8618static bool 8619s390_valid_pointer_mode (enum machine_mode mode) 8620{ 8621 return (mode == SImode || (TARGET_64BIT && mode == DImode)); 8622} 8623 8624/* Checks whether the given ARGUMENT_LIST would use a caller 8625 saved register. This is used to decide whether sibling call 8626 optimization could be performed on the respective function 8627 call. */ 8628 8629static bool 8630s390_call_saved_register_used (tree argument_list) 8631{ 8632 CUMULATIVE_ARGS cum; 8633 tree parameter; 8634 enum machine_mode mode; 8635 tree type; 8636 rtx parm_rtx; 8637 int reg; 8638 8639 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0); 8640 8641 while (argument_list) 8642 { 8643 parameter = TREE_VALUE (argument_list); 8644 argument_list = TREE_CHAIN (argument_list); 8645 8646 gcc_assert (parameter); 8647 8648 /* For an undeclared variable passed as parameter we will get 8649 an ERROR_MARK node here. */ 8650 if (TREE_CODE (parameter) == ERROR_MARK) 8651 return true; 8652 8653 type = TREE_TYPE (parameter); 8654 gcc_assert (type); 8655 8656 mode = TYPE_MODE (type); 8657 gcc_assert (mode); 8658 8659 if (pass_by_reference (&cum, mode, type, true)) 8660 { 8661 mode = Pmode; 8662 type = build_pointer_type (type); 8663 } 8664 8665 parm_rtx = s390_function_arg (&cum, mode, type, 0); 8666 8667 s390_function_arg_advance (&cum, mode, type, 0); 8668 8669 if (parm_rtx && REG_P (parm_rtx)) 8670 { 8671 for (reg = 0; 8672 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx)); 8673 reg++) 8674 if (! call_used_regs[reg + REGNO (parm_rtx)]) 8675 return true; 8676 } 8677 } 8678 return false; 8679} 8680 8681/* Return true if the given call expression can be 8682 turned into a sibling call. 8683 DECL holds the declaration of the function to be called whereas 8684 EXP is the call expression itself. */ 8685 8686static bool 8687s390_function_ok_for_sibcall (tree decl, tree exp) 8688{ 8689 /* The TPF epilogue uses register 1. */ 8690 if (TARGET_TPF_PROFILING) 8691 return false; 8692 8693 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved) 8694 which would have to be restored before the sibcall. */ 8695 if (!TARGET_64BIT && flag_pic && decl && TREE_PUBLIC (decl)) 8696 return false; 8697 8698 /* Register 6 on s390 is available as an argument register but unfortunately 8699 "caller saved". This makes functions needing this register for arguments 8700 not suitable for sibcalls. */ 8701 if (TREE_OPERAND (exp, 1) 8702 && s390_call_saved_register_used (TREE_OPERAND (exp, 1))) 8703 return false; 8704 8705 return true; 8706} 8707 8708/* Return the fixed registers used for condition codes. */ 8709 8710static bool 8711s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) 8712{ 8713 *p1 = CC_REGNUM; 8714 *p2 = INVALID_REGNUM; 8715 8716 return true; 8717} 8718 8719/* This function is used by the call expanders of the machine description. 8720 It emits the call insn itself together with the necessary operations 8721 to adjust the target address and returns the emitted insn. 8722 ADDR_LOCATION is the target address rtx 8723 TLS_CALL the location of the thread-local symbol 8724 RESULT_REG the register where the result of the call should be stored 8725 RETADDR_REG the register where the return address should be stored 8726 If this parameter is NULL_RTX the call is considered 8727 to be a sibling call. */ 8728 8729rtx 8730s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg, 8731 rtx retaddr_reg) 8732{ 8733 bool plt_call = false; 8734 rtx insn; 8735 rtx call; 8736 rtx clobber; 8737 rtvec vec; 8738 8739 /* Direct function calls need special treatment. */ 8740 if (GET_CODE (addr_location) == SYMBOL_REF) 8741 { 8742 /* When calling a global routine in PIC mode, we must 8743 replace the symbol itself with the PLT stub. */ 8744 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location)) 8745 { 8746 addr_location = gen_rtx_UNSPEC (Pmode, 8747 gen_rtvec (1, addr_location), 8748 UNSPEC_PLT); 8749 addr_location = gen_rtx_CONST (Pmode, addr_location); 8750 plt_call = true; 8751 } 8752 8753 /* Unless we can use the bras(l) insn, force the 8754 routine address into a register. */ 8755 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) 8756 { 8757 if (flag_pic) 8758 addr_location = legitimize_pic_address (addr_location, 0); 8759 else 8760 addr_location = force_reg (Pmode, addr_location); 8761 } 8762 } 8763 8764 /* If it is already an indirect call or the code above moved the 8765 SYMBOL_REF to somewhere else make sure the address can be found in 8766 register 1. */ 8767 if (retaddr_reg == NULL_RTX 8768 && GET_CODE (addr_location) != SYMBOL_REF 8769 && !plt_call) 8770 { 8771 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location); 8772 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM); 8773 } 8774 8775 addr_location = gen_rtx_MEM (QImode, addr_location); 8776 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx); 8777 8778 if (result_reg != NULL_RTX) 8779 call = gen_rtx_SET (VOIDmode, result_reg, call); 8780 8781 if (retaddr_reg != NULL_RTX) 8782 { 8783 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg); 8784 8785 if (tls_call != NULL_RTX) 8786 vec = gen_rtvec (3, call, clobber, 8787 gen_rtx_USE (VOIDmode, tls_call)); 8788 else 8789 vec = gen_rtvec (2, call, clobber); 8790 8791 call = gen_rtx_PARALLEL (VOIDmode, vec); 8792 } 8793 8794 insn = emit_call_insn (call); 8795 8796 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */ 8797 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX) 8798 { 8799 /* s390_function_ok_for_sibcall should 8800 have denied sibcalls in this case. */ 8801 gcc_assert (retaddr_reg != NULL_RTX); 8802 8803 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 8804 } 8805 return insn; 8806} 8807 8808/* Implement CONDITIONAL_REGISTER_USAGE. */ 8809 8810void 8811s390_conditional_register_usage (void) 8812{ 8813 int i; 8814 8815 if (flag_pic) 8816 { 8817 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; 8818 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; 8819 } 8820 if (TARGET_CPU_ZARCH) 8821 { 8822 fixed_regs[BASE_REGNUM] = 0; 8823 call_used_regs[BASE_REGNUM] = 0; 8824 fixed_regs[RETURN_REGNUM] = 0; 8825 call_used_regs[RETURN_REGNUM] = 0; 8826 } 8827 if (TARGET_64BIT) 8828 { 8829 for (i = 24; i < 32; i++) 8830 call_used_regs[i] = call_really_used_regs[i] = 0; 8831 } 8832 else 8833 { 8834 for (i = 18; i < 20; i++) 8835 call_used_regs[i] = call_really_used_regs[i] = 0; 8836 } 8837 8838 if (TARGET_SOFT_FLOAT) 8839 { 8840 for (i = 16; i < 32; i++) 8841 call_used_regs[i] = fixed_regs[i] = 1; 8842 } 8843} 8844 8845/* Corresponding function to eh_return expander. */ 8846 8847static GTY(()) rtx s390_tpf_eh_return_symbol; 8848void 8849s390_emit_tpf_eh_return (rtx target) 8850{ 8851 rtx insn, reg; 8852 8853 if (!s390_tpf_eh_return_symbol) 8854 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return"); 8855 8856 reg = gen_rtx_REG (Pmode, 2); 8857 8858 emit_move_insn (reg, target); 8859 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg, 8860 gen_rtx_REG (Pmode, RETURN_REGNUM)); 8861 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); 8862 8863 emit_move_insn (EH_RETURN_HANDLER_RTX, reg); 8864} 8865 8866/* Rework the prologue/epilogue to avoid saving/restoring 8867 registers unnecessarily. */ 8868 8869static void 8870s390_optimize_prologue (void) 8871{ 8872 rtx insn, new_insn, next_insn; 8873 8874 /* Do a final recompute of the frame-related data. */ 8875 8876 s390_update_frame_layout (); 8877 8878 /* If all special registers are in fact used, there's nothing we 8879 can do, so no point in walking the insn list. */ 8880 8881 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM 8882 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM 8883 && (TARGET_CPU_ZARCH 8884 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM 8885 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM))) 8886 return; 8887 8888 /* Search for prologue/epilogue insns and replace them. */ 8889 8890 for (insn = get_insns (); insn; insn = next_insn) 8891 { 8892 int first, last, off; 8893 rtx set, base, offset; 8894 8895 next_insn = NEXT_INSN (insn); 8896 8897 if (GET_CODE (insn) != INSN) 8898 continue; 8899 8900 if (GET_CODE (PATTERN (insn)) == PARALLEL 8901 && store_multiple_operation (PATTERN (insn), VOIDmode)) 8902 { 8903 set = XVECEXP (PATTERN (insn), 0, 0); 8904 first = REGNO (SET_SRC (set)); 8905 last = first + XVECLEN (PATTERN (insn), 0) - 1; 8906 offset = const0_rtx; 8907 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); 8908 off = INTVAL (offset); 8909 8910 if (GET_CODE (base) != REG || off < 0) 8911 continue; 8912 if (cfun_frame_layout.first_save_gpr != -1 8913 && (cfun_frame_layout.first_save_gpr < first 8914 || cfun_frame_layout.last_save_gpr > last)) 8915 continue; 8916 if (REGNO (base) != STACK_POINTER_REGNUM 8917 && REGNO (base) != HARD_FRAME_POINTER_REGNUM) 8918 continue; 8919 if (first > BASE_REGNUM || last < BASE_REGNUM) 8920 continue; 8921 8922 if (cfun_frame_layout.first_save_gpr != -1) 8923 { 8924 new_insn = save_gprs (base, 8925 off + (cfun_frame_layout.first_save_gpr 8926 - first) * UNITS_PER_WORD, 8927 cfun_frame_layout.first_save_gpr, 8928 cfun_frame_layout.last_save_gpr); 8929 new_insn = emit_insn_before (new_insn, insn); 8930 INSN_ADDRESSES_NEW (new_insn, -1); 8931 } 8932 8933 remove_insn (insn); 8934 continue; 8935 } 8936 8937 if (cfun_frame_layout.first_save_gpr == -1 8938 && GET_CODE (PATTERN (insn)) == SET 8939 && GET_CODE (SET_SRC (PATTERN (insn))) == REG 8940 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM 8941 || (!TARGET_CPU_ZARCH 8942 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM)) 8943 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM) 8944 { 8945 set = PATTERN (insn); 8946 first = REGNO (SET_SRC (set)); 8947 offset = const0_rtx; 8948 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); 8949 off = INTVAL (offset); 8950 8951 if (GET_CODE (base) != REG || off < 0) 8952 continue; 8953 if (REGNO (base) != STACK_POINTER_REGNUM 8954 && REGNO (base) != HARD_FRAME_POINTER_REGNUM) 8955 continue; 8956 8957 remove_insn (insn); 8958 continue; 8959 } 8960 8961 if (GET_CODE (PATTERN (insn)) == PARALLEL 8962 && load_multiple_operation (PATTERN (insn), VOIDmode)) 8963 { 8964 set = XVECEXP (PATTERN (insn), 0, 0); 8965 first = REGNO (SET_DEST (set)); 8966 last = first + XVECLEN (PATTERN (insn), 0) - 1; 8967 offset = const0_rtx; 8968 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset); 8969 off = INTVAL (offset); 8970 8971 if (GET_CODE (base) != REG || off < 0) 8972 continue; 8973 if (cfun_frame_layout.first_restore_gpr != -1 8974 && (cfun_frame_layout.first_restore_gpr < first 8975 || cfun_frame_layout.last_restore_gpr > last)) 8976 continue; 8977 if (REGNO (base) != STACK_POINTER_REGNUM 8978 && REGNO (base) != HARD_FRAME_POINTER_REGNUM) 8979 continue; 8980 if (first > BASE_REGNUM || last < BASE_REGNUM) 8981 continue; 8982 8983 if (cfun_frame_layout.first_restore_gpr != -1) 8984 { 8985 new_insn = restore_gprs (base, 8986 off + (cfun_frame_layout.first_restore_gpr 8987 - first) * UNITS_PER_WORD, 8988 cfun_frame_layout.first_restore_gpr, 8989 cfun_frame_layout.last_restore_gpr); 8990 new_insn = emit_insn_before (new_insn, insn); 8991 INSN_ADDRESSES_NEW (new_insn, -1); 8992 } 8993 8994 remove_insn (insn); 8995 continue; 8996 } 8997 8998 if (cfun_frame_layout.first_restore_gpr == -1 8999 && GET_CODE (PATTERN (insn)) == SET 9000 && GET_CODE (SET_DEST (PATTERN (insn))) == REG 9001 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM 9002 || (!TARGET_CPU_ZARCH 9003 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM)) 9004 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM) 9005 { 9006 set = PATTERN (insn); 9007 first = REGNO (SET_DEST (set)); 9008 offset = const0_rtx; 9009 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset); 9010 off = INTVAL (offset); 9011 9012 if (GET_CODE (base) != REG || off < 0) 9013 continue; 9014 if (REGNO (base) != STACK_POINTER_REGNUM 9015 && REGNO (base) != HARD_FRAME_POINTER_REGNUM) 9016 continue; 9017 9018 remove_insn (insn); 9019 continue; 9020 } 9021 } 9022} 9023 9024/* Perform machine-dependent processing. */ 9025 9026static void 9027s390_reorg (void) 9028{ 9029 bool pool_overflow = false; 9030 9031 /* Make sure all splits have been performed; splits after 9032 machine_dependent_reorg might confuse insn length counts. */ 9033 split_all_insns_noflow (); 9034 9035 /* From here on decomposed literal pool addresses must be accepted. */ 9036 cfun->machine->decomposed_literal_pool_addresses_ok_p = true; 9037 9038 /* Install the main literal pool and the associated base 9039 register load insns. 9040 9041 In addition, there are two problematic situations we need 9042 to correct: 9043 9044 - the literal pool might be > 4096 bytes in size, so that 9045 some of its elements cannot be directly accessed 9046 9047 - a branch target might be > 64K away from the branch, so that 9048 it is not possible to use a PC-relative instruction. 9049 9050 To fix those, we split the single literal pool into multiple 9051 pool chunks, reloading the pool base register at various 9052 points throughout the function to ensure it always points to 9053 the pool chunk the following code expects, and / or replace 9054 PC-relative branches by absolute branches. 9055 9056 However, the two problems are interdependent: splitting the 9057 literal pool can move a branch further away from its target, 9058 causing the 64K limit to overflow, and on the other hand, 9059 replacing a PC-relative branch by an absolute branch means 9060 we need to put the branch target address into the literal 9061 pool, possibly causing it to overflow. 9062 9063 So, we loop trying to fix up both problems until we manage 9064 to satisfy both conditions at the same time. Note that the 9065 loop is guaranteed to terminate as every pass of the loop 9066 strictly decreases the total number of PC-relative branches 9067 in the function. (This is not completely true as there 9068 might be branch-over-pool insns introduced by chunkify_start. 9069 Those never need to be split however.) */ 9070 9071 for (;;) 9072 { 9073 struct constant_pool *pool = NULL; 9074 9075 /* Collect the literal pool. */ 9076 if (!pool_overflow) 9077 { 9078 pool = s390_mainpool_start (); 9079 if (!pool) 9080 pool_overflow = true; 9081 } 9082 9083 /* If literal pool overflowed, start to chunkify it. */ 9084 if (pool_overflow) 9085 pool = s390_chunkify_start (); 9086 9087 /* Split out-of-range branches. If this has created new 9088 literal pool entries, cancel current chunk list and 9089 recompute it. zSeries machines have large branch 9090 instructions, so we never need to split a branch. */ 9091 if (!TARGET_CPU_ZARCH && s390_split_branches ()) 9092 { 9093 if (pool_overflow) 9094 s390_chunkify_cancel (pool); 9095 else 9096 s390_mainpool_cancel (pool); 9097 9098 continue; 9099 } 9100 9101 /* If we made it up to here, both conditions are satisfied. 9102 Finish up literal pool related changes. */ 9103 if (pool_overflow) 9104 s390_chunkify_finish (pool); 9105 else 9106 s390_mainpool_finish (pool); 9107 9108 /* We're done splitting branches. */ 9109 cfun->machine->split_branches_pending_p = false; 9110 break; 9111 } 9112 9113 /* Generate out-of-pool execute target insns. */ 9114 if (TARGET_CPU_ZARCH) 9115 { 9116 rtx insn, label, target; 9117 9118 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 9119 { 9120 label = s390_execute_label (insn); 9121 if (!label) 9122 continue; 9123 9124 gcc_assert (label != const0_rtx); 9125 9126 target = emit_label (XEXP (label, 0)); 9127 INSN_ADDRESSES_NEW (target, -1); 9128 9129 target = emit_insn (s390_execute_target (insn)); 9130 INSN_ADDRESSES_NEW (target, -1); 9131 } 9132 } 9133 9134 /* Try to optimize prologue and epilogue further. */ 9135 s390_optimize_prologue (); 9136} 9137 9138 9139/* Initialize GCC target structure. */ 9140 9141#undef TARGET_ASM_ALIGNED_HI_OP 9142#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 9143#undef TARGET_ASM_ALIGNED_DI_OP 9144#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" 9145#undef TARGET_ASM_INTEGER 9146#define TARGET_ASM_INTEGER s390_assemble_integer 9147 9148#undef TARGET_ASM_OPEN_PAREN 9149#define TARGET_ASM_OPEN_PAREN "" 9150 9151#undef TARGET_ASM_CLOSE_PAREN 9152#define TARGET_ASM_CLOSE_PAREN "" 9153 9154#undef TARGET_DEFAULT_TARGET_FLAGS 9155#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD) 9156#undef TARGET_HANDLE_OPTION 9157#define TARGET_HANDLE_OPTION s390_handle_option 9158 9159#undef TARGET_ENCODE_SECTION_INFO 9160#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info 9161 9162#ifdef HAVE_AS_TLS 9163#undef TARGET_HAVE_TLS 9164#define TARGET_HAVE_TLS true 9165#endif 9166#undef TARGET_CANNOT_FORCE_CONST_MEM 9167#define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem 9168 9169#undef TARGET_DELEGITIMIZE_ADDRESS 9170#define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address 9171 9172#undef TARGET_RETURN_IN_MEMORY 9173#define TARGET_RETURN_IN_MEMORY s390_return_in_memory 9174 9175#undef TARGET_INIT_BUILTINS 9176#define TARGET_INIT_BUILTINS s390_init_builtins 9177#undef TARGET_EXPAND_BUILTIN 9178#define TARGET_EXPAND_BUILTIN s390_expand_builtin 9179 9180#undef TARGET_ASM_OUTPUT_MI_THUNK 9181#define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk 9182#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 9183#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true 9184 9185#undef TARGET_SCHED_ADJUST_PRIORITY 9186#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority 9187#undef TARGET_SCHED_ISSUE_RATE 9188#define TARGET_SCHED_ISSUE_RATE s390_issue_rate 9189#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 9190#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead 9191 9192#undef TARGET_CANNOT_COPY_INSN_P 9193#define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p 9194#undef TARGET_RTX_COSTS 9195#define TARGET_RTX_COSTS s390_rtx_costs 9196#undef TARGET_ADDRESS_COST 9197#define TARGET_ADDRESS_COST s390_address_cost 9198 9199#undef TARGET_MACHINE_DEPENDENT_REORG 9200#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg 9201 9202#undef TARGET_VALID_POINTER_MODE 9203#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode 9204 9205#undef TARGET_BUILD_BUILTIN_VA_LIST 9206#define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list 9207#undef TARGET_GIMPLIFY_VA_ARG_EXPR 9208#define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg 9209 9210#undef TARGET_PROMOTE_FUNCTION_ARGS 9211#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true 9212#undef TARGET_PROMOTE_FUNCTION_RETURN 9213#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true 9214#undef TARGET_PASS_BY_REFERENCE 9215#define TARGET_PASS_BY_REFERENCE s390_pass_by_reference 9216 9217#undef TARGET_FUNCTION_OK_FOR_SIBCALL 9218#define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall 9219 9220#undef TARGET_FIXED_CONDITION_CODE_REGS 9221#define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs 9222 9223#undef TARGET_CC_MODES_COMPATIBLE 9224#define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible 9225 9226#undef TARGET_INVALID_WITHIN_DOLOOP 9227#define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null 9228 9229#ifdef HAVE_AS_TLS 9230#undef TARGET_ASM_OUTPUT_DWARF_DTPREL 9231#define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel 9232#endif 9233 9234#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING 9235#undef TARGET_MANGLE_FUNDAMENTAL_TYPE 9236#define TARGET_MANGLE_FUNDAMENTAL_TYPE s390_mangle_fundamental_type 9237#endif 9238 9239struct gcc_target targetm = TARGET_INITIALIZER; 9240 9241#include "gt-s390.h" 9242