README revision 1.1.1.1
1Copyright 2001 Free Software Foundation, Inc. 2 3This file is part of the GNU MP Library. 4 5The GNU MP Library is free software; you can redistribute it and/or modify 6it under the terms of the GNU Lesser General Public License as published by 7the Free Software Foundation; either version 3 of the License, or (at your 8option) any later version. 9 10The GNU MP Library is distributed in the hope that it will be useful, but 11WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public 13License for more details. 14 15You should have received a copy of the GNU Lesser General Public License 16along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. 17 18 19 20 21 INTEL PENTIUM-4 MPN SUBROUTINES 22 23 24This directory contains mpn functions optimized for Intel Pentium-4. 25 26The mmx subdirectory has routines using MMX instructions, the sse2 27subdirectory has routines using SSE2 instructions. All P4s have these, the 28separate directories are just so configure can omit that code if the 29assembler doesn't support it. 30 31 32STATUS 33 34 cycles/limb 35 36 mpn_add_n/sub_n 4 normal, 6 in-place 37 38 mpn_mul_1 4 normal, 6 in-place 39 mpn_addmul_1 6 40 mpn_submul_1 7 41 42 mpn_mul_basecase 6 cycles/crossproduct (approx) 43 44 mpn_sqr_basecase 3.5 cycles/crossproduct (approx) 45 or 7.0 cycles/triangleproduct (approx) 46 47 mpn_l/rshift 1.75 48 49 50 51The shifts ought to be able to go at 1.5 c/l, but not much effort has been 52applied to them yet. 53 54In-place operations, and all addmul, submul, mul_basecase and sqr_basecase 55calls, suffer from pipeline anomalies associated with write combining and 56movd reads and writes to the same or nearby locations. The movq 57instructions do not trigger the same hardware problems. Unfortunately, 58using movq and splitting/combining seems to require too many extra 59instructions to help. Perhaps future chip steppings will be better. 60 61 62 63NOTES 64 65The Pentium-4 pipeline "Netburst", provides for quite a number of surprises. 66Many traditional x86 instructions run very slowly, requiring use of 67alterative instructions for acceptable performance. 68 69adcl and sbbl are quite slow at 8 cycles for reg->reg. paddq of 32-bits 70within a 64-bit mmx register seems better, though the combination 71paddq/psrlq when propagating a carry is still a 4 cycle latency. 72 73incl and decl should be avoided, instead use add $1 and sub $1. Apparently 74the carry flag is not separately renamed, so incl and decl depend on all 75previous flags-setting instructions. 76 77shll and shrl have a 4 cycle latency, or 8 times the latency of the fastest 78integer instructions (addl, subl, orl, andl, and some more). shldl and 79shrdl seem to have 13 and 15 cycles latency, respectively. Bizarre. 80 81movq mmx -> mmx does have 6 cycle latency, as noted in the documentation. 82pxor/por or similar combination at 2 cycles latency can be used instead. 83The movq however executes in the float unit, thereby saving MMX execution 84resources. With the right juggling, data moves shouldn't be on a dependent 85chain. 86 87L1 is write-through, but the write-combining sounds like it does enough to 88not require explicit destination prefetching. 89 90xmm registers so far haven't found a use, but not much effort has been 91expended. A configure test for whether the operating system knows 92fxsave/fxrestor will be needed if they're used. 93 94 95 96REFERENCES 97 98Intel Pentium-4 processor manuals, 99 100 http://developer.intel.com/design/pentium4/manuals 101 102"Intel Pentium 4 Processor Optimization Reference Manual", Intel, 2001, 103order number 248966. Available on-line: 104 105 http://developer.intel.com/design/pentium4/manuals/248966.htm 106 107 108 109---------------- 110Local variables: 111mode: text 112fill-column: 76 113End: 114