1# Hitachi H8 testcase 'mov.w' 2# mach(): h8300h h8300s h8sx 3# as(h8300h): --defsym sim_cpu=1 4# as(h8300s): --defsym sim_cpu=2 5# as(h8sx): --defsym sim_cpu=3 6# ld(h8300h): -m h8300helf 7# ld(h8300s): -m h8300self 8# ld(h8sx): -m h8300sxelf 9 10 .include "testutils.inc" 11 12 start 13 14 .data 15 .align 4 16byte_src: 17 .byte 0x77 18byte_dst: 19 .byte 0 20 21 .text 22 23 ;; 24 ;; Move byte from immediate source 25 ;; 26 27.if (sim_cpu == h8sx) 28mov_b_imm8_to_reg8: 29 set_grs_a5a5 ; Fill all general regs with a fixed pattern 30 set_ccr_zero 31 32 ;; mov.b #xx:8, rd 33 mov.b #0x77:8, r0l ; Immediate 3-bit operand 34;;; .word 0xf877 35 36 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 37 test_neg_clear 38 test_zero_clear 39 test_ovf_clear 40 test_carry_clear 41 42 test_h_gr32 0xa5a5a577 er0 43 44 test_gr_a5a5 1 ; Make sure other general regs not disturbed 45 test_gr_a5a5 2 46 test_gr_a5a5 3 47 test_gr_a5a5 4 48 test_gr_a5a5 5 49 test_gr_a5a5 6 50 test_gr_a5a5 7 51.endif 52 53.if (sim_cpu == h8sx) 54mov_b_imm4_to_abs16: 55 set_grs_a5a5 ; Fill all general regs with a fixed pattern 56 set_ccr_zero 57 58 ;; mov.b #xx:4, @aa:16 59 mov.b #0xf:4, @byte_dst:16 ; 16-bit address-direct operand 60;;; .word 0x6adf 61;;; .word @byte_dst 62 63 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 64 test_neg_clear 65 test_zero_clear 66 test_ovf_clear 67 test_carry_clear 68 69 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 70 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 71 test_gr_a5a5 2 ; to examine the destination memory). 72 test_gr_a5a5 3 73 test_gr_a5a5 4 74 test_gr_a5a5 5 75 test_gr_a5a5 6 76 test_gr_a5a5 7 77 78 ;; Now check the result of the move to memory. 79 cmp.b #0xf, @byte_dst 80 beq .Lnext21 81 fail 82.Lnext21: 83 mov.b #0, @byte_dst ; zero it again for the next use. 84 85mov_b_imm4_to_abs32: 86 set_grs_a5a5 ; Fill all general regs with a fixed pattern 87 set_ccr_zero 88 89 ;; mov.b #xx:4, @aa:32 90 mov.b #0xf:4, @byte_dst:32 ; 32-bit address-direct operand 91;;; .word 0x6aff 92;;; .long @byte_dst 93 94 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 95 test_neg_clear 96 test_zero_clear 97 test_ovf_clear 98 test_carry_clear 99 100 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 101 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 102 test_gr_a5a5 2 ; to examine the destination memory). 103 test_gr_a5a5 3 104 test_gr_a5a5 4 105 test_gr_a5a5 5 106 test_gr_a5a5 6 107 test_gr_a5a5 7 108 109 ;; Now check the result of the move to memory. 110 cmp.b #0xf, @byte_dst 111 beq .Lnext22 112 fail 113.Lnext22: 114 mov.b #0, @byte_dst ; zero it again for the next use. 115 116mov_b_imm8_to_indirect: 117 set_grs_a5a5 ; Fill all general regs with a fixed pattern 118 set_ccr_zero 119 120 ;; mov.b #xx:8, @erd 121 mov.l #byte_dst, er1 122 mov.b #0xa5:8, @er1 ; Register indirect operand 123;;; .word 0x017d 124;;; .word 0x01a5 125 126 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 127 test_neg_set 128 test_zero_clear 129 test_ovf_clear 130 test_carry_clear 131 132 test_gr_a5a5 0 ; Make sure other general regs not disturbed 133 test_h_gr32 byte_dst, er1 134 test_gr_a5a5 2 135 test_gr_a5a5 3 136 test_gr_a5a5 4 137 test_gr_a5a5 5 138 test_gr_a5a5 6 139 test_gr_a5a5 7 140 141 ;; Now check the result of the move to memory. 142 cmp.b #0xa5, @byte_dst 143 beq .Lnext1 144 fail 145.Lnext1: 146 mov.b #0, @byte_dst ; zero it again for the next use. 147 148mov_b_imm8_to_postinc: ; post-increment from imm8 to mem 149 set_grs_a5a5 ; Fill all general regs with a fixed pattern 150 set_ccr_zero 151 152 ;; mov.b #xx:8, @erd+ 153 mov.l #byte_dst, er1 154 mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands. 155;;; .word 0x017d 156;;; .word 0x81a5 157 158 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 159 test_neg_set 160 test_zero_clear 161 test_ovf_clear 162 test_carry_clear 163 164 test_gr_a5a5 0 ; Make sure other general regs not disturbed 165 test_h_gr32 byte_dst+1, er1 166 test_gr_a5a5 2 167 test_gr_a5a5 3 168 test_gr_a5a5 4 169 test_gr_a5a5 5 170 test_gr_a5a5 6 171 test_gr_a5a5 7 172 173 ;; Now check the result of the move to memory. 174 cmp.b #0xa5, @byte_dst 175 beq .Lnext2 176 fail 177.Lnext2: 178 mov.b #0, @byte_dst ; zero it again for the next use. 179 180mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem 181 set_grs_a5a5 ; Fill all general regs with a fixed pattern 182 set_ccr_zero 183 184 ;; mov.b #xx:8, @erd- 185 mov.l #byte_dst, er1 186 mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands. 187;;; .word 0x017d 188;;; .word 0xa1a5 189 190 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 191 test_neg_set 192 test_zero_clear 193 test_ovf_clear 194 test_carry_clear 195 196 test_gr_a5a5 0 ; Make sure other general regs not disturbed 197 test_h_gr32 byte_dst-1, er1 198 test_gr_a5a5 2 199 test_gr_a5a5 3 200 test_gr_a5a5 4 201 test_gr_a5a5 5 202 test_gr_a5a5 6 203 test_gr_a5a5 7 204 205 ;; Now check the result of the move to memory. 206 cmp.b #0xa5, @byte_dst 207 beq .Lnext3 208 fail 209.Lnext3: 210 mov.b #0, @byte_dst ; zero it again for the next use. 211 212mov_b_imm8_to_preinc: ; pre-increment from register to mem 213 set_grs_a5a5 ; Fill all general regs with a fixed pattern 214 set_ccr_zero 215 216 ;; mov.b #xx:8, @+erd 217 mov.l #byte_dst-1, er1 218 mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands 219;;; .word 0x017d 220;;; .word 0x91a5 221 222 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 223 test_neg_set 224 test_zero_clear 225 test_ovf_clear 226 test_carry_clear 227 228 test_gr_a5a5 0 ; Make sure other general regs not disturbed 229 test_h_gr32 byte_dst, er1 230 test_gr_a5a5 2 231 test_gr_a5a5 3 232 test_gr_a5a5 4 233 test_gr_a5a5 5 234 test_gr_a5a5 6 235 test_gr_a5a5 7 236 237 ;; Now check the result of the move to memory. 238 cmp.b #0xa5, @byte_dst 239 beq .Lnext4 240 fail 241.Lnext4: 242 mov.b #0, @byte_dst ; zero it again for the next use. 243 244mov_b_imm8_to_predec: ; pre-decrement from register to mem 245 set_grs_a5a5 ; Fill all general regs with a fixed pattern 246 set_ccr_zero 247 248 ;; mov.b #xx:8, @-erd 249 mov.l #byte_dst+1, er1 250 mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands 251;;; .word 0x017d 252;;; .word 0xb1a5 253 254 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 255 test_neg_set 256 test_zero_clear 257 test_ovf_clear 258 test_carry_clear 259 260 test_gr_a5a5 0 ; Make sure other general regs not disturbed 261 test_h_gr32 byte_dst, er1 262 test_gr_a5a5 2 263 test_gr_a5a5 3 264 test_gr_a5a5 4 265 test_gr_a5a5 5 266 test_gr_a5a5 6 267 test_gr_a5a5 7 268 269 ;; Now check the result of the move to memory. 270 cmp.b #0xa5, @byte_dst 271 beq .Lnext5 272 fail 273.Lnext5: 274 mov.b #0, @byte_dst ; zero it again for the next use. 275 276mov_b_imm8_to_disp2: 277 set_grs_a5a5 ; Fill all general regs with a fixed pattern 278 set_ccr_zero 279 280 ;; mov.b #xx:8, @(dd:2, erd) 281 mov.l #byte_dst-3, er1 282 mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand 283;;; .word 0x017d 284;;; .word 0x31a5 285 286 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 287 test_neg_set 288 test_zero_clear 289 test_ovf_clear 290 test_carry_clear 291 292 test_gr_a5a5 0 ; Make sure other general regs not disturbed 293 test_h_gr32 byte_dst-3, er1 294 test_gr_a5a5 2 295 test_gr_a5a5 3 296 test_gr_a5a5 4 297 test_gr_a5a5 5 298 test_gr_a5a5 6 299 test_gr_a5a5 7 300 301 ;; Now check the result of the move to memory. 302 cmp.b #0xa5, @byte_dst 303 beq .Lnext6 304 fail 305.Lnext6: 306 mov.b #0, @byte_dst ; zero it again for the next use. 307 308mov_b_imm8_to_disp16: 309 set_grs_a5a5 ; Fill all general regs with a fixed pattern 310 set_ccr_zero 311 312 ;; mov.b #xx:8, @(dd:16, erd) 313 mov.l #byte_dst-4, er1 314 mov.b #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand 315;;; .word 0x017d 316;;; .word 0x6f90 317;;; .word 0x0004 318 319 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 320 test_neg_set 321 test_zero_clear 322 test_ovf_clear 323 test_carry_clear 324 325 test_gr_a5a5 0 ; Make sure other general regs not disturbed 326 test_h_gr32 byte_dst-4, er1 327 test_gr_a5a5 2 328 test_gr_a5a5 3 329 test_gr_a5a5 4 330 test_gr_a5a5 5 331 test_gr_a5a5 6 332 test_gr_a5a5 7 333 334 ;; Now check the result of the move to memory. 335 cmp.b #0xa5, @byte_dst 336 beq .Lnext7 337 fail 338.Lnext7: 339 mov.b #0, @byte_dst ; zero it again for the next use. 340 341mov_b_imm8_to_disp32: 342 set_grs_a5a5 ; Fill all general regs with a fixed pattern 343 set_ccr_zero 344 345 ;; mov.b #xx:8, @(dd:32, erd) 346 mov.l #byte_dst-8, er1 347 mov.b #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand 348;;; .word 0x017d 349;;; .word 0xc9a5 350;;; .long 8 351 352 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 353 test_neg_set 354 test_zero_clear 355 test_ovf_clear 356 test_carry_clear 357 358 test_gr_a5a5 0 ; Make sure other general regs not disturbed 359 test_h_gr32 byte_dst-8, er1 360 test_gr_a5a5 2 361 test_gr_a5a5 3 362 test_gr_a5a5 4 363 test_gr_a5a5 5 364 test_gr_a5a5 6 365 test_gr_a5a5 7 366 367 ;; Now check the result of the move to memory. 368 cmp.b #0xa5, @byte_dst 369 beq .Lnext8 370 fail 371.Lnext8: 372 mov.b #0, @byte_dst ; zero it again for the next use. 373 374mov_b_imm8_to_indexb16: 375 set_grs_a5a5 ; Fill all general regs with a fixed pattern 376 mov.l #0xffffff01, er1 377 set_ccr_zero 378 ;; mov.b #xx:8, @(dd:16, rd.b) 379 mov.b #0xa5:8, @(byte_dst-1:16, r1.b) ; byte indexed operand 380 381 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 382 test_neg_set 383 test_zero_clear 384 test_ovf_clear 385 test_carry_clear 386 387 test_gr_a5a5 0 ; Make sure other general regs not disturbed 388 test_h_gr32 0xffffff01, er1 389 test_gr_a5a5 2 390 test_gr_a5a5 3 391 test_gr_a5a5 4 392 test_gr_a5a5 5 393 test_gr_a5a5 6 394 test_gr_a5a5 7 395 396 ;; Now check the result of the move to memory. 397 cmp.b #0xa5, @byte_dst 398 bne fail1 399 mov.b #0, @byte_dst ; zero it again for the next use. 400 401mov_b_imm8_to_indexw16: 402 set_grs_a5a5 ; Fill all general regs with a fixed pattern 403 mov.l #0xffff0002, er1 404 set_ccr_zero 405 ;; mov.b #xx:8, @(dd:16, rd.w) 406 mov.b #0xa5:8, @(byte_dst-2:16, r1.w) ; byte indexed operand 407 408 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 409 test_neg_set 410 test_zero_clear 411 test_ovf_clear 412 test_carry_clear 413 414 test_gr_a5a5 0 ; Make sure other general regs not disturbed 415 test_h_gr32 0xffff0002, er1 416 test_gr_a5a5 2 417 test_gr_a5a5 3 418 test_gr_a5a5 4 419 test_gr_a5a5 5 420 test_gr_a5a5 6 421 test_gr_a5a5 7 422 423 ;; Now check the result of the move to memory. 424 cmp.b #0xa5, @byte_dst 425 bne fail1 426 mov.b #0, @byte_dst ; zero it again for the next use. 427 428mov_b_imm8_to_indexl16: 429 set_grs_a5a5 ; Fill all general regs with a fixed pattern 430 mov.l #0x00000003, er1 431 set_ccr_zero 432 ;; mov.b #xx:8, @(dd:16, erd.l) 433 mov.b #0xa5:8, @(byte_dst-3:16, er1.l) ; byte indexed operand 434 435 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 436 test_neg_set 437 test_zero_clear 438 test_ovf_clear 439 test_carry_clear 440 441 test_gr_a5a5 0 ; Make sure other general regs not disturbed 442 test_h_gr32 0x00000003, er1 443 test_gr_a5a5 2 444 test_gr_a5a5 3 445 test_gr_a5a5 4 446 test_gr_a5a5 5 447 test_gr_a5a5 6 448 test_gr_a5a5 7 449 450 ;; Now check the result of the move to memory. 451 cmp.b #0xa5, @byte_dst 452 bne fail1 453 mov.b #0, @byte_dst ; zero it again for the next use. 454 455mov_b_imm8_to_indexb32: 456 set_grs_a5a5 ; Fill all general regs with a fixed pattern 457 mov.l #0xffffff04, er1 458 set_ccr_zero 459 ;; mov.b #xx:8, @(dd:32, rd.b) 460 mov.b #0xa5:8, @(byte_dst-4:32, r1.b) ; byte indexed operand 461 462 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 463 test_neg_set 464 test_zero_clear 465 test_ovf_clear 466 test_carry_clear 467 468 test_gr_a5a5 0 ; Make sure other general regs not disturbed 469 test_h_gr32 0xffffff04 er1 470 test_gr_a5a5 2 471 test_gr_a5a5 3 472 test_gr_a5a5 4 473 test_gr_a5a5 5 474 test_gr_a5a5 6 475 test_gr_a5a5 7 476 477 ;; Now check the result of the move to memory. 478 cmp.b #0xa5, @byte_dst 479 bne fail1 480 mov.b #0, @byte_dst ; zero it again for the next use. 481 482mov_b_imm8_to_indexw32: 483 set_grs_a5a5 ; Fill all general regs with a fixed pattern 484 mov.l #0xffff0005, er1 485 set_ccr_zero 486 ;; mov.b #xx:8, @(dd:32, rd.w) 487 mov.b #0xa5:8, @(byte_dst-5:32, r1.w) ; byte indexed operand 488 489 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 490 test_neg_set 491 test_zero_clear 492 test_ovf_clear 493 test_carry_clear 494 495 test_gr_a5a5 0 ; Make sure other general regs not disturbed 496 test_h_gr32 0xffff0005 er1 497 test_gr_a5a5 2 498 test_gr_a5a5 3 499 test_gr_a5a5 4 500 test_gr_a5a5 5 501 test_gr_a5a5 6 502 test_gr_a5a5 7 503 504 ;; Now check the result of the move to memory. 505 cmp.b #0xa5, @byte_dst 506 bne fail1 507 mov.b #0, @byte_dst ; zero it again for the next use. 508 509mov_b_imm8_to_indexl32: 510 set_grs_a5a5 ; Fill all general regs with a fixed pattern 511 mov.l #0x00000006, er1 512 set_ccr_zero 513 ;; mov.b #xx:8, @(dd:32, erd.l) 514 mov.b #0xa5:8, @(byte_dst-6:32, er1.l) ; byte indexed operand 515 516 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 517 test_neg_set 518 test_zero_clear 519 test_ovf_clear 520 test_carry_clear 521 522 test_gr_a5a5 0 ; Make sure other general regs not disturbed 523 test_h_gr32 0x00000006 er1 524 test_gr_a5a5 2 525 test_gr_a5a5 3 526 test_gr_a5a5 4 527 test_gr_a5a5 5 528 test_gr_a5a5 6 529 test_gr_a5a5 7 530 531 ;; Now check the result of the move to memory. 532 cmp.b #0xa5, @byte_dst 533 bne fail1 534 mov.b #0, @byte_dst ; zero it again for the next use. 535 536mov_b_imm8_to_abs16: 537 set_grs_a5a5 ; Fill all general regs with a fixed pattern 538 set_ccr_zero 539 540 ;; mov.b #xx:8, @aa:16 541 mov.b #0xa5:8, @byte_dst:16 ; 16-bit address-direct operand 542;;; .word 0x017d 543;;; .word 0x40a5 544;;; .word @byte_dst 545 546 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 547 test_neg_set 548 test_zero_clear 549 test_ovf_clear 550 test_carry_clear 551 552 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 553 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 554 test_gr_a5a5 2 ; to examine the destination memory). 555 test_gr_a5a5 3 556 test_gr_a5a5 4 557 test_gr_a5a5 5 558 test_gr_a5a5 6 559 test_gr_a5a5 7 560 561 ;; Now check the result of the move to memory. 562 cmp.b #0xa5, @byte_dst 563 beq .Lnext9 564 fail 565.Lnext9: 566 mov.b #0, @byte_dst ; zero it again for the next use. 567 568mov_b_imm8_to_abs32: 569 set_grs_a5a5 ; Fill all general regs with a fixed pattern 570 set_ccr_zero 571 572 ;; mov.b #xx:8, @aa:32 573 mov.b #0xa5:8, @byte_dst:32 ; 32-bit address-direct operand 574;;; .word 0x017d 575;;; .word 0x48a5 576;;; .long @byte_dst 577 578 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 579 test_neg_set 580 test_zero_clear 581 test_ovf_clear 582 test_carry_clear 583 584 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 585 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 586 test_gr_a5a5 2 ; to examine the destination memory). 587 test_gr_a5a5 3 588 test_gr_a5a5 4 589 test_gr_a5a5 5 590 test_gr_a5a5 6 591 test_gr_a5a5 7 592 593 ;; Now check the result of the move to memory. 594 cmp.b #0xa5, @byte_dst 595 beq .Lnext10 596 fail 597.Lnext10: 598 mov.b #0, @byte_dst ; zero it again for the next use. 599 600.endif 601 602 ;; 603 ;; Move byte from register source 604 ;; 605 606mov_b_reg8_to_reg8: 607 set_grs_a5a5 ; Fill all general regs with a fixed pattern 608 set_ccr_zero 609 610 ;; mov.b ers, erd 611 mov.b #0x12, r1l 612 mov.b r1l, r0l ; Register 8-bit operand 613;;; .word 0x0c98 614 615 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 616 test_neg_clear 617 test_zero_clear 618 test_ovf_clear 619 test_carry_clear 620 test_h_gr16 0xa512 r0 621 test_h_gr16 0xa512 r1 ; mov src unchanged 622.if (sim_cpu) 623 test_h_gr32 0xa5a5a512 er0 624 test_h_gr32 0xa5a5a512 er1 ; mov src unchanged 625.endif 626 test_gr_a5a5 2 ; Make sure other general regs not disturbed 627 test_gr_a5a5 3 628 test_gr_a5a5 4 629 test_gr_a5a5 5 630 test_gr_a5a5 6 631 test_gr_a5a5 7 632 633 634mov_b_reg8_to_indirect: 635 set_grs_a5a5 ; Fill all general regs with a fixed pattern 636 set_ccr_zero 637 638 ;; mov.b ers, @erd 639 mov.l #byte_dst, er1 640 mov.b r0l, @er1 ; Register indirect operand 641;;; .word 0x6898 642 643 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 644 test_neg_set 645 test_zero_clear 646 test_ovf_clear 647 test_carry_clear 648 649 test_gr_a5a5 0 ; Make sure other general regs not disturbed 650 test_h_gr32 byte_dst, er1 651 test_gr_a5a5 2 652 test_gr_a5a5 3 653 test_gr_a5a5 4 654 test_gr_a5a5 5 655 test_gr_a5a5 6 656 test_gr_a5a5 7 657 658 ;; Now check the result of the move to memory. 659 mov.b @byte_dst, r0l 660 cmp.b r2l, r0l 661 beq .Lnext44 662 fail 663.Lnext44: 664 mov.b #0, r0l 665 mov.b r0l, @byte_dst ; zero it again for the next use. 666 667.if (sim_cpu == h8sx) 668mov_b_reg8_to_postinc: ; post-increment from register to mem 669 set_grs_a5a5 ; Fill all general regs with a fixed pattern 670 set_ccr_zero 671 672 ;; mov.b ers, @erd+ 673 mov.l #byte_dst, er1 674 mov.b r0l, @er1+ ; Register post-incr operand 675;;; .word 0x0173 676;;; .word 0x6c98 677 678 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 679 test_neg_set 680 test_zero_clear 681 test_ovf_clear 682 test_carry_clear 683 684 test_gr_a5a5 0 ; Make sure other general regs not disturbed 685 test_h_gr32 byte_dst+1, er1 686 test_gr_a5a5 2 687 test_gr_a5a5 3 688 test_gr_a5a5 4 689 test_gr_a5a5 5 690 test_gr_a5a5 6 691 test_gr_a5a5 7 692 693 ;; Now check the result of the move to memory. 694 cmp.b r2l, @byte_dst 695 beq .Lnext49 696 fail 697.Lnext49: 698 mov.b #0, @byte_dst ; zero it again for the next use. 699 700mov_b_reg8_to_postdec: ; post-decrement from register to mem 701 set_grs_a5a5 ; Fill all general regs with a fixed pattern 702 set_ccr_zero 703 704 ;; mov.b ers, @erd- 705 mov.l #byte_dst, er1 706 mov.b r0l, @er1- ; Register post-decr operand 707;;; .word 0x0171 708;;; .word 0x6c98 709 710 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 711 test_neg_set 712 test_zero_clear 713 test_ovf_clear 714 test_carry_clear 715 716 test_gr_a5a5 0 ; Make sure other general regs not disturbed 717 test_h_gr32 byte_dst-1, er1 718 test_gr_a5a5 2 719 test_gr_a5a5 3 720 test_gr_a5a5 4 721 test_gr_a5a5 5 722 test_gr_a5a5 6 723 test_gr_a5a5 7 724 725 ;; Now check the result of the move to memory. 726 cmp.b r2l, @byte_dst 727 beq .Lnext50 728 fail 729.Lnext50: 730 mov.b #0, @byte_dst ; zero it again for the next use. 731 732mov_b_reg8_to_preinc: ; pre-increment from register to mem 733 set_grs_a5a5 ; Fill all general regs with a fixed pattern 734 set_ccr_zero 735 736 ;; mov.b ers, @+erd 737 mov.l #byte_dst-1, er1 738 mov.b r0l, @+er1 ; Register pre-incr operand 739;;; .word 0x0172 740;;; .word 0x6c98 741 742 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 743 test_neg_set 744 test_zero_clear 745 test_ovf_clear 746 test_carry_clear 747 748 test_gr_a5a5 0 ; Make sure other general regs not disturbed 749 test_h_gr32 byte_dst, er1 750 test_gr_a5a5 2 751 test_gr_a5a5 3 752 test_gr_a5a5 4 753 test_gr_a5a5 5 754 test_gr_a5a5 6 755 test_gr_a5a5 7 756 757 ;; Now check the result of the move to memory. 758 cmp.b r2l, @byte_dst 759 beq .Lnext51 760 fail 761.Lnext51: 762 mov.b #0, @byte_dst ; zero it again for the next use. 763.endif 764 765mov_b_reg8_to_predec: ; pre-decrement from register to mem 766 set_grs_a5a5 ; Fill all general regs with a fixed pattern 767 set_ccr_zero 768 769 ;; mov.b ers, @-erd 770 mov.l #byte_dst+1, er1 771 mov.b r0l, @-er1 ; Register pre-decr operand 772;;; .word 0x6c98 773 774 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 775 test_neg_set 776 test_zero_clear 777 test_ovf_clear 778 test_carry_clear 779 780 test_gr_a5a5 0 ; Make sure other general regs not disturbed 781 test_h_gr32 byte_dst, er1 782 test_gr_a5a5 2 783 test_gr_a5a5 3 784 test_gr_a5a5 4 785 test_gr_a5a5 5 786 test_gr_a5a5 6 787 test_gr_a5a5 7 788 789 ;; Now check the result of the move to memory. 790 mov.b @byte_dst, r0l 791 cmp.b r2l, r0l 792 beq .Lnext48 793 fail 794.Lnext48: 795 mov.b #0, r0l 796 mov.b r0l, @byte_dst ; zero it again for the next use. 797 798.if (sim_cpu == h8sx) 799mov_b_reg8_to_disp2: 800 set_grs_a5a5 ; Fill all general regs with a fixed pattern 801 set_ccr_zero 802 803 ;; mov.b ers, @(dd:2, erd) 804 mov.l #byte_dst-3, er1 805 mov.b r0l, @(3:2, er1) ; Register plus 2-bit disp. operand 806;;; .word 0x0173 807;;; .word 0x6898 808 809 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 810 test_neg_set 811 test_zero_clear 812 test_ovf_clear 813 test_carry_clear 814 815 test_gr_a5a5 0 ; Make sure other general regs not disturbed 816 test_h_gr32 byte_dst-3, er1 817 test_gr_a5a5 2 818 test_gr_a5a5 3 819 test_gr_a5a5 4 820 test_gr_a5a5 5 821 test_gr_a5a5 6 822 test_gr_a5a5 7 823 824 ;; Now check the result of the move to memory. 825 cmp.b r2l, @byte_dst 826 beq .Lnext52 827 fail 828.Lnext52: 829 mov.b #0, @byte_dst ; zero it again for the next use. 830.endif 831 832mov_b_reg8_to_disp16: 833 set_grs_a5a5 ; Fill all general regs with a fixed pattern 834 set_ccr_zero 835 836 ;; mov.b ers, @(dd:16, erd) 837 mov.l #byte_dst-4, er1 838 mov.b r0l, @(4:16, er1) ; Register plus 16-bit disp. operand 839;;; .word 0x6e98 840;;; .word 0x0004 841 842 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 843 test_neg_set 844 test_zero_clear 845 test_ovf_clear 846 test_carry_clear 847 848 test_h_gr32 byte_dst-4, er1 849 test_gr_a5a5 0 ; Make sure other general regs not disturbed 850 test_gr_a5a5 2 851 test_gr_a5a5 3 852 test_gr_a5a5 4 853 test_gr_a5a5 5 854 test_gr_a5a5 6 855 test_gr_a5a5 7 856 857 ;; Now check the result of the move to memory. 858 mov.b @byte_dst, r0l 859 cmp.b r2l, r0l 860 beq .Lnext45 861 fail 862.Lnext45: 863 mov.b #0, r0l 864 mov.b r0l, @byte_dst ; zero it again for the next use. 865 866mov_b_reg8_to_disp32: 867 set_grs_a5a5 ; Fill all general regs with a fixed pattern 868 set_ccr_zero 869 870 ;; mov.b ers, @(dd:32, erd) 871 mov.l #byte_dst-8, er1 872 mov.b r0l, @(8:32, er1) ; Register plus 32-bit disp. operand 873;;; .word 0x7810 874;;; .word 0x6aa8 875;;; .long 8 876 877 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 878 test_neg_set 879 test_zero_clear 880 test_ovf_clear 881 test_carry_clear 882 883 test_h_gr32 byte_dst-8, er1 884 test_gr_a5a5 0 ; Make sure other general regs not disturbed 885 test_gr_a5a5 2 886 test_gr_a5a5 3 887 test_gr_a5a5 4 888 test_gr_a5a5 5 889 test_gr_a5a5 6 890 test_gr_a5a5 7 891 892 ;; Now check the result of the move to memory. 893 mov.b @byte_dst, r0l 894 cmp.b r2l, r0l 895 beq .Lnext46 896 fail 897.Lnext46: 898 mov.b #0, r0l 899 mov.b r0l, @byte_dst ; zero it again for the next use. 900 901.if (sim_cpu == h8sx) 902mov_b_reg8_to_indexb16: 903 set_grs_a5a5 ; Fill all general regs with a fixed pattern 904 mov.l #0xffffff01, er1 905 set_ccr_zero 906 ;; mov.b ers, @(dd:16, rd.b) 907 mov.b r0l, @(byte_dst-1:16, r1.b) ; byte indexed operand 908 909 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 910 test_neg_set 911 test_zero_clear 912 test_ovf_clear 913 test_carry_clear 914 915 test_h_gr32 0xffffff01 er1 916 test_gr_a5a5 0 ; Make sure other general regs not disturbed 917 test_gr_a5a5 2 918 test_gr_a5a5 3 919 test_gr_a5a5 4 920 test_gr_a5a5 5 921 test_gr_a5a5 6 922 test_gr_a5a5 7 923 924 ;; Now check the result of the move to memory. 925 cmp.b @byte_dst, r0l 926 bne fail1 927 mov.b #0, @byte_dst ; zero it again for the next use. 928 929mov_b_reg8_to_indexw16: 930 set_grs_a5a5 ; Fill all general regs with a fixed pattern 931 mov.l #0xffff0002, er1 932 set_ccr_zero 933 ;; mov.b ers, @(dd:16, rd.w) 934 mov.b r0l, @(byte_dst-2:16, r1.w) ; byte indexed operand 935 936 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 937 test_neg_set 938 test_zero_clear 939 test_ovf_clear 940 test_carry_clear 941 942 test_h_gr32 0xffff0002 er1 943 test_gr_a5a5 0 ; Make sure other general regs not disturbed 944 test_gr_a5a5 2 945 test_gr_a5a5 3 946 test_gr_a5a5 4 947 test_gr_a5a5 5 948 test_gr_a5a5 6 949 test_gr_a5a5 7 950 951 ;; Now check the result of the move to memory. 952 cmp.b @byte_dst, r0l 953 bne fail1 954 mov.b #0, @byte_dst ; zero it again for the next use. 955 956mov_b_reg8_to_indexl16: 957 set_grs_a5a5 ; Fill all general regs with a fixed pattern 958 mov.l #0x00000003, er1 959 set_ccr_zero 960 ;; mov.b ers, @(dd:16, erd.l) 961 mov.b r0l, @(byte_dst-3:16, er1.l) ; byte indexed operand 962 963 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 964 test_neg_set 965 test_zero_clear 966 test_ovf_clear 967 test_carry_clear 968 969 test_h_gr32 0x00000003 er1 970 test_gr_a5a5 0 ; Make sure other general regs not disturbed 971 test_gr_a5a5 2 972 test_gr_a5a5 3 973 test_gr_a5a5 4 974 test_gr_a5a5 5 975 test_gr_a5a5 6 976 test_gr_a5a5 7 977 978 ;; Now check the result of the move to memory. 979 cmp.b @byte_dst, r0l 980 bne fail1 981 mov.b #0, @byte_dst ; zero it again for the next use. 982 983mov_b_reg8_to_indexb32: 984 set_grs_a5a5 ; Fill all general regs with a fixed pattern 985 mov.l #0xffffff04 er1 986 set_ccr_zero 987 ;; mov.b ers, @(dd:32, rd.b) 988 mov.b r0l, @(byte_dst-4:32, r1.b) ; byte indexed operand 989 990 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 991 test_neg_set 992 test_zero_clear 993 test_ovf_clear 994 test_carry_clear 995 996 test_h_gr32 0xffffff04, er1 997 test_gr_a5a5 0 ; Make sure other general regs not disturbed 998 test_gr_a5a5 2 999 test_gr_a5a5 3 1000 test_gr_a5a5 4 1001 test_gr_a5a5 5 1002 test_gr_a5a5 6 1003 test_gr_a5a5 7 1004 1005 ;; Now check the result of the move to memory. 1006 cmp.b @byte_dst, r0l 1007 bne fail1 1008 mov.b #0, @byte_dst ; zero it again for the next use. 1009 1010mov_b_reg8_to_indexw32: 1011 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1012 mov.l #0xffff0005 er1 1013 set_ccr_zero 1014 ;; mov.b ers, @(dd:32, rd.w) 1015 mov.b r0l, @(byte_dst-5:32, r1.w) ; byte indexed operand 1016 1017 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1018 test_neg_set 1019 test_zero_clear 1020 test_ovf_clear 1021 test_carry_clear 1022 1023 test_h_gr32 0xffff0005, er1 1024 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1025 test_gr_a5a5 2 1026 test_gr_a5a5 3 1027 test_gr_a5a5 4 1028 test_gr_a5a5 5 1029 test_gr_a5a5 6 1030 test_gr_a5a5 7 1031 1032 ;; Now check the result of the move to memory. 1033 cmp.b @byte_dst, r0l 1034 bne fail1 1035 mov.b #0, @byte_dst ; zero it again for the next use. 1036 1037mov_b_reg8_to_indexl32: 1038 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1039 mov.l #0x00000006 er1 1040 set_ccr_zero 1041 ;; mov.b ers, @(dd:32, erd.l) 1042 mov.b r0l, @(byte_dst-6:32, er1.l) ; byte indexed operand 1043 1044 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1045 test_neg_set 1046 test_zero_clear 1047 test_ovf_clear 1048 test_carry_clear 1049 1050 test_h_gr32 0x00000006, er1 1051 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1052 test_gr_a5a5 2 1053 test_gr_a5a5 3 1054 test_gr_a5a5 4 1055 test_gr_a5a5 5 1056 test_gr_a5a5 6 1057 test_gr_a5a5 7 1058 1059 ;; Now check the result of the move to memory. 1060 cmp.b @byte_dst, r0l 1061 bne fail1 1062 mov.b #0, @byte_dst ; zero it again for the next use. 1063.endif 1064 1065.if (sim_cpu == h8sx) 1066mov_b_reg8_to_abs8: 1067 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1068 1069 mov.l #byte_dst-20, er0 1070 ldc er0, sbr 1071 set_ccr_zero 1072 ;; mov.b ers, @aa:8 1073 mov.b r1l, @20:8 ; 8-bit address-direct (sbr-relative) operand 1074 1075 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1076 test_neg_set 1077 test_zero_clear 1078 test_ovf_clear 1079 test_carry_clear 1080 1081 test_h_gr32 byte_dst-20, er0 1082 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1083 test_gr_a5a5 2 1084 test_gr_a5a5 3 1085 test_gr_a5a5 4 1086 test_gr_a5a5 5 1087 test_gr_a5a5 6 1088 test_gr_a5a5 7 1089 1090 ;; Now check the result of the move to memory. 1091 cmp.b @byte_dst, r1l 1092 bne fail1 1093 mov.b #0, @byte_dst ; zero it again for the next use. 1094.endif 1095 1096mov_b_reg8_to_abs16: 1097 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1098 set_ccr_zero 1099 1100 ;; mov.b ers, @aa:16 1101 mov.b r0l, @byte_dst:16 ; 16-bit address-direct operand 1102;;; .word 0x6a88 1103;;; .word @byte_dst 1104 1105 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1106 test_neg_set 1107 test_zero_clear 1108 test_ovf_clear 1109 test_carry_clear 1110 1111 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 1112 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 1113 test_gr_a5a5 2 ; to examine the destination memory). 1114 test_gr_a5a5 3 1115 test_gr_a5a5 4 1116 test_gr_a5a5 5 1117 test_gr_a5a5 6 1118 test_gr_a5a5 7 1119 1120 ;; Now check the result of the move to memory. 1121 mov.b @byte_dst, r0l 1122 cmp.b r0l, r1l 1123 beq .Lnext41 1124 fail 1125.Lnext41: 1126 mov.b #0, r0l 1127 mov.b r0l, @byte_dst ; zero it again for the next use. 1128 1129mov_b_reg8_to_abs32: 1130 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1131 set_ccr_zero 1132 1133 ;; mov.b ers, @aa:32 1134 mov.b r0l, @byte_dst:32 ; 32-bit address-direct operand 1135;;; .word 0x6aa8 1136;;; .long @byte_dst 1137 1138 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1139 test_neg_set 1140 test_zero_clear 1141 test_ovf_clear 1142 test_carry_clear 1143 1144 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 1145 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 1146 test_gr_a5a5 2 ; to examine the destination memory). 1147 test_gr_a5a5 3 1148 test_gr_a5a5 4 1149 test_gr_a5a5 5 1150 test_gr_a5a5 6 1151 test_gr_a5a5 7 1152 1153 ;; Now check the result of the move to memory. 1154 mov.b @byte_dst, r0l 1155 cmp.b r0l, r1l 1156 beq .Lnext42 1157 fail 1158.Lnext42: 1159 mov.b #0, r0l 1160 mov.b r0l, @byte_dst ; zero it again for the next use. 1161 1162 ;; 1163 ;; Move byte to register destination. 1164 ;; 1165 1166mov_b_indirect_to_reg8: 1167 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1168 set_ccr_zero 1169 1170 ;; mov.b @ers, rd 1171 mov.l #byte_src, er1 1172 mov.b @er1, r0l ; Register indirect operand 1173;;; .word 0x6818 1174 1175 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1176 test_neg_clear 1177 test_zero_clear 1178 test_ovf_clear 1179 test_carry_clear 1180 1181 test_h_gr32 0xa5a5a577 er0 1182 1183 test_h_gr32 byte_src, er1 1184 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1185 test_gr_a5a5 3 1186 test_gr_a5a5 4 1187 test_gr_a5a5 5 1188 test_gr_a5a5 6 1189 test_gr_a5a5 7 1190 1191mov_b_postinc_to_reg8: ; post-increment from mem to register 1192 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1193 set_ccr_zero 1194 1195 ;; mov.b @ers+, rd 1196 1197 mov.l #byte_src, er1 1198 mov.b @er1+, r0l ; Register post-incr operand 1199;;; .word 0x6c18 1200 1201 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1202 test_neg_clear 1203 test_zero_clear 1204 test_ovf_clear 1205 test_carry_clear 1206 1207 test_h_gr32 0xa5a5a577 er0 1208 1209 test_h_gr32 byte_src+1, er1 1210 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1211 test_gr_a5a5 3 1212 test_gr_a5a5 4 1213 test_gr_a5a5 5 1214 test_gr_a5a5 6 1215 test_gr_a5a5 7 1216 1217.if (sim_cpu == h8sx) 1218mov_b_postdec_to_reg8: ; post-decrement from mem to register 1219 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1220 set_ccr_zero 1221 1222 ;; mov.b @ers-, rd 1223 1224 mov.l #byte_src, er1 1225 mov.b @er1-, r0l ; Register post-decr operand 1226;;; .word 0x0172 1227;;; .word 0x6c18 1228 1229 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1230 test_neg_clear 1231 test_zero_clear 1232 test_ovf_clear 1233 test_carry_clear 1234 1235 test_h_gr32 0xa5a5a577 er0 1236 1237 test_h_gr32 byte_src-1, er1 1238 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1239 test_gr_a5a5 3 1240 test_gr_a5a5 4 1241 test_gr_a5a5 5 1242 test_gr_a5a5 6 1243 test_gr_a5a5 7 1244 1245mov_b_preinc_to_reg8: ; pre-increment from mem to register 1246 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1247 set_ccr_zero 1248 1249 ;; mov.b @+ers, rd 1250 1251 mov.l #byte_src-1, er1 1252 mov.b @+er1, r0l ; Register pre-incr operand 1253;;; .word 0x0171 1254;;; .word 0x6c18 1255 1256 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1257 test_neg_clear 1258 test_zero_clear 1259 test_ovf_clear 1260 test_carry_clear 1261 1262 test_h_gr32 0xa5a5a577 er0 1263 1264 test_h_gr32 byte_src, er1 1265 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1266 test_gr_a5a5 3 1267 test_gr_a5a5 4 1268 test_gr_a5a5 5 1269 test_gr_a5a5 6 1270 test_gr_a5a5 7 1271 1272mov_b_predec_to_reg8: ; pre-decrement from mem to register 1273 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1274 set_ccr_zero 1275 1276 ;; mov.b @-ers, rd 1277 1278 mov.l #byte_src+1, er1 1279 mov.b @-er1, r0l ; Register pre-decr operand 1280;;; .word 0x0173 1281;;; .word 0x6c18 1282 1283 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1284 test_neg_clear 1285 test_zero_clear 1286 test_ovf_clear 1287 test_carry_clear 1288 1289 test_h_gr32 0xa5a5a577 er0 1290 1291 test_h_gr32 byte_src, er1 1292 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1293 test_gr_a5a5 3 1294 test_gr_a5a5 4 1295 test_gr_a5a5 5 1296 test_gr_a5a5 6 1297 test_gr_a5a5 7 1298 1299 1300mov_b_disp2_to_reg8: 1301 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1302 set_ccr_zero 1303 1304 ;; mov.b @(dd:2, ers), rd 1305 mov.l #byte_src-1, er1 1306 mov.b @(1:2, er1), r0l ; Register plus 2-bit disp. operand 1307;;; .word 0x0171 1308;;; .word 0x6818 1309 1310 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1311 test_neg_clear 1312 test_zero_clear 1313 test_ovf_clear 1314 test_carry_clear 1315 1316 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 1317 1318 test_h_gr32 byte_src-1, er1 1319 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1320 test_gr_a5a5 3 1321 test_gr_a5a5 4 1322 test_gr_a5a5 5 1323 test_gr_a5a5 6 1324 test_gr_a5a5 7 1325.endif 1326 1327mov_b_disp16_to_reg8: 1328 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1329 set_ccr_zero 1330 1331 ;; mov.b @(dd:16, ers), rd 1332 mov.l #byte_src+0x1234, er1 1333 mov.b @(-0x1234:16, er1), r0l ; Register plus 16-bit disp. operand 1334;;; .word 0x6e18 1335;;; .word -0x1234 1336 1337 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1338 test_neg_clear 1339 test_zero_clear 1340 test_ovf_clear 1341 test_carry_clear 1342 1343 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 1344 1345 test_h_gr32 byte_src+0x1234, er1 1346 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1347 test_gr_a5a5 3 1348 test_gr_a5a5 4 1349 test_gr_a5a5 5 1350 test_gr_a5a5 6 1351 test_gr_a5a5 7 1352 1353mov_b_disp32_to_reg8: 1354 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1355 set_ccr_zero 1356 1357 ;; mov.b @(dd:32, ers), rd 1358 mov.l #byte_src+65536, er1 1359 mov.b @(-65536:32, er1), r0l ; Register plus 32-bit disp. operand 1360;;; .word 0x7810 1361;;; .word 0x6a28 1362;;; .long -65536 1363 1364 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1365 test_neg_clear 1366 test_zero_clear 1367 test_ovf_clear 1368 test_carry_clear 1369 1370 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 1371 1372 test_h_gr32 byte_src+65536, er1 1373 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1374 test_gr_a5a5 3 1375 test_gr_a5a5 4 1376 test_gr_a5a5 5 1377 test_gr_a5a5 6 1378 test_gr_a5a5 7 1379 1380.if (sim_cpu == h8sx) 1381mov_b_indexb16_to_reg8: 1382 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1383 mov.l #0xffffff01, er1 1384 set_ccr_zero 1385 ;; mov.b @(dd:16, rs.b), rd 1386 mov.b @(byte_src-1:16, r1.b), r0l ; indexed byte operand 1387 1388 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1389 test_neg_clear 1390 test_zero_clear 1391 test_ovf_clear 1392 test_carry_clear 1393 1394 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 1395 1396 test_h_gr32 0xffffff01, er1 1397 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1398 test_gr_a5a5 3 1399 test_gr_a5a5 4 1400 test_gr_a5a5 5 1401 test_gr_a5a5 6 1402 test_gr_a5a5 7 1403 1404mov_b_indexw16_to_reg8: 1405 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1406 mov.l #0xffff0002, er1 1407 set_ccr_zero 1408 ;; mov.b @(dd:16, rs.w), rd 1409 mov.b @(byte_src-2:16, r1.w), r0l ; indexed byte operand 1410 1411 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1412 test_neg_clear 1413 test_zero_clear 1414 test_ovf_clear 1415 test_carry_clear 1416 1417 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 1418 1419 test_h_gr32 0xffff0002, er1 1420 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1421 test_gr_a5a5 3 1422 test_gr_a5a5 4 1423 test_gr_a5a5 5 1424 test_gr_a5a5 6 1425 test_gr_a5a5 7 1426 1427mov_b_indexl16_to_reg8: 1428 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1429 mov.l #0x00000003, er1 1430 set_ccr_zero 1431 ;; mov.b @(dd:16, ers.l), rd 1432 mov.b @(byte_src-3:16, er1.l), r0l ; indexed byte operand 1433 1434 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1435 test_neg_clear 1436 test_zero_clear 1437 test_ovf_clear 1438 test_carry_clear 1439 1440 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 1441 1442 test_h_gr32 0x00000003, er1 1443 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1444 test_gr_a5a5 3 1445 test_gr_a5a5 4 1446 test_gr_a5a5 5 1447 test_gr_a5a5 6 1448 test_gr_a5a5 7 1449 1450mov_b_indexb32_to_reg8: 1451 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1452 mov.l #0xffffff04, er1 1453 set_ccr_zero 1454 ;; mov.b @(dd:32, rs.b), rd 1455 mov.b @(byte_src-4:32, r1.b), r0l ; indexed byte operand 1456 1457 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1458 test_neg_clear 1459 test_zero_clear 1460 test_ovf_clear 1461 test_carry_clear 1462 1463 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 1464 1465 test_h_gr32 0xffffff04 er1 1466 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1467 test_gr_a5a5 3 1468 test_gr_a5a5 4 1469 test_gr_a5a5 5 1470 test_gr_a5a5 6 1471 test_gr_a5a5 7 1472 1473mov_b_indexw32_to_reg8: 1474 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1475 mov.l #0xffff0005, er1 1476 set_ccr_zero 1477 ;; mov.b @(dd:32, rs.w), rd 1478 mov.b @(byte_src-5:32, r1.w), r0l ; indexed byte operand 1479 1480 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1481 test_neg_clear 1482 test_zero_clear 1483 test_ovf_clear 1484 test_carry_clear 1485 1486 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 1487 1488 test_h_gr32 0xffff0005 er1 1489 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1490 test_gr_a5a5 3 1491 test_gr_a5a5 4 1492 test_gr_a5a5 5 1493 test_gr_a5a5 6 1494 test_gr_a5a5 7 1495 1496mov_b_indexl32_to_reg8: 1497 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1498 mov.l #0x00000006, er1 1499 set_ccr_zero 1500 ;; mov.b @(dd:32, ers.l), rd 1501 mov.b @(byte_src-6:32, er1.l), r0l ; indexed byte operand 1502 1503 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1504 test_neg_clear 1505 test_zero_clear 1506 test_ovf_clear 1507 test_carry_clear 1508 1509 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 1510 1511 test_h_gr32 0x00000006 er1 1512 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1513 test_gr_a5a5 3 1514 test_gr_a5a5 4 1515 test_gr_a5a5 5 1516 test_gr_a5a5 6 1517 test_gr_a5a5 7 1518 1519.endif 1520 1521.if (sim_cpu == h8sx) 1522mov_b_abs8_to_reg8: 1523 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1524 mov.l #byte_src-255, er1 1525 ldc er1, sbr 1526 set_ccr_zero 1527 ;; mov.b @aa:8, rd 1528 mov.b @0xff:8, r0l ; 8-bit (sbr relative) address-direct operand 1529 1530 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1531 test_neg_clear 1532 test_zero_clear 1533 test_ovf_clear 1534 test_carry_clear 1535 1536 test_h_gr32 0xa5a5a577 er0 1537 1538 test_h_gr32 byte_src-255, er1 1539 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1540 test_gr_a5a5 3 1541 test_gr_a5a5 4 1542 test_gr_a5a5 5 1543 test_gr_a5a5 6 1544 test_gr_a5a5 7 1545.endif 1546 1547mov_b_abs16_to_reg8: 1548 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1549 set_ccr_zero 1550 1551 ;; mov.b @aa:16, rd 1552 mov.b @byte_src:16, r0l ; 16-bit address-direct operand 1553;;; .word 0x6a08 1554;;; .word @byte_src 1555 1556 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1557 test_neg_clear 1558 test_zero_clear 1559 test_ovf_clear 1560 test_carry_clear 1561 1562 test_h_gr32 0xa5a5a577 er0 1563 1564 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1565 test_gr_a5a5 2 1566 test_gr_a5a5 3 1567 test_gr_a5a5 4 1568 test_gr_a5a5 5 1569 test_gr_a5a5 6 1570 test_gr_a5a5 7 1571 1572mov_b_abs32_to_reg8: 1573 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1574 set_ccr_zero 1575 1576 ;; mov.b @aa:32, rd 1577 mov.b @byte_src:32, r0l ; 32-bit address-direct operand 1578;;; .word 0x6a28 1579;;; .long @byte_src 1580 1581 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1582 test_neg_clear 1583 test_zero_clear 1584 test_ovf_clear 1585 test_carry_clear 1586 1587 test_h_gr32 0xa5a5a577 er0 1588 1589 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1590 test_gr_a5a5 2 1591 test_gr_a5a5 3 1592 test_gr_a5a5 4 1593 test_gr_a5a5 5 1594 test_gr_a5a5 6 1595 test_gr_a5a5 7 1596 1597.if (sim_cpu == h8sx) 1598 1599 ;; 1600 ;; Move byte from memory to memory 1601 ;; 1602 1603mov_b_indirect_to_indirect: ; reg indirect, memory to memory 1604 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1605 set_ccr_zero 1606 1607 ;; mov.b @ers, @erd 1608 1609 mov.l #byte_src, er1 1610 mov.l #byte_dst, er0 1611 mov.b @er1, @er0 1612;;; .word 0x0178 1613;;; .word 0x0100 1614 1615 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1616 test_neg_clear 1617 test_zero_clear 1618 test_ovf_clear 1619 test_carry_clear 1620 1621 ;; Verify the affected registers. 1622 1623 test_h_gr32 byte_dst er0 1624 test_h_gr32 byte_src er1 1625 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1626 test_gr_a5a5 3 1627 test_gr_a5a5 4 1628 test_gr_a5a5 5 1629 test_gr_a5a5 6 1630 test_gr_a5a5 7 1631 1632 ;; Now check the result of the move to memory. 1633 cmp.b @byte_src, @byte_dst 1634 beq .Lnext55 1635 fail 1636.Lnext55: 1637 ;; Now clear the destination location, and verify that. 1638 mov.b #0, @byte_dst 1639 cmp.b @byte_src, @byte_dst 1640 bne .Lnext56 1641 fail 1642.Lnext56: ; OK, pass on. 1643 1644mov_b_postinc_to_postinc: ; reg post-increment, memory to memory 1645 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1646 set_ccr_zero 1647 1648 ;; mov.b @ers+, @erd+ 1649 1650 mov.l #byte_src, er1 1651 mov.l #byte_dst, er0 1652 mov.b @er1+, @er0+ 1653;;; .word 0x0178 1654;;; .word 0x8180 1655 1656 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1657 test_neg_clear 1658 test_zero_clear 1659 test_ovf_clear 1660 test_carry_clear 1661 1662 ;; Verify the affected registers. 1663 1664 test_h_gr32 byte_dst+1 er0 1665 test_h_gr32 byte_src+1 er1 1666 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1667 test_gr_a5a5 3 1668 test_gr_a5a5 4 1669 test_gr_a5a5 5 1670 test_gr_a5a5 6 1671 test_gr_a5a5 7 1672 1673 ;; Now check the result of the move to memory. 1674 cmp.b @byte_src, @byte_dst 1675 beq .Lnext65 1676 fail 1677.Lnext65: 1678 ;; Now clear the destination location, and verify that. 1679 mov.b #0, @byte_dst 1680 cmp.b @byte_src, @byte_dst 1681 bne .Lnext66 1682 fail 1683.Lnext66: ; OK, pass on. 1684 1685mov_b_postdec_to_postdec: ; reg post-decrement, memory to memory 1686 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1687 set_ccr_zero 1688 1689 ;; mov.b @ers-, @erd- 1690 1691 mov.l #byte_src, er1 1692 mov.l #byte_dst, er0 1693 mov.b @er1-, @er0- 1694;;; .word 0x0178 1695;;; .word 0xa1a0 1696 1697 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1698 test_neg_clear 1699 test_zero_clear 1700 test_ovf_clear 1701 test_carry_clear 1702 1703 ;; Verify the affected registers. 1704 1705 test_h_gr32 byte_dst-1 er0 1706 test_h_gr32 byte_src-1 er1 1707 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1708 test_gr_a5a5 3 1709 test_gr_a5a5 4 1710 test_gr_a5a5 5 1711 test_gr_a5a5 6 1712 test_gr_a5a5 7 1713 1714 ;; Now check the result of the move to memory. 1715 cmp.b @byte_src, @byte_dst 1716 beq .Lnext75 1717 fail 1718.Lnext75: 1719 ;; Now clear the destination location, and verify that. 1720 mov.b #0, @byte_dst 1721 cmp.b @byte_src, @byte_dst 1722 bne .Lnext76 1723 fail 1724.Lnext76: ; OK, pass on. 1725 1726mov_b_preinc_to_preinc: ; reg pre-increment, memory to memory 1727 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1728 set_ccr_zero 1729 1730 ;; mov.b @+ers, @+erd 1731 1732 mov.l #byte_src-1, er1 1733 mov.l #byte_dst-1, er0 1734 mov.b @+er1, @+er0 1735;;; .word 0x0178 1736;;; .word 0x9190 1737 1738 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1739 test_neg_clear 1740 test_zero_clear 1741 test_ovf_clear 1742 test_carry_clear 1743 1744 ;; Verify the affected registers. 1745 1746 test_h_gr32 byte_dst er0 1747 test_h_gr32 byte_src er1 1748 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1749 test_gr_a5a5 3 1750 test_gr_a5a5 4 1751 test_gr_a5a5 5 1752 test_gr_a5a5 6 1753 test_gr_a5a5 7 1754 1755 ;; Now check the result of the move to memory. 1756 cmp.b @byte_src, @byte_dst 1757 beq .Lnext85 1758 fail 1759.Lnext85: 1760 ;; Now clear the destination location, and verify that. 1761 mov.b #0, @byte_dst 1762 cmp.b @byte_src, @byte_dst 1763 bne .Lnext86 1764 fail 1765.Lnext86: ; OK, pass on. 1766 1767mov_b_predec_to_predec: ; reg pre-decrement, memory to memory 1768 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1769 set_ccr_zero 1770 1771 ;; mov.b @-ers, @-erd 1772 1773 mov.l #byte_src+1, er1 1774 mov.l #byte_dst+1, er0 1775 mov.b @-er1, @-er0 1776;;; .word 0x0178 1777;;; .word 0xb1b0 1778 1779 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1780 test_neg_clear 1781 test_zero_clear 1782 test_ovf_clear 1783 test_carry_clear 1784 1785 ;; Verify the affected registers. 1786 1787 test_h_gr32 byte_dst er0 1788 test_h_gr32 byte_src er1 1789 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1790 test_gr_a5a5 3 1791 test_gr_a5a5 4 1792 test_gr_a5a5 5 1793 test_gr_a5a5 6 1794 test_gr_a5a5 7 1795 1796 ;; Now check the result of the move to memory. 1797 cmp.b @byte_src, @byte_dst 1798 beq .Lnext95 1799 fail 1800.Lnext95: 1801 ;; Now clear the destination location, and verify that. 1802 mov.b #0, @byte_dst 1803 cmp.b @byte_src, @byte_dst 1804 bne .Lnext96 1805 fail 1806.Lnext96: ; OK, pass on. 1807 1808mov_b_disp2_to_disp2: ; reg 2-bit disp, memory to memory 1809 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1810 set_ccr_zero 1811 1812 ;; mov.b @(dd:2, ers), @(dd:2, erd) 1813 1814 mov.l #byte_src-1, er1 1815 mov.l #byte_dst-2, er0 1816 mov.b @(1:2, er1), @(2:2, er0) 1817;;; .word 0x0178 1818;;; .word 0x1120 1819 1820 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1821 test_neg_clear 1822 test_zero_clear 1823 test_ovf_clear 1824 test_carry_clear 1825 1826 ;; Verify the affected registers. 1827 1828 test_h_gr32 byte_dst-2 er0 1829 test_h_gr32 byte_src-1 er1 1830 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1831 test_gr_a5a5 3 1832 test_gr_a5a5 4 1833 test_gr_a5a5 5 1834 test_gr_a5a5 6 1835 test_gr_a5a5 7 1836 1837 ;; Now check the result of the move to memory. 1838 cmp.b @byte_src, @byte_dst 1839 beq .Lnext105 1840 fail 1841.Lnext105: 1842 ;; Now clear the destination location, and verify that. 1843 mov.b #0, @byte_dst 1844 cmp.b @byte_src, @byte_dst 1845 bne .Lnext106 1846 fail 1847.Lnext106: ; OK, pass on. 1848 1849mov_b_disp16_to_disp16: ; reg 16-bit disp, memory to memory 1850 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1851 set_ccr_zero 1852 1853 ;; mov.b @(dd:16, ers), @(dd:16, erd) 1854 1855 mov.l #byte_src-1, er1 1856 mov.l #byte_dst-2, er0 1857 mov.b @(1:16, er1), @(2:16, er0) 1858;;; .word 0x0178 1859;;; .word 0xc1c0 1860;;; .word 0x0001 1861;;; .word 0x0002 1862 1863 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1864 test_neg_clear 1865 test_zero_clear 1866 test_ovf_clear 1867 test_carry_clear 1868 1869 ;; Verify the affected registers. 1870 1871 test_h_gr32 byte_dst-2 er0 1872 test_h_gr32 byte_src-1 er1 1873 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1874 test_gr_a5a5 3 1875 test_gr_a5a5 4 1876 test_gr_a5a5 5 1877 test_gr_a5a5 6 1878 test_gr_a5a5 7 1879 1880 ;; Now check the result of the move to memory. 1881 cmp.b @byte_src, @byte_dst 1882 beq .Lnext115 1883 fail 1884.Lnext115: 1885 ;; Now clear the destination location, and verify that. 1886 mov.b #0, @byte_dst 1887 cmp.b @byte_src, @byte_dst 1888 bne .Lnext116 1889 fail 1890.Lnext116: ; OK, pass on. 1891 1892mov_b_disp32_to_disp32: ; reg 32-bit disp, memory to memory 1893 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1894 set_ccr_zero 1895 1896 ;; mov.b @(dd:32, ers), @(dd:32, erd) 1897 1898 mov.l #byte_src-1, er1 1899 mov.l #byte_dst-2, er0 1900 mov.b @(1:32, er1), @(2:32, er0) 1901;;; .word 0x0178 1902;;; .word 0xc9c8 1903;;; .long 1 1904;;; .long 2 1905 1906 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1907 test_neg_clear 1908 test_zero_clear 1909 test_ovf_clear 1910 test_carry_clear 1911 1912 ;; Verify the affected registers. 1913 1914 test_h_gr32 byte_dst-2 er0 1915 test_h_gr32 byte_src-1 er1 1916 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1917 test_gr_a5a5 3 1918 test_gr_a5a5 4 1919 test_gr_a5a5 5 1920 test_gr_a5a5 6 1921 test_gr_a5a5 7 1922 1923 ;; Now check the result of the move to memory. 1924 cmp.b @byte_src, @byte_dst 1925 beq .Lnext125 1926 fail 1927.Lnext125: 1928 ;; Now clear the destination location, and verify that. 1929 mov.b #0, @byte_dst 1930 cmp.b @byte_src, @byte_dst 1931 bne .Lnext126 1932 fail 1933.Lnext126: ; OK, pass on. 1934 1935mov_b_indexb16_to_indexb16: ; reg 16-bit indexed, memory to memory 1936 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1937 mov.l #0xffffff01, er1 1938 mov.l #0xffffff02, er0 1939 ;; mov.b @(dd:16, rs.b), @(dd:16, rd.b) 1940 set_ccr_zero 1941 mov.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r0.b) 1942 1943 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1944 test_neg_clear 1945 test_zero_clear 1946 test_ovf_clear 1947 test_carry_clear 1948 1949 ;; Verify the affected registers. 1950 1951 test_h_gr32 0xffffff02 er0 1952 test_h_gr32 0xffffff01 er1 1953 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1954 test_gr_a5a5 3 1955 test_gr_a5a5 4 1956 test_gr_a5a5 5 1957 test_gr_a5a5 6 1958 test_gr_a5a5 7 1959 1960 ;; Now check the result of the move to memory. 1961 cmp.b @byte_src, @byte_dst 1962 bne fail1 1963 ;; Now clear the destination location, and verify that. 1964 mov.b #0, @byte_dst 1965 cmp.b @byte_src, @byte_dst 1966 beq fail1 1967 1968mov_b_indexw16_to_indewb16: ; reg 16-bit indexed, memory to memory 1969 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1970 mov.l #0xffff0003, er1 1971 mov.l #0xffff0004, er0 1972 ;; mov.b @(dd:16, rs.w), @(dd:16, rd.w) 1973 set_ccr_zero 1974 mov.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r0.w) 1975 1976 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1977 test_neg_clear 1978 test_zero_clear 1979 test_ovf_clear 1980 test_carry_clear 1981 1982 ;; Verify the affected registers. 1983 1984 test_h_gr32 0xffff0004 er0 1985 test_h_gr32 0xffff0003 er1 1986 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1987 test_gr_a5a5 3 1988 test_gr_a5a5 4 1989 test_gr_a5a5 5 1990 test_gr_a5a5 6 1991 test_gr_a5a5 7 1992 1993 ;; Now check the result of the move to memory. 1994 cmp.b @byte_src, @byte_dst 1995 bne fail1 1996 ;; Now clear the destination location, and verify that. 1997 mov.b #0, @byte_dst 1998 cmp.b @byte_src, @byte_dst 1999 beq fail1 2000 2001mov_b_indexl16_to_indexl16: ; reg 16-bit indexed, memory to memory 2002 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2003 mov.l #0x00000005, er1 2004 mov.l #0x00000006, er0 2005 ;; mov.b @(dd:16, ers.l), @(dd:16, erd.l) 2006 set_ccr_zero 2007 mov.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er0.l) 2008 2009 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2010 test_neg_clear 2011 test_zero_clear 2012 test_ovf_clear 2013 test_carry_clear 2014 2015 ;; Verify the affected registers. 2016 2017 test_h_gr32 0x00000006 er0 2018 test_h_gr32 0x00000005 er1 2019 test_gr_a5a5 2 ; Make sure other general regs not disturbed 2020 test_gr_a5a5 3 2021 test_gr_a5a5 4 2022 test_gr_a5a5 5 2023 test_gr_a5a5 6 2024 test_gr_a5a5 7 2025 2026 ;; Now check the result of the move to memory. 2027 cmp.b @byte_src, @byte_dst 2028 bne fail1 2029 ;; Now clear the destination location, and verify that. 2030 mov.b #0, @byte_dst 2031 cmp.b @byte_src, @byte_dst 2032 beq fail1 2033 2034mov_b_indexb32_to_indexb32: ; reg 32-bit indexed, memory to memory 2035 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2036 mov.l #0xffffff01, er1 2037 mov.l #0xffffff02, er0 2038 set_ccr_zero 2039 ;; mov.b @(dd:32, rs.b), @(dd:32, rd.b) 2040 mov.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r0.b) 2041 2042 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2043 test_neg_clear 2044 test_zero_clear 2045 test_ovf_clear 2046 test_carry_clear 2047 2048 ;; Verify the affected registers. 2049 2050 test_h_gr32 0xffffff02 er0 2051 test_h_gr32 0xffffff01 er1 2052 test_gr_a5a5 2 ; Make sure other general regs not disturbed 2053 test_gr_a5a5 3 2054 test_gr_a5a5 4 2055 test_gr_a5a5 5 2056 test_gr_a5a5 6 2057 test_gr_a5a5 7 2058 2059 ;; Now check the result of the move to memory. 2060 cmp.b @byte_src, @byte_dst 2061 bne fail1 2062 ;; Now clear the destination location, and verify that. 2063 mov.b #0, @byte_dst 2064 cmp.b @byte_src, @byte_dst 2065 beq fail1 2066 2067mov_b_indexw32_to_indexw32: ; reg 32-bit indexed, memory to memory 2068 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2069 mov.l #0xffff0003, er1 2070 mov.l #0xffff0004, er0 2071 set_ccr_zero 2072 ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) 2073 mov.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r0.w) 2074 2075 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2076 test_neg_clear 2077 test_zero_clear 2078 test_ovf_clear 2079 test_carry_clear 2080 2081 ;; Verify the affected registers. 2082 2083 test_h_gr32 0xffff0004 er0 2084 test_h_gr32 0xffff0003 er1 2085 test_gr_a5a5 2 ; Make sure other general regs not disturbed 2086 test_gr_a5a5 3 2087 test_gr_a5a5 4 2088 test_gr_a5a5 5 2089 test_gr_a5a5 6 2090 test_gr_a5a5 7 2091 2092 ;; Now check the result of the move to memory. 2093 cmp.b @byte_src, @byte_dst 2094 bne fail1 2095 ;; Now clear the destination location, and verify that. 2096 mov.b #0, @byte_dst 2097 cmp.b @byte_src, @byte_dst 2098 beq fail1 2099 2100mov_b_indexl32_to_indexl32: ; reg 32-bit indexed, memory to memory 2101 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2102 mov.l #0x00000005, er1 2103 mov.l #0x00000006, er0 2104 set_ccr_zero 2105 ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) 2106 mov.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er0.l) 2107 2108 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2109 test_neg_clear 2110 test_zero_clear 2111 test_ovf_clear 2112 test_carry_clear 2113 2114 ;; Verify the affected registers. 2115 2116 test_h_gr32 0x00000006 er0 2117 test_h_gr32 0x00000005 er1 2118 test_gr_a5a5 2 ; Make sure other general regs not disturbed 2119 test_gr_a5a5 3 2120 test_gr_a5a5 4 2121 test_gr_a5a5 5 2122 test_gr_a5a5 6 2123 test_gr_a5a5 7 2124 2125 ;; Now check the result of the move to memory. 2126 cmp.b @byte_src, @byte_dst 2127 bne fail1 2128 ;; Now clear the destination location, and verify that. 2129 mov.b #0, @byte_dst 2130 cmp.b @byte_src, @byte_dst 2131 beq fail1 2132 2133mov_b_abs16_to_abs16: ; 16-bit absolute addr, memory to memory 2134 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2135 set_ccr_zero 2136 2137 ;; mov.b @aa:16, @aa:16 2138 2139 mov.b @byte_src:16, @byte_dst:16 2140;;; .word 0x0178 2141;;; .word 0x4040 2142;;; .word @byte_src 2143;;; .word @byte_dst 2144 2145 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2146 test_neg_clear 2147 test_zero_clear 2148 test_ovf_clear 2149 test_carry_clear 2150 2151 2152 test_gr_a5a5 0 ; Make sure *NO* general registers are changed 2153 test_gr_a5a5 1 2154 test_gr_a5a5 2 2155 test_gr_a5a5 3 2156 test_gr_a5a5 4 2157 test_gr_a5a5 5 2158 test_gr_a5a5 6 2159 test_gr_a5a5 7 2160 2161 ;; Now check the result of the move to memory. 2162 cmp.b @byte_src, @byte_dst 2163 beq .Lnext135 2164 fail 2165.Lnext135: 2166 ;; Now clear the destination location, and verify that. 2167 mov.b #0, @byte_dst 2168 cmp.b @byte_src, @byte_dst 2169 bne .Lnext136 2170 fail 2171.Lnext136: ; OK, pass on. 2172 2173mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory 2174 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2175 set_ccr_zero 2176 2177 ;; mov.b @aa:32, @aa:32 2178 2179 mov.b @byte_src:32, @byte_dst:32 2180;;; .word 0x0178 2181;;; .word 0x4848 2182;;; .long @byte_src 2183;;; .long @byte_dst 2184 2185 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2186 test_neg_clear 2187 test_zero_clear 2188 test_ovf_clear 2189 test_carry_clear 2190 2191 test_gr_a5a5 0 ; Make sure *NO* general registers are changed 2192 test_gr_a5a5 1 2193 test_gr_a5a5 2 2194 test_gr_a5a5 3 2195 test_gr_a5a5 4 2196 test_gr_a5a5 5 2197 test_gr_a5a5 6 2198 test_gr_a5a5 7 2199 2200 ;; Now check the result of the move to memory. 2201 cmp.b @byte_src, @byte_dst 2202 beq .Lnext145 2203 fail 2204.Lnext145: 2205 ;; Now clear the destination location, and verify that. 2206 mov.b #0, @byte_dst 2207 cmp.b @byte_src, @byte_dst 2208 bne .Lnext146 2209 fail 2210.Lnext146: ; OK, pass on. 2211 2212 2213.endif 2214 2215 pass 2216 2217 exit 0 2218 2219fail1: 2220 fail 2221