1/* frv simulator support code
2   Copyright (C) 1998, 2000, 2001, 2007, 2008, 2009, 2010, 2011
3   Free Software Foundation, Inc.
4   Contributed by Red Hat.
5
6This file is part of the GNU simulators.
7
8This program is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 3 of the License, or
11(at your option) any later version.
12
13This program is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
21/* Main header for the frv.  */
22
23#define USING_SIM_BASE_H /* FIXME: quick hack */
24
25struct _sim_cpu; /* FIXME: should be in sim-basics.h */
26typedef struct _sim_cpu SIM_CPU;
27
28/* Set the mask of unsupported traces.  */
29#define WITH_TRACE \
30  (~(TRACE_alu | TRACE_decode | TRACE_memory | TRACE_model | TRACE_fpu \
31     | TRACE_branch | TRACE_debug))
32
33/* sim-basics.h includes config.h but cgen-types.h must be included before
34   sim-basics.h and cgen-types.h needs config.h.  */
35#include "config.h"
36
37#include "symcat.h"
38#include "sim-basics.h"
39#include "cgen-types.h"
40#include "frv-desc.h"
41#include "frv-opc.h"
42#include "arch.h"
43
44/* These must be defined before sim-base.h.  */
45typedef USI sim_cia;
46
47#define CIA_GET(cpu)     CPU_PC_GET (cpu)
48#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
49
50void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia);
51#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \
52  frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA))
53
54#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) 0
55
56#include "sim-base.h"
57#include "cgen-sim.h"
58#include "frv-sim.h"
59#include "cache.h"
60#include "registers.h"
61#include "profile.h"
62
63/* The _sim_cpu struct.  */
64
65struct _sim_cpu {
66  /* sim/common cpu base.  */
67  sim_cpu_base base;
68
69  /* Static parts of cgen.  */
70  CGEN_CPU cgen_cpu;
71
72  /* CPU specific parts go here.
73     Note that in files that don't need to access these pieces WANT_CPU_FOO
74     won't be defined and thus these parts won't appear.  This is ok in the
75     sense that things work.  It is a source of bugs though.
76     One has to of course be careful to not take the size of this
77     struct and no structure members accessed in non-cpu specific files can
78     go after here.  Oh for a better language.  */
79#if defined (WANT_CPU_FRVBF)
80  FRVBF_CPU_DATA cpu_data;
81
82  /* Control information for registers */
83  FRV_REGISTER_CONTROL register_control;
84#define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control)
85
86  FRV_VLIW vliw;
87#define CPU_VLIW(cpu) (& (cpu)->vliw)
88
89  FRV_CACHE insn_cache;
90#define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache)
91
92  FRV_CACHE data_cache;
93#define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache)
94
95  FRV_PROFILE_STATE profile_state;
96#define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state)
97
98  int debug_state;
99#define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state)
100
101  SI load_address;
102#define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address)
103
104  SI load_length;
105#define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length)
106
107  SI load_flag;
108#define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag)
109#define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag)
110
111  SI store_flag;
112#define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag)
113
114  unsigned long elf_flags;
115#define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags)
116#endif /* defined (WANT_CPU_FRVBF) */
117};
118
119/* The sim_state struct.  */
120
121struct sim_state {
122  sim_cpu *cpu;
123#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
124
125  CGEN_STATE cgen_state;
126
127  sim_state_base base;
128};
129
130/* Misc.  */
131
132/* Catch address exceptions.  */
133extern SIM_CORE_SIGNAL_FN frv_core_signal;
134#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
135frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
136		  (TRANSFER), (ERROR))
137
138/* Default memory size.  */
139#define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */
140