1/* CPU support. 2 Copyright (C) 1998, 2007, 2008, 2009, 2010, 2011 3 Free Software Foundation, Inc. 4 Contributed by Cygnus Solutions. 5 6This file is part of GDB, the GNU debugger. 7 8This program is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 3 of the License, or 11(at your option) any later version. 12 13This program is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21/* This file is intended to be included by sim-base.h. 22 23 This file provides an interface between the simulator framework and 24 the selected cpu. */ 25 26#ifndef SIM_CPU_H 27#define SIM_CPU_H 28 29/* Type of function to return an insn name. */ 30typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int); 31 32/* Types for register access functions. 33 These routines implement the sim_{fetch,store}_register interface. */ 34typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int); 35typedef int (CPUREG_STORE_FN) (sim_cpu *, int, unsigned char *, int); 36 37/* Types for PC access functions. 38 Some simulators require a functional interface to access the program 39 counter [a macro is insufficient as the PC is kept in a cpu-specific part 40 of the sim_cpu struct]. */ 41typedef sim_cia (PC_FETCH_FN) (sim_cpu *); 42typedef void (PC_STORE_FN) (sim_cpu *, sim_cia); 43 44/* Pseudo baseclass for each cpu. */ 45 46typedef struct { 47 48 /* Backlink to main state struct. */ 49 SIM_DESC state; 50#define CPU_STATE(cpu) ((cpu)->base.state) 51 52 /* Processor index within the SD_DESC */ 53 int index; 54#define CPU_INDEX(cpu) ((cpu)->base.index) 55 56 /* The name of the cpu. */ 57 const char *name; 58#define CPU_NAME(cpu) ((cpu)->base.name) 59 60 /* Options specific to this cpu. */ 61 struct option_list *options; 62#define CPU_OPTIONS(cpu) ((cpu)->base.options) 63 64 /* Processor specific core data */ 65 sim_cpu_core core; 66#define CPU_CORE(cpu) (& (cpu)->base.core) 67 68 /* Number of instructions (used to iterate over CPU_INSN_NAME). */ 69 unsigned int max_insns; 70#define CPU_MAX_INSNS(cpu) ((cpu)->base.max_insns) 71 72 /* Function to return the name of an insn. */ 73 CPU_INSN_NAME_FN *insn_name; 74#define CPU_INSN_NAME(cpu) ((cpu)->base.insn_name) 75 76 /* Trace data. See sim-trace.h. */ 77 TRACE_DATA trace_data; 78#define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data) 79 80 /* Maximum number of debuggable entities. 81 This debugging is not intended for normal use. 82 It is only enabled when the simulator is configured with --with-debug 83 which shouldn't normally be specified. */ 84#ifndef MAX_DEBUG_VALUES 85#define MAX_DEBUG_VALUES 4 86#endif 87 88 /* Boolean array of specified debugging flags. */ 89 char debug_flags[MAX_DEBUG_VALUES]; 90#define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags) 91 /* Standard values. */ 92#define DEBUG_INSN_IDX 0 93#define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */ 94 95 /* Debugging output goes to this or stderr if NULL. 96 We can't store `stderr' here as stderr goes through a callback. */ 97 FILE *debug_file; 98#define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file) 99 100 /* Profile data. See sim-profile.h. */ 101 PROFILE_DATA profile_data; 102#define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data) 103 104#ifdef SIM_HAVE_MODEL 105 /* Machine tables for this cpu. See sim-model.h. */ 106 const MACH *mach; 107#define CPU_MACH(cpu) ((cpu)->base.mach) 108 /* The selected model. */ 109 const MODEL *model; 110#define CPU_MODEL(cpu) ((cpu)->base.model) 111 /* Model data (profiling state, etc.). */ 112 void *model_data; 113#define CPU_MODEL_DATA(cpu) ((cpu)->base.model_data) 114#endif 115 116 /* Routines to fetch/store registers. */ 117 CPUREG_FETCH_FN *reg_fetch; 118#define CPU_REG_FETCH(c) ((c)->base.reg_fetch) 119 CPUREG_STORE_FN *reg_store; 120#define CPU_REG_STORE(c) ((c)->base.reg_store) 121 PC_FETCH_FN *pc_fetch; 122#define CPU_PC_FETCH(c) ((c)->base.pc_fetch) 123 PC_STORE_FN *pc_store; 124#define CPU_PC_STORE(c) ((c)->base.pc_store) 125 126} sim_cpu_base; 127 128/* Create all cpus. */ 129extern SIM_RC sim_cpu_alloc_all (SIM_DESC, int, int); 130/* Create a cpu. */ 131extern sim_cpu *sim_cpu_alloc (SIM_DESC, int); 132/* Release resources held by all cpus. */ 133extern void sim_cpu_free_all (SIM_DESC); 134/* Release resources held by a cpu. */ 135extern void sim_cpu_free (sim_cpu *); 136 137/* Return a pointer to the cpu data for CPU_NAME, or NULL if not found. */ 138extern sim_cpu *sim_cpu_lookup (SIM_DESC, const char *); 139 140/* Return prefix to use in cpu specific messages. */ 141extern const char *sim_cpu_msg_prefix (sim_cpu *); 142/* Cover fn to sim_io_eprintf. */ 143extern void sim_io_eprintf_cpu (sim_cpu *, const char *, ...); 144 145/* Get/set a pc value. */ 146#define CPU_PC_GET(cpu) ((* CPU_PC_FETCH (cpu)) (cpu)) 147#define CPU_PC_SET(cpu,newval) ((* CPU_PC_STORE (cpu)) ((cpu), (newval))) 148/* External interface to accessing the pc. */ 149sim_cia sim_pc_get (sim_cpu *); 150void sim_pc_set (sim_cpu *, sim_cia); 151 152#endif /* SIM_CPU_H */ 153