1/* General Cpu tools GENerated simulator support. 2 Copyright (C) 1996, 1997, 1998, 1999, 2007, 2008, 2009, 2010, 2011 3 Free Software Foundation, Inc. 4 Contributed by Cygnus Support. 5 6This file is part of GDB, the GNU debugger. 7 8This program is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 3 of the License, or 11(at your option) any later version. 12 13This program is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21#ifndef CGEN_DEFS_H 22#define CGEN_DEFS_H 23 24/* Compute number of longs required to hold N bits. */ 25#define HOST_LONGS_FOR_BITS(n) \ 26 (((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8) 27 28/* Forward decls. Defined in the machine generated files. */ 29 30/* This holds the contents of the extracted insn. 31 There are a few common entries (e.g. pc address), and then one big 32 union with an entry for each of the instruction formats. */ 33typedef struct argbuf ARGBUF; 34 35/* ARGBUF accessors. */ 36#define ARGBUF_ADDR(abuf) ((abuf)->addr) 37#define ARGBUF_IDESC(abuf) ((abuf)->idesc) 38#define ARGBUF_TRACE_P(abuf) ((abuf)->trace_p) 39#define ARGBUF_PROFILE_P(abuf) ((abuf)->profile_p) 40 41/* This is one ARGBUF plus whatever else is needed for WITH_SCACHE support. 42 At present there is nothing else, but it also provides a level of 43 abstraction. */ 44typedef struct scache SCACHE; 45 46/* This is a union with one entry for each instruction format. 47 Each entry contains all of the non-constant inputs of the instruction 48 in the case of read-before-exec support, or all outputs of the instruction 49 in the case of write-after-exec support. */ 50typedef struct parexec PAREXEC; 51 52/* An "Instruction DESCriptor". 53 This is the main handle on an instruction for the simulator. */ 54typedef struct idesc IDESC; 55 56/* Engine support. 57 ??? This is here because it's needed before eng.h (built by genmloop.sh) 58 which is needed before cgen-engine.h and cpu.h. 59 ??? This depends on a cpu family specific type, IADDR, but no machine 60 generated headers will have been included yet. sim/common currently 61 requires the typedef of sim_cia in sim-main.h between the inclusion of 62 sim-basics.h and sim-base.h so this is no different. */ 63 64/* SEM_ARG is intended to hide whether or not the scache is in use from the 65 semantic routines. In reality for the with-extraction case it is always 66 an SCACHE * even when not using the SCACHE since there's no current win to 67 making it something else ("not using the SCACHE" is like having a cache 68 size of 1). 69 The without-extraction case still uses an ARGBUF: 70 - consistency with scache version 71 - still need to record which operands are written 72 This wouldn't be needed if modeling was done in the semantic routines 73 but this isn't as general as handling it outside of the semantic routines. 74 For example Shade allows calling user-supplied code before/after each 75 instruction and this is something that is being planned. 76 ??? There is still some clumsiness in how much of ARGBUF to use. */ 77typedef SCACHE *SEM_ARG; 78 79/* instruction address 80 ??? This was intended to be a struct of two elements in the WITH_SCACHE_PBB 81 case. The first element is the IADDR, the second element is the SCACHE *. 82 Haven't found the time yet to make this work, but it seemed a nicer approach 83 than the current br_cache stuff. */ 84typedef IADDR PCADDR; 85 86/* Current instruction address, used by common. */ 87typedef IADDR CIA; 88 89/* Semantic routines' version of the PC. */ 90#if WITH_SCACHE_PBB 91typedef SCACHE *SEM_PC; 92#else 93typedef IADDR SEM_PC; 94#endif 95 96/* Kinds of branches. */ 97typedef enum { 98 SEM_BRANCH_UNTAKEN, 99 /* Branch to an uncacheable address (e.g. j reg). */ 100 SEM_BRANCH_UNCACHEABLE, 101 /* Branch to a cacheable (fixed) address. */ 102 SEM_BRANCH_CACHEABLE 103} SEM_BRANCH_TYPE; 104 105/* Virtual insn support. */ 106 107/* Opcode table for virtual insns (only used by the simulator). */ 108extern const CGEN_INSN cgen_virtual_insn_table[]; 109 110/* -ve of indices of virtual insns in cgen_virtual_insn_table. */ 111typedef enum { 112 VIRTUAL_INSN_X_INVALID = 0, 113 VIRTUAL_INSN_X_BEFORE = -1, VIRTUAL_INSN_X_AFTER = -2, 114 VIRTUAL_INSN_X_BEGIN = -3, 115 VIRTUAL_INSN_X_CHAIN= -4, VIRTUAL_INSN_X_CTI_CHAIN = -5 116} CGEN_INSN_VIRTUAL_TYPE; 117 118/* Return non-zero if CGEN_INSN* INSN is a virtual insn. */ 119#define CGEN_INSN_VIRTUAL_P(insn) \ 120 CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_VIRTUAL) 121 122/* GNU C's "computed goto" facility is used to speed things up where 123 possible. These macros provide a portable way to use them. 124 Nesting of these switch statements is done by providing an extra argument 125 that distinguishes them. `N' can be a number or symbol. 126 Variable `labels_##N' must be initialized with the labels of each case. */ 127 128#ifdef __GNUC__ 129#define SWITCH(N, X) goto *X; 130#define CASE(N, X) case_##N##_##X 131#define BREAK(N) goto end_switch_##N 132#define DEFAULT(N) default_##N 133#define ENDSWITCH(N) end_switch_##N:; 134#else 135#define SWITCH(N, X) switch (X) 136#define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */ 137#define BREAK(N) break 138#define DEFAULT(N) default 139#define ENDSWITCH(N) 140#endif 141 142/* Simulator state. */ 143 144/* Records simulator descriptor so utilities like @cpu@_dump_regs can be 145 called from gdb. */ 146extern SIM_DESC current_state; 147 148/* Simulator state. */ 149 150/* CGEN_STATE contains additional state information not present in 151 sim_state_base. */ 152 153typedef struct cgen_state { 154 /* FIXME: Moved to sim_state_base. */ 155 /* argv, env */ 156 char **argv; 157#define STATE_ARGV(s) ((s) -> cgen_state.argv) 158 /* FIXME: Move to sim_state_base. */ 159 char **envp; 160#define STATE_ENVP(s) ((s) -> cgen_state.envp) 161 162 /* Non-zero if no tracing or profiling is selected. */ 163 int run_fast_p; 164#define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p) 165} CGEN_STATE; 166 167/* Various utilities. */ 168 169/* Called after sim_post_argv_init to do any cgen initialization. */ 170extern void cgen_init (SIM_DESC); 171 172/* Return the name of an insn. */ 173extern CPU_INSN_NAME_FN cgen_insn_name; 174 175/* Return the maximum number of extra bytes required for a sim_cpu struct. */ 176/* ??? Ok, yes, this is less pretty than it should be. Give me a better 177 language [or suggest a better way]. */ 178extern int cgen_cpu_max_extra_bytes (void); 179 180/* Target supplied routine to process an invalid instruction. */ 181extern SEM_PC sim_engine_invalid_insn (SIM_CPU *, IADDR, SEM_PC); 182 183#endif /* CGEN_DEFS_H */ 184