1139790Simp/* Blackfin Core Event Controller (CEC) model. 266458Sdfr 366458Sdfr Copyright (C) 2010-2011 Free Software Foundation, Inc. 466458Sdfr Contributed by Analog Devices, Inc. 566458Sdfr 666458Sdfr This file is part of simulators. 766458Sdfr 866458Sdfr This program is free software; you can redistribute it and/or modify 966458Sdfr it under the terms of the GNU General Public License as published by 1066458Sdfr the Free Software Foundation; either version 3 of the License, or 1166458Sdfr (at your option) any later version. 1266458Sdfr 1366458Sdfr This program is distributed in the hope that it will be useful, 1466458Sdfr but WITHOUT ANY WARRANTY; without even the implied warranty of 1566458Sdfr MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1666458Sdfr GNU General Public License for more details. 1766458Sdfr 1866458Sdfr You should have received a copy of the GNU General Public License 1966458Sdfr along with this program. If not, see <http://www.gnu.org/licenses/>. */ 2066458Sdfr 2166458Sdfr#ifndef DV_BFIN_CEC_H 2266458Sdfr#define DV_BFIN_CEC_H 2366458Sdfr 2466458Sdfr#include "sim-main.h" 2566458Sdfr 2666458Sdfr#define BFIN_COREMMR_CEC_BASE 0xFFE02100 2766458Sdfr#define BFIN_COREMMR_CEC_SIZE (4 * 5) 2866458Sdfr 2966458Sdfr/* 0xFFE02100 ... 0xFFE02110 */ 3066458Sdfr#define BFIN_COREMMR_EVT_OVERRIDE (BFIN_COREMMR_CEC_BASE + (4 * 0)) 3166458Sdfr#define BFIN_COREMMR_IMASK (BFIN_COREMMR_CEC_BASE + (4 * 1)) 3266458Sdfr#define BFIN_COREMMR_IPEND (BFIN_COREMMR_CEC_BASE + (4 * 2)) 3366458Sdfr#define BFIN_COREMMR_ILAT (BFIN_COREMMR_CEC_BASE + (4 * 3)) 3466458Sdfr#define BFIN_COREMMR_IPRIO (BFIN_COREMMR_CEC_BASE + (4 * 4)) 3566458Sdfr 3666458Sdfr#define IVG_EMU 0 3766458Sdfr#define IVG_RST 1 3866458Sdfr#define IVG_NMI 2 3966458Sdfr#define IVG_EVX 3 4066458Sdfr#define IVG_IRPTEN 4 /* Global is Reserved */ 4166458Sdfr#define IVG_IVHW 5 4266458Sdfr#define IVG_IVTMR 6 4366458Sdfr#define IVG7 7 4466458Sdfr#define IVG8 8 4566458Sdfr#define IVG9 9 4666458Sdfr#define IVG10 10 4766458Sdfr#define IVG11 11 4866458Sdfr#define IVG12 12 49132378Salc#define IVG13 13 50132378Salc#define IVG14 14 51135590Smarcel#define IVG15 15 5283900Sdfr#define IVG_USER 16 /* Not real; for internal use */ 5366458Sdfr 5466458Sdfr#define IVG_EMU_B (1 << IVG_EMU) 5566458Sdfr#define IVG_RST_B (1 << IVG_RST) 5685142Sdfr#define IVG_NMI_B (1 << IVG_NMI) 5785142Sdfr#define IVG_EVX_B (1 << IVG_EVX) 5885142Sdfr#define IVG_IRPTEN_B (1 << IVG_IRPTEN) 5985142Sdfr#define IVG_IVHW_B (1 << IVG_IVHW) 6085142Sdfr#define IVG_IVTMR_B (1 << IVG_IVTMR) 61153179Sjhb#define IVG7_B (1 << IVG7) 6266458Sdfr#define IVG8_B (1 << IVG8) 6366458Sdfr#define IVG9_B (1 << IVG9) 6466458Sdfr#define IVG10_B (1 << IVG10) 6566458Sdfr#define IVG11_B (1 << IVG11) 6666458Sdfr#define IVG12_B (1 << IVG12) 6766458Sdfr#define IVG13_B (1 << IVG13) 6866458Sdfr#define IVG14_B (1 << IVG14) 6966458Sdfr#define IVG15_B (1 << IVG15) 7066458Sdfr#define IVG_UNMASKABLE_B \ 7166458Sdfr (IVG_EMU_B | IVG_RST_B | IVG_NMI_B | IVG_EVX_B | IVG_IRPTEN_B) 7266458Sdfr#define IVG_MASKABLE_B \ 7366458Sdfr (IVG_IVHW_B | IVG_IVTMR_B | IVG7_B | IVG8_B | IVG9_B | \ 7466458Sdfr IVG10_B | IVG11_B | IVG12_B | IVG13_B | IVG14_B | IVG15_B) 7566458Sdfr 76132378Salc#define VEC_SYS 0x0 7766458Sdfr#define VEC_EXCPT01 0x1 7886213Sdfr#define VEC_EXCPT02 0x2 7966458Sdfr#define VEC_EXCPT03 0x3 8066458Sdfr#define VEC_EXCPT04 0x4 8166458Sdfr#define VEC_EXCPT05 0x5 8266458Sdfr#define VEC_EXCPT06 0x6 8366458Sdfr#define VEC_EXCPT07 0x7 8466458Sdfr#define VEC_EXCPT08 0x8 8566458Sdfr#define VEC_EXCPT09 0x9 8695710Speter#define VEC_EXCPT10 0xa 8795710Speter#define VEC_EXCPT11 0xb 88132378Salc#define VEC_EXCPT12 0xc 89132378Salc#define VEC_EXCPT13 0xd 90132378Salc#define VEC_EXCPT14 0xe 91132378Salc#define VEC_EXCPT15 0xf 92132378Salc#define VEC_STEP 0x10 /* single step */ 93132378Salc#define VEC_OVFLOW 0x11 /* trace buffer overflow */ 94132378Salc#define VEC_UNDEF_I 0x21 /* undefined instruction */ 95132378Salc#define VEC_ILGAL_I 0x22 /* illegal instruction combo (multi-issue) */ 96132378Salc#define VEC_CPLB_VL 0x23 /* DCPLB protection violation */ 97132378Salc#define VEC_MISALI_D 0x24 /* unaligned data access */ 98132378Salc#define VEC_UNCOV 0x25 /* unrecoverable event (double fault) */ 9966458Sdfr#define VEC_CPLB_M 0x26 /* DCPLB miss */ 10066458Sdfr#define VEC_CPLB_MHIT 0x27 /* multiple DCPLB hit */ 10166458Sdfr#define VEC_WATCH 0x28 /* watchpoint match */ 10266458Sdfr#define VEC_ISTRU_VL 0x29 /* ADSP-BF535 only */ 103164250Sru#define VEC_MISALI_I 0x2a /* unaligned instruction access */ 10466458Sdfr#define VEC_CPLB_I_VL 0x2b /* ICPLB protection violation */ 10566458Sdfr#define VEC_CPLB_I_M 0x2c /* ICPLB miss */ 10666458Sdfr#define VEC_CPLB_I_MHIT 0x2d /* multiple ICPLB hit */ 10766458Sdfr#define VEC_ILL_RES 0x2e /* illegal supervisor resource */ 10866458Sdfr/* 10966458Sdfr * The hardware reserves 63+ for future use - we use it to tell our 11066458Sdfr * normal exception handling code we have a hardware error 11166458Sdfr */ 11266458Sdfr#define VEC_HWERR 63 11366458Sdfr#define VEC_SIM_BASE 64 11466458Sdfr#define VEC_SIM_HLT (VEC_SIM_BASE + 1) 11566458Sdfr#define VEC_SIM_ABORT (VEC_SIM_BASE + 2) 11666458Sdfr#define VEC_SIM_TRAP (VEC_SIM_BASE + 3) 11766458Sdfr#define VEC_SIM_DBGA (VEC_SIM_BASE + 4) 118149777Smarcelextern void cec_exception (SIM_CPU *, int vec_excp); 119149777Smarcel 120149777Smarcel#define HWERR_SYSTEM_MMR 0x02 121195649Salc#define HWERR_EXTERN_ADDR 0x03 122130965Salc#define HWERR_PERF_FLOW 0x12 123195649Salc#define HWERR_RAISE_5 0x18 124161223Sjhbextern void cec_hwerr (SIM_CPU *, int hwerr); 125161223Sjhbextern void cec_latch (SIM_CPU *, int ivg); 126130965Salcextern void cec_return (SIM_CPU *, int ivg); 12792843Salfred 128200200Smarcelextern int cec_get_ivg (SIM_CPU *); 12992843Salfredextern bool cec_is_supervisor_mode (SIM_CPU *); 130112312Sjakeextern bool cec_is_user_mode (SIM_CPU *); 131113831Smarcelextern void cec_require_supervisor (SIM_CPU *); 132112312Sjake 13392843Salfredextern bu32 cec_cli (SIM_CPU *); 13492843Salfredextern void cec_sti (SIM_CPU *, bu32 ints); 135203883Smarcel 13692843Salfredextern void cec_push_reti (SIM_CPU *); 13792843Salfredextern void cec_pop_reti (SIM_CPU *); 13892843Salfred 13992843Salfred#endif 140115148Smarcel