1/* d10v.h -- Header file for D10V opcode table 2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2010 3 Free Software Foundation, Inc. 4 Written by Martin Hunt (hunt@cygnus.com), Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 3, 11 or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING3. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23#ifndef D10V_H 24#define D10V_H 25 26/* Format Specifier */ 27#define FM00 0 28#define FM01 0x40000000 29#define FM10 0x80000000 30#define FM11 0xC0000000 31 32#define NOP 0x5e00 33#define OPCODE_DIVS 0x14002800 34 35/* The opcode table is an array of struct d10v_opcode. */ 36 37struct d10v_opcode 38{ 39 /* The opcode name. */ 40 const char *name; 41 42 /* the opcode format */ 43 int format; 44 45 /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ 46#define SHORT_OPCODE 1 47#define LONG_OPCODE 8 48#define SHORT_2 1 /* short with 2 operands */ 49#define SHORT_B 3 /* short with 8-bit branch */ 50#define LONG_B 8 /* long with 16-bit branch */ 51#define LONG_L 10 /* long with 3 operands */ 52#define LONG_R 12 /* reserved */ 53 54 /* just a placeholder for variable-length instructions */ 55 /* for example, "bra" will be a fake for "bra.s" and bra.l" */ 56 /* which will immediately follow in the opcode table. */ 57#define OPCODE_FAKE 32 58 59 /* the number of cycles */ 60 int cycles; 61 62 /* the execution unit(s) used */ 63 int unit; 64#define EITHER 0 65#define IU 1 66#define MU 2 67#define BOTH 3 68 69 /* execution type; parallel or sequential */ 70 /* this field is used to decide if two instructions */ 71 /* can be executed in parallel */ 72 int exec_type; 73#define PARONLY 1 /* parallel only */ 74#define SEQ 2 /* must be sequential */ 75#define PAR 4 /* may be parallel */ 76#define BRANCH_LINK 8 /* subroutine call. must be aligned */ 77#define RMEM 16 /* reads memory */ 78#define WMEM 32 /* writes memory */ 79#define RF0 64 /* reads f0 */ 80#define WF0 128 /* modifies f0 */ 81#define WCAR 256 /* write Carry */ 82#define BRANCH 512 /* branch, no link */ 83#define ALONE 1024 /* short but pack with a NOP if on asm line alone */ 84 85 /* the opcode */ 86 long opcode; 87 88 /* mask. if( (i & mask) == opcode ) then match */ 89 long mask; 90 91 /* An array of operand codes. Each code is an index into the 92 operand table. They appear in the order which the operands must 93 appear in assembly code, and are terminated by a zero. */ 94 unsigned char operands[6]; 95}; 96 97/* The table itself is sorted by major opcode number, and is otherwise 98 in the order in which the disassembler should consider 99 instructions. */ 100extern const struct d10v_opcode d10v_opcodes[]; 101extern const int d10v_num_opcodes; 102 103/* The operands table is an array of struct d10v_operand. */ 104struct d10v_operand 105{ 106 /* The number of bits in the operand. */ 107 int bits; 108 109 /* How far the operand is left shifted in the instruction. */ 110 int shift; 111 112 /* One bit syntax flags. */ 113 int flags; 114}; 115 116/* Elements in the table are retrieved by indexing with values from 117 the operands field of the d10v_opcodes table. */ 118 119extern const struct d10v_operand d10v_operands[]; 120 121/* Values defined for the flags field of a struct d10v_operand. */ 122 123/* the operand must be an even number */ 124#define OPERAND_EVEN (1) 125 126/* the operand must be an odd number */ 127#define OPERAND_ODD (2) 128 129/* this is the destination register; it will be modified */ 130/* this is used by the optimizer */ 131#define OPERAND_DEST (4) 132 133/* number or symbol */ 134#define OPERAND_NUM (8) 135 136/* address or label */ 137#define OPERAND_ADDR (0x10) 138 139/* register */ 140#define OPERAND_REG (0x20) 141 142/* postincrement + */ 143#define OPERAND_PLUS (0x40) 144 145/* postdecrement - */ 146#define OPERAND_MINUS (0x80) 147 148/* @ */ 149#define OPERAND_ATSIGN (0x100) 150 151/* @( */ 152#define OPERAND_ATPAR (0x200) 153 154/* accumulator 0 */ 155#define OPERAND_ACC0 (0x400) 156 157/* accumulator 1 */ 158#define OPERAND_ACC1 (0x800) 159 160/* f0 / f1 flag register */ 161#define OPERAND_FFLAG (0x1000) 162 163/* c flag register */ 164#define OPERAND_CFLAG (0x2000) 165 166/* control register */ 167#define OPERAND_CONTROL (0x4000) 168 169/* predecrement mode '@-sp' */ 170#define OPERAND_ATMINUS (0x8000) 171 172/* signed number */ 173#define OPERAND_SIGNED (0x10000) 174 175/* special accumulator shifts need a 4-bit number */ 176/* 1 <= x <= 16 */ 177#define OPERAND_SHIFT (0x20000) 178 179/* general purpose register */ 180#define OPERAND_GPR (0x40000) 181 182/* special imm3 values with range restricted to -2 <= imm3 <= 3 */ 183/* needed for rac/rachi */ 184#define RESTRICTED_NUM3 (0x80000) 185 186/* Pre-decrement is only supported for SP. */ 187#define OPERAND_SP (0x100000) 188 189/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and 190 unlike OPERAND_SP, this flag doesn't prevent the instruction from 191 matching, it only fails validation later on. */ 192#define OPERAND_NOSP (0x200000) 193 194/* Structure to hold information about predefined registers. */ 195struct pd_reg 196{ 197 char *name; /* name to recognize */ 198 char *pname; /* name to print for this register */ 199 int value; 200}; 201 202extern const struct pd_reg d10v_predefined_registers[]; 203int d10v_reg_name_cnt (void); 204 205/* an expressionS only has one register type, so we fake it */ 206/* by setting high bits to indicate type */ 207#define REGISTER_MASK 0xFF 208 209#endif /* D10V_H */ 210