1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
2
3   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
4   2009, 2010, 2011 Free Software Foundation, Inc.
5
6   This file is part of GDB.
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 3 of the License, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
21#include "defs.h"
22#include "inferior.h"
23#include "gdbcore.h"
24#include "arch-utils.h"
25#include "floatformat.h"
26#include "gdbtypes.h"
27#include "regcache.h"
28#include "reggroups.h"
29#include "frame.h"
30#include "frame-base.h"
31#include "frame-unwind.h"
32#include "doublest.h"
33#include "value.h"
34#include "gdb_assert.h"
35#include "objfiles.h"
36#include "elf/common.h"		/* for DT_PLTGOT value */
37#include "elf-bfd.h"
38#include "dis-asm.h"
39#include "infcall.h"
40#include "osabi.h"
41#include "ia64-tdep.h"
42#include "cp-abi.h"
43
44#ifdef HAVE_LIBUNWIND_IA64_H
45#include "elf/ia64.h"           /* for PT_IA_64_UNWIND value */
46#include "libunwind-frame.h"
47#include "libunwind-ia64.h"
48
49/* Note: KERNEL_START is supposed to be an address which is not going
50         to ever contain any valid unwind info.  For ia64 linux, the choice
51         of 0xc000000000000000 is fairly safe since that's uncached space.
52
53         We use KERNEL_START as follows: after obtaining the kernel's
54         unwind table via getunwind(), we project its unwind data into
55         address-range KERNEL_START-(KERNEL_START+ktab_size) and then
56         when ia64_access_mem() sees a memory access to this
57         address-range, we redirect it to ktab instead.
58
59         None of this hackery is needed with a modern kernel/libcs
60         which uses the kernel virtual DSO to provide access to the
61         kernel's unwind info.  In that case, ktab_size remains 0 and
62         hence the value of KERNEL_START doesn't matter.  */
63
64#define KERNEL_START 0xc000000000000000ULL
65
66static size_t ktab_size = 0;
67struct ia64_table_entry
68  {
69    uint64_t start_offset;
70    uint64_t end_offset;
71    uint64_t info_offset;
72  };
73
74static struct ia64_table_entry *ktab = NULL;
75
76#endif
77
78/* An enumeration of the different IA-64 instruction types.  */
79
80typedef enum instruction_type
81{
82  A,			/* Integer ALU ;    I-unit or M-unit */
83  I,			/* Non-ALU integer; I-unit */
84  M,			/* Memory ;         M-unit */
85  F,			/* Floating-point ; F-unit */
86  B,			/* Branch ;         B-unit */
87  L,			/* Extended (L+X) ; I-unit */
88  X,			/* Extended (L+X) ; I-unit */
89  undefined		/* undefined or reserved */
90} instruction_type;
91
92/* We represent IA-64 PC addresses as the value of the instruction
93   pointer or'd with some bit combination in the low nibble which
94   represents the slot number in the bundle addressed by the
95   instruction pointer.  The problem is that the Linux kernel
96   multiplies its slot numbers (for exceptions) by one while the
97   disassembler multiplies its slot numbers by 6.  In addition, I've
98   heard it said that the simulator uses 1 as the multiplier.
99
100   I've fixed the disassembler so that the bytes_per_line field will
101   be the slot multiplier.  If bytes_per_line comes in as zero, it
102   is set to six (which is how it was set up initially). -- objdump
103   displays pretty disassembly dumps with this value.  For our purposes,
104   we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
105   never want to also display the raw bytes the way objdump does.  */
106
107#define SLOT_MULTIPLIER 1
108
109/* Length in bytes of an instruction bundle.  */
110
111#define BUNDLE_LEN 16
112
113/* See the saved memory layout comment for ia64_memory_insert_breakpoint.  */
114
115#if BREAKPOINT_MAX < BUNDLE_LEN - 2
116# error "BREAKPOINT_MAX < BUNDLE_LEN - 2"
117#endif
118
119static gdbarch_init_ftype ia64_gdbarch_init;
120
121static gdbarch_register_name_ftype ia64_register_name;
122static gdbarch_register_type_ftype ia64_register_type;
123static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
124static gdbarch_skip_prologue_ftype ia64_skip_prologue;
125static struct type *is_float_or_hfa_type (struct type *t);
126static CORE_ADDR ia64_find_global_pointer (struct gdbarch *gdbarch,
127					   CORE_ADDR faddr);
128
129#define NUM_IA64_RAW_REGS 462
130
131static int sp_regnum = IA64_GR12_REGNUM;
132static int fp_regnum = IA64_VFP_REGNUM;
133static int lr_regnum = IA64_VRAP_REGNUM;
134
135/* NOTE: we treat the register stack registers r32-r127 as
136   pseudo-registers because they may not be accessible via the ptrace
137   register get/set interfaces.  */
138
139enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS,
140		   VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
141		   V127_REGNUM = V32_REGNUM + 95,
142		   VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16,
143		   VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
144
145/* Array of register names; There should be ia64_num_regs strings in
146   the initializer.  */
147
148static char *ia64_register_names[] =
149{ "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
150  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
151  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
152  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
153  "",     "",     "",     "",     "",     "",     "",     "",
154  "",     "",     "",     "",     "",     "",     "",     "",
155  "",     "",     "",     "",     "",     "",     "",     "",
156  "",     "",     "",     "",     "",     "",     "",     "",
157  "",     "",     "",     "",     "",     "",     "",     "",
158  "",     "",     "",     "",     "",     "",     "",     "",
159  "",     "",     "",     "",     "",     "",     "",     "",
160  "",     "",     "",     "",     "",     "",     "",     "",
161  "",     "",     "",     "",     "",     "",     "",     "",
162  "",     "",     "",     "",     "",     "",     "",     "",
163  "",     "",     "",     "",     "",     "",     "",     "",
164  "",     "",     "",     "",     "",     "",     "",     "",
165
166  "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7",
167  "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15",
168  "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",
169  "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",
170  "f32",  "f33",  "f34",  "f35",  "f36",  "f37",  "f38",  "f39",
171  "f40",  "f41",  "f42",  "f43",  "f44",  "f45",  "f46",  "f47",
172  "f48",  "f49",  "f50",  "f51",  "f52",  "f53",  "f54",  "f55",
173  "f56",  "f57",  "f58",  "f59",  "f60",  "f61",  "f62",  "f63",
174  "f64",  "f65",  "f66",  "f67",  "f68",  "f69",  "f70",  "f71",
175  "f72",  "f73",  "f74",  "f75",  "f76",  "f77",  "f78",  "f79",
176  "f80",  "f81",  "f82",  "f83",  "f84",  "f85",  "f86",  "f87",
177  "f88",  "f89",  "f90",  "f91",  "f92",  "f93",  "f94",  "f95",
178  "f96",  "f97",  "f98",  "f99",  "f100", "f101", "f102", "f103",
179  "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
180  "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
181  "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
182
183  "",     "",     "",     "",     "",     "",     "",     "",
184  "",     "",     "",     "",     "",     "",     "",     "",
185  "",     "",     "",     "",     "",     "",     "",     "",
186  "",     "",     "",     "",     "",     "",     "",     "",
187  "",     "",     "",     "",     "",     "",     "",     "",
188  "",     "",     "",     "",     "",     "",     "",     "",
189  "",     "",     "",     "",     "",     "",     "",     "",
190  "",     "",     "",     "",     "",     "",     "",     "",
191
192  "b0",   "b1",   "b2",   "b3",   "b4",   "b5",   "b6",   "b7",
193
194  "vfp", "vrap",
195
196  "pr", "ip", "psr", "cfm",
197
198  "kr0",   "kr1",   "kr2",   "kr3",   "kr4",   "kr5",   "kr6",   "kr7",
199  "", "", "", "", "", "", "", "",
200  "rsc", "bsp", "bspstore", "rnat",
201  "", "fcr", "", "",
202  "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr",  "",
203  "ccv", "", "", "", "unat", "", "", "",
204  "fpsr", "", "", "", "itc",
205  "", "", "", "", "", "", "", "", "", "",
206  "", "", "", "", "", "", "", "", "",
207  "pfs", "lc", "ec",
208  "", "", "", "", "", "", "", "", "", "",
209  "", "", "", "", "", "", "", "", "", "",
210  "", "", "", "", "", "", "", "", "", "",
211  "", "", "", "", "", "", "", "", "", "",
212  "", "", "", "", "", "", "", "", "", "",
213  "", "", "", "", "", "", "", "", "", "",
214  "",
215  "nat0",  "nat1",  "nat2",  "nat3",  "nat4",  "nat5",  "nat6",  "nat7",
216  "nat8",  "nat9",  "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
217  "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
218  "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
219  "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
220  "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
221  "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
222  "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
223  "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
224  "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
225  "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
226  "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
227  "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
228  "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
229  "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
230  "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
231
232  "bof",
233
234  "r32",  "r33",  "r34",  "r35",  "r36",  "r37",  "r38",  "r39",
235  "r40",  "r41",  "r42",  "r43",  "r44",  "r45",  "r46",  "r47",
236  "r48",  "r49",  "r50",  "r51",  "r52",  "r53",  "r54",  "r55",
237  "r56",  "r57",  "r58",  "r59",  "r60",  "r61",  "r62",  "r63",
238  "r64",  "r65",  "r66",  "r67",  "r68",  "r69",  "r70",  "r71",
239  "r72",  "r73",  "r74",  "r75",  "r76",  "r77",  "r78",  "r79",
240  "r80",  "r81",  "r82",  "r83",  "r84",  "r85",  "r86",  "r87",
241  "r88",  "r89",  "r90",  "r91",  "r92",  "r93",  "r94",  "r95",
242  "r96",  "r97",  "r98",  "r99",  "r100", "r101", "r102", "r103",
243  "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
244  "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
245  "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
246
247  "p0",   "p1",   "p2",   "p3",   "p4",   "p5",   "p6",   "p7",
248  "p8",   "p9",   "p10",  "p11",  "p12",  "p13",  "p14",  "p15",
249  "p16",  "p17",  "p18",  "p19",  "p20",  "p21",  "p22",  "p23",
250  "p24",  "p25",  "p26",  "p27",  "p28",  "p29",  "p30",  "p31",
251  "p32",  "p33",  "p34",  "p35",  "p36",  "p37",  "p38",  "p39",
252  "p40",  "p41",  "p42",  "p43",  "p44",  "p45",  "p46",  "p47",
253  "p48",  "p49",  "p50",  "p51",  "p52",  "p53",  "p54",  "p55",
254  "p56",  "p57",  "p58",  "p59",  "p60",  "p61",  "p62",  "p63",
255};
256
257struct ia64_frame_cache
258{
259  CORE_ADDR base;       /* frame pointer base for frame */
260  CORE_ADDR pc;		/* function start pc for frame */
261  CORE_ADDR saved_sp;	/* stack pointer for frame */
262  CORE_ADDR bsp;	/* points at r32 for the current frame */
263  CORE_ADDR cfm;	/* cfm value for current frame */
264  CORE_ADDR prev_cfm;   /* cfm value for previous frame */
265  int   frameless;
266  int   sof;		/* Size of frame  (decoded from cfm value).  */
267  int	sol;		/* Size of locals (decoded from cfm value).  */
268  int	sor;		/* Number of rotating registers (decoded from
269			   cfm value).  */
270  CORE_ADDR after_prologue;
271  /* Address of first instruction after the last
272     prologue instruction;  Note that there may
273     be instructions from the function's body
274     intermingled with the prologue.  */
275  int mem_stack_frame_size;
276  /* Size of the memory stack frame (may be zero),
277     or -1 if it has not been determined yet.  */
278  int	fp_reg;		/* Register number (if any) used a frame pointer
279			   for this frame.  0 if no register is being used
280			   as the frame pointer.  */
281
282  /* Saved registers.  */
283  CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
284
285};
286
287static int
288floatformat_valid (const struct floatformat *fmt, const void *from)
289{
290  return 1;
291}
292
293static const struct floatformat floatformat_ia64_ext_little =
294{
295  floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
296  floatformat_intbit_yes, "floatformat_ia64_ext_little", floatformat_valid, NULL
297};
298
299static const struct floatformat floatformat_ia64_ext_big =
300{
301  floatformat_big, 82, 46, 47, 17, 65535, 0x1ffff, 64, 64,
302  floatformat_intbit_yes, "floatformat_ia64_ext_big", floatformat_valid
303};
304
305static const struct floatformat *floatformats_ia64_ext[2] =
306{
307  &floatformat_ia64_ext_big,
308  &floatformat_ia64_ext_little
309};
310
311static struct type *
312ia64_ext_type (struct gdbarch *gdbarch)
313{
314  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
315
316  if (!tdep->ia64_ext_type)
317    tdep->ia64_ext_type
318      = arch_float_type (gdbarch, 128, "builtin_type_ia64_ext",
319			 floatformats_ia64_ext);
320
321  return tdep->ia64_ext_type;
322}
323
324static int
325ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
326			  struct reggroup *group)
327{
328  int vector_p;
329  int float_p;
330  int raw_p;
331  if (group == all_reggroup)
332    return 1;
333  vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
334  float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
335  raw_p = regnum < NUM_IA64_RAW_REGS;
336  if (group == float_reggroup)
337    return float_p;
338  if (group == vector_reggroup)
339    return vector_p;
340  if (group == general_reggroup)
341    return (!vector_p && !float_p);
342  if (group == save_reggroup || group == restore_reggroup)
343    return raw_p;
344  return 0;
345}
346
347static const char *
348ia64_register_name (struct gdbarch *gdbarch, int reg)
349{
350  return ia64_register_names[reg];
351}
352
353struct type *
354ia64_register_type (struct gdbarch *arch, int reg)
355{
356  if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
357    return ia64_ext_type (arch);
358  else
359    return builtin_type (arch)->builtin_long;
360}
361
362static int
363ia64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
364{
365  if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
366    return V32_REGNUM + (reg - IA64_GR32_REGNUM);
367  return reg;
368}
369
370
371/* Extract ``len'' bits from an instruction bundle starting at
372   bit ``from''.  */
373
374static long long
375extract_bit_field (const char *bundle, int from, int len)
376{
377  long long result = 0LL;
378  int to = from + len;
379  int from_byte = from / 8;
380  int to_byte = to / 8;
381  unsigned char *b = (unsigned char *) bundle;
382  unsigned char c;
383  int lshift;
384  int i;
385
386  c = b[from_byte];
387  if (from_byte == to_byte)
388    c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
389  result = c >> (from % 8);
390  lshift = 8 - (from % 8);
391
392  for (i = from_byte+1; i < to_byte; i++)
393    {
394      result |= ((long long) b[i]) << lshift;
395      lshift += 8;
396    }
397
398  if (from_byte < to_byte && (to % 8 != 0))
399    {
400      c = b[to_byte];
401      c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
402      result |= ((long long) c) << lshift;
403    }
404
405  return result;
406}
407
408/* Replace the specified bits in an instruction bundle.  */
409
410static void
411replace_bit_field (char *bundle, long long val, int from, int len)
412{
413  int to = from + len;
414  int from_byte = from / 8;
415  int to_byte = to / 8;
416  unsigned char *b = (unsigned char *) bundle;
417  unsigned char c;
418
419  if (from_byte == to_byte)
420    {
421      unsigned char left, right;
422      c = b[from_byte];
423      left = (c >> (to % 8)) << (to % 8);
424      right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
425      c = (unsigned char) (val & 0xff);
426      c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
427      c |= right | left;
428      b[from_byte] = c;
429    }
430  else
431    {
432      int i;
433      c = b[from_byte];
434      c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
435      c = c | (val << (from % 8));
436      b[from_byte] = c;
437      val >>= 8 - from % 8;
438
439      for (i = from_byte+1; i < to_byte; i++)
440	{
441	  c = val & 0xff;
442	  val >>= 8;
443	  b[i] = c;
444	}
445
446      if (to % 8 != 0)
447	{
448	  unsigned char cv = (unsigned char) val;
449	  c = b[to_byte];
450	  c = c >> (to % 8) << (to % 8);
451	  c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
452	  b[to_byte] = c;
453	}
454    }
455}
456
457/* Return the contents of slot N (for N = 0, 1, or 2) in
458   and instruction bundle.  */
459
460static long long
461slotN_contents (char *bundle, int slotnum)
462{
463  return extract_bit_field (bundle, 5+41*slotnum, 41);
464}
465
466/* Store an instruction in an instruction bundle.  */
467
468static void
469replace_slotN_contents (char *bundle, long long instr, int slotnum)
470{
471  replace_bit_field (bundle, instr, 5+41*slotnum, 41);
472}
473
474static const enum instruction_type template_encoding_table[32][3] =
475{
476  { M, I, I },				/* 00 */
477  { M, I, I },				/* 01 */
478  { M, I, I },				/* 02 */
479  { M, I, I },				/* 03 */
480  { M, L, X },				/* 04 */
481  { M, L, X },				/* 05 */
482  { undefined, undefined, undefined },  /* 06 */
483  { undefined, undefined, undefined },  /* 07 */
484  { M, M, I },				/* 08 */
485  { M, M, I },				/* 09 */
486  { M, M, I },				/* 0A */
487  { M, M, I },				/* 0B */
488  { M, F, I },				/* 0C */
489  { M, F, I },				/* 0D */
490  { M, M, F },				/* 0E */
491  { M, M, F },				/* 0F */
492  { M, I, B },				/* 10 */
493  { M, I, B },				/* 11 */
494  { M, B, B },				/* 12 */
495  { M, B, B },				/* 13 */
496  { undefined, undefined, undefined },  /* 14 */
497  { undefined, undefined, undefined },  /* 15 */
498  { B, B, B },				/* 16 */
499  { B, B, B },				/* 17 */
500  { M, M, B },				/* 18 */
501  { M, M, B },				/* 19 */
502  { undefined, undefined, undefined },  /* 1A */
503  { undefined, undefined, undefined },  /* 1B */
504  { M, F, B },				/* 1C */
505  { M, F, B },				/* 1D */
506  { undefined, undefined, undefined },  /* 1E */
507  { undefined, undefined, undefined },  /* 1F */
508};
509
510/* Fetch and (partially) decode an instruction at ADDR and return the
511   address of the next instruction to fetch.  */
512
513static CORE_ADDR
514fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
515{
516  char bundle[BUNDLE_LEN];
517  int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
518  long long template;
519  int val;
520
521  /* Warn about slot numbers greater than 2.  We used to generate
522     an error here on the assumption that the user entered an invalid
523     address.  But, sometimes GDB itself requests an invalid address.
524     This can (easily) happen when execution stops in a function for
525     which there are no symbols.  The prologue scanner will attempt to
526     find the beginning of the function - if the nearest symbol
527     happens to not be aligned on a bundle boundary (16 bytes), the
528     resulting starting address will cause GDB to think that the slot
529     number is too large.
530
531     So we warn about it and set the slot number to zero.  It is
532     not necessarily a fatal condition, particularly if debugging
533     at the assembly language level.  */
534  if (slotnum > 2)
535    {
536      warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
537	       "Using slot 0 instead"));
538      slotnum = 0;
539    }
540
541  addr &= ~0x0f;
542
543  val = target_read_memory (addr, bundle, BUNDLE_LEN);
544
545  if (val != 0)
546    return 0;
547
548  *instr = slotN_contents (bundle, slotnum);
549  template = extract_bit_field (bundle, 0, 5);
550  *it = template_encoding_table[(int)template][slotnum];
551
552  if (slotnum == 2 || (slotnum == 1 && *it == L))
553    addr += 16;
554  else
555    addr += (slotnum + 1) * SLOT_MULTIPLIER;
556
557  return addr;
558}
559
560/* There are 5 different break instructions (break.i, break.b,
561   break.m, break.f, and break.x), but they all have the same
562   encoding.  (The five bit template in the low five bits of the
563   instruction bundle distinguishes one from another.)
564
565   The runtime architecture manual specifies that break instructions
566   used for debugging purposes must have the upper two bits of the 21
567   bit immediate set to a 0 and a 1 respectively.  A breakpoint
568   instruction encodes the most significant bit of its 21 bit
569   immediate at bit 36 of the 41 bit instruction.  The penultimate msb
570   is at bit 25 which leads to the pattern below.
571
572   Originally, I had this set up to do, e.g, a "break.i 0x80000"  But
573   it turns out that 0x80000 was used as the syscall break in the early
574   simulators.  So I changed the pattern slightly to do "break.i 0x080001"
575   instead.  But that didn't work either (I later found out that this
576   pattern was used by the simulator that I was using.)  So I ended up
577   using the pattern seen below.
578
579   SHADOW_CONTENTS has byte-based addressing (PLACED_ADDRESS and SHADOW_LEN)
580   while we need bit-based addressing as the instructions length is 41 bits and
581   we must not modify/corrupt the adjacent slots in the same bundle.
582   Fortunately we may store larger memory incl. the adjacent bits with the
583   original memory content (not the possibly already stored breakpoints there).
584   We need to be careful in ia64_memory_remove_breakpoint to always restore
585   only the specific bits of this instruction ignoring any adjacent stored
586   bits.
587
588   We use the original addressing with the low nibble in the range <0..2> which
589   gets incorrectly interpreted by generic non-ia64 breakpoint_restore_shadows
590   as the direct byte offset of SHADOW_CONTENTS.  We store whole BUNDLE_LEN
591   bytes just without these two possibly skipped bytes to not to exceed to the
592   next bundle.
593
594   If we would like to store the whole bundle to SHADOW_CONTENTS we would have
595   to store already the base address (`address & ~0x0f') into PLACED_ADDRESS.
596   In such case there is no other place where to store
597   SLOTNUM (`adress & 0x0f', value in the range <0..2>).  We need to know
598   SLOTNUM in ia64_memory_remove_breakpoint.
599
600   There is one special case where we need to be extra careful:
601   L-X instructions, which are instructions that occupy 2 slots
602   (The L part is always in slot 1, and the X part is always in
603   slot 2).  We must refuse to insert breakpoints for an address
604   that points at slot 2 of a bundle where an L-X instruction is
605   present, since there is logically no instruction at that address.
606   However, to make things more interesting, the opcode of L-X
607   instructions is located in slot 2.  This means that, to insert
608   a breakpoint at an address that points to slot 1, we actually
609   need to write the breakpoint in slot 2!  Slot 1 is actually
610   the extended operand, so writing the breakpoint there would not
611   have the desired effect.  Another side-effect of this issue
612   is that we need to make sure that the shadow contents buffer
613   does save byte 15 of our instruction bundle (this is the tail
614   end of slot 2, which wouldn't be saved if we were to insert
615   the breakpoint in slot 1).
616
617   ia64 16-byte bundle layout:
618   | 5 bits | slot 0 with 41 bits | slot 1 with 41 bits | slot 2 with 41 bits |
619
620   The current addressing used by the code below:
621   original PC   placed_address   placed_size             required    covered
622                                  == bp_tgt->shadow_len   reqd \subset covered
623   0xABCDE0      0xABCDE0         0x10                    <0x0...0x5> <0x0..0xF>
624   0xABCDE1      0xABCDE1         0xF                     <0x5...0xA> <0x1..0xF>
625   0xABCDE2      0xABCDE2         0xE                     <0xA...0xF> <0x2..0xF>
626
627   L-X instructions are treated a little specially, as explained above:
628   0xABCDE1      0xABCDE1         0xF                     <0xA...0xF> <0x1..0xF>
629
630   `objdump -d' and some other tools show a bit unjustified offsets:
631   original PC   byte where starts the instruction   objdump offset
632   0xABCDE0      0xABCDE0                            0xABCDE0
633   0xABCDE1      0xABCDE5                            0xABCDE6
634   0xABCDE2      0xABCDEA                            0xABCDEC
635   */
636
637#define IA64_BREAKPOINT 0x00003333300LL
638
639static int
640ia64_memory_insert_breakpoint (struct gdbarch *gdbarch,
641			       struct bp_target_info *bp_tgt)
642{
643  CORE_ADDR addr = bp_tgt->placed_address;
644  gdb_byte bundle[BUNDLE_LEN];
645  int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER, shadow_slotnum;
646  long long instr_breakpoint;
647  int val;
648  int template;
649  struct cleanup *cleanup;
650
651  if (slotnum > 2)
652    error (_("Can't insert breakpoint for slot numbers greater than 2."));
653
654  addr &= ~0x0f;
655
656  /* Enable the automatic memory restoration from breakpoints while
657     we read our instruction bundle for the purpose of SHADOW_CONTENTS.
658     Otherwise, we could possibly store into the shadow parts of the adjacent
659     placed breakpoints.  It is due to our SHADOW_CONTENTS overlapping the real
660     breakpoint instruction bits region.  */
661  cleanup = make_show_memory_breakpoints_cleanup (0);
662  val = target_read_memory (addr, bundle, BUNDLE_LEN);
663  if (val != 0)
664    {
665      do_cleanups (cleanup);
666      return val;
667    }
668
669  /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
670     for addressing the SHADOW_CONTENTS placement.  */
671  shadow_slotnum = slotnum;
672
673  /* Always cover the last byte of the bundle in case we are inserting
674     a breakpoint on an L-X instruction.  */
675  bp_tgt->shadow_len = BUNDLE_LEN - shadow_slotnum;
676
677  template = extract_bit_field (bundle, 0, 5);
678  if (template_encoding_table[template][slotnum] == X)
679    {
680      /* X unit types can only be used in slot 2, and are actually
681	 part of a 2-slot L-X instruction.  We cannot break at this
682	 address, as this is the second half of an instruction that
683	 lives in slot 1 of that bundle.  */
684      gdb_assert (slotnum == 2);
685      error (_("Can't insert breakpoint for non-existing slot X"));
686    }
687  if (template_encoding_table[template][slotnum] == L)
688    {
689      /* L unit types can only be used in slot 1.  But the associated
690	 opcode for that instruction is in slot 2, so bump the slot number
691	 accordingly.  */
692      gdb_assert (slotnum == 1);
693      slotnum = 2;
694    }
695
696  /* Store the whole bundle, except for the initial skipped bytes by the slot
697     number interpreted as bytes offset in PLACED_ADDRESS.  */
698  memcpy (bp_tgt->shadow_contents, bundle + shadow_slotnum,
699	  bp_tgt->shadow_len);
700
701  /* Re-read the same bundle as above except that, this time, read it in order
702     to compute the new bundle inside which we will be inserting the
703     breakpoint.  Therefore, disable the automatic memory restoration from
704     breakpoints while we read our instruction bundle.  Otherwise, the general
705     restoration mechanism kicks in and we would possibly remove parts of the
706     adjacent placed breakpoints.  It is due to our SHADOW_CONTENTS overlapping
707     the real breakpoint instruction bits region.  */
708  make_show_memory_breakpoints_cleanup (1);
709  val = target_read_memory (addr, bundle, BUNDLE_LEN);
710  if (val != 0)
711    {
712      do_cleanups (cleanup);
713      return val;
714    }
715
716  /* Breakpoints already present in the code will get deteacted and not get
717     reinserted by bp_loc_is_permanent.  Multiple breakpoints at the same
718     location cannot induce the internal error as they are optimized into
719     a single instance by update_global_location_list.  */
720  instr_breakpoint = slotN_contents (bundle, slotnum);
721  if (instr_breakpoint == IA64_BREAKPOINT)
722    internal_error (__FILE__, __LINE__,
723		    _("Address %s already contains a breakpoint."),
724		    paddress (gdbarch, bp_tgt->placed_address));
725  replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
726
727  bp_tgt->placed_size = bp_tgt->shadow_len;
728
729  val = target_write_memory (addr + shadow_slotnum, bundle + shadow_slotnum,
730			     bp_tgt->shadow_len);
731
732  do_cleanups (cleanup);
733  return val;
734}
735
736static int
737ia64_memory_remove_breakpoint (struct gdbarch *gdbarch,
738			       struct bp_target_info *bp_tgt)
739{
740  CORE_ADDR addr = bp_tgt->placed_address;
741  gdb_byte bundle_mem[BUNDLE_LEN], bundle_saved[BUNDLE_LEN];
742  int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER, shadow_slotnum;
743  long long instr_breakpoint, instr_saved;
744  int val;
745  int template;
746  struct cleanup *cleanup;
747
748  addr &= ~0x0f;
749
750  /* Disable the automatic memory restoration from breakpoints while
751     we read our instruction bundle.  Otherwise, the general restoration
752     mechanism kicks in and we would possibly remove parts of the adjacent
753     placed breakpoints.  It is due to our SHADOW_CONTENTS overlapping the real
754     breakpoint instruction bits region.  */
755  cleanup = make_show_memory_breakpoints_cleanup (1);
756  val = target_read_memory (addr, bundle_mem, BUNDLE_LEN);
757  if (val != 0)
758    {
759      do_cleanups (cleanup);
760      return val;
761    }
762
763  /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
764     for addressing the SHADOW_CONTENTS placement.  */
765  shadow_slotnum = slotnum;
766
767  template = extract_bit_field (bundle_mem, 0, 5);
768  if (template_encoding_table[template][slotnum] == X)
769    {
770      /* X unit types can only be used in slot 2, and are actually
771	 part of a 2-slot L-X instruction.  We refuse to insert
772	 breakpoints at this address, so there should be no reason
773	 for us attempting to remove one there, except if the program's
774	 code somehow got modified in memory.  */
775      gdb_assert (slotnum == 2);
776      warning (_("Cannot remove breakpoint at address %s from non-existing "
777		 "X-type slot, memory has changed underneath"),
778	       paddress (gdbarch, bp_tgt->placed_address));
779      do_cleanups (cleanup);
780      return -1;
781    }
782  if (template_encoding_table[template][slotnum] == L)
783    {
784      /* L unit types can only be used in slot 1.  But the breakpoint
785	 was actually saved using slot 2, so update the slot number
786	 accordingly.  */
787      gdb_assert (slotnum == 1);
788      slotnum = 2;
789    }
790
791  gdb_assert (bp_tgt->placed_size == BUNDLE_LEN - shadow_slotnum);
792  gdb_assert (bp_tgt->placed_size == bp_tgt->shadow_len);
793
794  instr_breakpoint = slotN_contents (bundle_mem, slotnum);
795  if (instr_breakpoint != IA64_BREAKPOINT)
796    {
797      warning (_("Cannot remove breakpoint at address %s, "
798		 "no break instruction at such address."),
799	       paddress (gdbarch, bp_tgt->placed_address));
800      do_cleanups (cleanup);
801      return -1;
802    }
803
804  /* Extract the original saved instruction from SLOTNUM normalizing its
805     bit-shift for INSTR_SAVED.  */
806  memcpy (bundle_saved, bundle_mem, BUNDLE_LEN);
807  memcpy (bundle_saved + shadow_slotnum, bp_tgt->shadow_contents,
808	  bp_tgt->shadow_len);
809  instr_saved = slotN_contents (bundle_saved, slotnum);
810
811  /* In BUNDLE_MEM, be careful to modify only the bits belonging to SLOTNUM
812     and not any of the other ones that are stored in SHADOW_CONTENTS.  */
813  replace_slotN_contents (bundle_mem, instr_saved, slotnum);
814  val = target_write_memory (addr, bundle_mem, BUNDLE_LEN);
815
816  do_cleanups (cleanup);
817  return val;
818}
819
820/* As gdbarch_breakpoint_from_pc ranges have byte granularity and ia64
821   instruction slots ranges are bit-granular (41 bits) we have to provide an
822   extended range as described for ia64_memory_insert_breakpoint.  We also take
823   care of preserving the `break' instruction 21-bit (or 62-bit) parameter to
824   make a match for permanent breakpoints.  */
825
826static const gdb_byte *
827ia64_breakpoint_from_pc (struct gdbarch *gdbarch,
828			 CORE_ADDR *pcptr, int *lenptr)
829{
830  CORE_ADDR addr = *pcptr;
831  static gdb_byte bundle[BUNDLE_LEN];
832  int slotnum = (int) (*pcptr & 0x0f) / SLOT_MULTIPLIER, shadow_slotnum;
833  long long instr_fetched;
834  int val;
835  int template;
836  struct cleanup *cleanup;
837
838  if (slotnum > 2)
839    error (_("Can't insert breakpoint for slot numbers greater than 2."));
840
841  addr &= ~0x0f;
842
843  /* Enable the automatic memory restoration from breakpoints while
844     we read our instruction bundle to match bp_loc_is_permanent.  */
845  cleanup = make_show_memory_breakpoints_cleanup (0);
846  val = target_read_memory (addr, bundle, BUNDLE_LEN);
847  do_cleanups (cleanup);
848
849  /* The memory might be unreachable.  This can happen, for instance,
850     when the user inserts a breakpoint at an invalid address.  */
851  if (val != 0)
852    return NULL;
853
854  /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
855     for addressing the SHADOW_CONTENTS placement.  */
856  shadow_slotnum = slotnum;
857
858  /* Cover always the last byte of the bundle for the L-X slot case.  */
859  *lenptr = BUNDLE_LEN - shadow_slotnum;
860
861  /* Check for L type instruction in slot 1, if present then bump up the slot
862     number to the slot 2.  */
863  template = extract_bit_field (bundle, 0, 5);
864  if (template_encoding_table[template][slotnum] == X)
865    {
866      gdb_assert (slotnum == 2);
867      error (_("Can't insert breakpoint for non-existing slot X"));
868    }
869  if (template_encoding_table[template][slotnum] == L)
870    {
871      gdb_assert (slotnum == 1);
872      slotnum = 2;
873    }
874
875  /* A break instruction has its all its opcode bits cleared except for
876     the parameter value.  For L+X slot pair we are at the X slot (slot 2) so
877     we should not touch the L slot - the upper 41 bits of the parameter.  */
878  instr_fetched = slotN_contents (bundle, slotnum);
879  instr_fetched &= 0x1003ffffc0LL;
880  replace_slotN_contents (bundle, instr_fetched, slotnum);
881
882  return bundle + shadow_slotnum;
883}
884
885static CORE_ADDR
886ia64_read_pc (struct regcache *regcache)
887{
888  ULONGEST psr_value, pc_value;
889  int slot_num;
890
891  regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr_value);
892  regcache_cooked_read_unsigned (regcache, IA64_IP_REGNUM, &pc_value);
893  slot_num = (psr_value >> 41) & 3;
894
895  return pc_value | (slot_num * SLOT_MULTIPLIER);
896}
897
898void
899ia64_write_pc (struct regcache *regcache, CORE_ADDR new_pc)
900{
901  int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
902  ULONGEST psr_value;
903
904  regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr_value);
905  psr_value &= ~(3LL << 41);
906  psr_value |= (ULONGEST)(slot_num & 0x3) << 41;
907
908  new_pc &= ~0xfLL;
909
910  regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr_value);
911  regcache_cooked_write_unsigned (regcache, IA64_IP_REGNUM, new_pc);
912}
913
914#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
915
916/* Returns the address of the slot that's NSLOTS slots away from
917   the address ADDR.  NSLOTS may be positive or negative.  */
918static CORE_ADDR
919rse_address_add(CORE_ADDR addr, int nslots)
920{
921  CORE_ADDR new_addr;
922  int mandatory_nat_slots = nslots / 63;
923  int direction = nslots < 0 ? -1 : 1;
924
925  new_addr = addr + 8 * (nslots + mandatory_nat_slots);
926
927  if ((new_addr >> 9)  != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
928    new_addr += 8 * direction;
929
930  if (IS_NaT_COLLECTION_ADDR(new_addr))
931    new_addr += 8 * direction;
932
933  return new_addr;
934}
935
936static enum register_status
937ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
938                           int regnum, gdb_byte *buf)
939{
940  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
941  enum register_status status;
942
943  if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
944    {
945#ifdef HAVE_LIBUNWIND_IA64_H
946      /* First try and use the libunwind special reg accessor,
947	 otherwise fallback to standard logic.  */
948      if (!libunwind_is_initialized ()
949	  || libunwind_get_reg_special (gdbarch, regcache, regnum, buf) != 0)
950#endif
951	{
952	  /* The fallback position is to assume that r32-r127 are
953	     found sequentially in memory starting at $bof.  This
954	     isn't always true, but without libunwind, this is the
955	     best we can do.  */
956	  enum register_status status;
957	  ULONGEST cfm;
958	  ULONGEST bsp;
959	  CORE_ADDR reg;
960
961	  status = regcache_cooked_read_unsigned (regcache,
962						  IA64_BSP_REGNUM, &bsp);
963	  if (status != REG_VALID)
964	    return status;
965
966	  status = regcache_cooked_read_unsigned (regcache,
967						  IA64_CFM_REGNUM, &cfm);
968	  if (status != REG_VALID)
969	    return status;
970
971	  /* The bsp points at the end of the register frame so we
972	     subtract the size of frame from it to get start of
973	     register frame.  */
974	  bsp = rse_address_add (bsp, -(cfm & 0x7f));
975
976	  if ((cfm & 0x7f) > regnum - V32_REGNUM)
977	    {
978	      ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
979	      reg = read_memory_integer ((CORE_ADDR)reg_addr, 8, byte_order);
980	      store_unsigned_integer (buf, register_size (gdbarch, regnum),
981				      byte_order, reg);
982	    }
983	  else
984	    store_unsigned_integer (buf, register_size (gdbarch, regnum),
985				    byte_order, 0);
986	}
987    }
988  else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
989    {
990      ULONGEST unatN_val;
991      ULONGEST unat;
992      status = regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
993      if (status != REG_VALID)
994	return status;
995      unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
996      store_unsigned_integer (buf, register_size (gdbarch, regnum),
997			      byte_order, unatN_val);
998    }
999  else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1000    {
1001      ULONGEST natN_val = 0;
1002      ULONGEST bsp;
1003      ULONGEST cfm;
1004      CORE_ADDR gr_addr = 0;
1005      status = regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
1006      if (status != REG_VALID)
1007	return status;
1008      status = regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1009      if (status != REG_VALID)
1010	return status;
1011
1012      /* The bsp points at the end of the register frame so we
1013	 subtract the size of frame from it to get start of register frame.  */
1014      bsp = rse_address_add (bsp, -(cfm & 0x7f));
1015
1016      if ((cfm & 0x7f) > regnum - V32_REGNUM)
1017	gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
1018
1019      if (gr_addr != 0)
1020	{
1021	  /* Compute address of nat collection bits.  */
1022	  CORE_ADDR nat_addr = gr_addr | 0x1f8;
1023	  CORE_ADDR nat_collection;
1024	  int nat_bit;
1025	  /* If our nat collection address is bigger than bsp, we have to get
1026	     the nat collection from rnat.  Otherwise, we fetch the nat
1027	     collection from the computed address.  */
1028	  if (nat_addr >= bsp)
1029	    regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM,
1030					   &nat_collection);
1031	  else
1032	    nat_collection = read_memory_integer (nat_addr, 8, byte_order);
1033	  nat_bit = (gr_addr >> 3) & 0x3f;
1034	  natN_val = (nat_collection >> nat_bit) & 1;
1035	}
1036
1037      store_unsigned_integer (buf, register_size (gdbarch, regnum),
1038			      byte_order, natN_val);
1039    }
1040  else if (regnum == VBOF_REGNUM)
1041    {
1042      /* A virtual register frame start is provided for user convenience.
1043         It can be calculated as the bsp - sof (sizeof frame).  */
1044      ULONGEST bsp, vbsp;
1045      ULONGEST cfm;
1046      CORE_ADDR reg;
1047      status = regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
1048      if (status != REG_VALID)
1049	return status;
1050      status = regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1051      if (status != REG_VALID)
1052	return status;
1053
1054      /* The bsp points at the end of the register frame so we
1055	 subtract the size of frame from it to get beginning of frame.  */
1056      vbsp = rse_address_add (bsp, -(cfm & 0x7f));
1057      store_unsigned_integer (buf, register_size (gdbarch, regnum),
1058			      byte_order, vbsp);
1059    }
1060  else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1061    {
1062      ULONGEST pr;
1063      ULONGEST cfm;
1064      ULONGEST prN_val;
1065      CORE_ADDR reg;
1066      status = regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
1067      if (status != REG_VALID)
1068	return status;
1069      status = regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1070      if (status != REG_VALID)
1071	return status;
1072
1073      if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1074	{
1075	  /* Fetch predicate register rename base from current frame
1076	     marker for this frame.  */
1077	  int rrb_pr = (cfm >> 32) & 0x3f;
1078
1079	  /* Adjust the register number to account for register rotation.  */
1080	  regnum = VP16_REGNUM
1081	         + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1082	}
1083      prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
1084      store_unsigned_integer (buf, register_size (gdbarch, regnum),
1085			      byte_order, prN_val);
1086    }
1087  else
1088    memset (buf, 0, register_size (gdbarch, regnum));
1089
1090  return REG_VALID;
1091}
1092
1093static void
1094ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1095			    int regnum, const gdb_byte *buf)
1096{
1097  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1098
1099  if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
1100    {
1101      ULONGEST bsp;
1102      ULONGEST cfm;
1103      CORE_ADDR reg;
1104      regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
1105      regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1106
1107      bsp = rse_address_add (bsp, -(cfm & 0x7f));
1108
1109      if ((cfm & 0x7f) > regnum - V32_REGNUM)
1110	{
1111	  ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
1112	  write_memory (reg_addr, (void *) buf, 8);
1113	}
1114    }
1115  else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1116    {
1117      ULONGEST unatN_val, unat, unatN_mask;
1118      regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
1119      unatN_val = extract_unsigned_integer (buf, register_size (gdbarch,
1120								regnum),
1121					    byte_order);
1122      unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
1123      if (unatN_val == 0)
1124	unat &= ~unatN_mask;
1125      else if (unatN_val == 1)
1126	unat |= unatN_mask;
1127      regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
1128    }
1129  else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1130    {
1131      ULONGEST natN_val;
1132      ULONGEST bsp;
1133      ULONGEST cfm;
1134      CORE_ADDR gr_addr = 0;
1135      regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
1136      regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1137
1138      /* The bsp points at the end of the register frame so we
1139	 subtract the size of frame from it to get start of register frame.  */
1140      bsp = rse_address_add (bsp, -(cfm & 0x7f));
1141
1142      if ((cfm & 0x7f) > regnum - V32_REGNUM)
1143	gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
1144
1145      natN_val = extract_unsigned_integer (buf, register_size (gdbarch,
1146							       regnum),
1147					   byte_order);
1148
1149      if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
1150	{
1151	  /* Compute address of nat collection bits.  */
1152	  CORE_ADDR nat_addr = gr_addr | 0x1f8;
1153	  CORE_ADDR nat_collection;
1154	  int natN_bit = (gr_addr >> 3) & 0x3f;
1155	  ULONGEST natN_mask = (1LL << natN_bit);
1156	  /* If our nat collection address is bigger than bsp, we have to get
1157	     the nat collection from rnat.  Otherwise, we fetch the nat
1158	     collection from the computed address.  */
1159	  if (nat_addr >= bsp)
1160	    {
1161	      regcache_cooked_read_unsigned (regcache,
1162					     IA64_RNAT_REGNUM,
1163					     &nat_collection);
1164	      if (natN_val)
1165		nat_collection |= natN_mask;
1166	      else
1167		nat_collection &= ~natN_mask;
1168	      regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM,
1169					      nat_collection);
1170	    }
1171	  else
1172	    {
1173	      char nat_buf[8];
1174	      nat_collection = read_memory_integer (nat_addr, 8, byte_order);
1175	      if (natN_val)
1176		nat_collection |= natN_mask;
1177	      else
1178		nat_collection &= ~natN_mask;
1179	      store_unsigned_integer (nat_buf, register_size (gdbarch, regnum),
1180				      byte_order, nat_collection);
1181	      write_memory (nat_addr, nat_buf, 8);
1182	    }
1183	}
1184    }
1185  else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1186    {
1187      ULONGEST pr;
1188      ULONGEST cfm;
1189      ULONGEST prN_val;
1190      ULONGEST prN_mask;
1191
1192      regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
1193      regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1194
1195      if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1196	{
1197	  /* Fetch predicate register rename base from current frame
1198	     marker for this frame.  */
1199	  int rrb_pr = (cfm >> 32) & 0x3f;
1200
1201	  /* Adjust the register number to account for register rotation.  */
1202	  regnum = VP16_REGNUM
1203	         + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1204	}
1205      prN_val = extract_unsigned_integer (buf, register_size (gdbarch, regnum),
1206					  byte_order);
1207      prN_mask = (1LL << (regnum - VP0_REGNUM));
1208      if (prN_val == 0)
1209	pr &= ~prN_mask;
1210      else if (prN_val == 1)
1211	pr |= prN_mask;
1212      regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
1213    }
1214}
1215
1216/* The ia64 needs to convert between various ieee floating-point formats
1217   and the special ia64 floating point register format.  */
1218
1219static int
1220ia64_convert_register_p (struct gdbarch *gdbarch, int regno, struct type *type)
1221{
1222  return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM
1223	  && type != ia64_ext_type (gdbarch));
1224}
1225
1226static int
1227ia64_register_to_value (struct frame_info *frame, int regnum,
1228			struct type *valtype, gdb_byte *out,
1229			int *optimizedp, int *unavailablep)
1230{
1231  struct gdbarch *gdbarch = get_frame_arch (frame);
1232  char in[MAX_REGISTER_SIZE];
1233
1234  /* Convert to TYPE.  */
1235  if (!get_frame_register_bytes (frame, regnum, 0,
1236				 register_size (gdbarch, regnum),
1237				 in, optimizedp, unavailablep))
1238    return 0;
1239
1240  convert_typed_floating (in, ia64_ext_type (gdbarch), out, valtype);
1241  *optimizedp = *unavailablep = 0;
1242  return 1;
1243}
1244
1245static void
1246ia64_value_to_register (struct frame_info *frame, int regnum,
1247                         struct type *valtype, const gdb_byte *in)
1248{
1249  struct gdbarch *gdbarch = get_frame_arch (frame);
1250  char out[MAX_REGISTER_SIZE];
1251  convert_typed_floating (in, valtype, out, ia64_ext_type (gdbarch));
1252  put_frame_register (frame, regnum, out);
1253}
1254
1255
1256/* Limit the number of skipped non-prologue instructions since examining
1257   of the prologue is expensive.  */
1258static int max_skip_non_prologue_insns = 40;
1259
1260/* Given PC representing the starting address of a function, and
1261   LIM_PC which is the (sloppy) limit to which to scan when looking
1262   for a prologue, attempt to further refine this limit by using
1263   the line data in the symbol table.  If successful, a better guess
1264   on where the prologue ends is returned, otherwise the previous
1265   value of lim_pc is returned.  TRUST_LIMIT is a pointer to a flag
1266   which will be set to indicate whether the returned limit may be
1267   used with no further scanning in the event that the function is
1268   frameless.  */
1269
1270/* FIXME: cagney/2004-02-14: This function and logic have largely been
1271   superseded by skip_prologue_using_sal.  */
1272
1273static CORE_ADDR
1274refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
1275{
1276  struct symtab_and_line prologue_sal;
1277  CORE_ADDR start_pc = pc;
1278  CORE_ADDR end_pc;
1279
1280  /* The prologue can not possibly go past the function end itself,
1281     so we can already adjust LIM_PC accordingly.  */
1282  if (find_pc_partial_function (pc, NULL, NULL, &end_pc) && end_pc < lim_pc)
1283    lim_pc = end_pc;
1284
1285  /* Start off not trusting the limit.  */
1286  *trust_limit = 0;
1287
1288  prologue_sal = find_pc_line (pc, 0);
1289  if (prologue_sal.line != 0)
1290    {
1291      int i;
1292      CORE_ADDR addr = prologue_sal.end;
1293
1294      /* Handle the case in which compiler's optimizer/scheduler
1295         has moved instructions into the prologue.  We scan ahead
1296	 in the function looking for address ranges whose corresponding
1297	 line number is less than or equal to the first one that we
1298	 found for the function.  (It can be less than when the
1299	 scheduler puts a body instruction before the first prologue
1300	 instruction.)  */
1301      for (i = 2 * max_skip_non_prologue_insns;
1302           i > 0 && (lim_pc == 0 || addr < lim_pc);
1303	   i--)
1304        {
1305	  struct symtab_and_line sal;
1306
1307	  sal = find_pc_line (addr, 0);
1308	  if (sal.line == 0)
1309	    break;
1310	  if (sal.line <= prologue_sal.line
1311	      && sal.symtab == prologue_sal.symtab)
1312	    {
1313	      prologue_sal = sal;
1314	    }
1315	  addr = sal.end;
1316	}
1317
1318      if (lim_pc == 0 || prologue_sal.end < lim_pc)
1319	{
1320	  lim_pc = prologue_sal.end;
1321	  if (start_pc == get_pc_function_start (lim_pc))
1322	    *trust_limit = 1;
1323	}
1324    }
1325  return lim_pc;
1326}
1327
1328#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1329  || (8 <= (_regnum_) && (_regnum_) <= 11) \
1330  || (14 <= (_regnum_) && (_regnum_) <= 31))
1331#define imm9(_instr_) \
1332  ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1333   | (((_instr_) & 0x00008000000LL) >> 20) \
1334   | (((_instr_) & 0x00000001fc0LL) >> 6))
1335
1336/* Allocate and initialize a frame cache.  */
1337
1338static struct ia64_frame_cache *
1339ia64_alloc_frame_cache (void)
1340{
1341  struct ia64_frame_cache *cache;
1342  int i;
1343
1344  cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1345
1346  /* Base address.  */
1347  cache->base = 0;
1348  cache->pc = 0;
1349  cache->cfm = 0;
1350  cache->prev_cfm = 0;
1351  cache->sof = 0;
1352  cache->sol = 0;
1353  cache->sor = 0;
1354  cache->bsp = 0;
1355  cache->fp_reg = 0;
1356  cache->frameless = 1;
1357
1358  for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1359    cache->saved_regs[i] = 0;
1360
1361  return cache;
1362}
1363
1364static CORE_ADDR
1365examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc,
1366                  struct frame_info *this_frame,
1367                  struct ia64_frame_cache *cache)
1368{
1369  CORE_ADDR next_pc;
1370  CORE_ADDR last_prologue_pc = pc;
1371  instruction_type it;
1372  long long instr;
1373  int cfm_reg  = 0;
1374  int ret_reg  = 0;
1375  int fp_reg   = 0;
1376  int unat_save_reg = 0;
1377  int pr_save_reg = 0;
1378  int mem_stack_frame_size = 0;
1379  int spill_reg   = 0;
1380  CORE_ADDR spill_addr = 0;
1381  char instores[8];
1382  char infpstores[8];
1383  char reg_contents[256];
1384  int trust_limit;
1385  int frameless = 1;
1386  int i;
1387  CORE_ADDR addr;
1388  char buf[8];
1389  CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
1390
1391  memset (instores, 0, sizeof instores);
1392  memset (infpstores, 0, sizeof infpstores);
1393  memset (reg_contents, 0, sizeof reg_contents);
1394
1395  if (cache->after_prologue != 0
1396      && cache->after_prologue <= lim_pc)
1397    return cache->after_prologue;
1398
1399  lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
1400  next_pc = fetch_instruction (pc, &it, &instr);
1401
1402  /* We want to check if we have a recognizable function start before we
1403     look ahead for a prologue.  */
1404  if (pc < lim_pc && next_pc
1405      && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1406    {
1407      /* alloc - start of a regular function.  */
1408      int sor = (int) ((instr & 0x00078000000LL) >> 27);
1409      int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1410      int sof = (int) ((instr & 0x000000fe000LL) >> 13);
1411      int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1412
1413      /* Verify that the current cfm matches what we think is the
1414	 function start.  If we have somehow jumped within a function,
1415	 we do not want to interpret the prologue and calculate the
1416	 addresses of various registers such as the return address.
1417	 We will instead treat the frame as frameless.  */
1418      if (!this_frame ||
1419	  (sof == (cache->cfm & 0x7f) &&
1420	   sol == ((cache->cfm >> 7) & 0x7f)))
1421	frameless = 0;
1422
1423      cfm_reg = rN;
1424      last_prologue_pc = next_pc;
1425      pc = next_pc;
1426    }
1427  else
1428    {
1429      /* Look for a leaf routine.  */
1430      if (pc < lim_pc && next_pc
1431	  && (it == I || it == M)
1432          && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1433	{
1434	  /* adds rN = imm14, rM   (or mov rN, rM  when imm14 is 0) */
1435	  int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1436	                   | ((instr & 0x001f8000000LL) >> 20)
1437		           | ((instr & 0x000000fe000LL) >> 13));
1438	  int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1439	  int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1440	  int qp = (int) (instr & 0x0000000003fLL);
1441	  if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1442	    {
1443	      /* mov r2, r12 - beginning of leaf routine.  */
1444	      fp_reg = rN;
1445	      last_prologue_pc = next_pc;
1446	    }
1447	}
1448
1449      /* If we don't recognize a regular function or leaf routine, we are
1450	 done.  */
1451      if (!fp_reg)
1452	{
1453	  pc = lim_pc;
1454	  if (trust_limit)
1455	    last_prologue_pc = lim_pc;
1456	}
1457    }
1458
1459  /* Loop, looking for prologue instructions, keeping track of
1460     where preserved registers were spilled.  */
1461  while (pc < lim_pc)
1462    {
1463      next_pc = fetch_instruction (pc, &it, &instr);
1464      if (next_pc == 0)
1465	break;
1466
1467      if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
1468	{
1469	  /* Exit loop upon hitting a non-nop branch instruction.  */
1470	  if (trust_limit)
1471	    lim_pc = pc;
1472	  break;
1473	}
1474      else if (((instr & 0x3fLL) != 0LL) &&
1475	       (frameless || ret_reg != 0))
1476	{
1477	  /* Exit loop upon hitting a predicated instruction if
1478	     we already have the return register or if we are frameless.  */
1479	  if (trust_limit)
1480	    lim_pc = pc;
1481	  break;
1482	}
1483      else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
1484        {
1485	  /* Move from BR */
1486	  int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1487	  int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1488	  int qp = (int) (instr & 0x0000000003f);
1489
1490	  if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1491	    {
1492	      ret_reg = rN;
1493	      last_prologue_pc = next_pc;
1494	    }
1495	}
1496      else if ((it == I || it == M)
1497          && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1498	{
1499	  /* adds rN = imm14, rM   (or mov rN, rM  when imm14 is 0) */
1500	  int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1501	                   | ((instr & 0x001f8000000LL) >> 20)
1502		           | ((instr & 0x000000fe000LL) >> 13));
1503	  int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1504	  int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1505	  int qp = (int) (instr & 0x0000000003fLL);
1506
1507	  if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1508	    {
1509	      /* mov rN, r12 */
1510	      fp_reg = rN;
1511	      last_prologue_pc = next_pc;
1512	    }
1513	  else if (qp == 0 && rN == 12 && rM == 12)
1514	    {
1515	      /* adds r12, -mem_stack_frame_size, r12 */
1516	      mem_stack_frame_size -= imm;
1517	      last_prologue_pc = next_pc;
1518	    }
1519	  else if (qp == 0 && rN == 2
1520	        && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1521	    {
1522	      char buf[MAX_REGISTER_SIZE];
1523	      CORE_ADDR saved_sp = 0;
1524	      /* adds r2, spilloffset, rFramePointer
1525	           or
1526		 adds r2, spilloffset, r12
1527
1528	         Get ready for stf.spill or st8.spill instructions.
1529		 The address to start spilling at is loaded into r2.
1530		 FIXME:  Why r2?  That's what gcc currently uses; it
1531		 could well be different for other compilers.  */
1532
1533	      /* Hmm...  whether or not this will work will depend on
1534	         where the pc is.  If it's still early in the prologue
1535		 this'll be wrong.  FIXME */
1536	      if (this_frame)
1537		{
1538		  struct gdbarch *gdbarch = get_frame_arch (this_frame);
1539		  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1540		  get_frame_register (this_frame, sp_regnum, buf);
1541		  saved_sp = extract_unsigned_integer (buf, 8, byte_order);
1542		}
1543	      spill_addr  = saved_sp
1544	                  + (rM == 12 ? 0 : mem_stack_frame_size)
1545			  + imm;
1546	      spill_reg   = rN;
1547	      last_prologue_pc = next_pc;
1548	    }
1549	  else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM-32] &&
1550		   rN < 256 && imm == 0)
1551	    {
1552	      /* mov rN, rM where rM is an input register.  */
1553	      reg_contents[rN] = rM;
1554	      last_prologue_pc = next_pc;
1555	    }
1556	  else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1557		   rM == 2)
1558	    {
1559	      /* mov r12, r2 */
1560	      last_prologue_pc = next_pc;
1561	      break;
1562	    }
1563	}
1564      else if (it == M
1565            && (   ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1566                || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1567	{
1568	  /* stf.spill [rN] = fM, imm9
1569	     or
1570	     stf.spill [rN] = fM  */
1571
1572	  int imm = imm9(instr);
1573	  int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1574	  int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1575	  int qp = (int) (instr & 0x0000000003fLL);
1576	  if (qp == 0 && rN == spill_reg && spill_addr != 0
1577	      && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1578	    {
1579	      cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
1580
1581              if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1582		spill_addr += imm;
1583	      else
1584		spill_addr = 0;		/* last one; must be done.  */
1585	      last_prologue_pc = next_pc;
1586	    }
1587	}
1588      else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1589            || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1590	{
1591	  /* mov.m rN = arM
1592	       or
1593	     mov.i rN = arM */
1594
1595	  int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1596	  int rN  = (int) ((instr & 0x00000001fc0LL) >> 6);
1597	  int qp  = (int) (instr & 0x0000000003fLL);
1598	  if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1599	    {
1600	      /* We have something like "mov.m r3 = ar.unat".  Remember the
1601		 r3 (or whatever) and watch for a store of this register...  */
1602	      unat_save_reg = rN;
1603	      last_prologue_pc = next_pc;
1604	    }
1605	}
1606      else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1607	{
1608	  /* mov rN = pr */
1609	  int rN  = (int) ((instr & 0x00000001fc0LL) >> 6);
1610	  int qp  = (int) (instr & 0x0000000003fLL);
1611	  if (qp == 0 && isScratch (rN))
1612	    {
1613	      pr_save_reg = rN;
1614	      last_prologue_pc = next_pc;
1615	    }
1616	}
1617      else if (it == M
1618            && (   ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1619	        || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1620	{
1621	  /* st8 [rN] = rM
1622	      or
1623	     st8 [rN] = rM, imm9 */
1624	  int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1625	  int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1626	  int qp = (int) (instr & 0x0000000003fLL);
1627	  int indirect = rM < 256 ? reg_contents[rM] : 0;
1628	  if (qp == 0 && rN == spill_reg && spill_addr != 0
1629	      && (rM == unat_save_reg || rM == pr_save_reg))
1630	    {
1631	      /* We've found a spill of either the UNAT register or the PR
1632	         register.  (Well, not exactly; what we've actually found is
1633		 a spill of the register that UNAT or PR was moved to).
1634		 Record that fact and move on...  */
1635	      if (rM == unat_save_reg)
1636		{
1637		  /* Track UNAT register.  */
1638		  cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
1639		  unat_save_reg = 0;
1640		}
1641	      else
1642	        {
1643		  /* Track PR register.  */
1644		  cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
1645		  pr_save_reg = 0;
1646		}
1647	      if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1648		/* st8 [rN] = rM, imm9 */
1649		spill_addr += imm9(instr);
1650	      else
1651		spill_addr = 0;		/* Must be done spilling.  */
1652	      last_prologue_pc = next_pc;
1653	    }
1654	  else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1655	    {
1656	      /* Allow up to one store of each input register.  */
1657	      instores[rM-32] = 1;
1658	      last_prologue_pc = next_pc;
1659	    }
1660	  else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1661		   !instores[indirect-32])
1662	    {
1663	      /* Allow an indirect store of an input register.  */
1664	      instores[indirect-32] = 1;
1665	      last_prologue_pc = next_pc;
1666	    }
1667	}
1668      else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1669	{
1670	  /* One of
1671	       st1 [rN] = rM
1672	       st2 [rN] = rM
1673	       st4 [rN] = rM
1674	       st8 [rN] = rM
1675	     Note that the st8 case is handled in the clause above.
1676
1677	     Advance over stores of input registers.  One store per input
1678	     register is permitted.  */
1679	  int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1680	  int qp = (int) (instr & 0x0000000003fLL);
1681	  int indirect = rM < 256 ? reg_contents[rM] : 0;
1682	  if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1683	    {
1684	      instores[rM-32] = 1;
1685	      last_prologue_pc = next_pc;
1686	    }
1687	  else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1688		   !instores[indirect-32])
1689	    {
1690	      /* Allow an indirect store of an input register.  */
1691	      instores[indirect-32] = 1;
1692	      last_prologue_pc = next_pc;
1693	    }
1694	}
1695      else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1696        {
1697	  /* Either
1698	       stfs [rN] = fM
1699	     or
1700	       stfd [rN] = fM
1701
1702	     Advance over stores of floating point input registers.  Again
1703	     one store per register is permitted.  */
1704	  int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1705	  int qp = (int) (instr & 0x0000000003fLL);
1706	  if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1707	    {
1708	      infpstores[fM-8] = 1;
1709	      last_prologue_pc = next_pc;
1710	    }
1711	}
1712      else if (it == M
1713            && (   ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1714	        || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1715	{
1716	  /* st8.spill [rN] = rM
1717	       or
1718	     st8.spill [rN] = rM, imm9 */
1719	  int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1720	  int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1721	  int qp = (int) (instr & 0x0000000003fLL);
1722	  if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1723	    {
1724	      /* We've found a spill of one of the preserved general purpose
1725	         regs.  Record the spill address and advance the spill
1726		 register if appropriate.  */
1727	      cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1728	      if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1729	        /* st8.spill [rN] = rM, imm9 */
1730		spill_addr += imm9(instr);
1731	      else
1732		spill_addr = 0;		/* Done spilling.  */
1733	      last_prologue_pc = next_pc;
1734	    }
1735	}
1736
1737      pc = next_pc;
1738    }
1739
1740  /* If not frameless and we aren't called by skip_prologue, then we need
1741     to calculate registers for the previous frame which will be needed
1742     later.  */
1743
1744  if (!frameless && this_frame)
1745    {
1746      struct gdbarch *gdbarch = get_frame_arch (this_frame);
1747      enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1748
1749      /* Extract the size of the rotating portion of the stack
1750	 frame and the register rename base from the current
1751	 frame marker.  */
1752      cfm = cache->cfm;
1753      sor = cache->sor;
1754      sof = cache->sof;
1755      sol = cache->sol;
1756      rrb_gr = (cfm >> 18) & 0x7f;
1757
1758      /* Find the bof (beginning of frame).  */
1759      bof = rse_address_add (cache->bsp, -sof);
1760
1761      for (i = 0, addr = bof;
1762	   i < sof;
1763	   i++, addr += 8)
1764	{
1765	  if (IS_NaT_COLLECTION_ADDR (addr))
1766	    {
1767	      addr += 8;
1768	    }
1769	  if (i+32 == cfm_reg)
1770	    cache->saved_regs[IA64_CFM_REGNUM] = addr;
1771	  if (i+32 == ret_reg)
1772	    cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1773	  if (i+32 == fp_reg)
1774	    cache->saved_regs[IA64_VFP_REGNUM] = addr;
1775	}
1776
1777      /* For the previous argument registers we require the previous bof.
1778	 If we can't find the previous cfm, then we can do nothing.  */
1779      cfm = 0;
1780      if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1781	{
1782	  cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM],
1783				     8, byte_order);
1784	}
1785      else if (cfm_reg != 0)
1786	{
1787	  get_frame_register (this_frame, cfm_reg, buf);
1788	  cfm = extract_unsigned_integer (buf, 8, byte_order);
1789	}
1790      cache->prev_cfm = cfm;
1791
1792      if (cfm != 0)
1793	{
1794	  sor = ((cfm >> 14) & 0xf) * 8;
1795	  sof = (cfm & 0x7f);
1796	  sol = (cfm >> 7) & 0x7f;
1797	  rrb_gr = (cfm >> 18) & 0x7f;
1798
1799	  /* The previous bof only requires subtraction of the sol (size of
1800             locals) due to the overlap between output and input of
1801             subsequent frames.  */
1802	  bof = rse_address_add (bof, -sol);
1803
1804	  for (i = 0, addr = bof;
1805	       i < sof;
1806	       i++, addr += 8)
1807	    {
1808	      if (IS_NaT_COLLECTION_ADDR (addr))
1809		{
1810		  addr += 8;
1811		}
1812	      if (i < sor)
1813		cache->saved_regs[IA64_GR32_REGNUM
1814				  + ((i + (sor - rrb_gr)) % sor)]
1815		  = addr;
1816	      else
1817		cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1818	    }
1819
1820	}
1821    }
1822
1823  /* Try and trust the lim_pc value whenever possible.  */
1824  if (trust_limit && lim_pc >= last_prologue_pc)
1825    last_prologue_pc = lim_pc;
1826
1827  cache->frameless = frameless;
1828  cache->after_prologue = last_prologue_pc;
1829  cache->mem_stack_frame_size = mem_stack_frame_size;
1830  cache->fp_reg = fp_reg;
1831
1832  return last_prologue_pc;
1833}
1834
1835CORE_ADDR
1836ia64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1837{
1838  struct ia64_frame_cache cache;
1839  cache.base = 0;
1840  cache.after_prologue = 0;
1841  cache.cfm = 0;
1842  cache.bsp = 0;
1843
1844  /* Call examine_prologue with - as third argument since we don't
1845     have a next frame pointer to send.  */
1846  return examine_prologue (pc, pc+1024, 0, &cache);
1847}
1848
1849
1850/* Normal frames.  */
1851
1852static struct ia64_frame_cache *
1853ia64_frame_cache (struct frame_info *this_frame, void **this_cache)
1854{
1855  struct gdbarch *gdbarch = get_frame_arch (this_frame);
1856  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1857  struct ia64_frame_cache *cache;
1858  char buf[8];
1859  CORE_ADDR cfm, sof, sol, bsp, psr;
1860  int i;
1861
1862  if (*this_cache)
1863    return *this_cache;
1864
1865  cache = ia64_alloc_frame_cache ();
1866  *this_cache = cache;
1867
1868  get_frame_register (this_frame, sp_regnum, buf);
1869  cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
1870
1871  /* We always want the bsp to point to the end of frame.
1872     This way, we can always get the beginning of frame (bof)
1873     by subtracting frame size.  */
1874  get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
1875  cache->bsp = extract_unsigned_integer (buf, 8, byte_order);
1876
1877  get_frame_register (this_frame, IA64_PSR_REGNUM, buf);
1878  psr = extract_unsigned_integer (buf, 8, byte_order);
1879
1880  get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
1881  cfm = extract_unsigned_integer (buf, 8, byte_order);
1882
1883  cache->sof = (cfm & 0x7f);
1884  cache->sol = (cfm >> 7) & 0x7f;
1885  cache->sor = ((cfm >> 14) & 0xf) * 8;
1886
1887  cache->cfm = cfm;
1888
1889  cache->pc = get_frame_func (this_frame);
1890
1891  if (cache->pc != 0)
1892    examine_prologue (cache->pc, get_frame_pc (this_frame), this_frame, cache);
1893
1894  cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1895
1896  return cache;
1897}
1898
1899static void
1900ia64_frame_this_id (struct frame_info *this_frame, void **this_cache,
1901		    struct frame_id *this_id)
1902{
1903  struct gdbarch *gdbarch = get_frame_arch (this_frame);
1904  struct ia64_frame_cache *cache =
1905    ia64_frame_cache (this_frame, this_cache);
1906
1907  /* If outermost frame, mark with null frame id.  */
1908  if (cache->base != 0)
1909    (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
1910  if (gdbarch_debug >= 1)
1911    fprintf_unfiltered (gdb_stdlog,
1912			"regular frame id: code %s, stack %s, "
1913			"special %s, this_frame %s\n",
1914			paddress (gdbarch, this_id->code_addr),
1915			paddress (gdbarch, this_id->stack_addr),
1916			paddress (gdbarch, cache->bsp),
1917			host_address_to_string (this_frame));
1918}
1919
1920static struct value *
1921ia64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1922			  int regnum)
1923{
1924  struct gdbarch *gdbarch = get_frame_arch (this_frame);
1925  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1926  struct ia64_frame_cache *cache = ia64_frame_cache (this_frame, this_cache);
1927  char buf[8];
1928
1929  gdb_assert (regnum >= 0);
1930
1931  if (!target_has_registers)
1932    error (_("No registers."));
1933
1934  if (regnum == gdbarch_sp_regnum (gdbarch))
1935    return frame_unwind_got_constant (this_frame, regnum, cache->base);
1936
1937  else if (regnum == IA64_BSP_REGNUM)
1938    {
1939      struct value *val;
1940      CORE_ADDR prev_cfm, bsp, prev_bsp;
1941
1942      /* We want to calculate the previous bsp as the end of the previous
1943         register stack frame.  This corresponds to what the hardware bsp
1944         register will be if we pop the frame back which is why we might
1945         have been called.  We know the beginning of the current frame is
1946         cache->bsp - cache->sof.  This value in the previous frame points
1947         to the start of the output registers.  We can calculate the end of
1948         that frame by adding the size of output:
1949            (sof (size of frame) - sol (size of locals)).  */
1950      val = ia64_frame_prev_register (this_frame, this_cache, IA64_CFM_REGNUM);
1951      prev_cfm = extract_unsigned_integer (value_contents_all (val),
1952					   8, byte_order);
1953      bsp = rse_address_add (cache->bsp, -(cache->sof));
1954      prev_bsp =
1955        rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1956
1957      return frame_unwind_got_constant (this_frame, regnum, prev_bsp);
1958    }
1959
1960  else if (regnum == IA64_CFM_REGNUM)
1961    {
1962      CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1963
1964      if (addr != 0)
1965        return frame_unwind_got_memory (this_frame, regnum, addr);
1966
1967      if (cache->prev_cfm)
1968        return frame_unwind_got_constant (this_frame, regnum, cache->prev_cfm);
1969
1970      if (cache->frameless)
1971        return frame_unwind_got_register (this_frame, IA64_PFS_REGNUM,
1972                                          IA64_PFS_REGNUM);
1973      return frame_unwind_got_register (this_frame, regnum, 0);
1974    }
1975
1976  else if (regnum == IA64_VFP_REGNUM)
1977    {
1978      /* If the function in question uses an automatic register (r32-r127)
1979         for the frame pointer, it'll be found by ia64_find_saved_register()
1980	 above.  If the function lacks one of these frame pointers, we can
1981	 still provide a value since we know the size of the frame.  */
1982      return frame_unwind_got_constant (this_frame, regnum, cache->base);
1983    }
1984
1985  else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1986    {
1987      struct value *pr_val;
1988      ULONGEST prN;
1989
1990      pr_val = ia64_frame_prev_register (this_frame, this_cache,
1991                                         IA64_PR_REGNUM);
1992      if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1993	{
1994	  /* Fetch predicate register rename base from current frame
1995	     marker for this frame.  */
1996	  int rrb_pr = (cache->cfm >> 32) & 0x3f;
1997
1998	  /* Adjust the register number to account for register rotation.  */
1999	  regnum = VP16_REGNUM + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2000	}
2001      prN = extract_bit_field (value_contents_all (pr_val),
2002                               regnum - VP0_REGNUM, 1);
2003      return frame_unwind_got_constant (this_frame, regnum, prN);
2004    }
2005
2006  else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
2007    {
2008      struct value *unat_val;
2009      ULONGEST unatN;
2010      unat_val = ia64_frame_prev_register (this_frame, this_cache,
2011                                           IA64_UNAT_REGNUM);
2012      unatN = extract_bit_field (value_contents_all (unat_val),
2013                                 regnum - IA64_NAT0_REGNUM, 1);
2014      return frame_unwind_got_constant (this_frame, regnum, unatN);
2015    }
2016
2017  else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2018    {
2019      int natval = 0;
2020      /* Find address of general register corresponding to nat bit we're
2021         interested in.  */
2022      CORE_ADDR gr_addr;
2023
2024      gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM + IA64_GR0_REGNUM];
2025
2026      if (gr_addr != 0)
2027	{
2028	  /* Compute address of nat collection bits.  */
2029	  CORE_ADDR nat_addr = gr_addr | 0x1f8;
2030	  CORE_ADDR bsp;
2031	  CORE_ADDR nat_collection;
2032	  int nat_bit;
2033
2034	  /* If our nat collection address is bigger than bsp, we have to get
2035	     the nat collection from rnat.  Otherwise, we fetch the nat
2036	     collection from the computed address.  */
2037	  get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2038	  bsp = extract_unsigned_integer (buf, 8, byte_order);
2039	  if (nat_addr >= bsp)
2040	    {
2041	      get_frame_register (this_frame, IA64_RNAT_REGNUM, buf);
2042	      nat_collection = extract_unsigned_integer (buf, 8, byte_order);
2043	    }
2044	  else
2045	    nat_collection = read_memory_integer (nat_addr, 8, byte_order);
2046	  nat_bit = (gr_addr >> 3) & 0x3f;
2047	  natval = (nat_collection >> nat_bit) & 1;
2048	}
2049
2050      return frame_unwind_got_constant (this_frame, regnum, natval);
2051    }
2052
2053  else if (regnum == IA64_IP_REGNUM)
2054    {
2055      CORE_ADDR pc = 0;
2056      CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2057
2058      if (addr != 0)
2059        {
2060          read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
2061          pc = extract_unsigned_integer (buf, 8, byte_order);
2062        }
2063      else if (cache->frameless)
2064	{
2065	  get_frame_register (this_frame, IA64_BR0_REGNUM, buf);
2066	  pc = extract_unsigned_integer (buf, 8, byte_order);
2067	}
2068      pc &= ~0xf;
2069      return frame_unwind_got_constant (this_frame, regnum, pc);
2070    }
2071
2072  else if (regnum == IA64_PSR_REGNUM)
2073    {
2074      /* We don't know how to get the complete previous PSR, but we need it
2075         for the slot information when we unwind the pc (pc is formed of IP
2076         register plus slot information from PSR).  To get the previous
2077         slot information, we mask it off the return address.  */
2078      ULONGEST slot_num = 0;
2079      CORE_ADDR pc = 0;
2080      CORE_ADDR psr = 0;
2081      CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2082
2083      get_frame_register (this_frame, IA64_PSR_REGNUM, buf);
2084      psr = extract_unsigned_integer (buf, 8, byte_order);
2085
2086      if (addr != 0)
2087	{
2088	  read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
2089	  pc = extract_unsigned_integer (buf, 8, byte_order);
2090	}
2091      else if (cache->frameless)
2092	{
2093	  get_frame_register (this_frame, IA64_BR0_REGNUM, buf);
2094	  pc = extract_unsigned_integer (buf, 8, byte_order);
2095	}
2096      psr &= ~(3LL << 41);
2097      slot_num = pc & 0x3LL;
2098      psr |= (CORE_ADDR)slot_num << 41;
2099      return frame_unwind_got_constant (this_frame, regnum, psr);
2100    }
2101
2102  else if (regnum == IA64_BR0_REGNUM)
2103    {
2104      CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
2105
2106      if (addr != 0)
2107        return frame_unwind_got_memory (this_frame, regnum, addr);
2108
2109      return frame_unwind_got_constant (this_frame, regnum, 0);
2110    }
2111
2112  else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM)
2113           || (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2114    {
2115      CORE_ADDR addr = 0;
2116
2117      if (regnum >= V32_REGNUM)
2118	regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2119      addr = cache->saved_regs[regnum];
2120      if (addr != 0)
2121        return frame_unwind_got_memory (this_frame, regnum, addr);
2122
2123      if (cache->frameless)
2124        {
2125          struct value *reg_val;
2126          CORE_ADDR prev_cfm, prev_bsp, prev_bof;
2127
2128          /* FIXME: brobecker/2008-05-01: Doesn't this seem redundant
2129             with the same code above?  */
2130	  if (regnum >= V32_REGNUM)
2131	    regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2132          reg_val = ia64_frame_prev_register (this_frame, this_cache,
2133                                              IA64_CFM_REGNUM);
2134	  prev_cfm = extract_unsigned_integer (value_contents_all (reg_val),
2135                                               8, byte_order);
2136	  reg_val = ia64_frame_prev_register (this_frame, this_cache,
2137                                              IA64_BSP_REGNUM);
2138	  prev_bsp = extract_unsigned_integer (value_contents_all (reg_val),
2139                                               8, byte_order);
2140	  prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
2141
2142	  addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
2143          return frame_unwind_got_memory (this_frame, regnum, addr);
2144        }
2145
2146      return frame_unwind_got_constant (this_frame, regnum, 0);
2147    }
2148
2149  else /* All other registers.  */
2150    {
2151      CORE_ADDR addr = 0;
2152
2153      if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
2154	{
2155	  /* Fetch floating point register rename base from current
2156	     frame marker for this frame.  */
2157	  int rrb_fr = (cache->cfm >> 25) & 0x7f;
2158
2159	  /* Adjust the floating point register number to account for
2160	     register rotation.  */
2161	  regnum = IA64_FR32_REGNUM
2162	         + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
2163	}
2164
2165      /* If we have stored a memory address, access the register.  */
2166      addr = cache->saved_regs[regnum];
2167      if (addr != 0)
2168        return frame_unwind_got_memory (this_frame, regnum, addr);
2169      /* Otherwise, punt and get the current value of the register.  */
2170      else
2171        return frame_unwind_got_register (this_frame, regnum, regnum);
2172    }
2173}
2174
2175static const struct frame_unwind ia64_frame_unwind =
2176{
2177  NORMAL_FRAME,
2178  default_frame_unwind_stop_reason,
2179  &ia64_frame_this_id,
2180  &ia64_frame_prev_register,
2181  NULL,
2182  default_frame_sniffer
2183};
2184
2185/* Signal trampolines.  */
2186
2187static void
2188ia64_sigtramp_frame_init_saved_regs (struct frame_info *this_frame,
2189				     struct ia64_frame_cache *cache)
2190{
2191  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2192  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2193
2194  if (tdep->sigcontext_register_address)
2195    {
2196      int regno;
2197
2198      cache->saved_regs[IA64_VRAP_REGNUM]
2199	= tdep->sigcontext_register_address (gdbarch, cache->base,
2200					     IA64_IP_REGNUM);
2201      cache->saved_regs[IA64_CFM_REGNUM]
2202	= tdep->sigcontext_register_address (gdbarch, cache->base,
2203					     IA64_CFM_REGNUM);
2204      cache->saved_regs[IA64_PSR_REGNUM]
2205	= tdep->sigcontext_register_address (gdbarch, cache->base,
2206					     IA64_PSR_REGNUM);
2207      cache->saved_regs[IA64_BSP_REGNUM]
2208	= tdep->sigcontext_register_address (gdbarch, cache->base,
2209					     IA64_BSP_REGNUM);
2210      cache->saved_regs[IA64_RNAT_REGNUM]
2211	= tdep->sigcontext_register_address (gdbarch, cache->base,
2212					     IA64_RNAT_REGNUM);
2213      cache->saved_regs[IA64_CCV_REGNUM]
2214	= tdep->sigcontext_register_address (gdbarch, cache->base,
2215					     IA64_CCV_REGNUM);
2216      cache->saved_regs[IA64_UNAT_REGNUM]
2217	= tdep->sigcontext_register_address (gdbarch, cache->base,
2218					     IA64_UNAT_REGNUM);
2219      cache->saved_regs[IA64_FPSR_REGNUM]
2220	= tdep->sigcontext_register_address (gdbarch, cache->base,
2221					     IA64_FPSR_REGNUM);
2222      cache->saved_regs[IA64_PFS_REGNUM]
2223	= tdep->sigcontext_register_address (gdbarch, cache->base,
2224					     IA64_PFS_REGNUM);
2225      cache->saved_regs[IA64_LC_REGNUM]
2226	= tdep->sigcontext_register_address (gdbarch, cache->base,
2227					     IA64_LC_REGNUM);
2228
2229      for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
2230	cache->saved_regs[regno] =
2231	  tdep->sigcontext_register_address (gdbarch, cache->base, regno);
2232      for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
2233	cache->saved_regs[regno] =
2234	  tdep->sigcontext_register_address (gdbarch, cache->base, regno);
2235      for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
2236	cache->saved_regs[regno] =
2237	  tdep->sigcontext_register_address (gdbarch, cache->base, regno);
2238    }
2239}
2240
2241static struct ia64_frame_cache *
2242ia64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2243{
2244  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2245  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2246  struct ia64_frame_cache *cache;
2247  CORE_ADDR addr;
2248  char buf[8];
2249  int i;
2250
2251  if (*this_cache)
2252    return *this_cache;
2253
2254  cache = ia64_alloc_frame_cache ();
2255
2256  get_frame_register (this_frame, sp_regnum, buf);
2257  /* Note that frame size is hard-coded below.  We cannot calculate it
2258     via prologue examination.  */
2259  cache->base = extract_unsigned_integer (buf, 8, byte_order) + 16;
2260
2261  get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2262  cache->bsp = extract_unsigned_integer (buf, 8, byte_order);
2263
2264  get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
2265  cache->cfm = extract_unsigned_integer (buf, 8, byte_order);
2266  cache->sof = cache->cfm & 0x7f;
2267
2268  ia64_sigtramp_frame_init_saved_regs (this_frame, cache);
2269
2270  *this_cache = cache;
2271  return cache;
2272}
2273
2274static void
2275ia64_sigtramp_frame_this_id (struct frame_info *this_frame,
2276			     void **this_cache, struct frame_id *this_id)
2277{
2278  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2279  struct ia64_frame_cache *cache =
2280    ia64_sigtramp_frame_cache (this_frame, this_cache);
2281
2282  (*this_id) = frame_id_build_special (cache->base,
2283                                       get_frame_pc (this_frame),
2284                                       cache->bsp);
2285  if (gdbarch_debug >= 1)
2286    fprintf_unfiltered (gdb_stdlog,
2287			"sigtramp frame id: code %s, stack %s, "
2288			"special %s, this_frame %s\n",
2289			paddress (gdbarch, this_id->code_addr),
2290			paddress (gdbarch, this_id->stack_addr),
2291			paddress (gdbarch, cache->bsp),
2292			host_address_to_string (this_frame));
2293}
2294
2295static struct value *
2296ia64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2297				   void **this_cache, int regnum)
2298{
2299  char buf[MAX_REGISTER_SIZE];
2300
2301  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2302  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2303  struct ia64_frame_cache *cache =
2304    ia64_sigtramp_frame_cache (this_frame, this_cache);
2305
2306  gdb_assert (regnum >= 0);
2307
2308  if (!target_has_registers)
2309    error (_("No registers."));
2310
2311  if (regnum == IA64_IP_REGNUM)
2312    {
2313      CORE_ADDR pc = 0;
2314      CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2315
2316      if (addr != 0)
2317	{
2318	  read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
2319	  pc = extract_unsigned_integer (buf, 8, byte_order);
2320	}
2321      pc &= ~0xf;
2322      return frame_unwind_got_constant (this_frame, regnum, pc);
2323    }
2324
2325  else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM)
2326           || (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2327    {
2328      CORE_ADDR addr = 0;
2329
2330      if (regnum >= V32_REGNUM)
2331	regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2332      addr = cache->saved_regs[regnum];
2333      if (addr != 0)
2334        return frame_unwind_got_memory (this_frame, regnum, addr);
2335
2336      return frame_unwind_got_constant (this_frame, regnum, 0);
2337    }
2338
2339  else  /* All other registers not listed above.  */
2340    {
2341      CORE_ADDR addr = cache->saved_regs[regnum];
2342
2343      if (addr != 0)
2344        return frame_unwind_got_memory (this_frame, regnum, addr);
2345
2346      return frame_unwind_got_constant (this_frame, regnum, 0);
2347    }
2348}
2349
2350static int
2351ia64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2352                             struct frame_info *this_frame,
2353                             void **this_cache)
2354{
2355  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2356  if (tdep->pc_in_sigtramp)
2357    {
2358      CORE_ADDR pc = get_frame_pc (this_frame);
2359
2360      if (tdep->pc_in_sigtramp (pc))
2361	return 1;
2362    }
2363
2364  return 0;
2365}
2366
2367static const struct frame_unwind ia64_sigtramp_frame_unwind =
2368{
2369  SIGTRAMP_FRAME,
2370  default_frame_unwind_stop_reason,
2371  ia64_sigtramp_frame_this_id,
2372  ia64_sigtramp_frame_prev_register,
2373  NULL,
2374  ia64_sigtramp_frame_sniffer
2375};
2376
2377
2378
2379static CORE_ADDR
2380ia64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2381{
2382  struct ia64_frame_cache *cache = ia64_frame_cache (this_frame, this_cache);
2383
2384  return cache->base;
2385}
2386
2387static const struct frame_base ia64_frame_base =
2388{
2389  &ia64_frame_unwind,
2390  ia64_frame_base_address,
2391  ia64_frame_base_address,
2392  ia64_frame_base_address
2393};
2394
2395#ifdef HAVE_LIBUNWIND_IA64_H
2396
2397struct ia64_unwind_table_entry
2398  {
2399    unw_word_t start_offset;
2400    unw_word_t end_offset;
2401    unw_word_t info_offset;
2402  };
2403
2404static __inline__ uint64_t
2405ia64_rse_slot_num (uint64_t addr)
2406{
2407  return (addr >> 3) & 0x3f;
2408}
2409
2410/* Skip over a designated number of registers in the backing
2411   store, remembering every 64th position is for NAT.  */
2412static __inline__ uint64_t
2413ia64_rse_skip_regs (uint64_t addr, long num_regs)
2414{
2415  long delta = ia64_rse_slot_num(addr) + num_regs;
2416
2417  if (num_regs < 0)
2418    delta -= 0x3e;
2419  return addr + ((num_regs + delta/0x3f) << 3);
2420}
2421
2422/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2423   number to a libunwind register number.  */
2424static int
2425ia64_gdb2uw_regnum (int regnum)
2426{
2427  if (regnum == sp_regnum)
2428    return UNW_IA64_SP;
2429  else if (regnum == IA64_BSP_REGNUM)
2430    return UNW_IA64_BSP;
2431  else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2432    return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2433  else if ((unsigned) (regnum - V32_REGNUM) < 95)
2434    return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2435  else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2436    return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2437  else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2438    return -1;
2439  else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2440    return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2441  else if (regnum == IA64_PR_REGNUM)
2442    return UNW_IA64_PR;
2443  else if (regnum == IA64_IP_REGNUM)
2444    return UNW_REG_IP;
2445  else if (regnum == IA64_CFM_REGNUM)
2446    return UNW_IA64_CFM;
2447  else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2448    return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2449  else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2450    return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2451  else
2452    return -1;
2453}
2454
2455/* Gdb libunwind-frame callback function to convert from a libunwind register
2456   number to a ia64 gdb register number.  */
2457static int
2458ia64_uw2gdb_regnum (int uw_regnum)
2459{
2460  if (uw_regnum == UNW_IA64_SP)
2461    return sp_regnum;
2462  else if (uw_regnum == UNW_IA64_BSP)
2463    return IA64_BSP_REGNUM;
2464  else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2465    return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2466  else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2467    return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2468  else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2469    return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2470  else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2471    return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2472  else if (uw_regnum == UNW_IA64_PR)
2473    return IA64_PR_REGNUM;
2474  else if (uw_regnum == UNW_REG_IP)
2475    return IA64_IP_REGNUM;
2476  else if (uw_regnum == UNW_IA64_CFM)
2477    return IA64_CFM_REGNUM;
2478  else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2479    return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2480  else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2481    return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2482  else
2483    return -1;
2484}
2485
2486/* Gdb libunwind-frame callback function to reveal if register is a float
2487   register or not.  */
2488static int
2489ia64_is_fpreg (int uw_regnum)
2490{
2491  return unw_is_fpreg (uw_regnum);
2492}
2493
2494/* Libunwind callback accessor function for general registers.  */
2495static int
2496ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2497		 int write, void *arg)
2498{
2499  int regnum = ia64_uw2gdb_regnum (uw_regnum);
2500  unw_word_t bsp, sof, sol, cfm, psr, ip;
2501  struct frame_info *this_frame = arg;
2502  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2503  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2504  long new_sof, old_sof;
2505  char buf[MAX_REGISTER_SIZE];
2506
2507  /* We never call any libunwind routines that need to write registers.  */
2508  gdb_assert (!write);
2509
2510  switch (uw_regnum)
2511    {
2512      case UNW_REG_IP:
2513	/* Libunwind expects to see the pc value which means the slot number
2514	   from the psr must be merged with the ip word address.  */
2515	get_frame_register (this_frame, IA64_IP_REGNUM, buf);
2516	ip = extract_unsigned_integer (buf, 8, byte_order);
2517	get_frame_register (this_frame, IA64_PSR_REGNUM, buf);
2518	psr = extract_unsigned_integer (buf, 8, byte_order);
2519	*val = ip | ((psr >> 41) & 0x3);
2520	break;
2521
2522      case UNW_IA64_AR_BSP:
2523	/* Libunwind expects to see the beginning of the current
2524	   register frame so we must account for the fact that
2525	   ptrace() will return a value for bsp that points *after*
2526	   the current register frame.  */
2527	get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2528	bsp = extract_unsigned_integer (buf, 8, byte_order);
2529	get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
2530	cfm = extract_unsigned_integer (buf, 8, byte_order);
2531	sof = gdbarch_tdep (gdbarch)->size_of_register_frame (this_frame, cfm);
2532	*val = ia64_rse_skip_regs (bsp, -sof);
2533	break;
2534
2535      case UNW_IA64_AR_BSPSTORE:
2536	/* Libunwind wants bspstore to be after the current register frame.
2537	   This is what ptrace() and gdb treats as the regular bsp value.  */
2538	get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2539	*val = extract_unsigned_integer (buf, 8, byte_order);
2540	break;
2541
2542      default:
2543	/* For all other registers, just unwind the value directly.  */
2544	get_frame_register (this_frame, regnum, buf);
2545	*val = extract_unsigned_integer (buf, 8, byte_order);
2546	break;
2547    }
2548
2549  if (gdbarch_debug >= 1)
2550    fprintf_unfiltered (gdb_stdlog,
2551			"  access_reg: from cache: %4s=%s\n",
2552			(((unsigned) regnum <= IA64_NAT127_REGNUM)
2553			? ia64_register_names[regnum] : "r??"),
2554			paddress (gdbarch, *val));
2555  return 0;
2556}
2557
2558/* Libunwind callback accessor function for floating-point registers.  */
2559static int
2560ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum,
2561		   unw_fpreg_t *val, int write, void *arg)
2562{
2563  int regnum = ia64_uw2gdb_regnum (uw_regnum);
2564  struct frame_info *this_frame = arg;
2565
2566  /* We never call any libunwind routines that need to write registers.  */
2567  gdb_assert (!write);
2568
2569  get_frame_register (this_frame, regnum, (char *) val);
2570
2571  return 0;
2572}
2573
2574/* Libunwind callback accessor function for top-level rse registers.  */
2575static int
2576ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum,
2577		     unw_word_t *val, int write, void *arg)
2578{
2579  int regnum = ia64_uw2gdb_regnum (uw_regnum);
2580  unw_word_t bsp, sof, sol, cfm, psr, ip;
2581  struct regcache *regcache = arg;
2582  struct gdbarch *gdbarch = get_regcache_arch (regcache);
2583  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2584  long new_sof, old_sof;
2585  char buf[MAX_REGISTER_SIZE];
2586
2587  /* We never call any libunwind routines that need to write registers.  */
2588  gdb_assert (!write);
2589
2590  switch (uw_regnum)
2591    {
2592      case UNW_REG_IP:
2593	/* Libunwind expects to see the pc value which means the slot number
2594	   from the psr must be merged with the ip word address.  */
2595	regcache_cooked_read (regcache, IA64_IP_REGNUM, buf);
2596	ip = extract_unsigned_integer (buf, 8, byte_order);
2597	regcache_cooked_read (regcache, IA64_PSR_REGNUM, buf);
2598	psr = extract_unsigned_integer (buf, 8, byte_order);
2599	*val = ip | ((psr >> 41) & 0x3);
2600	break;
2601
2602      case UNW_IA64_AR_BSP:
2603	/* Libunwind expects to see the beginning of the current
2604	   register frame so we must account for the fact that
2605	   ptrace() will return a value for bsp that points *after*
2606	   the current register frame.  */
2607	regcache_cooked_read (regcache, IA64_BSP_REGNUM, buf);
2608	bsp = extract_unsigned_integer (buf, 8, byte_order);
2609	regcache_cooked_read (regcache, IA64_CFM_REGNUM, buf);
2610	cfm = extract_unsigned_integer (buf, 8, byte_order);
2611	sof = (cfm & 0x7f);
2612	*val = ia64_rse_skip_regs (bsp, -sof);
2613	break;
2614
2615      case UNW_IA64_AR_BSPSTORE:
2616	/* Libunwind wants bspstore to be after the current register frame.
2617	   This is what ptrace() and gdb treats as the regular bsp value.  */
2618	regcache_cooked_read (regcache, IA64_BSP_REGNUM, buf);
2619	*val = extract_unsigned_integer (buf, 8, byte_order);
2620	break;
2621
2622      default:
2623        /* For all other registers, just unwind the value directly.  */
2624	regcache_cooked_read (regcache, regnum, buf);
2625	*val = extract_unsigned_integer (buf, 8, byte_order);
2626	break;
2627    }
2628
2629  if (gdbarch_debug >= 1)
2630    fprintf_unfiltered (gdb_stdlog,
2631			"  access_rse_reg: from cache: %4s=%s\n",
2632			(((unsigned) regnum <= IA64_NAT127_REGNUM)
2633			 ? ia64_register_names[regnum] : "r??"),
2634			paddress (gdbarch, *val));
2635
2636  return 0;
2637}
2638
2639/* Libunwind callback accessor function for top-level fp registers.  */
2640static int
2641ia64_access_rse_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum,
2642		       unw_fpreg_t *val, int write, void *arg)
2643{
2644  int regnum = ia64_uw2gdb_regnum (uw_regnum);
2645  struct regcache *regcache = arg;
2646
2647  /* We never call any libunwind routines that need to write registers.  */
2648  gdb_assert (!write);
2649
2650  regcache_cooked_read (regcache, regnum, (char *) val);
2651
2652  return 0;
2653}
2654
2655/* Libunwind callback accessor function for accessing memory.  */
2656static int
2657ia64_access_mem (unw_addr_space_t as,
2658		 unw_word_t addr, unw_word_t *val,
2659		 int write, void *arg)
2660{
2661  if (addr - KERNEL_START < ktab_size)
2662    {
2663      unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2664                          + (addr - KERNEL_START));
2665
2666      if (write)
2667        *laddr = *val;
2668      else
2669        *val = *laddr;
2670      return 0;
2671    }
2672
2673  /* XXX do we need to normalize byte-order here?  */
2674  if (write)
2675    return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2676  else
2677    return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2678}
2679
2680/* Call low-level function to access the kernel unwind table.  */
2681static LONGEST
2682getunwind_table (gdb_byte **buf_p)
2683{
2684  LONGEST x;
2685
2686  /* FIXME drow/2005-09-10: This code used to call
2687     ia64_linux_xfer_unwind_table directly to fetch the unwind table
2688     for the currently running ia64-linux kernel.  That data should
2689     come from the core file and be accessed via the auxv vector; if
2690     we want to preserve fall back to the running kernel's table, then
2691     we should find a way to override the corefile layer's
2692     xfer_partial method.  */
2693
2694  x = target_read_alloc (&current_target, TARGET_OBJECT_UNWIND_TABLE,
2695			 NULL, buf_p);
2696
2697  return x;
2698}
2699
2700/* Get the kernel unwind table.  */
2701static int
2702get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2703{
2704  static struct ia64_table_entry *etab;
2705
2706  if (!ktab)
2707    {
2708      gdb_byte *ktab_buf;
2709      LONGEST size;
2710
2711      size = getunwind_table (&ktab_buf);
2712      if (size <= 0)
2713	return -UNW_ENOINFO;
2714
2715      ktab = (struct ia64_table_entry *) ktab_buf;
2716      ktab_size = size;
2717
2718      for (etab = ktab; etab->start_offset; ++etab)
2719        etab->info_offset += KERNEL_START;
2720    }
2721
2722  if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2723    return -UNW_ENOINFO;
2724
2725  di->format = UNW_INFO_FORMAT_TABLE;
2726  di->gp = 0;
2727  di->start_ip = ktab[0].start_offset;
2728  di->end_ip = etab[-1].end_offset;
2729  di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2730  di->u.ti.segbase = 0;
2731  di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2732  di->u.ti.table_data = (unw_word_t *) ktab;
2733
2734  if (gdbarch_debug >= 1)
2735    fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
2736			"segbase=%s, length=%s, gp=%s\n",
2737			(char *) di->u.ti.name_ptr,
2738			hex_string (di->u.ti.segbase),
2739			pulongest (di->u.ti.table_len),
2740			hex_string (di->gp));
2741  return 0;
2742}
2743
2744/* Find the unwind table entry for a specified address.  */
2745static int
2746ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2747			unw_dyn_info_t *dip, void **buf)
2748{
2749  Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2750  Elf_Internal_Ehdr *ehdr;
2751  unw_word_t segbase = 0;
2752  CORE_ADDR load_base;
2753  bfd *bfd;
2754  int i;
2755
2756  bfd = objfile->obfd;
2757
2758  ehdr = elf_tdata (bfd)->elf_header;
2759  phdr = elf_tdata (bfd)->phdr;
2760
2761  load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2762
2763  for (i = 0; i < ehdr->e_phnum; ++i)
2764    {
2765      switch (phdr[i].p_type)
2766	{
2767	case PT_LOAD:
2768	  if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2769	      < phdr[i].p_memsz)
2770	    p_text = phdr + i;
2771	  break;
2772
2773	case PT_IA_64_UNWIND:
2774	  p_unwind = phdr + i;
2775	  break;
2776
2777	default:
2778	  break;
2779	}
2780    }
2781
2782  if (!p_text || !p_unwind)
2783    return -UNW_ENOINFO;
2784
2785  /* Verify that the segment that contains the IP also contains
2786     the static unwind table.  If not, we may be in the Linux kernel's
2787     DSO gate page in which case the unwind table is another segment.
2788     Otherwise, we are dealing with runtime-generated code, for which we
2789     have no info here.  */
2790  segbase = p_text->p_vaddr + load_base;
2791
2792  if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2793    {
2794      int ok = 0;
2795      for (i = 0; i < ehdr->e_phnum; ++i)
2796        {
2797          if (phdr[i].p_type == PT_LOAD
2798	      && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2799	    {
2800              ok = 1;
2801	      /* Get the segbase from the section containing the
2802		 libunwind table.  */
2803	      segbase = phdr[i].p_vaddr + load_base;
2804	    }
2805	}
2806      if (!ok)
2807        return -UNW_ENOINFO;
2808    }
2809
2810  dip->start_ip = p_text->p_vaddr + load_base;
2811  dip->end_ip = dip->start_ip + p_text->p_memsz;
2812  dip->gp = ia64_find_global_pointer (get_objfile_arch (objfile), ip);
2813  dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2814  dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2815  dip->u.rti.segbase = segbase;
2816  dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2817  dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
2818
2819  return 0;
2820}
2821
2822/* Libunwind callback accessor function to acquire procedure unwind-info.  */
2823static int
2824ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2825		       int need_unwind_info, void *arg)
2826{
2827  struct obj_section *sec = find_pc_section (ip);
2828  unw_dyn_info_t di;
2829  int ret;
2830  void *buf = NULL;
2831
2832  if (!sec)
2833    {
2834      /* XXX This only works if the host and the target architecture are
2835	 both ia64 and if the have (more or less) the same kernel
2836	 version.  */
2837      if (get_kernel_table (ip, &di) < 0)
2838	return -UNW_ENOINFO;
2839
2840      if (gdbarch_debug >= 1)
2841	fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: %s -> "
2842			    "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2843			    "length=%s,data=%s)\n",
2844			    hex_string (ip), (char *)di.u.ti.name_ptr,
2845			    hex_string (di.u.ti.segbase),
2846			    hex_string (di.start_ip), hex_string (di.end_ip),
2847			    hex_string (di.gp),
2848			    pulongest (di.u.ti.table_len),
2849			    hex_string ((CORE_ADDR)di.u.ti.table_data));
2850    }
2851  else
2852    {
2853      ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2854      if (ret < 0)
2855	return ret;
2856
2857      if (gdbarch_debug >= 1)
2858	fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: %s -> "
2859			    "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2860			    "length=%s,data=%s)\n",
2861			    hex_string (ip), (char *)di.u.rti.name_ptr,
2862			    hex_string (di.u.rti.segbase),
2863			    hex_string (di.start_ip), hex_string (di.end_ip),
2864			    hex_string (di.gp),
2865			    pulongest (di.u.rti.table_len),
2866			    hex_string (di.u.rti.table_data));
2867    }
2868
2869  ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2870				       arg);
2871
2872  /* We no longer need the dyn info storage so free it.  */
2873  xfree (buf);
2874
2875  return ret;
2876}
2877
2878/* Libunwind callback accessor function for cleanup.  */
2879static void
2880ia64_put_unwind_info (unw_addr_space_t as,
2881		      unw_proc_info_t *pip, void *arg)
2882{
2883  /* Nothing required for now.  */
2884}
2885
2886/* Libunwind callback accessor function to get head of the dynamic
2887   unwind-info registration list.  */
2888static int
2889ia64_get_dyn_info_list (unw_addr_space_t as,
2890			unw_word_t *dilap, void *arg)
2891{
2892  struct obj_section *text_sec;
2893  struct objfile *objfile;
2894  unw_word_t ip, addr;
2895  unw_dyn_info_t di;
2896  int ret;
2897
2898  if (!libunwind_is_initialized ())
2899    return -UNW_ENOINFO;
2900
2901  for (objfile = object_files; objfile; objfile = objfile->next)
2902    {
2903      void *buf = NULL;
2904
2905      text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2906      ip = obj_section_addr (text_sec);
2907      ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2908      if (ret >= 0)
2909	{
2910	  addr = libunwind_find_dyn_list (as, &di, arg);
2911	  /* We no longer need the dyn info storage so free it.  */
2912	  xfree (buf);
2913
2914	  if (addr)
2915	    {
2916	      if (gdbarch_debug >= 1)
2917		fprintf_unfiltered (gdb_stdlog,
2918				    "dynamic unwind table in objfile %s "
2919				    "at %s (gp=%s)\n",
2920				    bfd_get_filename (objfile->obfd),
2921				    hex_string (addr), hex_string (di.gp));
2922	      *dilap = addr;
2923	      return 0;
2924	    }
2925	}
2926    }
2927  return -UNW_ENOINFO;
2928}
2929
2930
2931/* Frame interface functions for libunwind.  */
2932
2933static void
2934ia64_libunwind_frame_this_id (struct frame_info *this_frame, void **this_cache,
2935			      struct frame_id *this_id)
2936{
2937  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2938  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2939  struct frame_id id = outer_frame_id;
2940  char buf[8];
2941  CORE_ADDR bsp;
2942
2943  libunwind_frame_this_id (this_frame, this_cache, &id);
2944  if (frame_id_eq (id, outer_frame_id))
2945    {
2946      (*this_id) = outer_frame_id;
2947      return;
2948    }
2949
2950  /* We must add the bsp as the special address for frame comparison
2951     purposes.  */
2952  get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2953  bsp = extract_unsigned_integer (buf, 8, byte_order);
2954
2955  (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2956
2957  if (gdbarch_debug >= 1)
2958    fprintf_unfiltered (gdb_stdlog,
2959			"libunwind frame id: code %s, stack %s, "
2960			"special %s, this_frame %s\n",
2961			paddress (gdbarch, id.code_addr),
2962			paddress (gdbarch, id.stack_addr),
2963			paddress (gdbarch, bsp),
2964			host_address_to_string (this_frame));
2965}
2966
2967static struct value *
2968ia64_libunwind_frame_prev_register (struct frame_info *this_frame,
2969				    void **this_cache, int regnum)
2970{
2971  int reg = regnum;
2972  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2973  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2974  struct value *val;
2975
2976  if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2977    reg = IA64_PR_REGNUM;
2978  else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2979    reg = IA64_UNAT_REGNUM;
2980
2981  /* Let libunwind do most of the work.  */
2982  val = libunwind_frame_prev_register (this_frame, this_cache, reg);
2983
2984  if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2985    {
2986      ULONGEST prN_val;
2987
2988      if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2989	{
2990	  int rrb_pr = 0;
2991	  ULONGEST cfm;
2992	  unsigned char buf[MAX_REGISTER_SIZE];
2993
2994	  /* Fetch predicate register rename base from current frame
2995	     marker for this frame.  */
2996	  get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
2997	  cfm = extract_unsigned_integer (buf, 8, byte_order);
2998	  rrb_pr = (cfm >> 32) & 0x3f;
2999
3000	  /* Adjust the register number to account for register rotation.  */
3001	  regnum = VP16_REGNUM + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3002	}
3003      prN_val = extract_bit_field (value_contents_all (val),
3004				   regnum - VP0_REGNUM, 1);
3005      return frame_unwind_got_constant (this_frame, regnum, prN_val);
3006    }
3007
3008  else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
3009    {
3010      ULONGEST unatN_val;
3011
3012      unatN_val = extract_bit_field (value_contents_all (val),
3013                                     regnum - IA64_NAT0_REGNUM, 1);
3014      return frame_unwind_got_constant (this_frame, regnum, unatN_val);
3015    }
3016
3017  else if (regnum == IA64_BSP_REGNUM)
3018    {
3019      struct value *cfm_val;
3020      CORE_ADDR prev_bsp, prev_cfm;
3021
3022      /* We want to calculate the previous bsp as the end of the previous
3023         register stack frame.  This corresponds to what the hardware bsp
3024         register will be if we pop the frame back which is why we might
3025         have been called.  We know that libunwind will pass us back the
3026         beginning of the current frame so we should just add sof to it.  */
3027      prev_bsp = extract_unsigned_integer (value_contents_all (val),
3028					   8, byte_order);
3029      cfm_val = libunwind_frame_prev_register (this_frame, this_cache,
3030                                               IA64_CFM_REGNUM);
3031      prev_cfm = extract_unsigned_integer (value_contents_all (cfm_val),
3032					   8, byte_order);
3033      prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
3034
3035      return frame_unwind_got_constant (this_frame, regnum, prev_bsp);
3036    }
3037  else
3038    return val;
3039}
3040
3041static int
3042ia64_libunwind_frame_sniffer (const struct frame_unwind *self,
3043                              struct frame_info *this_frame,
3044                              void **this_cache)
3045{
3046  if (libunwind_is_initialized ()
3047      && libunwind_frame_sniffer (self, this_frame, this_cache))
3048    return 1;
3049
3050  return 0;
3051}
3052
3053static const struct frame_unwind ia64_libunwind_frame_unwind =
3054{
3055  NORMAL_FRAME,
3056  default_frame_unwind_stop_reason,
3057  ia64_libunwind_frame_this_id,
3058  ia64_libunwind_frame_prev_register,
3059  NULL,
3060  ia64_libunwind_frame_sniffer,
3061  libunwind_frame_dealloc_cache
3062};
3063
3064static void
3065ia64_libunwind_sigtramp_frame_this_id (struct frame_info *this_frame,
3066                                       void **this_cache,
3067				       struct frame_id *this_id)
3068{
3069  struct gdbarch *gdbarch = get_frame_arch (this_frame);
3070  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3071  char buf[8];
3072  CORE_ADDR bsp;
3073  struct frame_id id = outer_frame_id;
3074  CORE_ADDR prev_ip;
3075
3076  libunwind_frame_this_id (this_frame, this_cache, &id);
3077  if (frame_id_eq (id, outer_frame_id))
3078    {
3079      (*this_id) = outer_frame_id;
3080      return;
3081    }
3082
3083  /* We must add the bsp as the special address for frame comparison
3084     purposes.  */
3085  get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
3086  bsp = extract_unsigned_integer (buf, 8, byte_order);
3087
3088  /* For a sigtramp frame, we don't make the check for previous ip being 0.  */
3089  (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
3090
3091  if (gdbarch_debug >= 1)
3092    fprintf_unfiltered (gdb_stdlog,
3093			"libunwind sigtramp frame id: code %s, "
3094			"stack %s, special %s, this_frame %s\n",
3095			paddress (gdbarch, id.code_addr),
3096			paddress (gdbarch, id.stack_addr),
3097			paddress (gdbarch, bsp),
3098			host_address_to_string (this_frame));
3099}
3100
3101static struct value *
3102ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *this_frame,
3103					     void **this_cache, int regnum)
3104{
3105  struct gdbarch *gdbarch = get_frame_arch (this_frame);
3106  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3107  struct value *prev_ip_val;
3108  CORE_ADDR prev_ip;
3109
3110  /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
3111     method of getting previous registers.  */
3112  prev_ip_val = libunwind_frame_prev_register (this_frame, this_cache,
3113                                               IA64_IP_REGNUM);
3114  prev_ip = extract_unsigned_integer (value_contents_all (prev_ip_val),
3115				      8, byte_order);
3116
3117  if (prev_ip == 0)
3118    {
3119      void *tmp_cache = NULL;
3120      return ia64_sigtramp_frame_prev_register (this_frame, &tmp_cache,
3121                                                regnum);
3122    }
3123  else
3124    return ia64_libunwind_frame_prev_register (this_frame, this_cache, regnum);
3125}
3126
3127static int
3128ia64_libunwind_sigtramp_frame_sniffer (const struct frame_unwind *self,
3129                                       struct frame_info *this_frame,
3130                                       void **this_cache)
3131{
3132  if (libunwind_is_initialized ())
3133    {
3134      if (libunwind_sigtramp_frame_sniffer (self, this_frame, this_cache))
3135        return 1;
3136      return 0;
3137    }
3138  else
3139    return ia64_sigtramp_frame_sniffer (self, this_frame, this_cache);
3140}
3141
3142static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
3143{
3144  SIGTRAMP_FRAME,
3145  default_frame_unwind_stop_reason,
3146  ia64_libunwind_sigtramp_frame_this_id,
3147  ia64_libunwind_sigtramp_frame_prev_register,
3148  NULL,
3149  ia64_libunwind_sigtramp_frame_sniffer
3150};
3151
3152/* Set of libunwind callback acccessor functions.  */
3153static unw_accessors_t ia64_unw_accessors =
3154{
3155  ia64_find_proc_info_x,
3156  ia64_put_unwind_info,
3157  ia64_get_dyn_info_list,
3158  ia64_access_mem,
3159  ia64_access_reg,
3160  ia64_access_fpreg,
3161  /* resume */
3162  /* get_proc_name */
3163};
3164
3165/* Set of special libunwind callback acccessor functions specific for accessing
3166   the rse registers.  At the top of the stack, we want libunwind to figure out
3167   how to read r32 - r127.  Though usually they are found sequentially in
3168   memory starting from $bof, this is not always true.  */
3169static unw_accessors_t ia64_unw_rse_accessors =
3170{
3171  ia64_find_proc_info_x,
3172  ia64_put_unwind_info,
3173  ia64_get_dyn_info_list,
3174  ia64_access_mem,
3175  ia64_access_rse_reg,
3176  ia64_access_rse_fpreg,
3177  /* resume */
3178  /* get_proc_name */
3179};
3180
3181/* Set of ia64 gdb libunwind-frame callbacks and data for generic
3182   libunwind-frame code to use.  */
3183static struct libunwind_descr ia64_libunwind_descr =
3184{
3185  ia64_gdb2uw_regnum,
3186  ia64_uw2gdb_regnum,
3187  ia64_is_fpreg,
3188  &ia64_unw_accessors,
3189  &ia64_unw_rse_accessors,
3190};
3191
3192#endif /* HAVE_LIBUNWIND_IA64_H  */
3193
3194static int
3195ia64_use_struct_convention (struct type *type)
3196{
3197  struct type *float_elt_type;
3198
3199  /* Don't use the struct convention for anything but structure,
3200     union, or array types.  */
3201  if (!(TYPE_CODE (type) == TYPE_CODE_STRUCT
3202	|| TYPE_CODE (type) == TYPE_CODE_UNION
3203	|| TYPE_CODE (type) == TYPE_CODE_ARRAY))
3204    return 0;
3205
3206  /* HFAs are structures (or arrays) consisting entirely of floating
3207     point values of the same length.  Up to 8 of these are returned
3208     in registers.  Don't use the struct convention when this is the
3209     case.  */
3210  float_elt_type = is_float_or_hfa_type (type);
3211  if (float_elt_type != NULL
3212      && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
3213    return 0;
3214
3215  /* Other structs of length 32 or less are returned in r8-r11.
3216     Don't use the struct convention for those either.  */
3217  return TYPE_LENGTH (type) > 32;
3218}
3219
3220/* Return non-zero if TYPE is a structure or union type.  */
3221
3222static int
3223ia64_struct_type_p (const struct type *type)
3224{
3225  return (TYPE_CODE (type) == TYPE_CODE_STRUCT
3226          || TYPE_CODE (type) == TYPE_CODE_UNION);
3227}
3228
3229static void
3230ia64_extract_return_value (struct type *type, struct regcache *regcache,
3231			   gdb_byte *valbuf)
3232{
3233  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3234  struct type *float_elt_type;
3235
3236  float_elt_type = is_float_or_hfa_type (type);
3237  if (float_elt_type != NULL)
3238    {
3239      char from[MAX_REGISTER_SIZE];
3240      int offset = 0;
3241      int regnum = IA64_FR8_REGNUM;
3242      int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3243
3244      while (n-- > 0)
3245	{
3246	  regcache_cooked_read (regcache, regnum, from);
3247	  convert_typed_floating (from, ia64_ext_type (gdbarch),
3248				  (char *)valbuf + offset, float_elt_type);
3249	  offset += TYPE_LENGTH (float_elt_type);
3250	  regnum++;
3251	}
3252    }
3253  else if (!ia64_struct_type_p (type) && TYPE_LENGTH (type) < 8)
3254    {
3255      /* This is an integral value, and its size is less than 8 bytes.
3256         These values are LSB-aligned, so extract the relevant bytes,
3257         and copy them into VALBUF.  */
3258      /* brobecker/2005-12-30: Actually, all integral values are LSB aligned,
3259	 so I suppose we should also add handling here for integral values
3260	 whose size is greater than 8.  But I wasn't able to create such
3261	 a type, neither in C nor in Ada, so not worrying about these yet.  */
3262      enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3263      ULONGEST val;
3264
3265      regcache_cooked_read_unsigned (regcache, IA64_GR8_REGNUM, &val);
3266      store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, val);
3267    }
3268  else
3269    {
3270      ULONGEST val;
3271      int offset = 0;
3272      int regnum = IA64_GR8_REGNUM;
3273      int reglen = TYPE_LENGTH (register_type (gdbarch, IA64_GR8_REGNUM));
3274      int n = TYPE_LENGTH (type) / reglen;
3275      int m = TYPE_LENGTH (type) % reglen;
3276
3277      while (n-- > 0)
3278	{
3279	  ULONGEST val;
3280	  regcache_cooked_read_unsigned (regcache, regnum, &val);
3281	  memcpy ((char *)valbuf + offset, &val, reglen);
3282	  offset += reglen;
3283	  regnum++;
3284	}
3285
3286      if (m)
3287	{
3288          regcache_cooked_read_unsigned (regcache, regnum, &val);
3289	  memcpy ((char *)valbuf + offset, &val, m);
3290	}
3291    }
3292}
3293
3294static void
3295ia64_store_return_value (struct type *type, struct regcache *regcache,
3296			 const gdb_byte *valbuf)
3297{
3298  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3299  struct type *float_elt_type;
3300
3301  float_elt_type = is_float_or_hfa_type (type);
3302  if (float_elt_type != NULL)
3303    {
3304      char to[MAX_REGISTER_SIZE];
3305      int offset = 0;
3306      int regnum = IA64_FR8_REGNUM;
3307      int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3308
3309      while (n-- > 0)
3310	{
3311	  convert_typed_floating ((char *)valbuf + offset, float_elt_type,
3312				  to, ia64_ext_type (gdbarch));
3313	  regcache_cooked_write (regcache, regnum, to);
3314	  offset += TYPE_LENGTH (float_elt_type);
3315	  regnum++;
3316	}
3317    }
3318  else
3319    {
3320      ULONGEST val;
3321      int offset = 0;
3322      int regnum = IA64_GR8_REGNUM;
3323      int reglen = TYPE_LENGTH (register_type (gdbarch, IA64_GR8_REGNUM));
3324      int n = TYPE_LENGTH (type) / reglen;
3325      int m = TYPE_LENGTH (type) % reglen;
3326
3327      while (n-- > 0)
3328	{
3329	  ULONGEST val;
3330	  memcpy (&val, (char *)valbuf + offset, reglen);
3331	  regcache_cooked_write_unsigned (regcache, regnum, val);
3332	  offset += reglen;
3333	  regnum++;
3334	}
3335
3336      if (m)
3337	{
3338	  memcpy (&val, (char *)valbuf + offset, m);
3339          regcache_cooked_write_unsigned (regcache, regnum, val);
3340	}
3341    }
3342}
3343
3344static enum return_value_convention
3345ia64_return_value (struct gdbarch *gdbarch, struct type *func_type,
3346		   struct type *valtype, struct regcache *regcache,
3347		   gdb_byte *readbuf, const gdb_byte *writebuf)
3348{
3349  int struct_return = ia64_use_struct_convention (valtype);
3350
3351  if (writebuf != NULL)
3352    {
3353      gdb_assert (!struct_return);
3354      ia64_store_return_value (valtype, regcache, writebuf);
3355    }
3356
3357  if (readbuf != NULL)
3358    {
3359      gdb_assert (!struct_return);
3360      ia64_extract_return_value (valtype, regcache, readbuf);
3361    }
3362
3363  if (struct_return)
3364    return RETURN_VALUE_STRUCT_CONVENTION;
3365  else
3366    return RETURN_VALUE_REGISTER_CONVENTION;
3367}
3368
3369static int
3370is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3371{
3372  switch (TYPE_CODE (t))
3373    {
3374    case TYPE_CODE_FLT:
3375      if (*etp)
3376	return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3377      else
3378	{
3379	  *etp = t;
3380	  return 1;
3381	}
3382      break;
3383    case TYPE_CODE_ARRAY:
3384      return
3385	is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3386				      etp);
3387      break;
3388    case TYPE_CODE_STRUCT:
3389      {
3390	int i;
3391
3392	for (i = 0; i < TYPE_NFIELDS (t); i++)
3393	  if (!is_float_or_hfa_type_recurse
3394	      (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
3395	    return 0;
3396	return 1;
3397      }
3398      break;
3399    default:
3400      return 0;
3401      break;
3402    }
3403}
3404
3405/* Determine if the given type is one of the floating point types or
3406   and HFA (which is a struct, array, or combination thereof whose
3407   bottom-most elements are all of the same floating point type).  */
3408
3409static struct type *
3410is_float_or_hfa_type (struct type *t)
3411{
3412  struct type *et = 0;
3413
3414  return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3415}
3416
3417
3418/* Return 1 if the alignment of T is such that the next even slot
3419   should be used.  Return 0, if the next available slot should
3420   be used.  (See section 8.5.1 of the IA-64 Software Conventions
3421   and Runtime manual).  */
3422
3423static int
3424slot_alignment_is_next_even (struct type *t)
3425{
3426  switch (TYPE_CODE (t))
3427    {
3428    case TYPE_CODE_INT:
3429    case TYPE_CODE_FLT:
3430      if (TYPE_LENGTH (t) > 8)
3431	return 1;
3432      else
3433	return 0;
3434    case TYPE_CODE_ARRAY:
3435      return
3436	slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3437    case TYPE_CODE_STRUCT:
3438      {
3439	int i;
3440
3441	for (i = 0; i < TYPE_NFIELDS (t); i++)
3442	  if (slot_alignment_is_next_even
3443	      (check_typedef (TYPE_FIELD_TYPE (t, i))))
3444	    return 1;
3445	return 0;
3446      }
3447    default:
3448      return 0;
3449    }
3450}
3451
3452/* Attempt to find (and return) the global pointer for the given
3453   function.
3454
3455   This is a rather nasty bit of code searchs for the .dynamic section
3456   in the objfile corresponding to the pc of the function we're trying
3457   to call.  Once it finds the addresses at which the .dynamic section
3458   lives in the child process, it scans the Elf64_Dyn entries for a
3459   DT_PLTGOT tag.  If it finds one of these, the corresponding
3460   d_un.d_ptr value is the global pointer.  */
3461
3462static CORE_ADDR
3463ia64_find_global_pointer_from_dynamic_section (struct gdbarch *gdbarch,
3464					       CORE_ADDR faddr)
3465{
3466  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3467  struct obj_section *faddr_sect;
3468
3469  faddr_sect = find_pc_section (faddr);
3470  if (faddr_sect != NULL)
3471    {
3472      struct obj_section *osect;
3473
3474      ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
3475	{
3476	  if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3477	    break;
3478	}
3479
3480      if (osect < faddr_sect->objfile->sections_end)
3481	{
3482	  CORE_ADDR addr, endaddr;
3483
3484	  addr = obj_section_addr (osect);
3485	  endaddr = obj_section_endaddr (osect);
3486
3487	  while (addr < endaddr)
3488	    {
3489	      int status;
3490	      LONGEST tag;
3491	      char buf[8];
3492
3493	      status = target_read_memory (addr, buf, sizeof (buf));
3494	      if (status != 0)
3495		break;
3496	      tag = extract_signed_integer (buf, sizeof (buf), byte_order);
3497
3498	      if (tag == DT_PLTGOT)
3499		{
3500		  CORE_ADDR global_pointer;
3501
3502		  status = target_read_memory (addr + 8, buf, sizeof (buf));
3503		  if (status != 0)
3504		    break;
3505		  global_pointer = extract_unsigned_integer (buf, sizeof (buf),
3506							     byte_order);
3507
3508		  /* The payoff...  */
3509		  return global_pointer;
3510		}
3511
3512	      if (tag == DT_NULL)
3513		break;
3514
3515	      addr += 16;
3516	    }
3517	}
3518    }
3519  return 0;
3520}
3521
3522/* Attempt to find (and return) the global pointer for the given
3523   function.  We first try the find_global_pointer_from_solib routine
3524   from the gdbarch tdep vector, if provided.  And if that does not
3525   work, then we try ia64_find_global_pointer_from_dynamic_section.  */
3526
3527static CORE_ADDR
3528ia64_find_global_pointer (struct gdbarch *gdbarch, CORE_ADDR faddr)
3529{
3530  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3531  CORE_ADDR addr = 0;
3532
3533  if (tdep->find_global_pointer_from_solib)
3534    addr = tdep->find_global_pointer_from_solib (gdbarch, faddr);
3535  if (addr == 0)
3536    addr = ia64_find_global_pointer_from_dynamic_section (gdbarch, faddr);
3537  return addr;
3538}
3539
3540/* Given a function's address, attempt to find (and return) the
3541   corresponding (canonical) function descriptor.  Return 0 if
3542   not found.  */
3543static CORE_ADDR
3544find_extant_func_descr (struct gdbarch *gdbarch, CORE_ADDR faddr)
3545{
3546  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3547  struct obj_section *faddr_sect;
3548
3549  /* Return early if faddr is already a function descriptor.  */
3550  faddr_sect = find_pc_section (faddr);
3551  if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
3552    return faddr;
3553
3554  if (faddr_sect != NULL)
3555    {
3556      struct obj_section *osect;
3557      ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
3558	{
3559	  if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3560	    break;
3561	}
3562
3563      if (osect < faddr_sect->objfile->sections_end)
3564	{
3565	  CORE_ADDR addr, endaddr;
3566
3567	  addr = obj_section_addr (osect);
3568	  endaddr = obj_section_endaddr (osect);
3569
3570	  while (addr < endaddr)
3571	    {
3572	      int status;
3573	      LONGEST faddr2;
3574	      char buf[8];
3575
3576	      status = target_read_memory (addr, buf, sizeof (buf));
3577	      if (status != 0)
3578		break;
3579	      faddr2 = extract_signed_integer (buf, sizeof (buf), byte_order);
3580
3581	      if (faddr == faddr2)
3582		return addr;
3583
3584	      addr += 16;
3585	    }
3586	}
3587    }
3588  return 0;
3589}
3590
3591/* Attempt to find a function descriptor corresponding to the
3592   given address.  If none is found, construct one on the
3593   stack using the address at fdaptr.  */
3594
3595static CORE_ADDR
3596find_func_descr (struct regcache *regcache, CORE_ADDR faddr, CORE_ADDR *fdaptr)
3597{
3598  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3599  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3600  CORE_ADDR fdesc;
3601
3602  fdesc = find_extant_func_descr (gdbarch, faddr);
3603
3604  if (fdesc == 0)
3605    {
3606      ULONGEST global_pointer;
3607      char buf[16];
3608
3609      fdesc = *fdaptr;
3610      *fdaptr += 16;
3611
3612      global_pointer = ia64_find_global_pointer (gdbarch, faddr);
3613
3614      if (global_pointer == 0)
3615	regcache_cooked_read_unsigned (regcache,
3616				       IA64_GR1_REGNUM, &global_pointer);
3617
3618      store_unsigned_integer (buf, 8, byte_order, faddr);
3619      store_unsigned_integer (buf + 8, 8, byte_order, global_pointer);
3620
3621      write_memory (fdesc, buf, 16);
3622    }
3623
3624  return fdesc;
3625}
3626
3627/* Use the following routine when printing out function pointers
3628   so the user can see the function address rather than just the
3629   function descriptor.  */
3630static CORE_ADDR
3631ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3632				 struct target_ops *targ)
3633{
3634  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3635  struct obj_section *s;
3636  gdb_byte buf[8];
3637
3638  s = find_pc_section (addr);
3639
3640  /* check if ADDR points to a function descriptor.  */
3641  if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3642    return read_memory_unsigned_integer (addr, 8, byte_order);
3643
3644  /* Normally, functions live inside a section that is executable.
3645     So, if ADDR points to a non-executable section, then treat it
3646     as a function descriptor and return the target address iff
3647     the target address itself points to a section that is executable.
3648     Check first the memory of the whole length of 8 bytes is readable.  */
3649  if (s && (s->the_bfd_section->flags & SEC_CODE) == 0
3650      && target_read_memory (addr, buf, 8) == 0)
3651    {
3652      CORE_ADDR pc = extract_unsigned_integer (buf, 8, byte_order);
3653      struct obj_section *pc_section = find_pc_section (pc);
3654
3655      if (pc_section && (pc_section->the_bfd_section->flags & SEC_CODE))
3656        return pc;
3657    }
3658
3659  /* There are also descriptors embedded in vtables.  */
3660  if (s)
3661    {
3662      struct minimal_symbol *minsym;
3663
3664      minsym = lookup_minimal_symbol_by_pc (addr);
3665
3666      if (minsym && is_vtable_name (SYMBOL_LINKAGE_NAME (minsym)))
3667	return read_memory_unsigned_integer (addr, 8, byte_order);
3668    }
3669
3670  return addr;
3671}
3672
3673static CORE_ADDR
3674ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3675{
3676  return sp & ~0xfLL;
3677}
3678
3679/* The default "allocate_new_rse_frame" ia64_infcall_ops routine for ia64.  */
3680
3681static void
3682ia64_allocate_new_rse_frame (struct regcache *regcache, ULONGEST bsp, int sof)
3683{
3684  ULONGEST cfm, pfs, new_bsp;
3685
3686  regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
3687
3688  new_bsp = rse_address_add (bsp, sof);
3689  regcache_cooked_write_unsigned (regcache, IA64_BSP_REGNUM, new_bsp);
3690
3691  regcache_cooked_read_unsigned (regcache, IA64_PFS_REGNUM, &pfs);
3692  pfs &= 0xc000000000000000LL;
3693  pfs |= (cfm & 0xffffffffffffLL);
3694  regcache_cooked_write_unsigned (regcache, IA64_PFS_REGNUM, pfs);
3695
3696  cfm &= 0xc000000000000000LL;
3697  cfm |= sof;
3698  regcache_cooked_write_unsigned (regcache, IA64_CFM_REGNUM, cfm);
3699}
3700
3701/* The default "store_argument_in_slot" ia64_infcall_ops routine for
3702   ia64.  */
3703
3704static void
3705ia64_store_argument_in_slot (struct regcache *regcache, CORE_ADDR bsp,
3706			     int slotnum, gdb_byte *buf)
3707{
3708  write_memory (rse_address_add (bsp, slotnum), buf, 8);
3709}
3710
3711/* The default "set_function_addr" ia64_infcall_ops routine for ia64.  */
3712
3713static void
3714ia64_set_function_addr (struct regcache *regcache, CORE_ADDR func_addr)
3715{
3716  /* Nothing needed.  */
3717}
3718
3719static CORE_ADDR
3720ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3721		      struct regcache *regcache, CORE_ADDR bp_addr,
3722		      int nargs, struct value **args, CORE_ADDR sp,
3723		      int struct_return, CORE_ADDR struct_addr)
3724{
3725  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3726  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3727  int argno;
3728  struct value *arg;
3729  struct type *type;
3730  int len, argoffset;
3731  int nslots, rseslots, memslots, slotnum, nfuncargs;
3732  int floatreg;
3733  ULONGEST bsp;
3734  CORE_ADDR funcdescaddr, pc, global_pointer;
3735  CORE_ADDR func_addr = find_function_addr (function, NULL);
3736
3737  nslots = 0;
3738  nfuncargs = 0;
3739  /* Count the number of slots needed for the arguments.  */
3740  for (argno = 0; argno < nargs; argno++)
3741    {
3742      arg = args[argno];
3743      type = check_typedef (value_type (arg));
3744      len = TYPE_LENGTH (type);
3745
3746      if ((nslots & 1) && slot_alignment_is_next_even (type))
3747	nslots++;
3748
3749      if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3750	nfuncargs++;
3751
3752      nslots += (len + 7) / 8;
3753    }
3754
3755  /* Divvy up the slots between the RSE and the memory stack.  */
3756  rseslots = (nslots > 8) ? 8 : nslots;
3757  memslots = nslots - rseslots;
3758
3759  /* Allocate a new RSE frame.  */
3760  regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
3761  tdep->infcall_ops.allocate_new_rse_frame (regcache, bsp, rseslots);
3762
3763  /* We will attempt to find function descriptors in the .opd segment,
3764     but if we can't we'll construct them ourselves.  That being the
3765     case, we'll need to reserve space on the stack for them.  */
3766  funcdescaddr = sp - nfuncargs * 16;
3767  funcdescaddr &= ~0xfLL;
3768
3769  /* Adjust the stack pointer to it's new value.  The calling conventions
3770     require us to have 16 bytes of scratch, plus whatever space is
3771     necessary for the memory slots and our function descriptors.  */
3772  sp = sp - 16 - (memslots + nfuncargs) * 8;
3773  sp &= ~0xfLL;				/* Maintain 16 byte alignment.  */
3774
3775  /* Place the arguments where they belong.  The arguments will be
3776     either placed in the RSE backing store or on the memory stack.
3777     In addition, floating point arguments or HFAs are placed in
3778     floating point registers.  */
3779  slotnum = 0;
3780  floatreg = IA64_FR8_REGNUM;
3781  for (argno = 0; argno < nargs; argno++)
3782    {
3783      struct type *float_elt_type;
3784
3785      arg = args[argno];
3786      type = check_typedef (value_type (arg));
3787      len = TYPE_LENGTH (type);
3788
3789      /* Special handling for function parameters.  */
3790      if (len == 8
3791          && TYPE_CODE (type) == TYPE_CODE_PTR
3792	  && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3793	{
3794	  char val_buf[8];
3795	  ULONGEST faddr = extract_unsigned_integer (value_contents (arg),
3796						     8, byte_order);
3797	  store_unsigned_integer (val_buf, 8, byte_order,
3798				  find_func_descr (regcache, faddr,
3799						   &funcdescaddr));
3800	  if (slotnum < rseslots)
3801	    tdep->infcall_ops.store_argument_in_slot (regcache, bsp,
3802						      slotnum, val_buf);
3803	  else
3804	    write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3805	  slotnum++;
3806	  continue;
3807	}
3808
3809      /* Normal slots.  */
3810
3811      /* Skip odd slot if necessary...  */
3812      if ((slotnum & 1) && slot_alignment_is_next_even (type))
3813	slotnum++;
3814
3815      argoffset = 0;
3816      while (len > 0)
3817	{
3818	  char val_buf[8];
3819
3820	  memset (val_buf, 0, 8);
3821          if (!ia64_struct_type_p (type) && len < 8)
3822            {
3823              /* Integral types are LSB-aligned, so we have to be careful
3824                 to insert the argument on the correct side of the buffer.
3825                 This is why we use store_unsigned_integer.  */
3826              store_unsigned_integer
3827                (val_buf, 8, byte_order,
3828                 extract_unsigned_integer (value_contents (arg), len,
3829					   byte_order));
3830            }
3831          else
3832            {
3833              /* This is either an 8bit integral type, or an aggregate.
3834                 For 8bit integral type, there is no problem, we just
3835                 copy the value over.
3836
3837                 For aggregates, the only potentially tricky portion
3838                 is to write the last one if it is less than 8 bytes.
3839                 In this case, the data is Byte0-aligned.  Happy news,
3840                 this means that we don't need to differentiate the
3841                 handling of 8byte blocks and less-than-8bytes blocks.  */
3842              memcpy (val_buf, value_contents (arg) + argoffset,
3843                      (len > 8) ? 8 : len);
3844            }
3845
3846	  if (slotnum < rseslots)
3847	    tdep->infcall_ops.store_argument_in_slot (regcache, bsp,
3848						      slotnum, val_buf);
3849	  else
3850	    write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3851
3852	  argoffset += 8;
3853	  len -= 8;
3854	  slotnum++;
3855	}
3856
3857      /* Handle floating point types (including HFAs).  */
3858      float_elt_type = is_float_or_hfa_type (type);
3859      if (float_elt_type != NULL)
3860	{
3861	  argoffset = 0;
3862	  len = TYPE_LENGTH (type);
3863	  while (len > 0 && floatreg < IA64_FR16_REGNUM)
3864	    {
3865	      char to[MAX_REGISTER_SIZE];
3866	      convert_typed_floating (value_contents (arg) + argoffset,
3867				      float_elt_type, to,
3868				      ia64_ext_type (gdbarch));
3869	      regcache_cooked_write (regcache, floatreg, (void *)to);
3870	      floatreg++;
3871	      argoffset += TYPE_LENGTH (float_elt_type);
3872	      len -= TYPE_LENGTH (float_elt_type);
3873	    }
3874	}
3875    }
3876
3877  /* Store the struct return value in r8 if necessary.  */
3878  if (struct_return)
3879    {
3880      regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM,
3881				      (ULONGEST) struct_addr);
3882    }
3883
3884  global_pointer = ia64_find_global_pointer (gdbarch, func_addr);
3885
3886  if (global_pointer != 0)
3887    regcache_cooked_write_unsigned (regcache, IA64_GR1_REGNUM, global_pointer);
3888
3889  /* The following is not necessary on HP-UX, because we're using
3890     a dummy code sequence pushed on the stack to make the call, and
3891     this sequence doesn't need b0 to be set in order for our dummy
3892     breakpoint to be hit.  Nonetheless, this doesn't interfere, and
3893     it's needed for other OSes, so we do this unconditionaly.  */
3894  regcache_cooked_write_unsigned (regcache, IA64_BR0_REGNUM, bp_addr);
3895
3896  regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
3897
3898  tdep->infcall_ops.set_function_addr (regcache, func_addr);
3899
3900  return sp;
3901}
3902
3903static const struct ia64_infcall_ops ia64_infcall_ops =
3904{
3905  ia64_allocate_new_rse_frame,
3906  ia64_store_argument_in_slot,
3907  ia64_set_function_addr
3908};
3909
3910static struct frame_id
3911ia64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3912{
3913  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3914  char buf[8];
3915  CORE_ADDR sp, bsp;
3916
3917  get_frame_register (this_frame, sp_regnum, buf);
3918  sp = extract_unsigned_integer (buf, 8, byte_order);
3919
3920  get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
3921  bsp = extract_unsigned_integer (buf, 8, byte_order);
3922
3923  if (gdbarch_debug >= 1)
3924    fprintf_unfiltered (gdb_stdlog,
3925			"dummy frame id: code %s, stack %s, special %s\n",
3926			paddress (gdbarch, get_frame_pc (this_frame)),
3927			paddress (gdbarch, sp), paddress (gdbarch, bsp));
3928
3929  return frame_id_build_special (sp, get_frame_pc (this_frame), bsp);
3930}
3931
3932static CORE_ADDR
3933ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3934{
3935  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3936  char buf[8];
3937  CORE_ADDR ip, psr, pc;
3938
3939  frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3940  ip = extract_unsigned_integer (buf, 8, byte_order);
3941  frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3942  psr = extract_unsigned_integer (buf, 8, byte_order);
3943
3944  pc = (ip & ~0xf) | ((psr >> 41) & 3);
3945  return pc;
3946}
3947
3948static int
3949ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3950{
3951  info->bytes_per_line = SLOT_MULTIPLIER;
3952  return print_insn_ia64 (memaddr, info);
3953}
3954
3955/* The default "size_of_register_frame" gdbarch_tdep routine for ia64.  */
3956
3957static int
3958ia64_size_of_register_frame (struct frame_info *this_frame, ULONGEST cfm)
3959{
3960  return (cfm & 0x7f);
3961}
3962
3963static struct gdbarch *
3964ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3965{
3966  struct gdbarch *gdbarch;
3967  struct gdbarch_tdep *tdep;
3968
3969  /* If there is already a candidate, use it.  */
3970  arches = gdbarch_list_lookup_by_info (arches, &info);
3971  if (arches != NULL)
3972    return arches->gdbarch;
3973
3974  tdep = xzalloc (sizeof (struct gdbarch_tdep));
3975  gdbarch = gdbarch_alloc (&info, tdep);
3976
3977  tdep->size_of_register_frame = ia64_size_of_register_frame;
3978
3979  /* According to the ia64 specs, instructions that store long double
3980     floats in memory use a long-double format different than that
3981     used in the floating registers.  The memory format matches the
3982     x86 extended float format which is 80 bits.  An OS may choose to
3983     use this format (e.g. GNU/Linux) or choose to use a different
3984     format for storing long doubles (e.g. HPUX).  In the latter case,
3985     the setting of the format may be moved/overridden in an
3986     OS-specific tdep file.  */
3987  set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
3988
3989  set_gdbarch_short_bit (gdbarch, 16);
3990  set_gdbarch_int_bit (gdbarch, 32);
3991  set_gdbarch_long_bit (gdbarch, 64);
3992  set_gdbarch_long_long_bit (gdbarch, 64);
3993  set_gdbarch_float_bit (gdbarch, 32);
3994  set_gdbarch_double_bit (gdbarch, 64);
3995  set_gdbarch_long_double_bit (gdbarch, 128);
3996  set_gdbarch_ptr_bit (gdbarch, 64);
3997
3998  set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3999  set_gdbarch_num_pseudo_regs (gdbarch,
4000			       LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
4001  set_gdbarch_sp_regnum (gdbarch, sp_regnum);
4002  set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
4003
4004  set_gdbarch_register_name (gdbarch, ia64_register_name);
4005  set_gdbarch_register_type (gdbarch, ia64_register_type);
4006
4007  set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
4008  set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
4009  set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
4010  set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
4011  set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
4012  set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
4013  set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
4014
4015  set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
4016
4017  set_gdbarch_return_value (gdbarch, ia64_return_value);
4018
4019  set_gdbarch_memory_insert_breakpoint (gdbarch,
4020					ia64_memory_insert_breakpoint);
4021  set_gdbarch_memory_remove_breakpoint (gdbarch,
4022					ia64_memory_remove_breakpoint);
4023  set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
4024  set_gdbarch_read_pc (gdbarch, ia64_read_pc);
4025  set_gdbarch_write_pc (gdbarch, ia64_write_pc);
4026
4027  /* Settings for calling functions in the inferior.  */
4028  set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
4029  tdep->infcall_ops = ia64_infcall_ops;
4030  set_gdbarch_frame_align (gdbarch, ia64_frame_align);
4031  set_gdbarch_dummy_id (gdbarch, ia64_dummy_id);
4032
4033  set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
4034#ifdef HAVE_LIBUNWIND_IA64_H
4035  frame_unwind_append_unwinder (gdbarch,
4036                                &ia64_libunwind_sigtramp_frame_unwind);
4037  frame_unwind_append_unwinder (gdbarch, &ia64_libunwind_frame_unwind);
4038  frame_unwind_append_unwinder (gdbarch, &ia64_sigtramp_frame_unwind);
4039  libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
4040#else
4041  frame_unwind_append_unwinder (gdbarch, &ia64_sigtramp_frame_unwind);
4042#endif
4043  frame_unwind_append_unwinder (gdbarch, &ia64_frame_unwind);
4044  frame_base_set_default (gdbarch, &ia64_frame_base);
4045
4046  /* Settings that should be unnecessary.  */
4047  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4048
4049  set_gdbarch_print_insn (gdbarch, ia64_print_insn);
4050  set_gdbarch_convert_from_func_ptr_addr (gdbarch,
4051					  ia64_convert_from_func_ptr_addr);
4052
4053  /* The virtual table contains 16-byte descriptors, not pointers to
4054     descriptors.  */
4055  set_gdbarch_vtable_function_descriptors (gdbarch, 1);
4056
4057  /* Hook in ABI-specific overrides, if they have been registered.  */
4058  gdbarch_init_osabi (info, gdbarch);
4059
4060  return gdbarch;
4061}
4062
4063extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
4064
4065void
4066_initialize_ia64_tdep (void)
4067{
4068  gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
4069}
4070