1/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
2/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
3/* { dg-require-effective-target powerpc_altivec_ok } */
4/* { dg-options "-maltivec -mabi=altivec -O2" } */
5
6/* Check that "easy" AltiVec constants are correctly synthesized.  */
7
8extern void abort (void);
9
10typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
11typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
12typedef __attribute__ ((vector_size (16))) unsigned int v4si;
13
14char w[16] __attribute__((aligned(16)));
15
16
17/* Emulate the vspltis? instructions on a 16-byte array of chars.  */
18
19void vspltisb (char *v, int val)
20{
21  int i;
22  for (i = 0; i < 16; i++)
23    v[i] = val;
24}
25
26void vspltish (char *v, int val)
27{
28  int i;
29  for (i = 0; i < 16; i += 2)
30    v[i] = val >> 7, v[i + 1] = val;
31}
32
33void vspltisw (char *v, int val)
34{
35  int i;
36  for (i = 0; i < 16; i += 4)
37    v[i] = v[i + 1] = v[i + 2] = val >> 7, v[i + 3] = val;
38}
39
40
41/* Use three different check functions for each mode-instruction pair.
42   The callers have no typecasting and no addressable vectors, to make
43   the test more robust.  */
44
45void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
46{
47  if (memcmp (&v1, v2, 16))
48    abort ();
49}
50
51void __attribute__ ((noinline)) check_v8hi (v8hi v1, char *v2)
52{
53  if (memcmp (&v1, v2, 16))
54    abort ();
55}
56
57void __attribute__ ((noinline)) check_v4si (v4si v1, char *v2)
58{
59  if (memcmp (&v1, v2, 16))
60    abort ();
61}
62
63
64/* V16QI tests.  */
65
66void v16qi_vspltisb ()
67{
68  v16qi v = { 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15 };
69  vspltisb (w, 15);
70  check_v16qi (v, w);
71}
72
73void v16qi_vspltisb_neg ()
74{
75  v16qi v = { -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5 };
76  vspltisb (w, -5);
77  check_v16qi (v, w);
78}
79
80void v16qi_vspltisb_addself ()
81{
82  v16qi v = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30 };
83  vspltisb (w, 30);
84  check_v16qi (v, w);
85}
86
87void v16qi_vspltisb_neg_addself ()
88{
89  v16qi v = { -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24 };
90  vspltisb (w, -24);
91  check_v16qi (v, w);
92}
93
94void v16qi_vspltish ()
95{
96  v16qi v = { 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15 };
97  vspltish (w, 15);
98  check_v16qi (v, w);
99}
100
101void v16qi_vspltish_addself ()
102{
103  v16qi v = { 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30 };
104  vspltish (w, 30);
105  check_v16qi (v, w);
106}
107
108void v16qi_vspltish_neg ()
109{
110  v16qi v = { -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5 };
111  vspltish (w, -5);
112  check_v16qi (v, w);
113}
114
115void v16qi_vspltisw ()
116{
117  v16qi v = { 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15 };
118  vspltisw (w, 15);
119  check_v16qi (v, w);
120}
121
122void v16qi_vspltisw_addself ()
123{
124  v16qi v = { 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30 };
125  vspltisw (w, 30);
126  check_v16qi (v, w);
127}
128
129void v16qi_vspltisw_neg ()
130{
131  v16qi v = { -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5 };
132  vspltisw (w, -5);
133  check_v16qi (v, w);
134}
135
136
137/* V8HI tests. */
138
139void v8hi_vspltisb ()
140{
141  v8hi v = { 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F };
142  vspltisb (w, 15);
143  check_v8hi (v, w);
144}
145
146void v8hi_vspltisb_addself ()
147{
148  v8hi v = { 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E };
149  vspltisb (w, 30);
150  check_v8hi (v, w);
151}
152
153void v8hi_vspltisb_neg ()
154{
155  v8hi v = { 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB };
156  vspltisb (w, -5);
157  check_v8hi (v, w);
158}
159
160void v8hi_vspltish ()
161{
162  v8hi v = { 15, 15, 15, 15, 15, 15, 15, 15 };
163  vspltish (w, 15);
164  check_v8hi (v, w);
165}
166
167void v8hi_vspltish_neg ()
168{
169  v8hi v = { -5, -5, -5, -5, -5, -5, -5, -5 };
170  vspltish (w, -5);
171  check_v8hi (v, w);
172}
173
174void v8hi_vspltish_addself ()
175{
176  v8hi v = { 30, 30, 30, 30, 30, 30, 30, 30 };
177  vspltish (w, 30);
178  check_v8hi (v, w);
179}
180
181void v8hi_vspltish_neg_addself ()
182{
183  v8hi v = { -24, -24, -24, -24, -24, -24, -24, -24 };
184  vspltish (w, -24);
185  check_v8hi (v, w);
186}
187
188void v8hi_vspltisw ()
189{
190  v8hi v = { 0, 15, 0, 15, 0, 15, 0, 15 };
191  vspltisw (w, 15);
192  check_v8hi (v, w);
193}
194
195void v8hi_vspltisw_addself ()
196{
197  v8hi v = { 0, 30, 0, 30, 0, 30, 0, 30 };
198  vspltisw (w, 30);
199  check_v8hi (v, w);
200}
201
202void v8hi_vspltisw_neg ()
203{
204  v8hi v = { -1, -5, -1, -5, -1, -5, -1, -5 };
205  vspltisw (w, -5);
206  check_v8hi (v, w);
207}
208
209/* V4SI tests. */
210
211void v4si_vspltisb ()
212{
213  v4si v = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F };
214  vspltisb (w, 15);
215  check_v4si (v, w);
216}
217
218void v4si_vspltisb_addself ()
219{
220  v4si v = { 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E };
221  vspltisb (w, 30);
222  check_v4si (v, w);
223}
224
225void v4si_vspltisb_neg ()
226{
227  v4si v = { 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB };
228  vspltisb (w, -5);
229  check_v4si (v, w);
230}
231
232void v4si_vspltish ()
233{
234  v4si v = { 0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F };
235  vspltish (w, 15);
236  check_v4si (v, w);
237}
238
239void v4si_vspltish_addself ()
240{
241  v4si v = { 0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E };
242  vspltish (w, 30);
243  check_v4si (v, w);
244}
245
246void v4si_vspltish_neg ()
247{
248  v4si v = { 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB };
249  vspltish (w, -5);
250  check_v4si (v, w);
251}
252
253void v4si_vspltisw ()
254{
255  v4si v = { 15, 15, 15, 15 };
256  vspltisw (w, 15);
257  check_v4si (v, w);
258}
259
260void v4si_vspltisw_neg ()
261{
262  v4si v = { -5, -5, -5, -5 };
263  vspltisw (w, -5);
264  check_v4si (v, w);
265}
266
267void v4si_vspltisw_addself ()
268{
269  v4si v = { 30, 30, 30, 30 };
270  vspltisw (w, 30);
271  check_v4si (v, w);
272}
273
274void v4si_vspltisw_neg_addself ()
275{
276  v4si v = { -24, -24, -24, -24 };
277  vspltisw (w, -24);
278  check_v4si (v, w);
279}
280
281
282
283int main ()
284{
285  v16qi_vspltisb ();
286  v16qi_vspltisb_neg ();
287  v16qi_vspltisb_addself ();
288  v16qi_vspltisb_neg_addself ();
289  v16qi_vspltish ();
290  v16qi_vspltish_addself ();
291  v16qi_vspltish_neg ();
292  v16qi_vspltisw ();
293  v16qi_vspltisw_addself ();
294  v16qi_vspltisw_neg ();
295
296  v8hi_vspltisb ();
297  v8hi_vspltisb_addself ();
298  v8hi_vspltisb_neg ();
299  v8hi_vspltish ();
300  v8hi_vspltish_neg ();
301  v8hi_vspltish_addself ();
302  v8hi_vspltish_neg_addself ();
303  v8hi_vspltisw ();
304  v8hi_vspltisw_addself ();
305  v8hi_vspltisw_neg ();
306
307  v4si_vspltisb ();
308  v4si_vspltisb_addself ();
309  v4si_vspltisb_neg ();
310  v4si_vspltish ();
311  v4si_vspltish_addself ();
312  v4si_vspltish_neg ();
313  v4si_vspltisw ();
314  v4si_vspltisw_neg ();
315  v4si_vspltisw_addself ();
316  v4si_vspltisw_neg_addself ();
317  return 0;
318}
319