1/* Definitions of Tensilica's Xtensa target machine for GNU compiler. 2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 3 Free Software Foundation, Inc. 4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. 5 6This file is part of GCC. 7 8GCC is free software; you can redistribute it and/or modify it under 9the terms of the GNU General Public License as published by the Free 10Software Foundation; either version 3, or (at your option) any later 11version. 12 13GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14WARRANTY; without even the implied warranty of MERCHANTABILITY or 15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16for more details. 17 18You should have received a copy of the GNU General Public License 19along with GCC; see the file COPYING3. If not see 20<http://www.gnu.org/licenses/>. */ 21 22/* Get Xtensa configuration settings */ 23#include "xtensa-config.h" 24 25/* Standard GCC variables that we reference. */ 26extern int optimize; 27 28/* External variables defined in xtensa.c. */ 29 30extern unsigned xtensa_current_frame_size; 31 32/* Macros used in the machine description to select various Xtensa 33 configuration options. */ 34#ifndef XCHAL_HAVE_MUL32_HIGH 35#define XCHAL_HAVE_MUL32_HIGH 0 36#endif 37#ifndef XCHAL_HAVE_RELEASE_SYNC 38#define XCHAL_HAVE_RELEASE_SYNC 0 39#endif 40#ifndef XCHAL_HAVE_S32C1I 41#define XCHAL_HAVE_S32C1I 0 42#endif 43#ifndef XCHAL_HAVE_THREADPTR 44#define XCHAL_HAVE_THREADPTR 0 45#endif 46#define TARGET_BIG_ENDIAN XCHAL_HAVE_BE 47#define TARGET_DENSITY XCHAL_HAVE_DENSITY 48#define TARGET_MAC16 XCHAL_HAVE_MAC16 49#define TARGET_MUL16 XCHAL_HAVE_MUL16 50#define TARGET_MUL32 XCHAL_HAVE_MUL32 51#define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH 52#define TARGET_DIV32 XCHAL_HAVE_DIV32 53#define TARGET_NSA XCHAL_HAVE_NSA 54#define TARGET_MINMAX XCHAL_HAVE_MINMAX 55#define TARGET_SEXT XCHAL_HAVE_SEXT 56#define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS 57#define TARGET_HARD_FLOAT XCHAL_HAVE_FP 58#define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV 59#define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP 60#define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT 61#define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT 62#define TARGET_ABS XCHAL_HAVE_ABS 63#define TARGET_ADDX XCHAL_HAVE_ADDX 64#define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC 65#define TARGET_S32C1I XCHAL_HAVE_S32C1I 66#define TARGET_ABSOLUTE_LITERALS XSHAL_USE_ABSOLUTE_LITERALS 67#define TARGET_THREADPTR XCHAL_HAVE_THREADPTR 68 69#define TARGET_DEFAULT \ 70 ((XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \ 71 MASK_SERIALIZE_VOLATILE) 72 73#ifndef HAVE_AS_TLS 74#define HAVE_AS_TLS 0 75#endif 76 77#define OVERRIDE_OPTIONS override_options () 78 79/* Reordering blocks for Xtensa is not a good idea unless the compiler 80 understands the range of conditional branches. Currently all branch 81 relaxation for Xtensa is handled in the assembler, so GCC cannot do a 82 good job of reordering blocks. Do not enable reordering unless it is 83 explicitly requested. */ 84#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 85 do \ 86 { \ 87 flag_reorder_blocks = 0; \ 88 } \ 89 while (0) 90 91 92/* Target CPU builtins. */ 93#define TARGET_CPU_CPP_BUILTINS() \ 94 do { \ 95 builtin_assert ("cpu=xtensa"); \ 96 builtin_assert ("machine=xtensa"); \ 97 builtin_define ("__xtensa__"); \ 98 builtin_define ("__XTENSA__"); \ 99 builtin_define ("__XTENSA_WINDOWED_ABI__"); \ 100 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \ 101 if (!TARGET_HARD_FLOAT) \ 102 builtin_define ("__XTENSA_SOFT_FLOAT__"); \ 103 } while (0) 104 105#define CPP_SPEC " %(subtarget_cpp_spec) " 106 107#ifndef SUBTARGET_CPP_SPEC 108#define SUBTARGET_CPP_SPEC "" 109#endif 110 111#define EXTRA_SPECS \ 112 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, 113 114#ifdef __XTENSA_EB__ 115#define LIBGCC2_WORDS_BIG_ENDIAN 1 116#else 117#define LIBGCC2_WORDS_BIG_ENDIAN 0 118#endif 119 120/* Show we can debug even without a frame pointer. */ 121#define CAN_DEBUG_WITHOUT_FP 122 123 124/* Target machine storage layout */ 125 126/* Define this if most significant bit is lowest numbered 127 in instructions that operate on numbered bit-fields. */ 128#define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 129 130/* Define this if most significant byte of a word is the lowest numbered. */ 131#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 132 133/* Define this if most significant word of a multiword number is the lowest. */ 134#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 135 136#define MAX_BITS_PER_WORD 32 137 138/* Width of a word, in units (bytes). */ 139#define UNITS_PER_WORD 4 140#define MIN_UNITS_PER_WORD 4 141 142/* Width of a floating point register. */ 143#define UNITS_PER_FPREG 4 144 145/* Size in bits of various types on the target machine. */ 146#define INT_TYPE_SIZE 32 147#define SHORT_TYPE_SIZE 16 148#define LONG_TYPE_SIZE 32 149#define LONG_LONG_TYPE_SIZE 64 150#define FLOAT_TYPE_SIZE 32 151#define DOUBLE_TYPE_SIZE 64 152#define LONG_DOUBLE_TYPE_SIZE 64 153 154/* Allocation boundary (in *bits*) for storing pointers in memory. */ 155#define POINTER_BOUNDARY 32 156 157/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 158#define PARM_BOUNDARY 32 159 160/* Allocation boundary (in *bits*) for the code of a function. */ 161#define FUNCTION_BOUNDARY 32 162 163/* Alignment of field after 'int : 0' in a structure. */ 164#define EMPTY_FIELD_BOUNDARY 32 165 166/* Every structure's size must be a multiple of this. */ 167#define STRUCTURE_SIZE_BOUNDARY 8 168 169/* There is no point aligning anything to a rounder boundary than this. */ 170#define BIGGEST_ALIGNMENT 128 171 172/* Set this nonzero if move instructions will actually fail to work 173 when given unaligned data. */ 174#define STRICT_ALIGNMENT 1 175 176/* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP 177 for QImode, because there is no 8-bit load from memory with sign 178 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit 179 loads both with and without sign extension. */ 180#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 181 do { \ 182 if (GET_MODE_CLASS (MODE) == MODE_INT \ 183 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 184 { \ 185 if ((MODE) == QImode) \ 186 (UNSIGNEDP) = 1; \ 187 (MODE) = SImode; \ 188 } \ 189 } while (0) 190 191/* Imitate the way many other C compilers handle alignment of 192 bitfields and the structures that contain them. */ 193#define PCC_BITFIELD_TYPE_MATTERS 1 194 195/* Disable the use of word-sized or smaller complex modes for structures, 196 and for function arguments in particular, where they cause problems with 197 register a7. The xtensa_copy_incoming_a7 function assumes that there is 198 a single reference to an argument in a7, but with small complex modes the 199 real and imaginary components may be extracted separately, leading to two 200 uses of the register, only one of which would be replaced. */ 201#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ 202 ((MODE) == CQImode || (MODE) == CHImode) 203 204/* Align string constants and constructors to at least a word boundary. 205 The typical use of this macro is to increase alignment for string 206 constants to be word aligned so that 'strcpy' calls that copy 207 constants can be done inline. */ 208#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 209 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 210 && (ALIGN) < BITS_PER_WORD \ 211 ? BITS_PER_WORD \ 212 : (ALIGN)) 213 214/* Align arrays, unions and records to at least a word boundary. 215 One use of this macro is to increase alignment of medium-size 216 data to make it all fit in fewer cache lines. Another is to 217 cause character arrays to be word-aligned so that 'strcpy' calls 218 that copy constants to character arrays can be done inline. */ 219#undef DATA_ALIGNMENT 220#define DATA_ALIGNMENT(TYPE, ALIGN) \ 221 ((((ALIGN) < BITS_PER_WORD) \ 222 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 223 || TREE_CODE (TYPE) == UNION_TYPE \ 224 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 225 226/* Operations between registers always perform the operation 227 on the full register even if a narrower mode is specified. */ 228#define WORD_REGISTER_OPERATIONS 229 230/* Xtensa loads are zero-extended by default. */ 231#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 232 233/* Standard register usage. */ 234 235/* Number of actual hardware registers. 236 The hardware registers are assigned numbers for the compiler 237 from 0 to just below FIRST_PSEUDO_REGISTER. 238 All registers that the compiler knows about must be given numbers, 239 even those that are not normally considered general registers. 240 241 The fake frame pointer and argument pointer will never appear in 242 the generated code, since they will always be eliminated and replaced 243 by either the stack pointer or the hard frame pointer. 244 245 0 - 15 AR[0] - AR[15] 246 16 FRAME_POINTER (fake = initial sp) 247 17 ARG_POINTER (fake = initial sp + framesize) 248 18 BR[0] for floating-point CC 249 19 - 34 FR[0] - FR[15] 250 35 MAC16 accumulator */ 251 252#define FIRST_PSEUDO_REGISTER 36 253 254/* Return the stabs register number to use for REGNO. */ 255#define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO) 256 257/* 1 for registers that have pervasive standard uses 258 and are not available for the register allocator. */ 259#define FIXED_REGISTERS \ 260{ \ 261 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 262 1, 1, 0, \ 263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 264 0, \ 265} 266 267/* 1 for registers not available across function calls. 268 These must include the FIXED_REGISTERS and also any 269 registers that can be used without being saved. 270 The latter must include the registers where values are returned 271 and the register where structure-value addresses are passed. 272 Aside from that, you can include as many other registers as you like. */ 273#define CALL_USED_REGISTERS \ 274{ \ 275 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 276 1, 1, 1, \ 277 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 278 1, \ 279} 280 281/* For non-leaf procedures on Xtensa processors, the allocation order 282 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we 283 want to use the lowest numbered registers first to minimize 284 register window overflows. However, local-alloc is not smart 285 enough to consider conflicts with incoming arguments. If an 286 incoming argument in a2 is live throughout the function and 287 local-alloc decides to use a2, then the incoming argument must 288 either be spilled or copied to another register. To get around 289 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine 290 reg_alloc_order for leaf functions such that lowest numbered 291 registers are used first with the exception that the incoming 292 argument registers are not used until after other register choices 293 have been exhausted. */ 294 295#define REG_ALLOC_ORDER \ 296{ 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \ 297 18, \ 298 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \ 299 0, 1, 16, 17, \ 300 35, \ 301} 302 303#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 304 305/* For Xtensa, the only point of this is to prevent GCC from otherwise 306 giving preference to call-used registers. To minimize window 307 overflows for the AR registers, we want to give preference to the 308 lower-numbered AR registers. For other register files, which are 309 not windowed, we still prefer call-used registers, if there are any. */ 310extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER]; 311#define LEAF_REGISTERS xtensa_leaf_regs 312 313/* For Xtensa, no remapping is necessary, but this macro must be 314 defined if LEAF_REGISTERS is defined. */ 315#define LEAF_REG_REMAP(REGNO) (REGNO) 316 317/* This must be declared if LEAF_REGISTERS is set. */ 318extern int leaf_function; 319 320/* Internal macros to classify a register number. */ 321 322/* 16 address registers + fake registers */ 323#define GP_REG_FIRST 0 324#define GP_REG_LAST 17 325#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 326 327/* Coprocessor registers */ 328#define BR_REG_FIRST 18 329#define BR_REG_LAST 18 330#define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1) 331 332/* 16 floating-point registers */ 333#define FP_REG_FIRST 19 334#define FP_REG_LAST 34 335#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 336 337/* MAC16 accumulator */ 338#define ACC_REG_FIRST 35 339#define ACC_REG_LAST 35 340#define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1) 341 342#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) 343#define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM) 344#define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM) 345#define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM) 346 347/* Return number of consecutive hard regs needed starting at reg REGNO 348 to hold something of mode MODE. */ 349#define HARD_REGNO_NREGS(REGNO, MODE) \ 350 (FP_REG_P (REGNO) ? \ 351 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \ 352 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 353 354/* Value is 1 if hard register REGNO can hold a value of machine-mode 355 MODE. */ 356extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; 357 358#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 359 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)] 360 361/* Value is 1 if it is a good idea to tie two pseudo registers 362 when one has mode MODE1 and one has mode MODE2. 363 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 364 for any hard reg, then this must be 0 for correct output. */ 365#define MODES_TIEABLE_P(MODE1, MODE2) \ 366 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ 367 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 368 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ 369 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 370 371/* Register to use for pushing function arguments. */ 372#define STACK_POINTER_REGNUM (GP_REG_FIRST + 1) 373 374/* Base register for access to local variables of the function. */ 375#define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7) 376 377/* The register number of the frame pointer register, which is used to 378 access automatic variables in the stack frame. For Xtensa, this 379 register never appears in the output. It is always eliminated to 380 either the stack pointer or the hard frame pointer. */ 381#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16) 382 383/* Base register for access to arguments of the function. */ 384#define ARG_POINTER_REGNUM (GP_REG_FIRST + 17) 385 386/* For now we don't try to use the full set of boolean registers. Without 387 software pipelining of FP operations, there's not much to gain and it's 388 a real pain to get them reloaded. */ 389#define FPCC_REGNUM (BR_REG_FIRST + 0) 390 391/* It is as good or better to call a constant function address than to 392 call an address kept in a register. */ 393#define NO_FUNCTION_CSE 1 394 395/* Xtensa processors have "register windows". GCC does not currently 396 take advantage of the possibility for variable-sized windows; instead, 397 we use a fixed window size of 8. */ 398 399#define INCOMING_REGNO(OUT) \ 400 ((GP_REG_P (OUT) && \ 401 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \ 402 (OUT) - WINDOW_SIZE : (OUT)) 403 404#define OUTGOING_REGNO(IN) \ 405 ((GP_REG_P (IN) && \ 406 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \ 407 (IN) + WINDOW_SIZE : (IN)) 408 409 410/* Define the classes of registers for register constraints in the 411 machine description. */ 412enum reg_class 413{ 414 NO_REGS, /* no registers in set */ 415 BR_REGS, /* coprocessor boolean registers */ 416 FP_REGS, /* floating point registers */ 417 ACC_REG, /* MAC16 accumulator */ 418 SP_REG, /* sp register (aka a1) */ 419 RL_REGS, /* preferred reload regs (not sp or fp) */ 420 GR_REGS, /* integer registers except sp */ 421 AR_REGS, /* all integer registers */ 422 ALL_REGS, /* all registers */ 423 LIM_REG_CLASSES /* max value + 1 */ 424}; 425 426#define N_REG_CLASSES (int) LIM_REG_CLASSES 427 428#define GENERAL_REGS AR_REGS 429 430/* An initializer containing the names of the register classes as C 431 string constants. These names are used in writing some of the 432 debugging dumps. */ 433#define REG_CLASS_NAMES \ 434{ \ 435 "NO_REGS", \ 436 "BR_REGS", \ 437 "FP_REGS", \ 438 "ACC_REG", \ 439 "SP_REG", \ 440 "RL_REGS", \ 441 "GR_REGS", \ 442 "AR_REGS", \ 443 "ALL_REGS" \ 444} 445 446/* Contents of the register classes. The Nth integer specifies the 447 contents of class N. The way the integer MASK is interpreted is 448 that register R is in the class if 'MASK & (1 << R)' is 1. */ 449#define REG_CLASS_CONTENTS \ 450{ \ 451 { 0x00000000, 0x00000000 }, /* no registers */ \ 452 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \ 453 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \ 454 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \ 455 { 0x00000002, 0x00000000 }, /* stack pointer register */ \ 456 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \ 457 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \ 458 { 0x0003ffff, 0x00000000 }, /* integer registers */ \ 459 { 0xffffffff, 0x0000000f } /* all registers */ \ 460} 461 462#define IRA_COVER_CLASSES \ 463{ \ 464 BR_REGS, FP_REGS, ACC_REG, AR_REGS, LIM_REG_CLASSES \ 465} 466 467/* A C expression whose value is a register class containing hard 468 register REGNO. In general there is more that one such class; 469 choose a class which is "minimal", meaning that no smaller class 470 also contains the register. */ 471extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER]; 472 473#define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ] 474 475/* Use the Xtensa AR register file for base registers. 476 No index registers. */ 477#define BASE_REG_CLASS AR_REGS 478#define INDEX_REG_CLASS NO_REGS 479 480/* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the 481 16 AR registers may be explicitly used in the RTL, as either 482 incoming or outgoing arguments. */ 483#define SMALL_REGISTER_CLASSES 1 484 485#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 486 xtensa_preferred_reload_class (X, CLASS, 0) 487 488#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ 489 xtensa_preferred_reload_class (X, CLASS, 1) 490 491/* Return the maximum number of consecutive registers 492 needed to represent mode MODE in a register of class CLASS. */ 493#define CLASS_UNITS(mode, size) \ 494 ((GET_MODE_SIZE (mode) + (size) - 1) / (size)) 495 496#define CLASS_MAX_NREGS(CLASS, MODE) \ 497 (CLASS_UNITS (MODE, UNITS_PER_WORD)) 498 499 500/* Stack layout; function entry, exit and calling. */ 501 502#define STACK_GROWS_DOWNWARD 503 504/* Offset within stack frame to start allocating local variables at. */ 505#define STARTING_FRAME_OFFSET \ 506 crtl->outgoing_args_size 507 508/* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so 509 they are eliminated to either the stack pointer or hard frame pointer. */ 510#define ELIMINABLE_REGS \ 511{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 512 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 513 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 514 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 515 516/* Specify the initial difference between the specified pair of registers. */ 517#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 518 do { \ 519 compute_frame_size (get_frame_size ()); \ 520 switch (FROM) \ 521 { \ 522 case FRAME_POINTER_REGNUM: \ 523 (OFFSET) = 0; \ 524 break; \ 525 case ARG_POINTER_REGNUM: \ 526 (OFFSET) = xtensa_current_frame_size; \ 527 break; \ 528 default: \ 529 gcc_unreachable (); \ 530 } \ 531 } while (0) 532 533/* If defined, the maximum amount of space required for outgoing 534 arguments will be computed and placed into the variable 535 'crtl->outgoing_args_size'. No space will be pushed 536 onto the stack for each call; instead, the function prologue 537 should increase the stack frame size by this amount. */ 538#define ACCUMULATE_OUTGOING_ARGS 1 539 540/* Offset from the argument pointer register to the first argument's 541 address. On some machines it may depend on the data type of the 542 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the 543 location above the first argument's address. */ 544#define FIRST_PARM_OFFSET(FNDECL) 0 545 546/* Align stack frames on 128 bits for Xtensa. This is necessary for 547 128-bit datatypes defined in TIE (e.g., for Vectra). */ 548#define STACK_BOUNDARY 128 549 550/* Functions do not pop arguments off the stack. */ 551#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 552 553/* Use a fixed register window size of 8. */ 554#define WINDOW_SIZE 8 555 556/* Symbolic macros for the registers used to return integer, floating 557 point, and values of coprocessor and user-defined modes. */ 558#define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE) 559#define GP_OUTGOING_RETURN (GP_REG_FIRST + 2) 560 561/* Symbolic macros for the first/last argument registers. */ 562#define GP_ARG_FIRST (GP_REG_FIRST + 2) 563#define GP_ARG_LAST (GP_REG_FIRST + 7) 564#define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE) 565#define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE) 566 567#define MAX_ARGS_IN_REGISTERS 6 568 569/* Don't worry about compatibility with PCC. */ 570#define DEFAULT_PCC_STRUCT_RETURN 0 571 572/* Define how to find the value returned by a library function 573 assuming the value has mode MODE. Because we have defined 574 TARGET_PROMOTE_FUNCTION_MODE to promote everything, we have to 575 perform the same promotions as PROMOTE_MODE. */ 576#define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \ 577 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \ 578 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 579 ? SImode : (MODE), \ 580 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN) 581 582#define LIBCALL_VALUE(MODE) \ 583 XTENSA_LIBCALL_VALUE ((MODE), 0) 584 585#define LIBCALL_OUTGOING_VALUE(MODE) \ 586 XTENSA_LIBCALL_VALUE ((MODE), 1) 587 588/* A C expression that is nonzero if REGNO is the number of a hard 589 register in which the values of called function may come back. A 590 register whose use for returning values is limited to serving as 591 the second of a pair (for a value of type 'double', say) need not 592 be recognized by this macro. If the machine has register windows, 593 so that the caller and the called function use different registers 594 for the return value, this macro should recognize only the caller's 595 register numbers. */ 596#define FUNCTION_VALUE_REGNO_P(N) \ 597 ((N) == GP_RETURN) 598 599/* A C expression that is nonzero if REGNO is the number of a hard 600 register in which function arguments are sometimes passed. This 601 does *not* include implicit arguments such as the static chain and 602 the structure-value address. On many machines, no registers can be 603 used for this purpose since all function arguments are pushed on 604 the stack. */ 605#define FUNCTION_ARG_REGNO_P(N) \ 606 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST) 607 608/* Record the number of argument words seen so far, along with a flag to 609 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG 610 is used for both incoming and outgoing args, so a separate flag is 611 needed. */ 612typedef struct xtensa_args 613{ 614 int arg_words; 615 int incoming; 616} CUMULATIVE_ARGS; 617 618#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 619 init_cumulative_args (&CUM, 0) 620 621#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 622 init_cumulative_args (&CUM, 1) 623 624/* Update the data in CUM to advance over an argument 625 of mode MODE and data type TYPE. 626 (TYPE is null for libcalls where that information may not be available.) */ 627#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 628 function_arg_advance (&CUM, MODE, TYPE) 629 630#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 631 function_arg (&CUM, MODE, TYPE, FALSE) 632 633#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 634 function_arg (&CUM, MODE, TYPE, TRUE) 635 636#define FUNCTION_ARG_BOUNDARY function_arg_boundary 637 638/* Profiling Xtensa code is typically done with the built-in profiling 639 feature of Tensilica's instruction set simulator, which does not 640 require any compiler support. Profiling code on a real (i.e., 641 non-simulated) Xtensa processor is currently only supported by 642 GNU/Linux with glibc. The glibc version of _mcount doesn't require 643 counter variables. The _mcount function needs the current PC and 644 the current return address to identify an arc in the call graph. 645 Pass the current return address as the first argument; the current 646 PC is available as a0 in _mcount's register window. Both of these 647 values contain window size information in the two most significant 648 bits; we assume that _mcount will mask off those bits. The call to 649 _mcount uses a window size of 8 to make sure that it doesn't clobber 650 any incoming argument values. */ 651 652#define NO_PROFILE_COUNTERS 1 653 654#define FUNCTION_PROFILER(FILE, LABELNO) \ 655 do { \ 656 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \ 657 if (flag_pic) \ 658 { \ 659 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \ 660 fprintf (FILE, "\tcallx8\ta8\n"); \ 661 } \ 662 else \ 663 fprintf (FILE, "\tcall8\t_mcount\n"); \ 664 } while (0) 665 666/* Stack pointer value doesn't matter at exit. */ 667#define EXIT_IGNORE_STACK 1 668 669/* Size in bytes of the trampoline, as an integer. Make sure this is 670 a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */ 671#define TRAMPOLINE_SIZE (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? 60 : 52) 672 673/* Alignment required for trampolines, in bits. */ 674#define TRAMPOLINE_ALIGNMENT 32 675 676/* If defined, a C expression that produces the machine-specific code 677 to setup the stack so that arbitrary frames can be accessed. 678 679 On Xtensa, a stack back-trace must always begin from the stack pointer, 680 so that the register overflow save area can be located. However, the 681 stack-walking code in GCC always begins from the hard_frame_pointer 682 register, not the stack pointer. The frame pointer is usually equal 683 to the stack pointer, but the __builtin_return_address and 684 __builtin_frame_address functions will not work if count > 0 and 685 they are called from a routine that uses alloca. These functions 686 are not guaranteed to work at all if count > 0 so maybe that is OK. 687 688 A nicer solution would be to allow the architecture-specific files to 689 specify whether to start from the stack pointer or frame pointer. That 690 would also allow us to skip the machine->accesses_prev_frame stuff that 691 we currently need to ensure that there is a frame pointer when these 692 builtin functions are used. */ 693 694#define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses 695 696/* A C expression whose value is RTL representing the address in a 697 stack frame where the pointer to the caller's frame is stored. 698 Assume that FRAMEADDR is an RTL expression for the address of the 699 stack frame itself. 700 701 For Xtensa, there is no easy way to get the frame pointer if it is 702 not equivalent to the stack pointer. Moreover, the result of this 703 macro is used for continuing to walk back up the stack, so it must 704 return the stack pointer address. Thus, there is some inconsistency 705 here in that __builtin_frame_address will return the frame pointer 706 when count == 0 and the stack pointer when count > 0. */ 707 708#define DYNAMIC_CHAIN_ADDRESS(frame) \ 709 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD)) 710 711/* Define this if the return address of a particular stack frame is 712 accessed from the frame pointer of the previous stack frame. */ 713#define RETURN_ADDR_IN_PREVIOUS_FRAME 714 715/* A C expression whose value is RTL representing the value of the 716 return address for the frame COUNT steps up from the current 717 frame, after the prologue. */ 718#define RETURN_ADDR_RTX xtensa_return_addr 719 720/* Addressing modes, and classification of registers for them. */ 721 722/* C expressions which are nonzero if register number NUM is suitable 723 for use as a base or index register in operand addresses. */ 724 725#define REGNO_OK_FOR_INDEX_P(NUM) 0 726#define REGNO_OK_FOR_BASE_P(NUM) \ 727 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM])) 728 729/* C expressions that are nonzero if X (assumed to be a `reg' RTX) is 730 valid for use as a base or index register. */ 731 732#ifdef REG_OK_STRICT 733#define REG_OK_STRICT_FLAG 1 734#else 735#define REG_OK_STRICT_FLAG 0 736#endif 737 738#define BASE_REG_P(X, STRICT) \ 739 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 740 || REGNO_OK_FOR_BASE_P (REGNO (X))) 741 742#define REG_OK_FOR_INDEX_P(X) 0 743#define REG_OK_FOR_BASE_P(X) BASE_REG_P (X, REG_OK_STRICT_FLAG) 744 745/* Maximum number of registers that can appear in a valid memory address. */ 746#define MAX_REGS_PER_ADDRESS 1 747 748/* A C expression that is 1 if the RTX X is a constant which is a 749 valid address. This is defined to be the same as 'CONSTANT_P (X)', 750 but rejecting CONST_DOUBLE. */ 751#define CONSTANT_ADDRESS_P(X) \ 752 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 753 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 754 || (GET_CODE (X) == CONST))) 755 756/* Nonzero if the constant value X is a legitimate general operand. 757 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 758#define LEGITIMATE_CONSTANT_P(X) (! xtensa_tls_referenced_p (X)) 759 760/* A C expression that is nonzero if X is a legitimate immediate 761 operand on the target machine when generating position independent 762 code. */ 763#define LEGITIMATE_PIC_OPERAND_P(X) \ 764 ((GET_CODE (X) != SYMBOL_REF \ 765 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \ 766 && GET_CODE (X) != LABEL_REF \ 767 && GET_CODE (X) != CONST) 768 769/* Treat constant-pool references as "mode dependent" since they can 770 only be accessed with SImode loads. This works around a bug in the 771 combiner where a constant pool reference is temporarily converted 772 to an HImode load, which is then assumed to zero-extend based on 773 our definition of LOAD_EXTEND_OP. This is wrong because the high 774 bits of a 16-bit value in the constant pool are now sign-extended 775 by default. */ 776 777#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 778 do { \ 779 if (constantpool_address_p (ADDR)) \ 780 goto LABEL; \ 781 } while (0) 782 783/* Specify the machine mode that this machine uses 784 for the index in the tablejump instruction. */ 785#define CASE_VECTOR_MODE (SImode) 786 787/* Define this as 1 if 'char' should by default be signed; else as 0. */ 788#define DEFAULT_SIGNED_CHAR 0 789 790/* Max number of bytes we can move from memory to memory 791 in one reasonably fast instruction. */ 792#define MOVE_MAX 4 793#define MAX_MOVE_MAX 4 794 795/* Prefer word-sized loads. */ 796#define SLOW_BYTE_ACCESS 1 797 798/* Shift instructions ignore all but the low-order few bits. */ 799#define SHIFT_COUNT_TRUNCATED 1 800 801/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 802 is done just by pretending it is already truncated. */ 803#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 804 805#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 806#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) 807 808/* Specify the machine mode that pointers have. 809 After generation of rtl, the compiler makes no further distinction 810 between pointers and any other objects of this machine mode. */ 811#define Pmode SImode 812 813/* A function address in a call instruction is a word address (for 814 indexing purposes) so give the MEM rtx a words's mode. */ 815#define FUNCTION_MODE SImode 816 817/* A C expression for the cost of moving data from a register in 818 class FROM to one in class TO. The classes are expressed using 819 the enumeration values such as 'GENERAL_REGS'. A value of 2 is 820 the default; other values are interpreted relative to that. */ 821#define REGISTER_MOVE_COST(MODE, FROM, TO) \ 822 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \ 823 ? 2 \ 824 : (reg_class_subset_p ((FROM), AR_REGS) \ 825 && reg_class_subset_p ((TO), AR_REGS) \ 826 ? 2 \ 827 : (reg_class_subset_p ((FROM), AR_REGS) \ 828 && (TO) == ACC_REG \ 829 ? 3 \ 830 : ((FROM) == ACC_REG \ 831 && reg_class_subset_p ((TO), AR_REGS) \ 832 ? 3 \ 833 : 10)))) 834 835#define MEMORY_MOVE_COST(MODE, CLASS, IN) 4 836 837#define BRANCH_COST(speed_p, predictable_p) 3 838 839/* How to refer to registers in assembler output. 840 This sequence is indexed by compiler's hard-register-number (see above). */ 841#define REGISTER_NAMES \ 842{ \ 843 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \ 844 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \ 845 "fp", "argp", "b0", \ 846 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 847 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 848 "acc" \ 849} 850 851/* If defined, a C initializer for an array of structures containing a 852 name and a register number. This macro defines additional names 853 for hard registers, thus allowing the 'asm' option in declarations 854 to refer to registers using alternate names. */ 855#define ADDITIONAL_REGISTER_NAMES \ 856{ \ 857 { "a1", 1 + GP_REG_FIRST } \ 858} 859 860#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 861#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 862 863/* Recognize machine-specific patterns that may appear within 864 constants. Used for PIC-specific UNSPECs. */ 865#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \ 866 do { \ 867 if (xtensa_output_addr_const_extra (STREAM, X) == FALSE) \ 868 goto FAIL; \ 869 } while (0) 870 871/* Globalizing directive for a label. */ 872#define GLOBAL_ASM_OP "\t.global\t" 873 874/* Declare an uninitialized external linkage data object. */ 875#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 876 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 877 878/* This is how to output an element of a case-vector that is absolute. */ 879#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 880 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \ 881 LOCAL_LABEL_PREFIX, VALUE) 882 883/* This is how to output an element of a case-vector that is relative. 884 This is used for pc-relative code. */ 885#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 886 do { \ 887 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \ 888 LOCAL_LABEL_PREFIX, (VALUE), \ 889 LOCAL_LABEL_PREFIX, (REL)); \ 890 } while (0) 891 892/* This is how to output an assembler line that says to advance the 893 location counter to a multiple of 2**LOG bytes. */ 894#define ASM_OUTPUT_ALIGN(STREAM, LOG) \ 895 do { \ 896 if ((LOG) != 0) \ 897 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \ 898 } while (0) 899 900/* Indicate that jump tables go in the text section. This is 901 necessary when compiling PIC code. */ 902#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 903 904 905/* Define the strings to put out for each section in the object file. */ 906#define TEXT_SECTION_ASM_OP "\t.text" 907#define DATA_SECTION_ASM_OP "\t.data" 908#define BSS_SECTION_ASM_OP "\t.section\t.bss" 909 910 911/* Define output to appear before the constant pool. */ 912#define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \ 913 do { \ 914 if ((SIZE) > 0) \ 915 { \ 916 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \ 917 switch_to_section (function_section (FUNDECL)); \ 918 fprintf (FILE, "\t.literal_position\n"); \ 919 } \ 920 } while (0) 921 922 923/* A C statement (with or without semicolon) to output a constant in 924 the constant pool, if it needs special treatment. */ 925#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \ 926 do { \ 927 xtensa_output_literal (FILE, X, MODE, LABELNO); \ 928 goto JUMPTO; \ 929 } while (0) 930 931/* How to start an assembler comment. */ 932#define ASM_COMMENT_START "#" 933 934/* Exception handling. Xtensa uses much of the standard DWARF2 unwinding 935 machinery, but the variable size register window save areas are too 936 complicated to efficiently describe with CFI entries. The CFA must 937 still be specified in DWARF so that DW_AT_frame_base is set correctly 938 for debugging. */ 939#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0) 940#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0) 941#define DWARF_FRAME_REGISTERS 16 942#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM) 943#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 944 (flag_pic \ 945 ? (((GLOBAL) ? DW_EH_PE_indirect : 0) \ 946 | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 947 : DW_EH_PE_absptr) 948 949/* Emit a PC-relative relocation. */ 950#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 951 do { \ 952 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 953 assemble_name (FILE, LABEL); \ 954 fputs ("@pcrel", FILE); \ 955 } while (0) 956 957/* Xtensa constant pool breaks the devices in crtstuff.c to control 958 section in where code resides. We have to write it as asm code. Use 959 a MOVI and let the assembler relax it -- for the .init and .fini 960 sections, the assembler knows to put the literal in the right 961 place. */ 962#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 963 asm (SECTION_OP "\n\ 964 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\ 965 callx8\ta8\n" \ 966 TEXT_SECTION_ASM_OP); 967