1/* Definitions of target machine GNU compiler. IA-64 version. 2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 3 2009 Free Software Foundation, Inc. 4 Contributed by James E. Wilson <wilson@cygnus.com> and 5 David Mosberger <davidm@hpl.hp.com>. 6 7This file is part of GCC. 8 9GCC is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 3, or (at your option) 12any later version. 13 14GCC is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with GCC; see the file COPYING3. If not see 21<http://www.gnu.org/licenses/>. */ 22 23/* ??? Look at ABI group documents for list of preprocessor macros and 24 other features required for ABI compliance. */ 25 26/* ??? Functions containing a non-local goto target save many registers. Why? 27 See for instance execute/920428-2.c. */ 28 29 30/* Run-time target specifications */ 31 32/* Target CPU builtins. */ 33#define TARGET_CPU_CPP_BUILTINS() \ 34do { \ 35 builtin_assert("cpu=ia64"); \ 36 builtin_assert("machine=ia64"); \ 37 builtin_define("__ia64"); \ 38 builtin_define("__ia64__"); \ 39 builtin_define("__itanium__"); \ 40 if (TARGET_BIG_ENDIAN) \ 41 builtin_define("__BIG_ENDIAN__"); \ 42} while (0) 43 44#ifndef SUBTARGET_EXTRA_SPECS 45#define SUBTARGET_EXTRA_SPECS 46#endif 47 48#define EXTRA_SPECS \ 49 { "asm_extra", ASM_EXTRA_SPEC }, \ 50 SUBTARGET_EXTRA_SPECS 51 52#define CC1_SPEC "%(cc1_cpu) " 53 54#define ASM_EXTRA_SPEC "" 55 56/* Variables which are this size or smaller are put in the sdata/sbss 57 sections. */ 58extern unsigned int ia64_section_threshold; 59 60/* If the assembler supports thread-local storage, assume that the 61 system does as well. If a particular target system has an 62 assembler that supports TLS -- but the rest of the system does not 63 support TLS -- that system should explicit define TARGET_HAVE_TLS 64 to false in its own configuration file. */ 65#if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS) 66#define TARGET_HAVE_TLS true 67#endif 68 69#define TARGET_TLS14 (ia64_tls_size == 14) 70#define TARGET_TLS22 (ia64_tls_size == 22) 71#define TARGET_TLS64 (ia64_tls_size == 64) 72 73#define TARGET_HPUX 0 74#define TARGET_HPUX_LD 0 75 76#define TARGET_ABI_OPEN_VMS 0 77 78#ifndef TARGET_ILP32 79#define TARGET_ILP32 0 80#endif 81 82#ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS 83#define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0 84#endif 85 86/* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and 87 TARGET_INLINE_SQRT. */ 88 89enum ia64_inline_type 90{ 91 INL_NO = 0, 92 INL_MIN_LAT = 1, 93 INL_MAX_THR = 2 94}; 95 96/* Default target_flags if no switches are specified */ 97 98#ifndef TARGET_DEFAULT 99#define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_FUSED_MADD) 100#endif 101 102#ifndef TARGET_CPU_DEFAULT 103#define TARGET_CPU_DEFAULT 0 104#endif 105 106/* Which processor to schedule for. The cpu attribute defines a list 107 that mirrors this list, so changes to ia64.md must be made at the 108 same time. */ 109 110enum processor_type 111{ 112 PROCESSOR_ITANIUM, /* Original Itanium. */ 113 PROCESSOR_ITANIUM2, 114 PROCESSOR_max 115}; 116 117extern enum processor_type ia64_tune; 118 119/* Sometimes certain combinations of command options do not make sense on a 120 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to 121 take account of this. This macro, if defined, is executed once just after 122 all the command options have been parsed. */ 123 124#define OVERRIDE_OPTIONS ia64_override_options () 125 126/* Some machines may desire to change what optimizations are performed for 127 various optimization levels. This macro, if defined, is executed once just 128 after the optimization level is determined and before the remainder of the 129 command options have been parsed. Values set in this macro are used as the 130 default values for the other command line options. */ 131 132/* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */ 133 134/* Driver configuration */ 135 136/* A C string constant that tells the GCC driver program options to pass to 137 `cc1'. It can also specify how to translate options you give to GCC into 138 options for GCC to pass to the `cc1'. */ 139 140#undef CC1_SPEC 141#define CC1_SPEC "%{G*}" 142 143/* A C string constant that tells the GCC driver program options to pass to 144 `cc1plus'. It can also specify how to translate options you give to GCC 145 into options for GCC to pass to the `cc1plus'. */ 146 147/* #define CC1PLUS_SPEC "" */ 148 149/* Storage Layout */ 150 151/* Define this macro to have the value 1 if the most significant bit in a byte 152 has the lowest number; otherwise define it to have the value zero. */ 153 154#define BITS_BIG_ENDIAN 0 155 156#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 157 158/* Define this macro to have the value 1 if, in a multiword object, the most 159 significant word has the lowest number. */ 160 161#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 162 163#if defined(__BIG_ENDIAN__) 164#define LIBGCC2_WORDS_BIG_ENDIAN 1 165#else 166#define LIBGCC2_WORDS_BIG_ENDIAN 0 167#endif 168 169#define UNITS_PER_WORD 8 170 171#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 172 173/* A C expression whose value is zero if pointers that need to be extended 174 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if 175 they are zero-extended and negative one if there is a ptr_extend operation. 176 177 You need not define this macro if the `POINTER_SIZE' is equal to the width 178 of `Pmode'. */ 179/* Need this for 32-bit pointers, see hpux.h for setting it. */ 180/* #define POINTERS_EXTEND_UNSIGNED */ 181 182/* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and 183 which has the specified mode and signedness is to be stored in a register. 184 This macro is only called when TYPE is a scalar type. */ 185#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 186do \ 187 { \ 188 if (GET_MODE_CLASS (MODE) == MODE_INT \ 189 && GET_MODE_SIZE (MODE) < 4) \ 190 (MODE) = SImode; \ 191 } \ 192while (0) 193 194#define PARM_BOUNDARY 64 195 196/* Define this macro if you wish to preserve a certain alignment for the stack 197 pointer. The definition is a C expression for the desired alignment 198 (measured in bits). */ 199 200#define STACK_BOUNDARY 128 201 202/* Align frames on double word boundaries */ 203#ifndef IA64_STACK_ALIGN 204#define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15) 205#endif 206 207#define FUNCTION_BOUNDARY 128 208 209/* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word 210 128-bit integers all require 128-bit alignment. */ 211#define BIGGEST_ALIGNMENT 128 212 213/* If defined, a C expression to compute the alignment for a static variable. 214 TYPE is the data type, and ALIGN is the alignment that the object 215 would ordinarily have. The value of this macro is used instead of that 216 alignment to align the object. */ 217 218#define DATA_ALIGNMENT(TYPE, ALIGN) \ 219 (TREE_CODE (TYPE) == ARRAY_TYPE \ 220 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 221 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 222 223/* If defined, a C expression to compute the alignment given to a constant that 224 is being placed in memory. CONSTANT is the constant and ALIGN is the 225 alignment that the object would ordinarily have. The value of this macro is 226 used instead of that alignment to align the object. */ 227 228#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 229 (TREE_CODE (EXP) == STRING_CST \ 230 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 231 232#define STRICT_ALIGNMENT 1 233 234/* Define this if you wish to imitate the way many other C compilers handle 235 alignment of bitfields and the structures that contain them. 236 The behavior is that the type written for a bit-field (`int', `short', or 237 other integer type) imposes an alignment for the entire structure, as if the 238 structure really did contain an ordinary field of that type. In addition, 239 the bit-field is placed within the structure so that it would fit within such 240 a field, not crossing a boundary for it. */ 241#define PCC_BITFIELD_TYPE_MATTERS 1 242 243/* An integer expression for the size in bits of the largest integer machine 244 mode that should actually be used. */ 245 246/* Allow pairs of registers to be used, which is the intent of the default. */ 247#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 248 249/* By default, the C++ compiler will use function addresses in the 250 vtable entries. Setting this nonzero tells the compiler to use 251 function descriptors instead. The value of this macro says how 252 many words wide the descriptor is (normally 2). It is assumed 253 that the address of a function descriptor may be treated as a 254 pointer to a function. 255 256 For reasons known only to HP, the vtable entries (as opposed to 257 normal function descriptors) are 16 bytes wide in 32-bit mode as 258 well, even though the 3rd and 4th words are unused. */ 259#define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2) 260 261/* Due to silliness in the HPUX linker, vtable entries must be 262 8-byte aligned even in 32-bit mode. Rather than create multiple 263 ABIs, force this restriction on everyone else too. */ 264#define TARGET_VTABLE_ENTRY_ALIGN 64 265 266/* Due to the above, we need extra padding for the data entries below 0 267 to retain the alignment of the descriptors. */ 268#define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1) 269 270/* Layout of Source Language Data Types */ 271 272#define INT_TYPE_SIZE 32 273 274#define SHORT_TYPE_SIZE 16 275 276#define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 277 278#define LONG_LONG_TYPE_SIZE 64 279 280#define FLOAT_TYPE_SIZE 32 281 282#define DOUBLE_TYPE_SIZE 64 283 284/* long double is XFmode normally, and TFmode for HPUX. It should be 285 TFmode for VMS as well but we only support up to DFmode now. */ 286#define LONG_DOUBLE_TYPE_SIZE \ 287 (TARGET_HPUX ? 128 \ 288 : TARGET_ABI_OPEN_VMS ? 64 \ 289 : 80) 290 291/* We always want the XFmode operations from libgcc2.c, except on VMS 292 where this yields references to unimplemented "insns". */ 293#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE (TARGET_ABI_OPEN_VMS ? 64 : 80) 294 295 296/* On HP-UX, we use the l suffix for TFmode in libgcc2.c. */ 297#define LIBGCC2_TF_CEXT l 298 299#define DEFAULT_SIGNED_CHAR 1 300 301/* A C expression for a string describing the name of the data type to use for 302 size values. The typedef name `size_t' is defined using the contents of the 303 string. */ 304/* ??? Needs to be defined for P64 code. */ 305/* #define SIZE_TYPE */ 306 307/* A C expression for a string describing the name of the data type to use for 308 the result of subtracting two pointers. The typedef name `ptrdiff_t' is 309 defined using the contents of the string. See `SIZE_TYPE' above for more 310 information. */ 311/* ??? Needs to be defined for P64 code. */ 312/* #define PTRDIFF_TYPE */ 313 314/* A C expression for a string describing the name of the data type to use for 315 wide characters. The typedef name `wchar_t' is defined using the contents 316 of the string. See `SIZE_TYPE' above for more information. */ 317/* #define WCHAR_TYPE */ 318 319/* A C expression for the size in bits of the data type for wide characters. 320 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */ 321/* #define WCHAR_TYPE_SIZE */ 322 323 324/* Register Basics */ 325 326/* Number of hardware registers known to the compiler. 327 We have 128 general registers, 128 floating point registers, 328 64 predicate registers, 8 branch registers, one frame pointer, 329 and several "application" registers. */ 330 331#define FIRST_PSEUDO_REGISTER 334 332 333/* Ranges for the various kinds of registers. */ 334#define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3) 335#define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127) 336#define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255) 337#define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159) 338#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319) 339#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327) 340#define GENERAL_REGNO_P(REGNO) \ 341 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM) 342 343#define GR_REG(REGNO) ((REGNO) + 0) 344#define FR_REG(REGNO) ((REGNO) + 128) 345#define PR_REG(REGNO) ((REGNO) + 256) 346#define BR_REG(REGNO) ((REGNO) + 320) 347#define OUT_REG(REGNO) ((REGNO) + 120) 348#define IN_REG(REGNO) ((REGNO) + 112) 349#define LOC_REG(REGNO) ((REGNO) + 32) 350 351#define AR_CCV_REGNUM 329 352#define AR_UNAT_REGNUM 330 353#define AR_PFS_REGNUM 331 354#define AR_LC_REGNUM 332 355#define AR_EC_REGNUM 333 356 357#define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7)) 358#define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79)) 359#define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7)) 360 361#define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \ 362 || (REGNO) == AR_UNAT_REGNUM) 363#define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \ 364 && (REGNO) < FIRST_PSEUDO_REGISTER) 365#define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \ 366 && (REGNO) < FIRST_PSEUDO_REGISTER) 367 368 369/* ??? Don't really need two sets of macros. I like this one better because 370 it is less typing. */ 371#define R_GR(REGNO) GR_REG (REGNO) 372#define R_FR(REGNO) FR_REG (REGNO) 373#define R_PR(REGNO) PR_REG (REGNO) 374#define R_BR(REGNO) BR_REG (REGNO) 375 376/* An initializer that says which registers are used for fixed purposes all 377 throughout the compiled code and are therefore not available for general 378 allocation. 379 380 r0: constant 0 381 r1: global pointer (gp) 382 r12: stack pointer (sp) 383 r13: thread pointer (tp) 384 f0: constant 0.0 385 f1: constant 1.0 386 p0: constant true 387 fp: eliminable frame pointer */ 388 389/* The last 16 stacked regs are reserved for the 8 input and 8 output 390 registers. */ 391 392#define FIXED_REGISTERS \ 393{ /* General registers. */ \ 394 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ 395 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 396 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 397 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 398 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 399 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 400 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 401 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 402 /* Floating-point registers. */ \ 403 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 404 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 405 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 406 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 407 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 409 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 410 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 411 /* Predicate registers. */ \ 412 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 413 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 414 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 415 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 416 /* Branch registers. */ \ 417 0, 0, 0, 0, 0, 0, 0, 0, \ 418 /*FP CCV UNAT PFS LC EC */ \ 419 1, 1, 1, 1, 0, 1 \ 420 } 421 422/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered 423 (in general) by function calls as well as for fixed registers. This 424 macro therefore identifies the registers that are not available for 425 general allocation of values that must live across function calls. */ 426 427#define CALL_USED_REGISTERS \ 428{ /* General registers. */ \ 429 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 430 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 431 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 432 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 433 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 434 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 436 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 437 /* Floating-point registers. */ \ 438 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 440 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 441 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 442 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 443 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 444 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 445 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 446 /* Predicate registers. */ \ 447 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 448 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 450 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 451 /* Branch registers. */ \ 452 1, 0, 0, 0, 0, 0, 1, 1, \ 453 /*FP CCV UNAT PFS LC EC */ \ 454 1, 1, 1, 1, 0, 1 \ 455} 456 457/* Like `CALL_USED_REGISTERS' but used to overcome a historical 458 problem which makes CALL_USED_REGISTERS *always* include 459 all the FIXED_REGISTERS. Until this problem has been 460 resolved this macro can be used to overcome this situation. 461 In particular, block_propagate() requires this list 462 be accurate, or we can remove registers which should be live. 463 This macro is used in regs_invalidated_by_call. */ 464 465#define CALL_REALLY_USED_REGISTERS \ 466{ /* General registers. */ \ 467 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, \ 468 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 471 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 474 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 475 /* Floating-point registers. */ \ 476 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 478 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 479 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 480 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 481 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 482 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 483 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 484 /* Predicate registers. */ \ 485 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 489 /* Branch registers. */ \ 490 1, 0, 0, 0, 0, 0, 1, 1, \ 491 /*FP CCV UNAT PFS LC EC */ \ 492 0, 1, 0, 1, 0, 0 \ 493} 494 495 496/* Define this macro if the target machine has register windows. This C 497 expression returns the register number as seen by the called function 498 corresponding to the register number OUT as seen by the calling function. 499 Return OUT if register number OUT is not an outbound register. */ 500 501#define INCOMING_REGNO(OUT) \ 502 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT)) 503 504/* Define this macro if the target machine has register windows. This C 505 expression returns the register number as seen by the calling function 506 corresponding to the register number IN as seen by the called function. 507 Return IN if register number IN is not an inbound register. */ 508 509#define OUTGOING_REGNO(IN) \ 510 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN)) 511 512/* Define this macro if the target machine has register windows. This 513 C expression returns true if the register is call-saved but is in the 514 register window. */ 515 516#define LOCAL_REGNO(REGNO) \ 517 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO)) 518 519/* We define CCImode in ia64-modes.def so we need a selector. */ 520 521#define SELECT_CC_MODE(OP,X,Y) CCmode 522 523/* Order of allocation of registers */ 524 525/* If defined, an initializer for a vector of integers, containing the numbers 526 of hard registers in the order in which GCC should prefer to use them 527 (from most preferred to least). 528 529 If this macro is not defined, registers are used lowest numbered first (all 530 else being equal). 531 532 One use of this macro is on machines where the highest numbered registers 533 must always be saved and the save-multiple-registers instruction supports 534 only sequences of consecutive registers. On such machines, define 535 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered 536 allocatable register first. */ 537 538/* ??? Should the GR return value registers come before or after the rest 539 of the caller-save GRs? */ 540 541#define REG_ALLOC_ORDER \ 542{ \ 543 /* Caller-saved general registers. */ \ 544 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \ 545 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \ 546 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \ 547 R_GR (30), R_GR (31), \ 548 /* Output registers. */ \ 549 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \ 550 R_GR (126), R_GR (127), \ 551 /* Caller-saved general registers, also used for return values. */ \ 552 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \ 553 /* addl caller-saved general registers. */ \ 554 R_GR (2), R_GR (3), \ 555 /* Caller-saved FP registers. */ \ 556 R_FR (6), R_FR (7), \ 557 /* Caller-saved FP registers, used for parameters and return values. */ \ 558 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \ 559 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \ 560 /* Rotating caller-saved FP registers. */ \ 561 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \ 562 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \ 563 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \ 564 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \ 565 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \ 566 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \ 567 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \ 568 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \ 569 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \ 570 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \ 571 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \ 572 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \ 573 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \ 574 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \ 575 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \ 576 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \ 577 R_FR (126), R_FR (127), \ 578 /* Caller-saved predicate registers. */ \ 579 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \ 580 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \ 581 /* Rotating caller-saved predicate registers. */ \ 582 R_PR (16), R_PR (17), \ 583 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \ 584 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \ 585 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \ 586 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \ 587 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \ 588 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \ 589 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \ 590 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \ 591 /* Caller-saved branch registers. */ \ 592 R_BR (6), R_BR (7), \ 593 \ 594 /* Stacked callee-saved general registers. */ \ 595 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \ 596 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \ 597 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \ 598 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \ 599 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \ 600 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \ 601 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \ 602 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \ 603 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \ 604 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \ 605 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \ 606 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \ 607 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \ 608 R_GR (108), \ 609 /* Input registers. */ \ 610 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \ 611 R_GR (118), R_GR (119), \ 612 /* Callee-saved general registers. */ \ 613 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \ 614 /* Callee-saved FP registers. */ \ 615 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \ 616 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \ 617 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \ 618 R_FR (30), R_FR (31), \ 619 /* Callee-saved predicate registers. */ \ 620 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \ 621 /* Callee-saved branch registers. */ \ 622 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \ 623 \ 624 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \ 625 R_GR (109), R_GR (110), R_GR (111), \ 626 \ 627 /* Special general registers. */ \ 628 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \ 629 /* Special FP registers. */ \ 630 R_FR (0), R_FR (1), \ 631 /* Special predicate registers. */ \ 632 R_PR (0), \ 633 /* Special branch registers. */ \ 634 R_BR (0), \ 635 /* Other fixed registers. */ \ 636 FRAME_POINTER_REGNUM, \ 637 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \ 638 AR_EC_REGNUM \ 639} 640 641/* How Values Fit in Registers */ 642 643/* A C expression for the number of consecutive hard registers, starting at 644 register number REGNO, required to hold a value of mode MODE. */ 645 646/* ??? We say that BImode PR values require two registers. This allows us to 647 easily store the normal and inverted values. We use CCImode to indicate 648 a single predicate register. */ 649 650#define HARD_REGNO_NREGS(REGNO, MODE) \ 651 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \ 652 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \ 653 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \ 654 : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \ 655 : FR_REGNO_P (REGNO) && (MODE) == RFmode ? 1 \ 656 : FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \ 657 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 658 659/* A C expression that is nonzero if it is permissible to store a value of mode 660 MODE in hard register number REGNO (or in several registers starting with 661 that one). */ 662 663#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 664 (FR_REGNO_P (REGNO) ? \ 665 GET_MODE_CLASS (MODE) != MODE_CC && \ 666 (MODE) != BImode && \ 667 (MODE) != TFmode \ 668 : PR_REGNO_P (REGNO) ? \ 669 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \ 670 : GR_REGNO_P (REGNO) ? \ 671 (MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \ 672 : AR_REGNO_P (REGNO) ? (MODE) == DImode \ 673 : BR_REGNO_P (REGNO) ? (MODE) == DImode \ 674 : 0) 675 676/* A C expression that is nonzero if it is desirable to choose register 677 allocation so as to avoid move instructions between a value of mode MODE1 678 and a value of mode MODE2. 679 680 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are 681 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be 682 zero. */ 683/* Don't tie integer and FP modes, as that causes us to get integer registers 684 allocated for FP instructions. XFmode only supported in FP registers so 685 we can't tie it with any other modes. */ 686#define MODES_TIEABLE_P(MODE1, MODE2) \ 687 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 688 && ((((MODE1) == XFmode) || ((MODE1) == XCmode) || ((MODE1) == RFmode)) \ 689 == (((MODE2) == XFmode) || ((MODE2) == XCmode) || ((MODE2) == RFmode))) \ 690 && (((MODE1) == BImode) == ((MODE2) == BImode))) 691 692/* Specify the modes required to caller save a given hard regno. 693 We need to ensure floating pt regs are not saved as DImode. */ 694 695#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 696 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode \ 697 : choose_hard_reg_mode ((REGNO), (NREGS), false)) 698 699/* Handling Leaf Functions */ 700 701/* A C initializer for a vector, indexed by hard register number, which 702 contains 1 for a register that is allowable in a candidate for leaf function 703 treatment. */ 704/* ??? This might be useful. */ 705/* #define LEAF_REGISTERS */ 706 707/* A C expression whose value is the register number to which REGNO should be 708 renumbered, when a function is treated as a leaf function. */ 709/* ??? This might be useful. */ 710/* #define LEAF_REG_REMAP(REGNO) */ 711 712 713/* Register Classes */ 714 715/* An enumeral type that must be defined with all the register class names as 716 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last 717 register class, followed by one more enumeral value, `LIM_REG_CLASSES', 718 which is not a register class but rather tells how many classes there 719 are. */ 720/* ??? When compiling without optimization, it is possible for the only use of 721 a pseudo to be a parameter load from the stack with a REG_EQUIV note. 722 Regclass handles this case specially and does not assign any costs to the 723 pseudo. The pseudo then ends up using the last class before ALL_REGS. 724 Thus we must not let either PR_REGS or BR_REGS be the last class. The 725 testcase for this is gcc.c-torture/execute/va-arg-7.c. */ 726enum reg_class 727{ 728 NO_REGS, 729 PR_REGS, 730 BR_REGS, 731 AR_M_REGS, 732 AR_I_REGS, 733 ADDL_REGS, 734 GR_REGS, 735 FP_REGS, 736 FR_REGS, 737 GR_AND_BR_REGS, 738 GR_AND_FR_REGS, 739 ALL_REGS, 740 LIM_REG_CLASSES 741}; 742 743#define GENERAL_REGS GR_REGS 744 745/* The number of distinct register classes. */ 746#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 747 748/* An initializer containing the names of the register classes as C string 749 constants. These names are used in writing some of the debugging dumps. */ 750#define REG_CLASS_NAMES \ 751{ "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \ 752 "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \ 753 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" } 754 755/* An initializer containing the contents of the register classes, as integers 756 which are bit masks. The Nth integer specifies the contents of class N. 757 The way the integer MASK is interpreted is that register R is in the class 758 if `MASK & (1 << R)' is 1. */ 759#define REG_CLASS_CONTENTS \ 760{ \ 761 /* NO_REGS. */ \ 762 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 763 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 764 0x00000000, 0x00000000, 0x0000 }, \ 765 /* PR_REGS. */ \ 766 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 767 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 768 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \ 769 /* BR_REGS. */ \ 770 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 771 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 772 0x00000000, 0x00000000, 0x00FF }, \ 773 /* AR_M_REGS. */ \ 774 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 775 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 776 0x00000000, 0x00000000, 0x0600 }, \ 777 /* AR_I_REGS. */ \ 778 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 779 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 780 0x00000000, 0x00000000, 0x3800 }, \ 781 /* ADDL_REGS. */ \ 782 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \ 783 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 784 0x00000000, 0x00000000, 0x0000 }, \ 785 /* GR_REGS. */ \ 786 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 787 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 788 0x00000000, 0x00000000, 0x0100 }, \ 789 /* FP_REGS. */ \ 790 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 791 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, \ 792 0x00000000, 0x00000000, 0x0000 }, \ 793 /* FR_REGS. */ \ 794 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 795 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 796 0x00000000, 0x00000000, 0x0000 }, \ 797 /* GR_AND_BR_REGS. */ \ 798 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 799 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 800 0x00000000, 0x00000000, 0x01FF }, \ 801 /* GR_AND_FR_REGS. */ \ 802 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 803 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 804 0x00000000, 0x00000000, 0x0100 }, \ 805 /* ALL_REGS. */ \ 806 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 807 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 808 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \ 809} 810 811/* The following macro defines cover classes for Integrated Register 812 Allocator. Cover classes is a set of non-intersected register 813 classes covering all hard registers used for register allocation 814 purpose. Any move between two registers of a cover class should be 815 cheaper than load or store of the registers. The macro value is 816 array of register classes with LIM_REG_CLASSES used as the end 817 marker. */ 818 819#define IRA_COVER_CLASSES \ 820{ \ 821 PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS, GR_REGS, FR_REGS, LIM_REG_CLASSES \ 822} 823 824/* A C expression whose value is a register class containing hard register 825 REGNO. In general there is more than one such class; choose a class which 826 is "minimal", meaning that no smaller class also contains the register. */ 827/* The NO_REGS case is primarily for the benefit of rws_access_reg, which 828 may call here with private (invalid) register numbers, such as 829 REG_VOLATILE. */ 830#define REGNO_REG_CLASS(REGNO) \ 831(ADDL_REGNO_P (REGNO) ? ADDL_REGS \ 832 : GENERAL_REGNO_P (REGNO) ? GR_REGS \ 833 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \ 834 && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \ 835 : PR_REGNO_P (REGNO) ? PR_REGS \ 836 : BR_REGNO_P (REGNO) ? BR_REGS \ 837 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \ 838 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \ 839 : NO_REGS) 840 841/* A macro whose definition is the name of the class to which a valid base 842 register must belong. A base register is one used in an address which is 843 the register value plus a displacement. */ 844#define BASE_REG_CLASS GENERAL_REGS 845 846/* A macro whose definition is the name of the class to which a valid index 847 register must belong. An index register is one used in an address where its 848 value is either multiplied by a scale factor or added to another register 849 (as well as added to a displacement). This is needed for POST_MODIFY. */ 850#define INDEX_REG_CLASS GENERAL_REGS 851 852/* A C expression which is nonzero if register number NUM is suitable for use 853 as a base register in operand addresses. It may be either a suitable hard 854 register or a pseudo register that has been allocated such a hard reg. */ 855#define REGNO_OK_FOR_BASE_P(REGNO) \ 856 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO])) 857 858/* A C expression which is nonzero if register number NUM is suitable for use 859 as an index register in operand addresses. It may be either a suitable hard 860 register or a pseudo register that has been allocated such a hard reg. 861 This is needed for POST_MODIFY. */ 862#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) 863 864/* A C expression that places additional restrictions on the register class to 865 use when it is necessary to copy value X into a register in class CLASS. 866 The value is a register class; perhaps CLASS, or perhaps another, smaller 867 class. */ 868 869#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 870 ia64_preferred_reload_class (X, CLASS) 871 872/* You should define this macro to indicate to the reload phase that it may 873 need to allocate at least one register for a reload in addition to the 874 register to contain the data. Specifically, if copying X to a register 875 CLASS in MODE requires an intermediate register, you should define this 876 to return the largest register class all of whose registers can be used 877 as intermediate registers or scratch registers. */ 878 879#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 880 ia64_secondary_reload_class (CLASS, MODE, X) 881 882/* Certain machines have the property that some registers cannot be copied to 883 some other registers without using memory. Define this macro on those 884 machines to be a C expression that is nonzero if objects of mode M in 885 registers of CLASS1 can only be copied to registers of class CLASS2 by 886 storing a register of CLASS1 into memory and loading that memory location 887 into a register of CLASS2. */ 888 889#if 0 890/* ??? May need this, but since we've disallowed XFmode in GR_REGS, 891 I'm not quite sure how it could be invoked. The normal problems 892 with unions should be solved with the addressof fiddling done by 893 movxf and friends. */ 894#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 895 (((MODE) == XFmode || (MODE) == XCmode) \ 896 && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \ 897 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS))) 898#endif 899 900/* A C expression for the maximum number of consecutive registers of 901 class CLASS needed to hold a value of mode MODE. 902 This is closely related to the macro `HARD_REGNO_NREGS'. */ 903 904#define CLASS_MAX_NREGS(CLASS, MODE) \ 905 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \ 906 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \ 907 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \ 908 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \ 909 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 910 911/* In BR regs, we can't change the DImode at all. 912 In FP regs, we can't change FP values to integer values and vice versa, 913 but we can change e.g. DImode to SImode, and V2SFmode into DImode. */ 914 915#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 916 (reg_classes_intersect_p (CLASS, BR_REGS) \ 917 ? (FROM) != (TO) \ 918 : (SCALAR_FLOAT_MODE_P (FROM) != SCALAR_FLOAT_MODE_P (TO) \ 919 ? reg_classes_intersect_p (CLASS, FR_REGS) \ 920 : 0)) 921 922/* Basic Stack Layout */ 923 924/* Define this macro if pushing a word onto the stack moves the stack pointer 925 to a smaller address. */ 926#define STACK_GROWS_DOWNWARD 1 927 928/* Define this macro to nonzero if the addresses of local variable slots 929 are at negative offsets from the frame pointer. */ 930#define FRAME_GROWS_DOWNWARD 0 931 932/* Offset from the frame pointer to the first local variable slot to 933 be allocated. */ 934#define STARTING_FRAME_OFFSET 0 935 936/* Offset from the stack pointer register to the first location at which 937 outgoing arguments are placed. If not specified, the default value of zero 938 is used. This is the proper value for most machines. */ 939/* IA64 has a 16 byte scratch area that is at the bottom of the stack. */ 940#define STACK_POINTER_OFFSET 16 941 942/* Offset from the argument pointer register to the first argument's address. 943 On some machines it may depend on the data type of the function. */ 944#define FIRST_PARM_OFFSET(FUNDECL) 0 945 946/* A C expression whose value is RTL representing the value of the return 947 address for the frame COUNT steps up from the current frame, after the 948 prologue. */ 949 950/* ??? Frames other than zero would likely require interpreting the frame 951 unwind info, so we don't try to support them. We would also need to define 952 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */ 953 954#define RETURN_ADDR_RTX(COUNT, FRAME) \ 955 ia64_return_addr_rtx (COUNT, FRAME) 956 957/* A C expression whose value is RTL representing the location of the incoming 958 return address at the beginning of any function, before the prologue. This 959 RTL is either a `REG', indicating that the return value is saved in `REG', 960 or a `MEM' representing a location in the stack. This enables DWARF2 961 unwind info for C++ EH. */ 962#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0)) 963 964/* A C expression whose value is an integer giving the offset, in bytes, from 965 the value of the stack pointer register to the top of the stack frame at the 966 beginning of any function, before the prologue. The top of the frame is 967 defined to be the value of the stack pointer in the previous frame, just 968 before the call instruction. */ 969/* The CFA is past the red zone, not at the entry-point stack 970 pointer. */ 971#define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET 972 973/* We shorten debug info by using CFA-16 as DW_AT_frame_base. */ 974#define CFA_FRAME_BASE_OFFSET(FUNDECL) (-INCOMING_FRAME_SP_OFFSET) 975 976 977/* Register That Address the Stack Frame. */ 978 979/* The register number of the stack pointer register, which must also be a 980 fixed register according to `FIXED_REGISTERS'. On most machines, the 981 hardware determines which register this is. */ 982 983#define STACK_POINTER_REGNUM 12 984 985/* The register number of the frame pointer register, which is used to access 986 automatic variables in the stack frame. On some machines, the hardware 987 determines which register this is. On other machines, you can choose any 988 register you wish for this purpose. */ 989 990#define FRAME_POINTER_REGNUM 328 991 992/* Base register for access to local variables of the function. */ 993#define HARD_FRAME_POINTER_REGNUM LOC_REG (79) 994 995/* The register number of the arg pointer register, which is used to access the 996 function's argument list. */ 997/* r0 won't otherwise be used, so put the always eliminated argument pointer 998 in it. */ 999#define ARG_POINTER_REGNUM R_GR(0) 1000 1001/* Due to the way varargs and argument spilling happens, the argument 1002 pointer is not 16-byte aligned like the stack pointer. */ 1003#define INIT_EXPANDERS \ 1004 do { \ 1005 ia64_init_expanders (); \ 1006 if (crtl->emit.regno_pointer_align) \ 1007 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \ 1008 } while (0) 1009 1010/* Register numbers used for passing a function's static chain pointer. */ 1011/* ??? The ABI sez the static chain should be passed as a normal parameter. */ 1012#define STATIC_CHAIN_REGNUM 15 1013 1014/* Eliminating the Frame Pointer and the Arg Pointer */ 1015 1016/* Show we can debug even without a frame pointer. */ 1017#define CAN_DEBUG_WITHOUT_FP 1018 1019/* If defined, this macro specifies a table of register pairs used to eliminate 1020 unneeded registers that point into the stack frame. */ 1021 1022#define ELIMINABLE_REGS \ 1023{ \ 1024 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1025 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1026 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1027 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1028} 1029 1030/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It 1031 specifies the initial difference between the specified pair of 1032 registers. This macro must be defined if `ELIMINABLE_REGS' is 1033 defined. */ 1034#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1035 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO))) 1036 1037/* Passing Function Arguments on the Stack */ 1038 1039/* If defined, the maximum amount of space required for outgoing arguments will 1040 be computed and placed into the variable 1041 `crtl->outgoing_args_size'. */ 1042 1043#define ACCUMULATE_OUTGOING_ARGS 1 1044 1045/* A C expression that should indicate the number of bytes of its own arguments 1046 that a function pops on returning, or 0 if the function pops no arguments 1047 and the caller must therefore pop them all after the function returns. */ 1048 1049#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 1050 1051 1052/* Function Arguments in Registers */ 1053 1054#define MAX_ARGUMENT_SLOTS 8 1055#define MAX_INT_RETURN_SLOTS 4 1056#define GR_ARG_FIRST IN_REG (0) 1057#define GR_RET_FIRST GR_REG (8) 1058#define GR_RET_LAST GR_REG (11) 1059#define FR_ARG_FIRST FR_REG (8) 1060#define FR_RET_FIRST FR_REG (8) 1061#define FR_RET_LAST FR_REG (15) 1062#define AR_ARG_FIRST OUT_REG (0) 1063 1064/* A C expression that controls whether a function argument is passed in a 1065 register, and which register. */ 1066 1067#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1068 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0) 1069 1070/* Define this macro if the target machine has "register windows", so that the 1071 register in which a function sees an arguments is not necessarily the same 1072 as the one in which the caller passed the argument. */ 1073 1074#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1075 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1) 1076 1077/* A C type for declaring a variable that is used as the first argument of 1078 `FUNCTION_ARG' and other related values. For some target machines, the type 1079 `int' suffices and can hold the number of bytes of argument so far. */ 1080 1081enum ivms_arg_type {I64, FF, FD, FG, FS, FT}; 1082/* VMS floating point formats VAX F, VAX D, VAX G, IEEE S, IEEE T. */ 1083 1084typedef struct ia64_args 1085{ 1086 int words; /* # words of arguments so far */ 1087 int int_regs; /* # GR registers used so far */ 1088 int fp_regs; /* # FR registers used so far */ 1089 int prototype; /* whether function prototyped */ 1090 enum ivms_arg_type atypes[8]; /* which VMS float type or if not float */ 1091} CUMULATIVE_ARGS; 1092 1093/* A C statement (sans semicolon) for initializing the variable CUM for the 1094 state at the beginning of the argument list. */ 1095 1096#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1097do { \ 1098 (CUM).words = 0; \ 1099 (CUM).int_regs = 0; \ 1100 (CUM).fp_regs = 0; \ 1101 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \ 1102 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \ 1103 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \ 1104 (CUM).atypes[6] = (CUM).atypes[7] = I64; \ 1105} while (0) 1106 1107/* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the 1108 arguments for the function being compiled. If this macro is undefined, 1109 `INIT_CUMULATIVE_ARGS' is used instead. */ 1110 1111/* We set prototype to true so that we never try to return a PARALLEL from 1112 function_arg. */ 1113#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1114do { \ 1115 (CUM).words = 0; \ 1116 (CUM).int_regs = 0; \ 1117 (CUM).fp_regs = 0; \ 1118 (CUM).prototype = 1; \ 1119 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \ 1120 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \ 1121 (CUM).atypes[6] = (CUM).atypes[7] = I64; \ 1122} while (0) 1123 1124/* A C statement (sans semicolon) to update the summarizer variable CUM to 1125 advance past an argument in the argument list. The values MODE, TYPE and 1126 NAMED describe that argument. Once this is done, the variable CUM is 1127 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */ 1128 1129#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1130 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED) 1131 1132/* If defined, a C expression that gives the alignment boundary, in bits, of an 1133 argument with the specified mode and type. */ 1134 1135/* Return the alignment boundary in bits for an argument with a specified 1136 mode and type. */ 1137 1138#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1139 ia64_function_arg_boundary (MODE, TYPE) 1140 1141/* A C expression that is nonzero if REGNO is the number of a hard register in 1142 which function arguments are sometimes passed. This does *not* include 1143 implicit arguments such as the static chain and the structure-value address. 1144 On many machines, no registers can be used for this purpose since all 1145 function arguments are pushed on the stack. */ 1146#define FUNCTION_ARG_REGNO_P(REGNO) \ 1147(((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \ 1148 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS))) 1149 1150/* How Scalar Function Values are Returned */ 1151 1152/* A C expression to create an RTX representing the place where a function 1153 returns a value of data type VALTYPE. */ 1154 1155#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1156 ia64_function_value (VALTYPE, FUNC) 1157 1158/* A C expression to create an RTX representing the place where a library 1159 function returns a value of mode MODE. */ 1160 1161#define LIBCALL_VALUE(MODE) \ 1162 gen_rtx_REG (MODE, \ 1163 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1164 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \ 1165 (MODE) != TFmode) \ 1166 ? FR_RET_FIRST : GR_RET_FIRST)) 1167 1168/* A C expression that is nonzero if REGNO is the number of a hard register in 1169 which the values of called function may come back. */ 1170 1171#define FUNCTION_VALUE_REGNO_P(REGNO) \ 1172 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \ 1173 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST)) 1174 1175 1176/* How Large Values are Returned */ 1177 1178#define DEFAULT_PCC_STRUCT_RETURN 0 1179 1180 1181/* Caller-Saves Register Allocation */ 1182 1183/* A C expression to determine whether it is worthwhile to consider placing a 1184 pseudo-register in a call-clobbered hard register and saving and restoring 1185 it around each function call. The expression should be 1 when this is worth 1186 doing, and 0 otherwise. 1187 1188 If you don't define this macro, a default is used which is good on most 1189 machines: `4 * CALLS < REFS'. */ 1190/* ??? Investigate. */ 1191/* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */ 1192 1193 1194/* Function Entry and Exit */ 1195 1196/* Define this macro as a C expression that is nonzero if the return 1197 instruction or the function epilogue ignores the value of the stack pointer; 1198 in other words, if it is safe to delete an instruction to adjust the stack 1199 pointer before a return from the function. */ 1200 1201#define EXIT_IGNORE_STACK 1 1202 1203/* Define this macro as a C expression that is nonzero for registers 1204 used by the epilogue or the `return' pattern. */ 1205 1206#define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO) 1207 1208/* Nonzero for registers used by the exception handling mechanism. */ 1209 1210#define EH_USES(REGNO) ia64_eh_uses (REGNO) 1211 1212/* Output part N of a function descriptor for DECL. For ia64, both 1213 words are emitted with a single relocation, so ignore N > 0. */ 1214#define ASM_OUTPUT_FDESC(FILE, DECL, PART) \ 1215do { \ 1216 if ((PART) == 0) \ 1217 { \ 1218 if (TARGET_ILP32) \ 1219 fputs ("\tdata8.ua @iplt(", FILE); \ 1220 else \ 1221 fputs ("\tdata16.ua @iplt(", FILE); \ 1222 mark_decl_referenced (DECL); \ 1223 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \ 1224 fputs (")\n", FILE); \ 1225 if (TARGET_ILP32) \ 1226 fputs ("\tdata8.ua 0\n", FILE); \ 1227 } \ 1228} while (0) 1229 1230/* Generating Code for Profiling. */ 1231 1232/* A C statement or compound statement to output to FILE some assembler code to 1233 call the profiling subroutine `mcount'. */ 1234 1235#undef FUNCTION_PROFILER 1236#define FUNCTION_PROFILER(FILE, LABELNO) \ 1237 ia64_output_function_profiler(FILE, LABELNO) 1238 1239/* Neither hpux nor linux use profile counters. */ 1240#define NO_PROFILE_COUNTERS 1 1241 1242/* Trampolines for Nested Functions. */ 1243 1244/* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of 1245 the function containing a non-local goto target. */ 1246 1247#define STACK_SAVEAREA_MODE(LEVEL) \ 1248 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode) 1249 1250/* A C expression for the size in bytes of the trampoline, as an integer. */ 1251 1252#define TRAMPOLINE_SIZE 32 1253 1254/* Alignment required for trampolines, in bits. */ 1255 1256#define TRAMPOLINE_ALIGNMENT 64 1257 1258/* Addressing Modes */ 1259 1260/* Define this macro if the machine supports post-increment addressing. */ 1261 1262#define HAVE_POST_INCREMENT 1 1263#define HAVE_POST_DECREMENT 1 1264#define HAVE_POST_MODIFY_DISP 1 1265#define HAVE_POST_MODIFY_REG 1 1266 1267/* A C expression that is 1 if the RTX X is a constant which is a valid 1268 address. */ 1269 1270#define CONSTANT_ADDRESS_P(X) 0 1271 1272/* The max number of registers that can appear in a valid memory address. */ 1273 1274#define MAX_REGS_PER_ADDRESS 2 1275 1276/* A C compound statement with a conditional `goto LABEL;' executed if X (an 1277 RTX) is a legitimate memory address on the target machine for a memory 1278 operand of mode MODE. */ 1279 1280#define LEGITIMATE_ADDRESS_REG(X) \ 1281 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1282 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \ 1283 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) 1284 1285#define LEGITIMATE_ADDRESS_DISP(R, X) \ 1286 (GET_CODE (X) == PLUS \ 1287 && rtx_equal_p (R, XEXP (X, 0)) \ 1288 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \ 1289 || (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1290 && INTVAL (XEXP (X, 1)) >= -256 \ 1291 && INTVAL (XEXP (X, 1)) < 256))) 1292 1293#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 1294do { \ 1295 if (LEGITIMATE_ADDRESS_REG (X)) \ 1296 goto LABEL; \ 1297 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ 1298 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \ 1299 && XEXP (X, 0) != arg_pointer_rtx) \ 1300 goto LABEL; \ 1301 else if (GET_CODE (X) == POST_MODIFY \ 1302 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \ 1303 && XEXP (X, 0) != arg_pointer_rtx \ 1304 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \ 1305 goto LABEL; \ 1306} while (0) 1307 1308/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for 1309 use as a base register. */ 1310 1311#ifdef REG_OK_STRICT 1312#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1313#else 1314#define REG_OK_FOR_BASE_P(X) \ 1315 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1316#endif 1317 1318/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for 1319 use as an index register. This is needed for POST_MODIFY. */ 1320 1321#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) 1322 1323/* A C expression that is nonzero if X is a legitimate constant for an 1324 immediate operand on the target machine. */ 1325 1326#define LEGITIMATE_CONSTANT_P(X) ia64_legitimate_constant_p (X) 1327 1328/* Condition Code Status */ 1329 1330/* One some machines not all possible comparisons are defined, but you can 1331 convert an invalid comparison into a valid one. */ 1332/* ??? Investigate. See the alpha definition. */ 1333/* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */ 1334 1335 1336/* Describing Relative Costs of Operations */ 1337 1338/* A C expression for the cost of moving data from a register in class FROM to 1339 one in class TO, using MODE. */ 1340 1341#define REGISTER_MOVE_COST ia64_register_move_cost 1342 1343/* A C expression for the cost of moving data of mode M between a 1344 register and memory. */ 1345#define MEMORY_MOVE_COST(MODE,CLASS,IN) \ 1346 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS || (CLASS) == FP_REGS \ 1347 || (CLASS) == GR_AND_FR_REGS ? 4 : 10) 1348 1349/* A C expression for the cost of a branch instruction. A value of 1 is the 1350 default; other values are interpreted relative to that. Used by the 1351 if-conversion code as max instruction count. */ 1352/* ??? This requires investigation. The primary effect might be how 1353 many additional insn groups we run into, vs how good the dynamic 1354 branch predictor is. */ 1355 1356#define BRANCH_COST(speed_p, predictable_p) 6 1357 1358/* Define this macro as a C expression which is nonzero if accessing less than 1359 a word of memory (i.e. a `char' or a `short') is no faster than accessing a 1360 word of memory. */ 1361 1362#define SLOW_BYTE_ACCESS 1 1363 1364/* Define this macro if it is as good or better to call a constant function 1365 address than to call an address kept in a register. 1366 1367 Indirect function calls are more expensive that direct function calls, so 1368 don't cse function addresses. */ 1369 1370#define NO_FUNCTION_CSE 1371 1372 1373/* Dividing the output into sections. */ 1374 1375/* A C expression whose value is a string containing the assembler operation 1376 that should precede instructions and read-only data. */ 1377 1378#define TEXT_SECTION_ASM_OP "\t.text" 1379 1380/* A C expression whose value is a string containing the assembler operation to 1381 identify the following data as writable initialized data. */ 1382 1383#define DATA_SECTION_ASM_OP "\t.data" 1384 1385/* If defined, a C expression whose value is a string containing the assembler 1386 operation to identify the following data as uninitialized global data. */ 1387 1388#define BSS_SECTION_ASM_OP "\t.bss" 1389 1390#define IA64_DEFAULT_GVALUE 8 1391 1392/* Position Independent Code. */ 1393 1394/* The register number of the register used to address a table of static data 1395 addresses in memory. */ 1396 1397/* ??? Should modify ia64.md to use pic_offset_table_rtx instead of 1398 gen_rtx_REG (DImode, 1). */ 1399 1400/* ??? Should we set flag_pic? Probably need to define 1401 LEGITIMIZE_PIC_OPERAND_P to make that work. */ 1402 1403#define PIC_OFFSET_TABLE_REGNUM GR_REG (1) 1404 1405/* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is 1406 clobbered by calls. */ 1407 1408#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1409 1410 1411/* The Overall Framework of an Assembler File. */ 1412 1413/* A C string constant describing how to begin a comment in the target 1414 assembler language. The compiler assumes that the comment will end at the 1415 end of the line. */ 1416 1417#define ASM_COMMENT_START "//" 1418 1419/* A C string constant for text to be output before each `asm' statement or 1420 group of consecutive ones. */ 1421 1422#define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n") 1423 1424/* A C string constant for text to be output after each `asm' statement or 1425 group of consecutive ones. */ 1426 1427#define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n") 1428 1429/* Output of Uninitialized Variables. */ 1430 1431/* This is all handled by svr4.h. */ 1432 1433 1434/* Output and Generation of Labels. */ 1435 1436/* A C statement (sans semicolon) to output to the stdio stream STREAM the 1437 assembler definition of a label named NAME. */ 1438 1439/* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of 1440 why ia64_asm_output_label exists. */ 1441 1442extern int ia64_asm_output_label; 1443#define ASM_OUTPUT_LABEL(STREAM, NAME) \ 1444do { \ 1445 ia64_asm_output_label = 1; \ 1446 assemble_name (STREAM, NAME); \ 1447 fputs (":\n", STREAM); \ 1448 ia64_asm_output_label = 0; \ 1449} while (0) 1450 1451/* Globalizing directive for a label. */ 1452#define GLOBAL_ASM_OP "\t.global " 1453 1454/* A C statement (sans semicolon) to output to the stdio stream STREAM any text 1455 necessary for declaring the name of an external symbol named NAME which is 1456 referenced in this compilation but not defined. */ 1457 1458#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ 1459 ia64_asm_output_external (FILE, DECL, NAME) 1460 1461/* A C statement to store into the string STRING a label whose name is made 1462 from the string PREFIX and the number NUM. */ 1463 1464#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ 1465do { \ 1466 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \ 1467} while (0) 1468 1469/* ??? Not sure if using a ? in the name for Intel as is safe. */ 1470 1471#define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu") 1472 1473/* A C statement to output to the stdio stream STREAM assembler code which 1474 defines (equates) the symbol NAME to have the value VALUE. */ 1475 1476#define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ 1477do { \ 1478 assemble_name (STREAM, NAME); \ 1479 fputs (" = ", STREAM); \ 1480 if (ISDIGIT (*VALUE)) \ 1481 ia64_asm_output_label = 1; \ 1482 assemble_name (STREAM, VALUE); \ 1483 fputc ('\n', STREAM); \ 1484 ia64_asm_output_label = 0; \ 1485} while (0) 1486 1487 1488/* Macros Controlling Initialization Routines. */ 1489 1490/* This is handled by svr4.h and sysv4.h. */ 1491 1492 1493/* Output of Assembler Instructions. */ 1494 1495/* A C initializer containing the assembler's names for the machine registers, 1496 each one as a C string constant. */ 1497 1498#define REGISTER_NAMES \ 1499{ \ 1500 /* General registers. */ \ 1501 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ 1502 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ 1503 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ 1504 "r30", "r31", \ 1505 /* Local registers. */ \ 1506 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \ 1507 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \ 1508 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \ 1509 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \ 1510 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \ 1511 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \ 1512 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \ 1513 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \ 1514 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \ 1515 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \ 1516 /* Input registers. */ \ 1517 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \ 1518 /* Output registers. */ \ 1519 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \ 1520 /* Floating-point registers. */ \ 1521 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \ 1522 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \ 1523 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \ 1524 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \ 1525 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \ 1526 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \ 1527 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \ 1528 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \ 1529 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \ 1530 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \ 1531 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\ 1532 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\ 1533 "f120","f121","f122","f123","f124","f125","f126","f127", \ 1534 /* Predicate registers. */ \ 1535 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \ 1536 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \ 1537 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \ 1538 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \ 1539 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \ 1540 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \ 1541 "p60", "p61", "p62", "p63", \ 1542 /* Branch registers. */ \ 1543 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \ 1544 /* Frame pointer. Application registers. */ \ 1545 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \ 1546} 1547 1548/* If defined, a C initializer for an array of structures containing a name and 1549 a register number. This macro defines additional names for hard registers, 1550 thus allowing the `asm' option in declarations to refer to registers using 1551 alternate names. */ 1552 1553#define ADDITIONAL_REGISTER_NAMES \ 1554{ \ 1555 { "gp", R_GR (1) }, \ 1556 { "sp", R_GR (12) }, \ 1557 { "in0", IN_REG (0) }, \ 1558 { "in1", IN_REG (1) }, \ 1559 { "in2", IN_REG (2) }, \ 1560 { "in3", IN_REG (3) }, \ 1561 { "in4", IN_REG (4) }, \ 1562 { "in5", IN_REG (5) }, \ 1563 { "in6", IN_REG (6) }, \ 1564 { "in7", IN_REG (7) }, \ 1565 { "out0", OUT_REG (0) }, \ 1566 { "out1", OUT_REG (1) }, \ 1567 { "out2", OUT_REG (2) }, \ 1568 { "out3", OUT_REG (3) }, \ 1569 { "out4", OUT_REG (4) }, \ 1570 { "out5", OUT_REG (5) }, \ 1571 { "out6", OUT_REG (6) }, \ 1572 { "out7", OUT_REG (7) }, \ 1573 { "loc0", LOC_REG (0) }, \ 1574 { "loc1", LOC_REG (1) }, \ 1575 { "loc2", LOC_REG (2) }, \ 1576 { "loc3", LOC_REG (3) }, \ 1577 { "loc4", LOC_REG (4) }, \ 1578 { "loc5", LOC_REG (5) }, \ 1579 { "loc6", LOC_REG (6) }, \ 1580 { "loc7", LOC_REG (7) }, \ 1581 { "loc8", LOC_REG (8) }, \ 1582 { "loc9", LOC_REG (9) }, \ 1583 { "loc10", LOC_REG (10) }, \ 1584 { "loc11", LOC_REG (11) }, \ 1585 { "loc12", LOC_REG (12) }, \ 1586 { "loc13", LOC_REG (13) }, \ 1587 { "loc14", LOC_REG (14) }, \ 1588 { "loc15", LOC_REG (15) }, \ 1589 { "loc16", LOC_REG (16) }, \ 1590 { "loc17", LOC_REG (17) }, \ 1591 { "loc18", LOC_REG (18) }, \ 1592 { "loc19", LOC_REG (19) }, \ 1593 { "loc20", LOC_REG (20) }, \ 1594 { "loc21", LOC_REG (21) }, \ 1595 { "loc22", LOC_REG (22) }, \ 1596 { "loc23", LOC_REG (23) }, \ 1597 { "loc24", LOC_REG (24) }, \ 1598 { "loc25", LOC_REG (25) }, \ 1599 { "loc26", LOC_REG (26) }, \ 1600 { "loc27", LOC_REG (27) }, \ 1601 { "loc28", LOC_REG (28) }, \ 1602 { "loc29", LOC_REG (29) }, \ 1603 { "loc30", LOC_REG (30) }, \ 1604 { "loc31", LOC_REG (31) }, \ 1605 { "loc32", LOC_REG (32) }, \ 1606 { "loc33", LOC_REG (33) }, \ 1607 { "loc34", LOC_REG (34) }, \ 1608 { "loc35", LOC_REG (35) }, \ 1609 { "loc36", LOC_REG (36) }, \ 1610 { "loc37", LOC_REG (37) }, \ 1611 { "loc38", LOC_REG (38) }, \ 1612 { "loc39", LOC_REG (39) }, \ 1613 { "loc40", LOC_REG (40) }, \ 1614 { "loc41", LOC_REG (41) }, \ 1615 { "loc42", LOC_REG (42) }, \ 1616 { "loc43", LOC_REG (43) }, \ 1617 { "loc44", LOC_REG (44) }, \ 1618 { "loc45", LOC_REG (45) }, \ 1619 { "loc46", LOC_REG (46) }, \ 1620 { "loc47", LOC_REG (47) }, \ 1621 { "loc48", LOC_REG (48) }, \ 1622 { "loc49", LOC_REG (49) }, \ 1623 { "loc50", LOC_REG (50) }, \ 1624 { "loc51", LOC_REG (51) }, \ 1625 { "loc52", LOC_REG (52) }, \ 1626 { "loc53", LOC_REG (53) }, \ 1627 { "loc54", LOC_REG (54) }, \ 1628 { "loc55", LOC_REG (55) }, \ 1629 { "loc56", LOC_REG (56) }, \ 1630 { "loc57", LOC_REG (57) }, \ 1631 { "loc58", LOC_REG (58) }, \ 1632 { "loc59", LOC_REG (59) }, \ 1633 { "loc60", LOC_REG (60) }, \ 1634 { "loc61", LOC_REG (61) }, \ 1635 { "loc62", LOC_REG (62) }, \ 1636 { "loc63", LOC_REG (63) }, \ 1637 { "loc64", LOC_REG (64) }, \ 1638 { "loc65", LOC_REG (65) }, \ 1639 { "loc66", LOC_REG (66) }, \ 1640 { "loc67", LOC_REG (67) }, \ 1641 { "loc68", LOC_REG (68) }, \ 1642 { "loc69", LOC_REG (69) }, \ 1643 { "loc70", LOC_REG (70) }, \ 1644 { "loc71", LOC_REG (71) }, \ 1645 { "loc72", LOC_REG (72) }, \ 1646 { "loc73", LOC_REG (73) }, \ 1647 { "loc74", LOC_REG (74) }, \ 1648 { "loc75", LOC_REG (75) }, \ 1649 { "loc76", LOC_REG (76) }, \ 1650 { "loc77", LOC_REG (77) }, \ 1651 { "loc78", LOC_REG (78) }, \ 1652 { "loc79", LOC_REG (79) }, \ 1653} 1654 1655/* A C compound statement to output to stdio stream STREAM the assembler syntax 1656 for an instruction operand X. X is an RTL expression. */ 1657 1658#define PRINT_OPERAND(STREAM, X, CODE) \ 1659 ia64_print_operand (STREAM, X, CODE) 1660 1661/* A C expression which evaluates to true if CODE is a valid punctuation 1662 character for use in the `PRINT_OPERAND' macro. */ 1663 1664/* ??? Keep this around for now, as we might need it later. */ 1665 1666#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1667 ((CODE) == '+' || (CODE) == ',') 1668 1669/* A C compound statement to output to stdio stream STREAM the assembler syntax 1670 for an instruction operand that is a memory reference whose address is X. X 1671 is an RTL expression. */ 1672 1673#define PRINT_OPERAND_ADDRESS(STREAM, X) \ 1674 ia64_print_operand_address (STREAM, X) 1675 1676/* If defined, C string expressions to be used for the `%R', `%L', `%U', and 1677 `%I' options of `asm_fprintf' (see `final.c'). */ 1678 1679#define REGISTER_PREFIX "" 1680#define LOCAL_LABEL_PREFIX "." 1681#define USER_LABEL_PREFIX "" 1682#define IMMEDIATE_PREFIX "" 1683 1684 1685/* Output of dispatch tables. */ 1686 1687/* This macro should be provided on machines where the addresses in a dispatch 1688 table are relative to the table's own address. */ 1689 1690/* ??? Depends on the pointer size. */ 1691 1692#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 1693 do { \ 1694 if (TARGET_ILP32) \ 1695 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \ 1696 else \ 1697 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \ 1698 } while (0) 1699 1700/* Jump tables only need 8 byte alignment. */ 1701 1702#define ADDR_VEC_ALIGN(ADDR_VEC) 3 1703 1704 1705/* Assembler Commands for Exception Regions. */ 1706 1707/* Select a format to encode pointers in exception handling data. CODE 1708 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1709 true if the symbol may be affected by dynamic relocations. */ 1710#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1711 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \ 1712 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \ 1713 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8)) 1714 1715/* Handle special EH pointer encodings. Absolute, pc-relative, and 1716 indirect are handled automatically. */ 1717#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ 1718 do { \ 1719 const char *reltag = NULL; \ 1720 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \ 1721 reltag = "@segrel("; \ 1722 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \ 1723 reltag = "@gprel("; \ 1724 if (reltag) \ 1725 { \ 1726 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1727 fputs (reltag, FILE); \ 1728 assemble_name (FILE, XSTR (ADDR, 0)); \ 1729 fputc (')', FILE); \ 1730 goto DONE; \ 1731 } \ 1732 } while (0) 1733 1734 1735/* Assembler Commands for Alignment. */ 1736 1737/* ??? Investigate. */ 1738 1739/* The alignment (log base 2) to put in front of LABEL, which follows 1740 a BARRIER. */ 1741 1742/* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */ 1743 1744/* The desired alignment for the location counter at the beginning 1745 of a loop. */ 1746 1747/* #define LOOP_ALIGN(LABEL) */ 1748 1749/* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text 1750 section because it fails put zeros in the bytes that are skipped. */ 1751 1752#define ASM_NO_SKIP_IN_TEXT 1 1753 1754/* A C statement to output to the stdio stream STREAM an assembler command to 1755 advance the location counter to a multiple of 2 to the POWER bytes. */ 1756 1757#define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 1758 fprintf (STREAM, "\t.align %d\n", 1<<(POWER)) 1759 1760 1761/* Macros Affecting all Debug Formats. */ 1762 1763/* This is handled in svr4.h and sysv4.h. */ 1764 1765 1766/* Specific Options for DBX Output. */ 1767 1768/* This is handled by dbxelf.h which is included by svr4.h. */ 1769 1770 1771/* Open ended Hooks for DBX Output. */ 1772 1773/* Likewise. */ 1774 1775 1776/* File names in DBX format. */ 1777 1778/* Likewise. */ 1779 1780 1781/* Macros for SDB and Dwarf Output. */ 1782 1783/* Define this macro if GCC should produce dwarf version 2 format debugging 1784 output in response to the `-g' option. */ 1785 1786#define DWARF2_DEBUGGING_INFO 1 1787 1788/* We do not want call-frame info to be output, since debuggers are 1789 supposed to use the target unwind info. Leave this undefined it 1790 TARGET_UNWIND_INFO might ever be false. */ 1791 1792#define DWARF2_FRAME_INFO 0 1793 1794#define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM) 1795 1796/* Use tags for debug info labels, so that they don't break instruction 1797 bundles. This also avoids getting spurious DV warnings from the 1798 assembler. This is similar to (*targetm.asm_out.internal_label), except that we 1799 add brackets around the label. */ 1800 1801#define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ 1802 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM) 1803 1804/* Use section-relative relocations for debugging offsets. Unlike other 1805 targets that fake this by putting the section VMA at 0, IA-64 has 1806 proper relocations for them. */ 1807#define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, SECTION) \ 1808 do { \ 1809 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1810 fputs ("@secrel(", FILE); \ 1811 assemble_name (FILE, LABEL); \ 1812 fputc (')', FILE); \ 1813 } while (0) 1814 1815/* Emit a PC-relative relocation. */ 1816#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1817 do { \ 1818 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1819 fputs ("@pcrel(", FILE); \ 1820 assemble_name (FILE, LABEL); \ 1821 fputc (')', FILE); \ 1822 } while (0) 1823 1824/* Register Renaming Parameters. */ 1825 1826/* A C expression that is nonzero if hard register number REGNO2 can be 1827 considered for use as a rename register for REGNO1 */ 1828 1829#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ 1830 ia64_hard_regno_rename_ok((REGNO1), (REGNO2)) 1831 1832 1833/* Miscellaneous Parameters. */ 1834 1835/* Flag to mark data that is in the small address area (addressable 1836 via "addl", that is, within a 2MByte offset of 0. */ 1837#define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 1838#define SYMBOL_REF_SMALL_ADDR_P(X) \ 1839 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0) 1840 1841/* An alias for a machine mode name. This is the machine mode that elements of 1842 a jump-table should have. */ 1843 1844#define CASE_VECTOR_MODE ptr_mode 1845 1846/* Define as C expression which evaluates to nonzero if the tablejump 1847 instruction expects the table to contain offsets from the address of the 1848 table. */ 1849 1850#define CASE_VECTOR_PC_RELATIVE 1 1851 1852/* Define this macro if operations between registers with integral mode smaller 1853 than a word are always performed on the entire register. */ 1854 1855#define WORD_REGISTER_OPERATIONS 1856 1857/* Define this macro to be a C expression indicating when insns that read 1858 memory in MODE, an integral mode narrower than a word, set the bits outside 1859 of MODE to be either the sign-extension or the zero-extension of the data 1860 read. */ 1861 1862#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1863 1864/* The maximum number of bytes that a single instruction can move quickly from 1865 memory to memory. */ 1866#define MOVE_MAX 8 1867 1868/* A C expression which is nonzero if on this machine it is safe to "convert" 1869 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller 1870 than INPREC) by merely operating on it as if it had only OUTPREC bits. */ 1871 1872#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1873 1874/* A C expression describing the value returned by a comparison operator with 1875 an integral mode and stored by a store-flag instruction (`sCOND') when the 1876 condition is true. */ 1877 1878/* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */ 1879 1880/* An alias for the machine mode for pointers. */ 1881 1882/* ??? This would change if we had ILP32 support. */ 1883 1884#define Pmode DImode 1885 1886/* An alias for the machine mode used for memory references to functions being 1887 called, in `call' RTL expressions. */ 1888 1889#define FUNCTION_MODE Pmode 1890 1891/* Define this macro to handle System V style pragmas: #pragma pack and 1892 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is 1893 defined. */ 1894 1895#define HANDLE_SYSV_PRAGMA 1 1896 1897/* A C expression for the maximum number of instructions to execute via 1898 conditional execution instructions instead of a branch. A value of 1899 BRANCH_COST+1 is the default if the machine does not use 1900 cc0, and 1 if it does use cc0. */ 1901/* ??? Investigate. */ 1902#define MAX_CONDITIONAL_EXECUTE 12 1903 1904extern int ia64_final_schedule; 1905 1906#define TARGET_UNWIND_INFO 1 1907 1908#define TARGET_UNWIND_TABLES_DEFAULT true 1909 1910#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM) 1911 1912/* This function contains machine specific function data. */ 1913struct GTY(()) machine_function 1914{ 1915 /* The new stack pointer when unwinding from EH. */ 1916 rtx ia64_eh_epilogue_sp; 1917 1918 /* The new bsp value when unwinding from EH. */ 1919 rtx ia64_eh_epilogue_bsp; 1920 1921 /* The GP value save register. */ 1922 rtx ia64_gp_save; 1923 1924 /* The number of varargs registers to save. */ 1925 int n_varargs; 1926 1927 /* The number of the next unwind state to copy. */ 1928 int state_num; 1929}; 1930 1931#define DONT_USE_BUILTIN_SETJMP 1932 1933/* Output any profiling code before the prologue. */ 1934 1935#undef PROFILE_BEFORE_PROLOGUE 1936#define PROFILE_BEFORE_PROLOGUE 1 1937 1938/* Initialize library function table. */ 1939#undef TARGET_INIT_LIBFUNCS 1940#define TARGET_INIT_LIBFUNCS ia64_init_libfuncs 1941 1942 1943/* Switch on code for querying unit reservations. */ 1944#define CPU_UNITS_QUERY 1 1945 1946/* Define this to change the optimizations performed by default. */ 1947#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 1948 ia64_optimization_options ((LEVEL), (SIZE)) 1949 1950/* End of ia64.h */ 1951