1/* Disassembler interface for targets using CGEN. -*- C -*- 2 CGEN: Cpu tools GENerator 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN. 5 - the resultant file is machine generated, cgen-dis.in isn't 6 7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 8 2008, 2010 Free Software Foundation, Inc. 9 10 This file is part of libopcodes. 11 12 This library is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 3, or (at your option) 15 any later version. 16 17 It is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with this program; if not, write to the Free Software Foundation, Inc., 24 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 25 26/* ??? Eventually more and more of this stuff can go to cpu-independent files. 27 Keep that in mind. */ 28 29#include "sysdep.h" 30#include <stdio.h> 31#include "ansidecl.h" 32#include "dis-asm.h" 33#include "bfd.h" 34#include "symcat.h" 35#include "libiberty.h" 36#include "iq2000-desc.h" 37#include "iq2000-opc.h" 38#include "opintl.h" 39 40/* Default text to print if an instruction isn't recognized. */ 41#define UNKNOWN_INSN_MSG _("*unknown*") 42 43static void print_normal 44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 45static void print_address 46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; 47static void print_keyword 48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; 49static void print_insn_normal 50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 51static int print_insn 52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); 53static int default_print_insn 54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; 55static int read_insn 56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, 57 unsigned long *); 58 59/* -- disassembler routines inserted here. */ 60 61 62void iq2000_cgen_print_operand 63 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); 64 65/* Main entry point for printing operands. 66 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 67 of dis-asm.h on cgen.h. 68 69 This function is basically just a big switch statement. Earlier versions 70 used tables to look up the function to use, but 71 - if the table contains both assembler and disassembler functions then 72 the disassembler contains much of the assembler and vice-versa, 73 - there's a lot of inlining possibilities as things grow, 74 - using a switch statement avoids the function call overhead. 75 76 This function could be moved into `print_insn_normal', but keeping it 77 separate makes clear the interface between `print_insn_normal' and each of 78 the handlers. */ 79 80void 81iq2000_cgen_print_operand (CGEN_CPU_DESC cd, 82 int opindex, 83 void * xinfo, 84 CGEN_FIELDS *fields, 85 void const *attrs ATTRIBUTE_UNUSED, 86 bfd_vma pc, 87 int length) 88{ 89 disassemble_info *info = (disassemble_info *) xinfo; 90 91 switch (opindex) 92 { 93 case IQ2000_OPERAND__INDEX : 94 print_normal (cd, info, fields->f_index, 0, pc, length); 95 break; 96 case IQ2000_OPERAND_BASE : 97 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0); 98 break; 99 case IQ2000_OPERAND_BASEOFF : 100 print_address (cd, info, fields->f_imm, 0, pc, length); 101 break; 102 case IQ2000_OPERAND_BITNUM : 103 print_normal (cd, info, fields->f_rt, 0, pc, length); 104 break; 105 case IQ2000_OPERAND_BYTECOUNT : 106 print_normal (cd, info, fields->f_bytecount, 0, pc, length); 107 break; 108 case IQ2000_OPERAND_CAM_Y : 109 print_normal (cd, info, fields->f_cam_y, 0, pc, length); 110 break; 111 case IQ2000_OPERAND_CAM_Z : 112 print_normal (cd, info, fields->f_cam_z, 0, pc, length); 113 break; 114 case IQ2000_OPERAND_CM_3FUNC : 115 print_normal (cd, info, fields->f_cm_3func, 0, pc, length); 116 break; 117 case IQ2000_OPERAND_CM_3Z : 118 print_normal (cd, info, fields->f_cm_3z, 0, pc, length); 119 break; 120 case IQ2000_OPERAND_CM_4FUNC : 121 print_normal (cd, info, fields->f_cm_4func, 0, pc, length); 122 break; 123 case IQ2000_OPERAND_CM_4Z : 124 print_normal (cd, info, fields->f_cm_4z, 0, pc, length); 125 break; 126 case IQ2000_OPERAND_COUNT : 127 print_normal (cd, info, fields->f_count, 0, pc, length); 128 break; 129 case IQ2000_OPERAND_EXECODE : 130 print_normal (cd, info, fields->f_excode, 0, pc, length); 131 break; 132 case IQ2000_OPERAND_HI16 : 133 print_normal (cd, info, fields->f_imm, 0, pc, length); 134 break; 135 case IQ2000_OPERAND_IMM : 136 print_normal (cd, info, fields->f_imm, 0, pc, length); 137 break; 138 case IQ2000_OPERAND_JMPTARG : 139 print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 140 break; 141 case IQ2000_OPERAND_JMPTARGQ10 : 142 print_address (cd, info, fields->f_jtargq10, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 143 break; 144 case IQ2000_OPERAND_LO16 : 145 print_normal (cd, info, fields->f_imm, 0, pc, length); 146 break; 147 case IQ2000_OPERAND_MASK : 148 print_normal (cd, info, fields->f_mask, 0, pc, length); 149 break; 150 case IQ2000_OPERAND_MASKL : 151 print_normal (cd, info, fields->f_maskl, 0, pc, length); 152 break; 153 case IQ2000_OPERAND_MASKQ10 : 154 print_normal (cd, info, fields->f_maskq10, 0, pc, length); 155 break; 156 case IQ2000_OPERAND_MASKR : 157 print_normal (cd, info, fields->f_rs, 0, pc, length); 158 break; 159 case IQ2000_OPERAND_MLO16 : 160 print_normal (cd, info, fields->f_imm, 0, pc, length); 161 break; 162 case IQ2000_OPERAND_OFFSET : 163 print_address (cd, info, fields->f_offset, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 164 break; 165 case IQ2000_OPERAND_RD : 166 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0); 167 break; 168 case IQ2000_OPERAND_RD_RS : 169 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<<CGEN_OPERAND_VIRTUAL)); 170 break; 171 case IQ2000_OPERAND_RD_RT : 172 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0|(1<<CGEN_OPERAND_VIRTUAL)); 173 break; 174 case IQ2000_OPERAND_RS : 175 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0); 176 break; 177 case IQ2000_OPERAND_RT : 178 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0); 179 break; 180 case IQ2000_OPERAND_RT_RS : 181 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<<CGEN_OPERAND_VIRTUAL)); 182 break; 183 case IQ2000_OPERAND_SHAMT : 184 print_normal (cd, info, fields->f_shamt, 0, pc, length); 185 break; 186 187 default : 188 /* xgettext:c-format */ 189 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), 190 opindex); 191 abort (); 192 } 193} 194 195cgen_print_fn * const iq2000_cgen_print_handlers[] = 196{ 197 print_insn_normal, 198}; 199 200 201void 202iq2000_cgen_init_dis (CGEN_CPU_DESC cd) 203{ 204 iq2000_cgen_init_opcode_table (cd); 205 iq2000_cgen_init_ibld_table (cd); 206 cd->print_handlers = & iq2000_cgen_print_handlers[0]; 207 cd->print_operand = iq2000_cgen_print_operand; 208} 209 210 211/* Default print handler. */ 212 213static void 214print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 215 void *dis_info, 216 long value, 217 unsigned int attrs, 218 bfd_vma pc ATTRIBUTE_UNUSED, 219 int length ATTRIBUTE_UNUSED) 220{ 221 disassemble_info *info = (disassemble_info *) dis_info; 222 223 /* Print the operand as directed by the attributes. */ 224 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 225 ; /* nothing to do */ 226 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 227 (*info->fprintf_func) (info->stream, "%ld", value); 228 else 229 (*info->fprintf_func) (info->stream, "0x%lx", value); 230} 231 232/* Default address handler. */ 233 234static void 235print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 236 void *dis_info, 237 bfd_vma value, 238 unsigned int attrs, 239 bfd_vma pc ATTRIBUTE_UNUSED, 240 int length ATTRIBUTE_UNUSED) 241{ 242 disassemble_info *info = (disassemble_info *) dis_info; 243 244 /* Print the operand as directed by the attributes. */ 245 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 246 ; /* Nothing to do. */ 247 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 248 (*info->print_address_func) (value, info); 249 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 250 (*info->print_address_func) (value, info); 251 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 252 (*info->fprintf_func) (info->stream, "%ld", (long) value); 253 else 254 (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 255} 256 257/* Keyword print handler. */ 258 259static void 260print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 261 void *dis_info, 262 CGEN_KEYWORD *keyword_table, 263 long value, 264 unsigned int attrs ATTRIBUTE_UNUSED) 265{ 266 disassemble_info *info = (disassemble_info *) dis_info; 267 const CGEN_KEYWORD_ENTRY *ke; 268 269 ke = cgen_keyword_lookup_value (keyword_table, value); 270 if (ke != NULL) 271 (*info->fprintf_func) (info->stream, "%s", ke->name); 272 else 273 (*info->fprintf_func) (info->stream, "???"); 274} 275 276/* Default insn printer. 277 278 DIS_INFO is defined as `void *' so the disassembler needn't know anything 279 about disassemble_info. */ 280 281static void 282print_insn_normal (CGEN_CPU_DESC cd, 283 void *dis_info, 284 const CGEN_INSN *insn, 285 CGEN_FIELDS *fields, 286 bfd_vma pc, 287 int length) 288{ 289 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 290 disassemble_info *info = (disassemble_info *) dis_info; 291 const CGEN_SYNTAX_CHAR_TYPE *syn; 292 293 CGEN_INIT_PRINT (cd); 294 295 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 296 { 297 if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 298 { 299 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 300 continue; 301 } 302 if (CGEN_SYNTAX_CHAR_P (*syn)) 303 { 304 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 305 continue; 306 } 307 308 /* We have an operand. */ 309 iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 310 fields, CGEN_INSN_ATTRS (insn), pc, length); 311 } 312} 313 314/* Subroutine of print_insn. Reads an insn into the given buffers and updates 315 the extract info. 316 Returns 0 if all is well, non-zero otherwise. */ 317 318static int 319read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 320 bfd_vma pc, 321 disassemble_info *info, 322 bfd_byte *buf, 323 int buflen, 324 CGEN_EXTRACT_INFO *ex_info, 325 unsigned long *insn_value) 326{ 327 int status = (*info->read_memory_func) (pc, buf, buflen, info); 328 329 if (status != 0) 330 { 331 (*info->memory_error_func) (status, pc, info); 332 return -1; 333 } 334 335 ex_info->dis_info = info; 336 ex_info->valid = (1 << buflen) - 1; 337 ex_info->insn_bytes = buf; 338 339 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 340 return 0; 341} 342 343/* Utility to print an insn. 344 BUF is the base part of the insn, target byte order, BUFLEN bytes long. 345 The result is the size of the insn in bytes or zero for an unknown insn 346 or -1 if an error occurs fetching data (memory_error_func will have 347 been called). */ 348 349static int 350print_insn (CGEN_CPU_DESC cd, 351 bfd_vma pc, 352 disassemble_info *info, 353 bfd_byte *buf, 354 unsigned int buflen) 355{ 356 CGEN_INSN_INT insn_value; 357 const CGEN_INSN_LIST *insn_list; 358 CGEN_EXTRACT_INFO ex_info; 359 int basesize; 360 361 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 362 basesize = cd->base_insn_bitsize < buflen * 8 ? 363 cd->base_insn_bitsize : buflen * 8; 364 insn_value = cgen_get_insn_value (cd, buf, basesize); 365 366 367 /* Fill in ex_info fields like read_insn would. Don't actually call 368 read_insn, since the incoming buffer is already read (and possibly 369 modified a la m32r). */ 370 ex_info.valid = (1 << buflen) - 1; 371 ex_info.dis_info = info; 372 ex_info.insn_bytes = buf; 373 374 /* The instructions are stored in hash lists. 375 Pick the first one and keep trying until we find the right one. */ 376 377 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 378 while (insn_list != NULL) 379 { 380 const CGEN_INSN *insn = insn_list->insn; 381 CGEN_FIELDS fields; 382 int length; 383 unsigned long insn_value_cropped; 384 385#ifdef CGEN_VALIDATE_INSN_SUPPORTED 386 /* Not needed as insn shouldn't be in hash lists if not supported. */ 387 /* Supported by this cpu? */ 388 if (! iq2000_cgen_insn_supported (cd, insn)) 389 { 390 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 391 continue; 392 } 393#endif 394 395 /* Basic bit mask must be correct. */ 396 /* ??? May wish to allow target to defer this check until the extract 397 handler. */ 398 399 /* Base size may exceed this instruction's size. Extract the 400 relevant part from the buffer. */ 401 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 402 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 403 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 404 info->endian == BFD_ENDIAN_BIG); 405 else 406 insn_value_cropped = insn_value; 407 408 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 409 == CGEN_INSN_BASE_VALUE (insn)) 410 { 411 /* Printing is handled in two passes. The first pass parses the 412 machine insn and extracts the fields. The second pass prints 413 them. */ 414 415 /* Make sure the entire insn is loaded into insn_value, if it 416 can fit. */ 417 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 418 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 419 { 420 unsigned long full_insn_value; 421 int rc = read_insn (cd, pc, info, buf, 422 CGEN_INSN_BITSIZE (insn) / 8, 423 & ex_info, & full_insn_value); 424 if (rc != 0) 425 return rc; 426 length = CGEN_EXTRACT_FN (cd, insn) 427 (cd, insn, &ex_info, full_insn_value, &fields, pc); 428 } 429 else 430 length = CGEN_EXTRACT_FN (cd, insn) 431 (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 432 433 /* Length < 0 -> error. */ 434 if (length < 0) 435 return length; 436 if (length > 0) 437 { 438 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 439 /* Length is in bits, result is in bytes. */ 440 return length / 8; 441 } 442 } 443 444 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 445 } 446 447 return 0; 448} 449 450/* Default value for CGEN_PRINT_INSN. 451 The result is the size of the insn in bytes or zero for an unknown insn 452 or -1 if an error occured fetching bytes. */ 453 454#ifndef CGEN_PRINT_INSN 455#define CGEN_PRINT_INSN default_print_insn 456#endif 457 458static int 459default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 460{ 461 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 462 int buflen; 463 int status; 464 465 /* Attempt to read the base part of the insn. */ 466 buflen = cd->base_insn_bitsize / 8; 467 status = (*info->read_memory_func) (pc, buf, buflen, info); 468 469 /* Try again with the minimum part, if min < base. */ 470 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 471 { 472 buflen = cd->min_insn_bitsize / 8; 473 status = (*info->read_memory_func) (pc, buf, buflen, info); 474 } 475 476 if (status != 0) 477 { 478 (*info->memory_error_func) (status, pc, info); 479 return -1; 480 } 481 482 return print_insn (cd, pc, info, buf, buflen); 483} 484 485/* Main entry point. 486 Print one instruction from PC on INFO->STREAM. 487 Return the size of the instruction (in bytes). */ 488 489typedef struct cpu_desc_list 490{ 491 struct cpu_desc_list *next; 492 CGEN_BITSET *isa; 493 int mach; 494 int endian; 495 CGEN_CPU_DESC cd; 496} cpu_desc_list; 497 498int 499print_insn_iq2000 (bfd_vma pc, disassemble_info *info) 500{ 501 static cpu_desc_list *cd_list = 0; 502 cpu_desc_list *cl = 0; 503 static CGEN_CPU_DESC cd = 0; 504 static CGEN_BITSET *prev_isa; 505 static int prev_mach; 506 static int prev_endian; 507 int length; 508 CGEN_BITSET *isa; 509 int mach; 510 int endian = (info->endian == BFD_ENDIAN_BIG 511 ? CGEN_ENDIAN_BIG 512 : CGEN_ENDIAN_LITTLE); 513 enum bfd_architecture arch; 514 515 /* ??? gdb will set mach but leave the architecture as "unknown" */ 516#ifndef CGEN_BFD_ARCH 517#define CGEN_BFD_ARCH bfd_arch_iq2000 518#endif 519 arch = info->arch; 520 if (arch == bfd_arch_unknown) 521 arch = CGEN_BFD_ARCH; 522 523 /* There's no standard way to compute the machine or isa number 524 so we leave it to the target. */ 525#ifdef CGEN_COMPUTE_MACH 526 mach = CGEN_COMPUTE_MACH (info); 527#else 528 mach = info->mach; 529#endif 530 531#ifdef CGEN_COMPUTE_ISA 532 { 533 static CGEN_BITSET *permanent_isa; 534 535 if (!permanent_isa) 536 permanent_isa = cgen_bitset_create (MAX_ISAS); 537 isa = permanent_isa; 538 cgen_bitset_clear (isa); 539 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); 540 } 541#else 542 isa = info->insn_sets; 543#endif 544 545 /* If we've switched cpu's, try to find a handle we've used before */ 546 if (cd 547 && (cgen_bitset_compare (isa, prev_isa) != 0 548 || mach != prev_mach 549 || endian != prev_endian)) 550 { 551 cd = 0; 552 for (cl = cd_list; cl; cl = cl->next) 553 { 554 if (cgen_bitset_compare (cl->isa, isa) == 0 && 555 cl->mach == mach && 556 cl->endian == endian) 557 { 558 cd = cl->cd; 559 prev_isa = cd->isas; 560 break; 561 } 562 } 563 } 564 565 /* If we haven't initialized yet, initialize the opcode table. */ 566 if (! cd) 567 { 568 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 569 const char *mach_name; 570 571 if (!arch_type) 572 abort (); 573 mach_name = arch_type->printable_name; 574 575 prev_isa = cgen_bitset_copy (isa); 576 prev_mach = mach; 577 prev_endian = endian; 578 cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 579 CGEN_CPU_OPEN_BFDMACH, mach_name, 580 CGEN_CPU_OPEN_ENDIAN, prev_endian, 581 CGEN_CPU_OPEN_END); 582 if (!cd) 583 abort (); 584 585 /* Save this away for future reference. */ 586 cl = xmalloc (sizeof (struct cpu_desc_list)); 587 cl->cd = cd; 588 cl->isa = prev_isa; 589 cl->mach = mach; 590 cl->endian = endian; 591 cl->next = cd_list; 592 cd_list = cl; 593 594 iq2000_cgen_init_dis (cd); 595 } 596 597 /* We try to have as much common code as possible. 598 But at this point some targets need to take over. */ 599 /* ??? Some targets may need a hook elsewhere. Try to avoid this, 600 but if not possible try to move this hook elsewhere rather than 601 have two hooks. */ 602 length = CGEN_PRINT_INSN (cd, pc, info); 603 if (length > 0) 604 return length; 605 if (length < 0) 606 return -1; 607 608 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 609 return cd->default_insn_bitsize / 8; 610} 611