11590Srgrimes/* Opcode table for the ARC. 21590Srgrimes Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010 31590Srgrimes Free Software Foundation, Inc. 41590Srgrimes Contributed by Doug Evans (dje@cygnus.com). 51590Srgrimes 61590Srgrimes This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 71590Srgrimes the GNU Binutils. 81590Srgrimes 91590Srgrimes GAS/GDB is free software; you can redistribute it and/or modify 101590Srgrimes it under the terms of the GNU General Public License as published by 111590Srgrimes the Free Software Foundation; either version 3, or (at your option) 121590Srgrimes any later version. 131590Srgrimes 141590Srgrimes GAS/GDB is distributed in the hope that it will be useful, 151590Srgrimes but WITHOUT ANY WARRANTY; without even the implied warranty of 161590Srgrimes MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 171590Srgrimes GNU General Public License for more details. 181590Srgrimes 191590Srgrimes You should have received a copy of the GNU General Public License 201590Srgrimes along with GAS or GDB; see the file COPYING3. If not, write to 211590Srgrimes the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 221590Srgrimes MA 02110-1301, USA. */ 231590Srgrimes 241590Srgrimes/* List of the various cpu types. 251590Srgrimes The tables currently use bit masks to say whether the instruction or 261590Srgrimes whatever is supported by a particular cpu. This lets us have one entry 271590Srgrimes apply to several cpus. 281590Srgrimes 291590Srgrimes The `base' cpu must be 0. The cpu type is treated independently of 301590Srgrimes endianness. The complete `mach' number includes endianness. 311590Srgrimes These values are internal to opcodes/bfd/binutils/gas. */ 321590Srgrimes#define ARC_MACH_5 0 331590Srgrimes#define ARC_MACH_6 1 341590Srgrimes#define ARC_MACH_7 2 3527753Scharnier#define ARC_MACH_8 4 361590Srgrimes 3727753Scharnier/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ 3827753Scharnier#define ARC_MACH_BIG 16 3927753Scharnier 401590Srgrimes/* Mask of number of bits necessary to record cpu type. */ 411590Srgrimes#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) 421590Srgrimes 431590Srgrimes/* Mask of number of bits necessary to record cpu type + endianness. */ 441590Srgrimes#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) 451590Srgrimes 461590Srgrimes/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ 4714543Sdg 481590Srgrimestypedef unsigned int arc_insn; 491590Srgrimes 501590Srgrimesstruct arc_opcode { 511590Srgrimes char *syntax; /* syntax of insn */ 521590Srgrimes unsigned long mask, value; /* recognize insn if (op&mask) == value */ 531590Srgrimes int flags; /* various flag bits */ 541590Srgrimes 551590Srgrimes/* Values for `flags'. */ 561590Srgrimes 571590Srgrimes/* Return CPU number, given flag bits. */ 581590Srgrimes#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) 591590Srgrimes 601590Srgrimes/* Return MACH number, given flag bits. */ 611590Srgrimes#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) 621590Srgrimes 631590Srgrimes/* First opcode flag bit available after machine mask. */ 641590Srgrimes#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) 651590Srgrimes 661590Srgrimes/* This insn is a conditional branch. */ 671590Srgrimes#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) 681590Srgrimes#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) 691590Srgrimes#define SYNTAX_LENGTH (SYNTAX_3OP ) 701590Srgrimes#define SYNTAX_2OP (SYNTAX_3OP << 1) 711590Srgrimes#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) 721590Srgrimes#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) 731590Srgrimes#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) 741590Srgrimes 751590Srgrimes#define I(x) (((x) & 31) << 27) 761590Srgrimes#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) 771590Srgrimes#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) 781590Srgrimes#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) 791590Srgrimes#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ 801590Srgrimes 811590Srgrimes/* These values are used to optimize assembly and disassembly. Each insn 821590Srgrimes is on a list of related insns (same first letter for assembly, same 831590Srgrimes insn code for disassembly). */ 841590Srgrimes 851590Srgrimes struct arc_opcode *next_asm; /* Next instr to try during assembly. */ 861590Srgrimes struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ 871590Srgrimes 881590Srgrimes/* Macros to create the hash values for the lists. */ 891590Srgrimes#define ARC_HASH_OPCODE(string) \ 901590Srgrimes ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) 911590Srgrimes#define ARC_HASH_ICODE(insn) \ 921590Srgrimes ((unsigned int) (insn) >> 27) 931590Srgrimes 941590Srgrimes /* Macros to access `next_asm', `next_dis' so users needn't care about the 951590Srgrimes underlying mechanism. */ 961590Srgrimes#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) 971590Srgrimes#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) 981590Srgrimes}; 991590Srgrimes 1001590Srgrimes/* this is an "insert at front" linked list per Metaware spec 1011590Srgrimes that new definitions override older ones. */ 1021590Srgrimesextern struct arc_opcode *arc_ext_opcodes; 1031590Srgrimes 1041590Srgrimesstruct arc_operand_value { 1051590Srgrimes char *name; /* eg: "eq" */ 1061590Srgrimes short value; /* eg: 1 */ 1071590Srgrimes unsigned char type; /* index into `arc_operands' */ 1081590Srgrimes unsigned char flags; /* various flag bits */ 1091590Srgrimes 11016080Salex/* Values for `flags'. */ 1111590Srgrimes 1121590Srgrimes/* Return CPU number, given flag bits. */ 1131590Srgrimes#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) 1141590Srgrimes/* Return MACH number, given flag bits. */ 1151590Srgrimes#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) 1161590Srgrimes}; 1171590Srgrimes 1181590Srgrimesstruct arc_ext_operand_value { 1191590Srgrimes struct arc_ext_operand_value *next; 1201590Srgrimes struct arc_operand_value operand; 1211590Srgrimes}; 1221590Srgrimes 1231590Srgrimesextern struct arc_ext_operand_value *arc_ext_operands; 1241590Srgrimes 1251590Srgrimesstruct arc_operand { 1261590Srgrimes/* One of the insn format chars. */ 1271590Srgrimes unsigned char fmt; 1281590Srgrimes 1291590Srgrimes/* The number of bits in the operand (may be unused for a modifier). */ 13016080Salex unsigned char bits; 13116080Salex 13216080Salex/* How far the operand is left shifted in the instruction, or 13316080Salex the modifier's flag bit (may be unused for a modifier. */ 1341590Srgrimes unsigned char shift; 1351590Srgrimes 1361590Srgrimes/* Various flag bits. */ 1371590Srgrimes int flags; 1381590Srgrimes 1391590Srgrimes/* Values for `flags'. */ 140 141/* This operand is a suffix to the opcode. */ 142#define ARC_OPERAND_SUFFIX 1 143 144/* This operand is a relative branch displacement. The disassembler 145 prints these symbolically if possible. */ 146#define ARC_OPERAND_RELATIVE_BRANCH 2 147 148/* This operand is an absolute branch address. The disassembler 149 prints these symbolically if possible. */ 150#define ARC_OPERAND_ABSOLUTE_BRANCH 4 151 152/* This operand is an address. The disassembler 153 prints these symbolically if possible. */ 154#define ARC_OPERAND_ADDRESS 8 155 156/* This operand is a long immediate value. */ 157#define ARC_OPERAND_LIMM 0x10 158 159/* This operand takes signed values. */ 160#define ARC_OPERAND_SIGNED 0x20 161 162/* This operand takes signed values, but also accepts a full positive 163 range of values. That is, if bits is 16, it takes any value from 164 -0x8000 to 0xffff. */ 165#define ARC_OPERAND_SIGNOPT 0x40 166 167/* This operand should be regarded as a negative number for the 168 purposes of overflow checking (i.e., the normal most negative 169 number is disallowed and one more than the normal most positive 170 number is allowed). This flag will only be set for a signed 171 operand. */ 172#define ARC_OPERAND_NEGATIVE 0x80 173 174/* This operand doesn't really exist. The program uses these operands 175 in special ways. */ 176#define ARC_OPERAND_FAKE 0x100 177 178/* separate flags operand for j and jl instructions */ 179#define ARC_OPERAND_JUMPFLAGS 0x200 180 181/* allow warnings and errors to be issued after call to insert_xxxxxx */ 182#define ARC_OPERAND_WARN 0x400 183#define ARC_OPERAND_ERROR 0x800 184 185/* this is a load operand */ 186#define ARC_OPERAND_LOAD 0x8000 187 188/* this is a store operand */ 189#define ARC_OPERAND_STORE 0x10000 190 191/* Modifier values. */ 192/* A dot is required before a suffix. Eg: .le */ 193#define ARC_MOD_DOT 0x1000 194 195/* A normal register is allowed (not used, but here for completeness). */ 196#define ARC_MOD_REG 0x2000 197 198/* An auxiliary register name is expected. */ 199#define ARC_MOD_AUXREG 0x4000 200 201/* Sum of all ARC_MOD_XXX bits. */ 202#define ARC_MOD_BITS 0x7000 203 204/* Non-zero if the operand type is really a modifier. */ 205#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) 206 207/* enforce read/write only register restrictions */ 208#define ARC_REGISTER_READONLY 0x01 209#define ARC_REGISTER_WRITEONLY 0x02 210#define ARC_REGISTER_NOSHORT_CUT 0x04 211 212/* Insertion function. This is used by the assembler. To insert an 213 operand value into an instruction, check this field. 214 215 If it is NULL, execute 216 i |= (p & ((1 << o->bits) - 1)) << o->shift; 217 (I is the instruction which we are filling in, O is a pointer to 218 this structure, and OP is the opcode value; this assumes twos 219 complement arithmetic). 220 221 If this field is not NULL, then simply call it with the 222 instruction and the operand value. It will return the new value 223 of the instruction. If the ERRMSG argument is not NULL, then if 224 the operand value is illegal, *ERRMSG will be set to a warning 225 string (the operand will be inserted in any case). If the 226 operand value is legal, *ERRMSG will be unchanged. 227 228 REG is non-NULL when inserting a register value. */ 229 230 arc_insn (*insert) 231 (arc_insn insn, const struct arc_operand *operand, int mods, 232 const struct arc_operand_value *reg, long value, const char **errmsg); 233 234/* Extraction function. This is used by the disassembler. To 235 extract this operand type from an instruction, check this field. 236 237 If it is NULL, compute 238 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 239 if ((o->flags & ARC_OPERAND_SIGNED) != 0 240 && (op & (1 << (o->bits - 1))) != 0) 241 op -= 1 << o->bits; 242 (I is the instruction, O is a pointer to this structure, and OP 243 is the result; this assumes twos complement arithmetic). 244 245 If this field is not NULL, then simply call it with the 246 instruction value. It will return the value of the operand. If 247 the INVALID argument is not NULL, *INVALID will be set to 248 non-zero if this operand type can not actually be extracted from 249 this operand (i.e., the instruction does not match). If the 250 operand is valid, *INVALID will not be changed. 251 252 INSN is a pointer to an array of two `arc_insn's. The first element is 253 the insn, the second is the limm if present. 254 255 Operands that have a printable form like registers and suffixes have 256 their struct arc_operand_value pointer stored in OPVAL. */ 257 258 long (*extract) 259 (arc_insn *insn, const struct arc_operand *operand, int mods, 260 const struct arc_operand_value **opval, int *invalid); 261}; 262 263/* Bits that say what version of cpu we have. These should be passed to 264 arc_init_opcode_tables. At present, all there is is the cpu type. */ 265 266/* CPU number, given value passed to `arc_init_opcode_tables'. */ 267#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) 268/* MACH number, given value passed to `arc_init_opcode_tables'. */ 269#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) 270 271/* Special register values: */ 272#define ARC_REG_SHIMM_UPDATE 61 273#define ARC_REG_SHIMM 63 274#define ARC_REG_LIMM 62 275 276/* Non-zero if REG is a constant marker. */ 277#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) 278 279/* Positions and masks of various fields: */ 280#define ARC_SHIFT_REGA 21 281#define ARC_SHIFT_REGB 15 282#define ARC_SHIFT_REGC 9 283#define ARC_MASK_REG 63 284 285/* Delay slot types. */ 286#define ARC_DELAY_NONE 0 /* no delay slot */ 287#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ 288#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ 289 290/* Non-zero if X will fit in a signed 9 bit field. */ 291#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) 292 293extern const struct arc_operand arc_operands[]; 294extern const int arc_operand_count; 295extern struct arc_opcode arc_opcodes[]; 296extern const int arc_opcodes_count; 297extern const struct arc_operand_value arc_suffixes[]; 298extern const int arc_suffixes_count; 299extern const struct arc_operand_value arc_reg_names[]; 300extern const int arc_reg_names_count; 301extern unsigned char arc_operand_map[]; 302 303/* Utility fns in arc-opc.c. */ 304int arc_get_opcode_mach (int, int); 305 306/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ 307void arc_opcode_init_tables (int); 308void arc_opcode_init_insert (void); 309void arc_opcode_init_extract (void); 310const struct arc_opcode *arc_opcode_lookup_asm (const char *); 311const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); 312int arc_opcode_limm_p (long *); 313const struct arc_operand_value *arc_opcode_lookup_suffix 314 (const struct arc_operand *type, int value); 315int arc_opcode_supported (const struct arc_opcode *); 316int arc_opval_supported (const struct arc_operand_value *); 317int arc_limm_fixup_adjust (arc_insn); 318int arc_insn_is_j (arc_insn); 319int arc_insn_not_jl (arc_insn); 320int arc_operand_type (int); 321struct arc_operand_value *get_ext_suffix (char *); 322int arc_get_noshortcut_flag (void); 323