1//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 Register file, defining the registers themselves, 11// aliases between the registers, and the register classes built out of the 12// registers. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// Register definitions... 18// 19let Namespace = "X86" in { 20 21 // Subregister indices. 22 def sub_8bit : SubRegIndex; 23 def sub_8bit_hi : SubRegIndex; 24 def sub_16bit : SubRegIndex; 25 def sub_32bit : SubRegIndex; 26 def sub_xmm : SubRegIndex; 27 28 29 // In the register alias definitions below, we define which registers alias 30 // which others. We only specify which registers the small registers alias, 31 // because the register file generator is smart enough to figure out that 32 // AL aliases AX if we tell it that AX aliased AL (for example). 33 34 // Dwarf numbering is different for 32-bit and 64-bit, and there are 35 // variations by target as well. Currently the first entry is for X86-64, 36 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux 37 // and debug information on X86-32/Darwin) 38 39 // 8-bit registers 40 // Low registers 41 def AL : Register<"al">; 42 def DL : Register<"dl">; 43 def CL : Register<"cl">; 44 def BL : Register<"bl">; 45 46 // X86-64 only, requires REX. 47 let CostPerUse = 1 in { 48 def SIL : Register<"sil">; 49 def DIL : Register<"dil">; 50 def BPL : Register<"bpl">; 51 def SPL : Register<"spl">; 52 def R8B : Register<"r8b">; 53 def R9B : Register<"r9b">; 54 def R10B : Register<"r10b">; 55 def R11B : Register<"r11b">; 56 def R12B : Register<"r12b">; 57 def R13B : Register<"r13b">; 58 def R14B : Register<"r14b">; 59 def R15B : Register<"r15b">; 60 } 61 62 // High registers. On x86-64, these cannot be used in any instruction 63 // with a REX prefix. 64 def AH : Register<"ah">; 65 def DH : Register<"dh">; 66 def CH : Register<"ch">; 67 def BH : Register<"bh">; 68 69 // 16-bit registers 70 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in { 71 def AX : RegisterWithSubRegs<"ax", [AL,AH]>; 72 def DX : RegisterWithSubRegs<"dx", [DL,DH]>; 73 def CX : RegisterWithSubRegs<"cx", [CL,CH]>; 74 def BX : RegisterWithSubRegs<"bx", [BL,BH]>; 75 } 76 let SubRegIndices = [sub_8bit] in { 77 def SI : RegisterWithSubRegs<"si", [SIL]>; 78 def DI : RegisterWithSubRegs<"di", [DIL]>; 79 def BP : RegisterWithSubRegs<"bp", [BPL]>; 80 def SP : RegisterWithSubRegs<"sp", [SPL]>; 81 } 82 def IP : Register<"ip">; 83 84 // X86-64 only, requires REX. 85 let SubRegIndices = [sub_8bit], CostPerUse = 1 in { 86 def R8W : RegisterWithSubRegs<"r8w", [R8B]>; 87 def R9W : RegisterWithSubRegs<"r9w", [R9B]>; 88 def R10W : RegisterWithSubRegs<"r10w", [R10B]>; 89 def R11W : RegisterWithSubRegs<"r11w", [R11B]>; 90 def R12W : RegisterWithSubRegs<"r12w", [R12B]>; 91 def R13W : RegisterWithSubRegs<"r13w", [R13B]>; 92 def R14W : RegisterWithSubRegs<"r14w", [R14B]>; 93 def R15W : RegisterWithSubRegs<"r15w", [R15B]>; 94 } 95 // 32-bit registers 96 let SubRegIndices = [sub_16bit] in { 97 def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[-2, 0, 0]>; 98 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[-2, 2, 2]>; 99 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[-2, 1, 1]>; 100 def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[-2, 3, 3]>; 101 def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[-2, 6, 6]>; 102 def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[-2, 7, 7]>; 103 def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[-2, 4, 5]>; 104 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[-2, 5, 4]>; 105 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[-2, 8, 8]>; 106 107 // X86-64 only, requires REX 108 let CostPerUse = 1 in { 109 def R8D : RegisterWithSubRegs<"r8d", [R8W]>; 110 def R9D : RegisterWithSubRegs<"r9d", [R9W]>; 111 def R10D : RegisterWithSubRegs<"r10d", [R10W]>; 112 def R11D : RegisterWithSubRegs<"r11d", [R11W]>; 113 def R12D : RegisterWithSubRegs<"r12d", [R12W]>; 114 def R13D : RegisterWithSubRegs<"r13d", [R13W]>; 115 def R14D : RegisterWithSubRegs<"r14d", [R14W]>; 116 def R15D : RegisterWithSubRegs<"r15d", [R15W]>; 117 }} 118 119 // 64-bit registers, X86-64 only 120 let SubRegIndices = [sub_32bit] in { 121 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>; 122 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>; 123 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>; 124 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>; 125 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>; 126 def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>; 127 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>; 128 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>; 129 130 // These also require REX. 131 let CostPerUse = 1 in { 132 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>; 133 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>; 134 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>; 135 def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>; 136 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>; 137 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>; 138 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>; 139 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>; 140 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>; 141 }} 142 143 // MMX Registers. These are actually aliased to ST0 .. ST7 144 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>; 145 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>; 146 def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>; 147 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>; 148 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>; 149 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>; 150 def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>; 151 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>; 152 153 // Pseudo Floating Point registers 154 def FP0 : Register<"fp0">; 155 def FP1 : Register<"fp1">; 156 def FP2 : Register<"fp2">; 157 def FP3 : Register<"fp3">; 158 def FP4 : Register<"fp4">; 159 def FP5 : Register<"fp5">; 160 def FP6 : Register<"fp6">; 161 162 // XMM Registers, used by the various SSE instruction set extensions. 163 def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>; 164 def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>; 165 def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>; 166 def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>; 167 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>; 168 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>; 169 def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>; 170 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>; 171 172 // X86-64 only 173 let CostPerUse = 1 in { 174 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>; 175 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>; 176 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>; 177 def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>; 178 def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>; 179 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>; 180 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>; 181 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>; 182 } // CostPerUse 183 184 // YMM Registers, used by AVX instructions 185 let SubRegIndices = [sub_xmm] in { 186 def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegAlias<XMM0>; 187 def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegAlias<XMM1>; 188 def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegAlias<XMM2>; 189 def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegAlias<XMM3>; 190 def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegAlias<XMM4>; 191 def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegAlias<XMM5>; 192 def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegAlias<XMM6>; 193 def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegAlias<XMM7>; 194 def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegAlias<XMM8>; 195 def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegAlias<XMM9>; 196 def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegAlias<XMM10>; 197 def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegAlias<XMM11>; 198 def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegAlias<XMM12>; 199 def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegAlias<XMM13>; 200 def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegAlias<XMM14>; 201 def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias<XMM15>; 202 } 203 204 class STRegister<string Name, list<Register> A> : Register<Name> { 205 let Aliases = A; 206 } 207 208 // Floating point stack registers. These don't map one-to-one to the FP 209 // pseudo registers, but we still mark them as aliasing FP registers. That 210 // way both kinds can be live without exceeding the stack depth. ST registers 211 // are only live around inline assembly. 212 def ST0 : STRegister<"st(0)", []>, DwarfRegNum<[33, 12, 11]>; 213 def ST1 : STRegister<"st(1)", [FP6]>, DwarfRegNum<[34, 13, 12]>; 214 def ST2 : STRegister<"st(2)", [FP5]>, DwarfRegNum<[35, 14, 13]>; 215 def ST3 : STRegister<"st(3)", [FP4]>, DwarfRegNum<[36, 15, 14]>; 216 def ST4 : STRegister<"st(4)", [FP3]>, DwarfRegNum<[37, 16, 15]>; 217 def ST5 : STRegister<"st(5)", [FP2]>, DwarfRegNum<[38, 17, 16]>; 218 def ST6 : STRegister<"st(6)", [FP1]>, DwarfRegNum<[39, 18, 17]>; 219 def ST7 : STRegister<"st(7)", [FP0]>, DwarfRegNum<[40, 19, 18]>; 220 221 // Floating-point status word 222 def FPSW : Register<"fpsw">; 223 224 // Status flags register 225 def EFLAGS : Register<"flags">; 226 227 // Segment registers 228 def CS : Register<"cs">; 229 def DS : Register<"ds">; 230 def SS : Register<"ss">; 231 def ES : Register<"es">; 232 def FS : Register<"fs">; 233 def GS : Register<"gs">; 234 235 // Debug registers 236 def DR0 : Register<"dr0">; 237 def DR1 : Register<"dr1">; 238 def DR2 : Register<"dr2">; 239 def DR3 : Register<"dr3">; 240 def DR4 : Register<"dr4">; 241 def DR5 : Register<"dr5">; 242 def DR6 : Register<"dr6">; 243 def DR7 : Register<"dr7">; 244 245 // Control registers 246 def CR0 : Register<"cr0">; 247 def CR1 : Register<"cr1">; 248 def CR2 : Register<"cr2">; 249 def CR3 : Register<"cr3">; 250 def CR4 : Register<"cr4">; 251 def CR5 : Register<"cr5">; 252 def CR6 : Register<"cr6">; 253 def CR7 : Register<"cr7">; 254 def CR8 : Register<"cr8">; 255 def CR9 : Register<"cr9">; 256 def CR10 : Register<"cr10">; 257 def CR11 : Register<"cr11">; 258 def CR12 : Register<"cr12">; 259 def CR13 : Register<"cr13">; 260 def CR14 : Register<"cr14">; 261 def CR15 : Register<"cr15">; 262 263 // Pseudo index registers 264 def EIZ : Register<"eiz">; 265 def RIZ : Register<"riz">; 266} 267 268 269//===----------------------------------------------------------------------===// 270// Register Class Definitions... now that we have all of the pieces, define the 271// top-level register classes. The order specified in the register list is 272// implicitly defined to be the register allocation order. 273// 274 275// List call-clobbered registers before callee-save registers. RBX, RBP, (and 276// R12, R13, R14, and R15 for X86-64) are callee-save registers. 277// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and 278// R8B, ... R15B. 279// Allocate R12 and R13 last, as these require an extra byte when 280// encoded in x86_64 instructions. 281// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 282// 64-bit mode. The main complication is that they cannot be encoded in an 283// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. 284// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" 285// cannot be encoded. 286def GR8 : RegisterClass<"X86", [i8], 8, 287 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 288 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> { 289 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 290 let AltOrderSelect = [{ 291 return MF.getTarget().getSubtarget<X86Subtarget>().is64Bit(); 292 }]; 293} 294 295def GR16 : RegisterClass<"X86", [i16], 16, 296 (add AX, CX, DX, SI, DI, BX, BP, SP, 297 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>; 298 299def GR32 : RegisterClass<"X86", [i32], 32, 300 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, 301 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>; 302 303// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 304// RIP isn't really a register and it can't be used anywhere except in an 305// address, but it doesn't cause trouble. 306def GR64 : RegisterClass<"X86", [i64], 64, 307 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 308 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; 309 310// Segment registers for use by MOV instructions (and others) that have a 311// segment register as one operand. Always contain a 16-bit segment 312// descriptor. 313def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; 314 315// Debug registers. 316def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>; 317 318// Control registers. 319def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; 320 321// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of 322// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" 323// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers 324// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, 325// and GR64_ABCD are classes for registers that support 8-bit h-register 326// operations. 327def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 328def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 329def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>; 330def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; 331def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; 332def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)>; 333def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 334 R8, R9, R11, RIP)>; 335def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 336 R8, R9, R11)>; 337 338// GR8_NOREX - GR8 registers which do not require a REX prefix. 339def GR8_NOREX : RegisterClass<"X86", [i8], 8, 340 (add AL, CL, DL, AH, CH, DH, BL, BH)> { 341 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; 342 let AltOrderSelect = [{ 343 return MF.getTarget().getSubtarget<X86Subtarget>().is64Bit(); 344 }]; 345} 346// GR16_NOREX - GR16 registers which do not require a REX prefix. 347def GR16_NOREX : RegisterClass<"X86", [i16], 16, 348 (add AX, CX, DX, SI, DI, BX, BP, SP)>; 349// GR32_NOREX - GR32 registers which do not require a REX prefix. 350def GR32_NOREX : RegisterClass<"X86", [i32], 32, 351 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; 352// GR64_NOREX - GR64 registers which do not require a REX prefix. 353def GR64_NOREX : RegisterClass<"X86", [i64], 64, 354 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; 355 356// GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit 357// mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs 358// to clear upper 32-bits of RAX so is not a NOP. 359def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)>; 360 361// GR32_NOSP - GR32 registers except ESP. 362def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; 363 364// GR64_NOSP - GR64 registers except RSP (and RIP). 365def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; 366 367// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except 368// ESP. 369def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, 370 (and GR32_NOREX, GR32_NOSP)>; 371 372// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. 373def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, 374 (and GR64_NOREX, GR64_NOSP)>; 375 376// A class to support the 'A' assembler constraint: EAX then EDX. 377def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; 378 379// Scalar SSE2 floating point registers. 380def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 381 382def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 383 384 385// FIXME: This sets up the floating point register files as though they are f64 386// values, though they really are f80 values. This will cause us to spill 387// values as 64-bit quantities instead of 80-bit quantities, which is much much 388// faster on common hardware. In reality, this should be controlled by a 389// command line option or something. 390 391def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; 392def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; 393def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; 394 395// Floating point stack registers (these are not allocatable by the 396// register allocator - the floating point stackifier is responsible 397// for transforming FPn allocations to STn registers) 398def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { 399 let isAllocatable = 0; 400} 401 402// Generic vector registers: VR64 and VR128. 403def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; 404def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 405 128, (add FR32)>; 406def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 407 256, (sequence "YMM%u", 0, 15)>; 408 409// Status flags registers. 410def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { 411 let CopyCost = -1; // Don't allow copying of status registers. 412 let isAllocatable = 0; 413} 414def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> { 415 let CopyCost = -1; // Don't allow copying of status registers. 416 let isAllocatable = 0; 417} 418