1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13let Namespace = "Mips" in { 14def sub_fpeven : SubRegIndex; 15def sub_fpodd : SubRegIndex; 16def sub_32 : SubRegIndex; 17def sub_lo : SubRegIndex; 18def sub_hi : SubRegIndex; 19} 20 21// We have banks of 32 registers each. 22class MipsReg<string n> : Register<n> { 23 field bits<5> Num; 24 let Namespace = "Mips"; 25} 26 27class MipsRegWithSubRegs<string n, list<Register> subregs> 28 : RegisterWithSubRegs<n, subregs> { 29 field bits<5> Num; 30 let Namespace = "Mips"; 31} 32 33// Mips CPU Registers 34class MipsGPRReg<bits<5> num, string n> : MipsReg<n> { 35 let Num = num; 36} 37 38// Mips 64-bit CPU Registers 39class Mips64GPRReg<bits<5> num, string n, list<Register> subregs> 40 : MipsRegWithSubRegs<n, subregs> { 41 let Num = num; 42 let SubRegIndices = [sub_32]; 43} 44 45// Mips 32-bit FPU Registers 46class FPR<bits<5> num, string n> : MipsReg<n> { 47 let Num = num; 48} 49 50// Mips 64-bit (aliased) FPU Registers 51class AFPR<bits<5> num, string n, list<Register> subregs> 52 : MipsRegWithSubRegs<n, subregs> { 53 let Num = num; 54 let SubRegIndices = [sub_fpeven, sub_fpodd]; 55 let CoveredBySubRegs = 1; 56} 57 58class AFPR64<bits<5> num, string n, list<Register> subregs> 59 : MipsRegWithSubRegs<n, subregs> { 60 let Num = num; 61 let SubRegIndices = [sub_32]; 62} 63 64// Mips Hardware Registers 65class HWR<bits<5> num, string n> : MipsReg<n> { 66 let Num = num; 67} 68 69//===----------------------------------------------------------------------===// 70// Registers 71//===----------------------------------------------------------------------===// 72 73let Namespace = "Mips" in { 74 // General Purpose Registers 75 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 76 def AT : MipsGPRReg< 1, "at">, DwarfRegNum<[1]>; 77 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 78 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 79 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 80 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 81 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 82 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 83 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 84 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 85 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 86 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 87 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 88 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 89 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 90 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 91 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 92 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 93 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 94 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 95 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 96 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 97 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 98 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 99 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 100 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 101 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 102 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 103 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 104 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 105 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 106 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 107 108 // General Purpose 64-bit Registers 109 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 110 def AT_64 : Mips64GPRReg< 1, "at", [AT]>, DwarfRegNum<[1]>; 111 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 112 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 113 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 114 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 115 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 116 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 117 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 118 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 119 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 120 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 121 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 122 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 123 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 124 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 125 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 126 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 127 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 128 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 129 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 130 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 131 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 132 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 133 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 134 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 135 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 136 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 137 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 138 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 139 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 140 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 141 142 /// Mips Single point precision FPU Registers 143 def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; 144 def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; 145 def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; 146 def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; 147 def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; 148 def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; 149 def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; 150 def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; 151 def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; 152 def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; 153 def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; 154 def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; 155 def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; 156 def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; 157 def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; 158 def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; 159 def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; 160 def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; 161 def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; 162 def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; 163 def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; 164 def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; 165 def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; 166 def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; 167 def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; 168 def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; 169 def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; 170 def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; 171 def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; 172 def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; 173 def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; 174 def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; 175 176 /// Mips Double point precision FPU Registers (aliased 177 /// with the single precision to hold 64 bit values) 178 def D0 : AFPR< 0, "f0", [F0, F1]>; 179 def D1 : AFPR< 2, "f2", [F2, F3]>; 180 def D2 : AFPR< 4, "f4", [F4, F5]>; 181 def D3 : AFPR< 6, "f6", [F6, F7]>; 182 def D4 : AFPR< 8, "f8", [F8, F9]>; 183 def D5 : AFPR<10, "f10", [F10, F11]>; 184 def D6 : AFPR<12, "f12", [F12, F13]>; 185 def D7 : AFPR<14, "f14", [F14, F15]>; 186 def D8 : AFPR<16, "f16", [F16, F17]>; 187 def D9 : AFPR<18, "f18", [F18, F19]>; 188 def D10 : AFPR<20, "f20", [F20, F21]>; 189 def D11 : AFPR<22, "f22", [F22, F23]>; 190 def D12 : AFPR<24, "f24", [F24, F25]>; 191 def D13 : AFPR<26, "f26", [F26, F27]>; 192 def D14 : AFPR<28, "f28", [F28, F29]>; 193 def D15 : AFPR<30, "f30", [F30, F31]>; 194 195 /// Mips Double point precision FPU Registers in MFP64 mode. 196 def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>; 197 def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>; 198 def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>; 199 def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>; 200 def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>; 201 def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>; 202 def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>; 203 def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>; 204 def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>; 205 def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>; 206 def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>; 207 def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>; 208 def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>; 209 def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>; 210 def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>; 211 def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>; 212 def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>; 213 def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>; 214 def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>; 215 def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>; 216 def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>; 217 def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>; 218 def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>; 219 def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>; 220 def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>; 221 def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>; 222 def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>; 223 def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>; 224 def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>; 225 def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>; 226 def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>; 227 def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>; 228 229 // Hi/Lo registers 230 def HI : Register<"hi">, DwarfRegNum<[64]>; 231 def LO : Register<"lo">, DwarfRegNum<[65]>; 232 233 let SubRegIndices = [sub_32] in { 234 def HI64 : RegisterWithSubRegs<"hi", [HI]>; 235 def LO64 : RegisterWithSubRegs<"lo", [LO]>; 236 } 237 238 // Status flags register 239 def FCR31 : Register<"31">; 240 241 // fcc0 register 242 def FCC0 : Register<"fcc0">; 243 244 // PC register 245 def PC : Register<"pc">; 246 247 // Hardware register $29 248 def HWR29 : Register<"29">; 249 def HWR29_64 : Register<"29">; 250 251 // Accum registers 252 let SubRegIndices = [sub_lo, sub_hi] in 253 def AC0 : RegisterWithSubRegs<"ac0", [LO, HI]>; 254 def AC1 : Register<"ac1">; 255 def AC2 : Register<"ac2">; 256 def AC3 : Register<"ac3">; 257 258 def DSPCtrl : Register<"dspctrl">; 259} 260 261//===----------------------------------------------------------------------===// 262// Register Classes 263//===----------------------------------------------------------------------===// 264 265class CPURegsClass<list<ValueType> regTypes> : 266 RegisterClass<"Mips", regTypes, 32, (add 267 // Reserved 268 ZERO, AT, 269 // Return Values and Arguments 270 V0, V1, A0, A1, A2, A3, 271 // Not preserved across procedure calls 272 T0, T1, T2, T3, T4, T5, T6, T7, 273 // Callee save 274 S0, S1, S2, S3, S4, S5, S6, S7, 275 // Not preserved across procedure calls 276 T8, T9, 277 // Reserved 278 K0, K1, GP, SP, FP, RA)>; 279 280def CPURegs : CPURegsClass<[i32]>; 281def DSPRegs : CPURegsClass<[v4i8, v2i16]>; 282 283def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 284// Reserved 285 ZERO_64, AT_64, 286 // Return Values and Arguments 287 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 288 // Not preserved across procedure calls 289 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 290 // Callee save 291 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 292 // Not preserved across procedure calls 293 T8_64, T9_64, 294 // Reserved 295 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 296 297def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 298 // Return Values and Arguments 299 V0, V1, A0, A1, A2, A3, 300 // Callee save 301 S0, S1)>; 302 303def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>; 304 305def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>; 306 307// 64bit fp: 308// * FGR64 - 32 64-bit registers 309// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 310// 311// 32bit fp: 312// * FGR32 - 16 32-bit even registers 313// * FGR32 - 32 32-bit registers (single float only mode) 314def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 315 316def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 317 // Return Values and Arguments 318 D0, D1, 319 // Not preserved across procedure calls 320 D2, D3, D4, D5, 321 // Return Values and Arguments 322 D6, D7, 323 // Not preserved across procedure calls 324 D8, D9, 325 // Callee save 326 D10, D11, D12, D13, D14, D15)>; 327 328def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 329 330// Condition Register for floating point operations 331def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>; 332 333// Hi/Lo Registers 334def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; 335def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>; 336 337// Hardware registers 338def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; 339def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>; 340 341// Accumulator Registers 342def ACRegs : RegisterClass<"Mips", [i64], 64, (sequence "AC%u", 0, 3)>; 343