1/* Disassemble ADI Blackfin Instructions. 2 Copyright 2005 Free Software Foundation, Inc. 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 2 of the License, or 7 (at your option) any later version. 8 9 This program is distributed in the hope that it will be useful, 10 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 GNU General Public License for more details. 13 14 You should have received a copy of the GNU General Public License 15 along with this program; if not, write to the Free Software 16 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 17 MA 02110-1301, USA. */ 18 19#include <stdio.h> 20#include <stdlib.h> 21#include <string.h> 22 23#include "opcode/bfin.h" 24 25#define M_S2RND 1 26#define M_T 2 27#define M_W32 3 28#define M_FU 4 29#define M_TFU 6 30#define M_IS 8 31#define M_ISS2 9 32#define M_IH 11 33#define M_IU 12 34 35#ifndef PRINTF 36#define PRINTF printf 37#endif 38 39#ifndef EXIT 40#define EXIT exit 41#endif 42 43typedef long TIword; 44 45#define HOST_LONG_WORD_SIZE (sizeof (long) * 8) 46#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p)) 47#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n))) 48#define MASKBITS(val, bits) (val & ((1 << bits) - 1)) 49 50#include "dis-asm.h" 51 52typedef enum 53{ 54 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4, 55 c_imm4, c_uimm4s4, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_uimm5, c_imm6, 56 c_imm7, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10, 57 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4, 58 c_uimm16, c_pcrel24, 59} const_forms_t; 60 61static struct 62{ 63 char *name; 64 int nbits; 65 char reloc; 66 char issigned; 67 char pcrel; 68 char scale; 69 char offset; 70 char negative; 71 char positive; 72} constant_formats[] = 73{ 74 { "0", 0, 0, 1, 0, 0, 0, 0, 0}, 75 { "1", 0, 0, 1, 0, 0, 0, 0, 0}, 76 { "4", 0, 0, 1, 0, 0, 0, 0, 0}, 77 { "2", 0, 0, 1, 0, 0, 0, 0, 0}, 78 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0}, 79 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0}, 80 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0}, 81 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0}, 82 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0}, 83 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1}, 84 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0}, 85 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1}, 86 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0}, 87 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0}, 88 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0}, 89 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0}, 90 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0}, 91 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0}, 92 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0}, 93 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0}, 94 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0}, 95 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0}, 96 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0}, 97 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0}, 98 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0}, 99 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0}, 100 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0}, 101 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0}, 102 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0}, 103 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0}, 104 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0}, 105 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0}, 106 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0}, 107 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0} 108}; 109 110int _print_insn_bfin (bfd_vma pc, disassemble_info * outf); 111int print_insn_bfin (bfd_vma pc, disassemble_info * outf); 112 113static char * 114fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf) 115{ 116 static char buf[60]; 117 118 if (constant_formats[cf].reloc) 119 { 120 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits) 121 : x) + constant_formats[cf].offset) << constant_formats[cf].scale); 122 if (constant_formats[cf].pcrel) 123 ea += pc; 124 125 outf->print_address_func (ea, outf); 126 return ""; 127 } 128 129 /* Negative constants have an implied sign bit. */ 130 if (constant_formats[cf].negative) 131 { 132 int nb = constant_formats[cf].nbits + 1; 133 134 x = x | (1 << constant_formats[cf].nbits); 135 x = SIGNEXTEND (x, nb); 136 } 137 else 138 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x; 139 140 if (constant_formats[cf].offset) 141 x += constant_formats[cf].offset; 142 143 if (constant_formats[cf].scale) 144 x <<= constant_formats[cf].scale; 145 146 if (constant_formats[cf].issigned && x < 0) 147 sprintf (buf, "%ld", x); 148 else 149 sprintf (buf, "0x%lx", x); 150 151 return buf; 152} 153 154enum machine_registers 155{ 156 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, 157 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, 158 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, 159 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3, 160 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w, 161 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, 162 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, 163 REG_L2, REG_L3, 164 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S, 165 REG_AQ, REG_V, REG_VS, 166 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0, 167 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1, 168 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, 169 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, 170 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, 171 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP, 172 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3, 173 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3, 174 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3, 175 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3, 176 REG_LASTREG, 177}; 178 179enum reg_class 180{ 181 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext, 182 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs, 183 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2, 184 rc_sysregs3, rc_allregs, 185 LIM_REG_CLASSES 186}; 187 188static char *reg_names[] = 189{ 190 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", 191 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", 192 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", 193 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3", 194 "P4", "P5", "SP", "FP", "A0.x", "A1.x", "A0.w", "A1.w", 195 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1", 196 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1", 197 "L2", "L3", 198 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S", 199 "AQ", "V", "VS", 200 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0", 201 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1", 202 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", 203 "RETE", "EMUDAT", 204 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", 205 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", 206 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", 207 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L", 208 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L", 209 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H", 210 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H", 211 "LASTREG", 212 0 213}; 214 215#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......") 216 217/* RL(0..7). */ 218static enum machine_registers decode_dregs_lo[] = 219{ 220 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, 221}; 222 223#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7]) 224 225/* RH(0..7). */ 226static enum machine_registers decode_dregs_hi[] = 227{ 228 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, 229}; 230 231#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7]) 232 233/* R(0..7). */ 234static enum machine_registers decode_dregs[] = 235{ 236 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, 237}; 238 239#define dregs(x) REGNAME (decode_dregs[(x) & 7]) 240 241/* R BYTE(0..7). */ 242static enum machine_registers decode_dregs_byte[] = 243{ 244 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7, 245}; 246 247#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7]) 248#define dregs_pair(x) REGNAME (decode_dregs_pair[(x) & 7]) 249 250/* P(0..5) SP FP. */ 251static enum machine_registers decode_pregs[] = 252{ 253 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, 254}; 255 256#define pregs(x) REGNAME (decode_pregs[(x) & 7]) 257#define spfp(x) REGNAME (decode_spfp[(x) & 1]) 258#define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x]) 259#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1]) 260#define accum_word(x) REGNAME (decode_accum_word[(x) & 1]) 261#define accum(x) REGNAME (decode_accum[(x) & 1]) 262 263/* I(0..3). */ 264static enum machine_registers decode_iregs[] = 265{ 266 REG_I0, REG_I1, REG_I2, REG_I3, 267}; 268 269#define iregs(x) REGNAME (decode_iregs[(x) & 3]) 270 271/* M(0..3). */ 272static enum machine_registers decode_mregs[] = 273{ 274 REG_M0, REG_M1, REG_M2, REG_M3, 275}; 276 277#define mregs(x) REGNAME (decode_mregs[(x) & 3]) 278#define bregs(x) REGNAME (decode_bregs[(x) & 3]) 279#define lregs(x) REGNAME (decode_lregs[(x) & 3]) 280 281/* dregs pregs. */ 282static enum machine_registers decode_dpregs[] = 283{ 284 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, 285 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, 286}; 287 288#define dpregs(x) REGNAME (decode_dpregs[(x) & 15]) 289 290/* [dregs pregs]. */ 291static enum machine_registers decode_gregs[] = 292{ 293 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, 294 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, 295}; 296 297#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x]) 298 299/* [dregs pregs (iregs mregs) (bregs lregs)]. */ 300static enum machine_registers decode_regs[] = 301{ 302 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, 303 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, 304 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, 305 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, 306}; 307 308#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x]) 309 310/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */ 311static enum machine_registers decode_regs_lo[] = 312{ 313 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, 314 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, 315 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3, 316 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3, 317}; 318 319#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x]) 320/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */ 321static enum machine_registers decode_regs_hi[] = 322{ 323 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, 324 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP, 325 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_LH2, REG_MH3, 326 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3, 327}; 328 329#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x]) 330 331static enum machine_registers decode_statbits[] = 332{ 333 REG_AZ, REG_AN, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG, 334 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG, 335 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, 336 REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, 337}; 338 339#define statbits(x) REGNAME (decode_statbits[(x) & 31]) 340#define ignore_bits(x) REGNAME (decode_ignore_bits[(x) & 7]) 341#define ccstat(x) REGNAME (decode_ccstat[(x) & 0]) 342 343/* LC0 LC1. */ 344static enum machine_registers decode_counters[] = 345{ 346 REG_LC0, REG_LC1, 347}; 348 349#define counters(x) REGNAME (decode_counters[(x) & 1]) 350#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7]) 351 352/* [dregs pregs (iregs mregs) (bregs lregs) 353 dregs2_sysregs1 open sysregs2 sysregs3]. */ 354static enum machine_registers decode_allregs[] = 355{ 356 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, 357 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, 358 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, 359 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, 360 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS, 361 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, 362 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, 363 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_LASTREG, 364}; 365 366#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x]) 367#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf) 368#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf) 369#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf) 370#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf) 371#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf) 372#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf) 373#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf) 374#define rimm16(x) fmtconst (c_rimm16, x, 0, outf) 375#define huimm16(x) fmtconst (c_huimm16, x, 0, outf) 376#define imm16(x) fmtconst (c_imm16, x, 0, outf) 377#define uimm2(x) fmtconst (c_uimm2, x, 0, outf) 378#define uimm3(x) fmtconst (c_uimm3, x, 0, outf) 379#define luimm16(x) fmtconst (c_luimm16, x, 0, outf) 380#define uimm4(x) fmtconst (c_uimm4, x, 0, outf) 381#define uimm5(x) fmtconst (c_uimm5, x, 0, outf) 382#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf) 383#define uimm8(x) fmtconst (c_uimm8, x, 0, outf) 384#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf) 385#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf) 386#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf) 387#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf) 388#define imm3(x) fmtconst (c_imm3, x, 0, outf) 389#define imm4(x) fmtconst (c_imm4, x, 0, outf) 390#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf) 391#define imm5(x) fmtconst (c_imm5, x, 0, outf) 392#define imm6(x) fmtconst (c_imm6, x, 0, outf) 393#define imm7(x) fmtconst (c_imm7, x, 0, outf) 394#define imm8(x) fmtconst (c_imm8, x, 0, outf) 395#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf) 396#define uimm16(x) fmtconst (c_uimm16, x, 0, outf) 397 398/* (arch.pm)arch_disassembler_functions. */ 399#ifndef OUTS 400#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, txt) :0) :0) 401#endif 402 403static void 404amod0 (int s0, int x0, disassemble_info *outf) 405{ 406 if (s0 == 1 && x0 == 0) 407 OUTS (outf, "(S)"); 408 else if (s0 == 0 && x0 == 1) 409 OUTS (outf, "(CO)"); 410 else if (s0 == 1 && x0 == 1) 411 OUTS (outf, "(SCO)"); 412} 413 414static void 415amod1 (int s0, int x0, disassemble_info *outf) 416{ 417 if (s0 == 0 && x0 == 0) 418 OUTS (outf, "(NS)"); 419 else if (s0 == 1 && x0 == 0) 420 OUTS (outf, "(S)"); 421} 422 423static void 424amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf) 425{ 426 if (s0 == 1 && x0 == 0 && aop0 == 0) 427 OUTS (outf, "(S)"); 428 else if (s0 == 0 && x0 == 1 && aop0 == 0) 429 OUTS (outf, "(CO)"); 430 else if (s0 == 1 && x0 == 1 && aop0 == 0) 431 OUTS (outf, "(SCO)"); 432 else if (s0 == 0 && x0 == 0 && aop0 == 2) 433 OUTS (outf, "(ASR)"); 434 else if (s0 == 1 && x0 == 0 && aop0 == 2) 435 OUTS (outf, "(S,ASR)"); 436 else if (s0 == 0 && x0 == 1 && aop0 == 2) 437 OUTS (outf, "(CO,ASR)"); 438 else if (s0 == 1 && x0 == 1 && aop0 == 2) 439 OUTS (outf, "(SCO,ASR)"); 440 else if (s0 == 0 && x0 == 0 && aop0 == 3) 441 OUTS (outf, "(ASL)"); 442 else if (s0 == 1 && x0 == 0 && aop0 == 3) 443 OUTS (outf, "(S,ASL)"); 444 else if (s0 == 0 && x0 == 1 && aop0 == 3) 445 OUTS (outf, "(CO,ASL)"); 446 else if (s0 == 1 && x0 == 1 && aop0 == 3) 447 OUTS (outf, "(SCO,ASL)"); 448} 449 450static void 451searchmod (int r0, disassemble_info *outf) 452{ 453 if (r0 == 0) 454 OUTS (outf, "GT"); 455 else if (r0 == 1) 456 OUTS (outf, "GE"); 457 else if (r0 == 2) 458 OUTS (outf, "LT"); 459 else if (r0 == 3) 460 OUTS (outf, "LE"); 461} 462 463static void 464aligndir (int r0, disassemble_info *outf) 465{ 466 if (r0 == 1) 467 OUTS (outf, "(R)"); 468} 469 470static int 471decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf) 472{ 473 char *s0, *s1; 474 475 if (h0) 476 s0 = dregs_hi (src0); 477 else 478 s0 = dregs_lo (src0); 479 480 if (h1) 481 s1 = dregs_hi (src1); 482 else 483 s1 = dregs_lo (src1); 484 485 OUTS (outf, s0); 486 OUTS (outf, " * "); 487 OUTS (outf, s1); 488 return 0; 489} 490 491static int 492decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf) 493{ 494 char *a; 495 char *sop = "<unknown op>"; 496 497 if (which) 498 a = "a1"; 499 else 500 a = "a0"; 501 502 if (op == 3) 503 { 504 OUTS (outf, a); 505 return 0; 506 } 507 508 switch (op) 509 { 510 case 0: sop = "="; break; 511 case 1: sop = "+="; break; 512 case 2: sop = "-="; break; 513 default: break; 514 } 515 516 OUTS (outf, a); 517 OUTS (outf, " "); 518 OUTS (outf, sop); 519 OUTS (outf, " "); 520 decode_multfunc (h0, h1, src0, src1, outf); 521 522 return 0; 523} 524 525static void 526decode_optmode (int mod, int MM, disassemble_info *outf) 527{ 528 if (mod == 0 && MM == 0) 529 return; 530 531 OUTS (outf, " ("); 532 533 if (MM && !mod) 534 { 535 OUTS (outf, "M)"); 536 return; 537 } 538 539 if (MM) 540 OUTS (outf, "M, "); 541 542 if (mod == M_S2RND) 543 OUTS (outf, "S2RND"); 544 else if (mod == M_T) 545 OUTS (outf, "T"); 546 else if (mod == M_W32) 547 OUTS (outf, "W32"); 548 else if (mod == M_FU) 549 OUTS (outf, "FU"); 550 else if (mod == M_TFU) 551 OUTS (outf, "TFU"); 552 else if (mod == M_IS) 553 OUTS (outf, "IS"); 554 else if (mod == M_ISS2) 555 OUTS (outf, "ISS2"); 556 else if (mod == M_IH) 557 OUTS (outf, "IH"); 558 else if (mod == M_IU) 559 OUTS (outf, "IU"); 560 else 561 abort (); 562 563 OUTS (outf, ")"); 564} 565 566static int 567decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf) 568{ 569 /* ProgCtrl 570 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 571 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| 572 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 573 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask); 574 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask); 575 576 if (prgfunc == 0 && poprnd == 0) 577 OUTS (outf, "NOP"); 578 else if (prgfunc == 1 && poprnd == 0) 579 OUTS (outf, "RTS"); 580 else if (prgfunc == 1 && poprnd == 1) 581 OUTS (outf, "RTI"); 582 else if (prgfunc == 1 && poprnd == 2) 583 OUTS (outf, "RTX"); 584 else if (prgfunc == 1 && poprnd == 3) 585 OUTS (outf, "RTN"); 586 else if (prgfunc == 1 && poprnd == 4) 587 OUTS (outf, "RTE"); 588 else if (prgfunc == 2 && poprnd == 0) 589 OUTS (outf, "IDLE"); 590 else if (prgfunc == 2 && poprnd == 3) 591 OUTS (outf, "CSYNC"); 592 else if (prgfunc == 2 && poprnd == 4) 593 OUTS (outf, "SSYNC"); 594 else if (prgfunc == 2 && poprnd == 5) 595 OUTS (outf, "EMUEXCPT"); 596 else if (prgfunc == 3) 597 { 598 OUTS (outf, "CLI "); 599 OUTS (outf, dregs (poprnd)); 600 } 601 else if (prgfunc == 4) 602 { 603 OUTS (outf, "STI "); 604 OUTS (outf, dregs (poprnd)); 605 } 606 else if (prgfunc == 5) 607 { 608 OUTS (outf, "JUMP ("); 609 OUTS (outf, pregs (poprnd)); 610 OUTS (outf, ")"); 611 } 612 else if (prgfunc == 6) 613 { 614 OUTS (outf, "CALL ("); 615 OUTS (outf, pregs (poprnd)); 616 OUTS (outf, ")"); 617 } 618 else if (prgfunc == 7) 619 { 620 OUTS (outf, "CALL (PC+"); 621 OUTS (outf, pregs (poprnd)); 622 OUTS (outf, ")"); 623 } 624 else if (prgfunc == 8) 625 { 626 OUTS (outf, "JUMP (PC+"); 627 OUTS (outf, pregs (poprnd)); 628 OUTS (outf, ")"); 629 } 630 else if (prgfunc == 9) 631 { 632 OUTS (outf, "RAISE "); 633 OUTS (outf, uimm4 (poprnd)); 634 } 635 else if (prgfunc == 10) 636 { 637 OUTS (outf, "EXCPT "); 638 OUTS (outf, uimm4 (poprnd)); 639 } 640 else if (prgfunc == 11) 641 { 642 OUTS (outf, "TESTSET ("); 643 OUTS (outf, pregs (poprnd)); 644 OUTS (outf, ")"); 645 } 646 else 647 return 0; 648 return 2; 649} 650 651static int 652decode_CaCTRL_0 (TIword iw0, disassemble_info *outf) 653{ 654 /* CaCTRL 655 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 656 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| 657 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 658 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask); 659 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask); 660 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask); 661 662 if (a == 0 && op == 0) 663 { 664 OUTS (outf, "PREFETCH["); 665 OUTS (outf, pregs (reg)); 666 OUTS (outf, "]"); 667 } 668 else if (a == 0 && op == 1) 669 { 670 OUTS (outf, "FLUSHINV["); 671 OUTS (outf, pregs (reg)); 672 OUTS (outf, "]"); 673 } 674 else if (a == 0 && op == 2) 675 { 676 OUTS (outf, "FLUSH["); 677 OUTS (outf, pregs (reg)); 678 OUTS (outf, "]"); 679 } 680 else if (a == 0 && op == 3) 681 { 682 OUTS (outf, "IFLUSH["); 683 OUTS (outf, pregs (reg)); 684 OUTS (outf, "]"); 685 } 686 else if (a == 1 && op == 0) 687 { 688 OUTS (outf, "PREFETCH["); 689 OUTS (outf, pregs (reg)); 690 OUTS (outf, "++]"); 691 } 692 else if (a == 1 && op == 1) 693 { 694 OUTS (outf, "FLUSHINV["); 695 OUTS (outf, pregs (reg)); 696 OUTS (outf, "++]"); 697 } 698 else if (a == 1 && op == 2) 699 { 700 OUTS (outf, "FLUSH["); 701 OUTS (outf, pregs (reg)); 702 OUTS (outf, "++]"); 703 } 704 else if (a == 1 && op == 3) 705 { 706 OUTS (outf, "IFLUSH["); 707 OUTS (outf, pregs (reg)); 708 OUTS (outf, "++]"); 709 } 710 else 711 return 0; 712 return 2; 713} 714 715static int 716decode_PushPopReg_0 (TIword iw0, disassemble_info *outf) 717{ 718 /* PushPopReg 719 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 720 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| 721 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 722 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask); 723 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask); 724 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask); 725 726 if (W == 0) 727 { 728 OUTS (outf, allregs (reg, grp)); 729 OUTS (outf, " = [SP++]"); 730 } 731 else if (W == 1) 732 { 733 OUTS (outf, "[--SP] = "); 734 OUTS (outf, allregs (reg, grp)); 735 } 736 else 737 return 0; 738 return 2; 739} 740 741static int 742decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf) 743{ 744 /* PushPopMultiple 745 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 746 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| 747 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 748 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask); 749 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask); 750 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask); 751 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask); 752 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask); 753 char ps[5], ds[5]; 754 755 sprintf (ps, "%d", pr); 756 sprintf (ds, "%d", dr); 757 758 if (W == 1 && d == 1 && p == 1) 759 { 760 OUTS (outf, "[--SP] = (R7:"); 761 OUTS (outf, ds); 762 OUTS (outf, ", P5:"); 763 OUTS (outf, ps); 764 OUTS (outf, ")"); 765 } 766 else if (W == 1 && d == 1 && p == 0) 767 { 768 OUTS (outf, "[--SP] = (R7:"); 769 OUTS (outf, ds); 770 OUTS (outf, ")"); 771 } 772 else if (W == 1 && d == 0 && p == 1) 773 { 774 OUTS (outf, "[--SP] = (P5:"); 775 OUTS (outf, ps); 776 OUTS (outf, ")"); 777 } 778 else if (W == 0 && d == 1 && p == 1) 779 { 780 OUTS (outf, "(R7:"); 781 OUTS (outf, ds); 782 OUTS (outf, ", P5:"); 783 OUTS (outf, ps); 784 OUTS (outf, ") = [SP++]"); 785 } 786 else if (W == 0 && d == 1 && p == 0) 787 { 788 OUTS (outf, "(R7:"); 789 OUTS (outf, ds); 790 OUTS (outf, ") = [SP++]"); 791 } 792 else if (W == 0 && d == 0 && p == 1) 793 { 794 OUTS (outf, "(P5:"); 795 OUTS (outf, ps); 796 OUTS (outf, ") = [SP++]"); 797 } 798 else 799 return 0; 800 return 2; 801} 802 803static int 804decode_ccMV_0 (TIword iw0, disassemble_info *outf) 805{ 806 /* ccMV 807 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 808 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| 809 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 810 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask); 811 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask); 812 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask); 813 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask); 814 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask); 815 816 if (T == 1) 817 { 818 OUTS (outf, "IF CC "); 819 OUTS (outf, gregs (dst, d)); 820 OUTS (outf, " = "); 821 OUTS (outf, gregs (src, s)); 822 } 823 else if (T == 0) 824 { 825 OUTS (outf, "IF ! CC "); 826 OUTS (outf, gregs (dst, d)); 827 OUTS (outf, " = "); 828 OUTS (outf, gregs (src, s)); 829 } 830 else 831 return 0; 832 return 2; 833} 834 835static int 836decode_CCflag_0 (TIword iw0, disassemble_info *outf) 837{ 838 /* CCflag 839 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 840 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| 841 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 842 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask); 843 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask); 844 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask); 845 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask); 846 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask); 847 848 if (opc == 0 && I == 0 && G == 0) 849 { 850 OUTS (outf, "CC="); 851 OUTS (outf, dregs (x)); 852 OUTS (outf, "=="); 853 OUTS (outf, dregs (y)); 854 } 855 else if (opc == 1 && I == 0 && G == 0) 856 { 857 OUTS (outf, "CC="); 858 OUTS (outf, dregs (x)); 859 OUTS (outf, "<"); 860 OUTS (outf, dregs (y)); 861 } 862 else if (opc == 2 && I == 0 && G == 0) 863 { 864 OUTS (outf, "CC="); 865 OUTS (outf, dregs (x)); 866 OUTS (outf, "<="); 867 OUTS (outf, dregs (y)); 868 } 869 else if (opc == 3 && I == 0 && G == 0) 870 { 871 OUTS (outf, "CC="); 872 OUTS (outf, dregs (x)); 873 OUTS (outf, "<"); 874 OUTS (outf, dregs (y)); 875 OUTS (outf, "(IU)"); 876 } 877 else if (opc == 4 && I == 0 && G == 0) 878 { 879 OUTS (outf, "CC="); 880 OUTS (outf, dregs (x)); 881 OUTS (outf, "<="); 882 OUTS (outf, dregs (y)); 883 OUTS (outf, "(IU)"); 884 } 885 else if (opc == 0 && I == 1 && G == 0) 886 { 887 OUTS (outf, "CC="); 888 OUTS (outf, dregs (x)); 889 OUTS (outf, "=="); 890 OUTS (outf, imm3 (y)); 891 } 892 else if (opc == 1 && I == 1 && G == 0) 893 { 894 OUTS (outf, "CC="); 895 OUTS (outf, dregs (x)); 896 OUTS (outf, "<"); 897 OUTS (outf, imm3 (y)); 898 } 899 else if (opc == 2 && I == 1 && G == 0) 900 { 901 OUTS (outf, "CC="); 902 OUTS (outf, dregs (x)); 903 OUTS (outf, "<="); 904 OUTS (outf, imm3 (y)); 905 } 906 else if (opc == 3 && I == 1 && G == 0) 907 { 908 OUTS (outf, "CC="); 909 OUTS (outf, dregs (x)); 910 OUTS (outf, "<"); 911 OUTS (outf, uimm3 (y)); 912 OUTS (outf, "(IU)"); 913 } 914 else if (opc == 4 && I == 1 && G == 0) 915 { 916 OUTS (outf, "CC="); 917 OUTS (outf, dregs (x)); 918 OUTS (outf, "<="); 919 OUTS (outf, uimm3 (y)); 920 OUTS (outf, "(IU)"); 921 } 922 else if (opc == 0 && I == 0 && G == 1) 923 { 924 OUTS (outf, "CC="); 925 OUTS (outf, pregs (x)); 926 OUTS (outf, "=="); 927 OUTS (outf, pregs (y)); 928 } 929 else if (opc == 1 && I == 0 && G == 1) 930 { 931 OUTS (outf, "CC="); 932 OUTS (outf, pregs (x)); 933 OUTS (outf, "<"); 934 OUTS (outf, pregs (y)); 935 } 936 else if (opc == 2 && I == 0 && G == 1) 937 { 938 OUTS (outf, "CC="); 939 OUTS (outf, pregs (x)); 940 OUTS (outf, "<="); 941 OUTS (outf, pregs (y)); 942 } 943 else if (opc == 3 && I == 0 && G == 1) 944 { 945 OUTS (outf, "CC="); 946 OUTS (outf, pregs (x)); 947 OUTS (outf, "<"); 948 OUTS (outf, pregs (y)); 949 OUTS (outf, "(IU)"); 950 } 951 else if (opc == 4 && I == 0 && G == 1) 952 { 953 OUTS (outf, "CC="); 954 OUTS (outf, pregs (x)); 955 OUTS (outf, "<="); 956 OUTS (outf, pregs (y)); 957 OUTS (outf, "(IU)"); 958 } 959 else if (opc == 0 && I == 1 && G == 1) 960 { 961 OUTS (outf, "CC="); 962 OUTS (outf, pregs (x)); 963 OUTS (outf, "=="); 964 OUTS (outf, imm3 (y)); 965 } 966 else if (opc == 1 && I == 1 && G == 1) 967 { 968 OUTS (outf, "CC="); 969 OUTS (outf, pregs (x)); 970 OUTS (outf, "<"); 971 OUTS (outf, imm3 (y)); 972 } 973 else if (opc == 2 && I == 1 && G == 1) 974 { 975 OUTS (outf, "CC="); 976 OUTS (outf, pregs (x)); 977 OUTS (outf, "<="); 978 OUTS (outf, imm3 (y)); 979 } 980 else if (opc == 3 && I == 1 && G == 1) 981 { 982 OUTS (outf, "CC="); 983 OUTS (outf, pregs (x)); 984 OUTS (outf, "<"); 985 OUTS (outf, uimm3 (y)); 986 OUTS (outf, "(IU)"); 987 } 988 else if (opc == 4 && I == 1 && G == 1) 989 { 990 OUTS (outf, "CC="); 991 OUTS (outf, pregs (x)); 992 OUTS (outf, "<="); 993 OUTS (outf, uimm3 (y)); 994 OUTS (outf, "(IU)"); 995 } 996 else if (opc == 5 && I == 0 && G == 0) 997 OUTS (outf, "CC=A0==A1"); 998 999 else if (opc == 6 && I == 0 && G == 0) 1000 OUTS (outf, "CC=A0<A1"); 1001 1002 else if (opc == 7 && I == 0 && G == 0) 1003 OUTS (outf, "CC=A0<=A1"); 1004 1005 else 1006 return 0; 1007 return 2; 1008} 1009 1010static int 1011decode_CC2dreg_0 (TIword iw0, disassemble_info *outf) 1012{ 1013 /* CC2dreg 1014 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1015 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| 1016 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1017 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask); 1018 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask); 1019 1020 if (op == 0) 1021 { 1022 OUTS (outf, dregs (reg)); 1023 OUTS (outf, "=CC"); 1024 } 1025 else if (op == 1) 1026 { 1027 OUTS (outf, "CC="); 1028 OUTS (outf, dregs (reg)); 1029 } 1030 else if (op == 3) 1031 OUTS (outf, "CC=!CC"); 1032 else 1033 return 0; 1034 1035 return 2; 1036} 1037 1038static int 1039decode_CC2stat_0 (TIword iw0, disassemble_info *outf) 1040{ 1041 /* CC2stat 1042 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1043 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| 1044 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1045 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask); 1046 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask); 1047 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask); 1048 1049 if (op == 0 && D == 0) 1050 { 1051 OUTS (outf, "CC = "); 1052 OUTS (outf, statbits (cbit)); 1053 } 1054 else if (op == 1 && D == 0) 1055 { 1056 OUTS (outf, "CC|="); 1057 OUTS (outf, statbits (cbit)); 1058 } 1059 else if (op == 2 && D == 0) 1060 { 1061 OUTS (outf, "CC&="); 1062 OUTS (outf, statbits (cbit)); 1063 } 1064 else if (op == 3 && D == 0) 1065 { 1066 OUTS (outf, "CC^="); 1067 OUTS (outf, statbits (cbit)); 1068 } 1069 else if (op == 0 && D == 1) 1070 { 1071 OUTS (outf, statbits (cbit)); 1072 OUTS (outf, "=CC"); 1073 } 1074 else if (op == 1 && D == 1) 1075 { 1076 OUTS (outf, statbits (cbit)); 1077 OUTS (outf, "|=CC"); 1078 } 1079 else if (op == 2 && D == 1) 1080 { 1081 OUTS (outf, statbits (cbit)); 1082 OUTS (outf, "&=CC"); 1083 } 1084 else if (op == 3 && D == 1) 1085 { 1086 OUTS (outf, statbits (cbit)); 1087 OUTS (outf, "^=CC"); 1088 } 1089 else 1090 return 0; 1091 1092 return 2; 1093} 1094 1095static int 1096decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf) 1097{ 1098 /* BRCC 1099 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1100 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| 1101 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1102 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask); 1103 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask); 1104 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask); 1105 1106 if (T == 1 && B == 1) 1107 { 1108 OUTS (outf, "IF CC JUMP "); 1109 OUTS (outf, pcrel10 (offset)); 1110 OUTS (outf, "(BP)"); 1111 } 1112 else if (T == 0 && B == 1) 1113 { 1114 OUTS (outf, "IF ! CC JUMP "); 1115 OUTS (outf, pcrel10 (offset)); 1116 OUTS (outf, "(BP)"); 1117 } 1118 else if (T == 1) 1119 { 1120 OUTS (outf, "IF CC JUMP "); 1121 OUTS (outf, pcrel10 (offset)); 1122 } 1123 else if (T == 0) 1124 { 1125 OUTS (outf, "IF ! CC JUMP "); 1126 OUTS (outf, pcrel10 (offset)); 1127 } 1128 else 1129 return 0; 1130 1131 return 2; 1132} 1133 1134static int 1135decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf) 1136{ 1137 /* UJUMP 1138 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1139 | 0 | 0 | 1 | 0 |.offset........................................| 1140 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1141 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask); 1142 1143 OUTS (outf, "JUMP.S "); 1144 OUTS (outf, pcrel12 (offset)); 1145 return 2; 1146} 1147 1148static int 1149decode_REGMV_0 (TIword iw0, disassemble_info *outf) 1150{ 1151 /* REGMV 1152 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1153 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| 1154 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1155 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask); 1156 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask); 1157 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask); 1158 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask); 1159 1160 OUTS (outf, allregs (dst, gd)); 1161 OUTS (outf, "="); 1162 OUTS (outf, allregs (src, gs)); 1163 return 2; 1164} 1165 1166static int 1167decode_ALU2op_0 (TIword iw0, disassemble_info *outf) 1168{ 1169 /* ALU2op 1170 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1171 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| 1172 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1173 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask); 1174 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask); 1175 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask); 1176 1177 if (opc == 0) 1178 { 1179 OUTS (outf, dregs (dst)); 1180 OUTS (outf, ">>>="); 1181 OUTS (outf, dregs (src)); 1182 } 1183 else if (opc == 1) 1184 { 1185 OUTS (outf, dregs (dst)); 1186 OUTS (outf, ">>="); 1187 OUTS (outf, dregs (src)); 1188 } 1189 else if (opc == 2) 1190 { 1191 OUTS (outf, dregs (dst)); 1192 OUTS (outf, "<<="); 1193 OUTS (outf, dregs (src)); 1194 } 1195 else if (opc == 3) 1196 { 1197 OUTS (outf, dregs (dst)); 1198 OUTS (outf, "*="); 1199 OUTS (outf, dregs (src)); 1200 } 1201 else if (opc == 4) 1202 { 1203 OUTS (outf, dregs (dst)); 1204 OUTS (outf, "=("); 1205 OUTS (outf, dregs (dst)); 1206 OUTS (outf, "+"); 1207 OUTS (outf, dregs (src)); 1208 OUTS (outf, ")<<1"); 1209 } 1210 else if (opc == 5) 1211 { 1212 OUTS (outf, dregs (dst)); 1213 OUTS (outf, "=("); 1214 OUTS (outf, dregs (dst)); 1215 OUTS (outf, "+"); 1216 OUTS (outf, dregs (src)); 1217 OUTS (outf, ")<<2"); 1218 } 1219 else if (opc == 8) 1220 { 1221 OUTS (outf, "DIVQ("); 1222 OUTS (outf, dregs (dst)); 1223 OUTS (outf, ","); 1224 OUTS (outf, dregs (src)); 1225 OUTS (outf, ")"); 1226 } 1227 else if (opc == 9) 1228 { 1229 OUTS (outf, "DIVS("); 1230 OUTS (outf, dregs (dst)); 1231 OUTS (outf, ","); 1232 OUTS (outf, dregs (src)); 1233 OUTS (outf, ")"); 1234 } 1235 else if (opc == 10) 1236 { 1237 OUTS (outf, dregs (dst)); 1238 OUTS (outf, "="); 1239 OUTS (outf, dregs_lo (src)); 1240 OUTS (outf, "(X)"); 1241 } 1242 else if (opc == 11) 1243 { 1244 OUTS (outf, dregs (dst)); 1245 OUTS (outf, "="); 1246 OUTS (outf, dregs_lo (src)); 1247 OUTS (outf, "(Z)"); 1248 } 1249 else if (opc == 12) 1250 { 1251 OUTS (outf, dregs (dst)); 1252 OUTS (outf, "="); 1253 OUTS (outf, dregs_byte (src)); 1254 OUTS (outf, "(X)"); 1255 } 1256 else if (opc == 13) 1257 { 1258 OUTS (outf, dregs (dst)); 1259 OUTS (outf, "="); 1260 OUTS (outf, dregs_byte (src)); 1261 OUTS (outf, "(Z)"); 1262 } 1263 else if (opc == 14) 1264 { 1265 OUTS (outf, dregs (dst)); 1266 OUTS (outf, "=-"); 1267 OUTS (outf, dregs (src)); 1268 } 1269 else if (opc == 15) 1270 { 1271 OUTS (outf, dregs (dst)); 1272 OUTS (outf, "=~"); 1273 OUTS (outf, dregs (src)); 1274 } 1275 else 1276 return 0; 1277 1278 return 2; 1279} 1280 1281static int 1282decode_PTR2op_0 (TIword iw0, disassemble_info *outf) 1283{ 1284 /* PTR2op 1285 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1286 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| 1287 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1288 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask); 1289 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask); 1290 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask); 1291 1292 if (opc == 0) 1293 { 1294 OUTS (outf, pregs (dst)); 1295 OUTS (outf, "-="); 1296 OUTS (outf, pregs (src)); 1297 } 1298 else if (opc == 1) 1299 { 1300 OUTS (outf, pregs (dst)); 1301 OUTS (outf, "="); 1302 OUTS (outf, pregs (src)); 1303 OUTS (outf, "<<2"); 1304 } 1305 else if (opc == 3) 1306 { 1307 OUTS (outf, pregs (dst)); 1308 OUTS (outf, "="); 1309 OUTS (outf, pregs (src)); 1310 OUTS (outf, ">>2"); 1311 } 1312 else if (opc == 4) 1313 { 1314 OUTS (outf, pregs (dst)); 1315 OUTS (outf, "="); 1316 OUTS (outf, pregs (src)); 1317 OUTS (outf, ">>1"); 1318 } 1319 else if (opc == 5) 1320 { 1321 OUTS (outf, pregs (dst)); 1322 OUTS (outf, "+="); 1323 OUTS (outf, pregs (src)); 1324 OUTS (outf, "(BREV)"); 1325 } 1326 else if (opc == 6) 1327 { 1328 OUTS (outf, pregs (dst)); 1329 OUTS (outf, "=("); 1330 OUTS (outf, pregs (dst)); 1331 OUTS (outf, "+"); 1332 OUTS (outf, pregs (src)); 1333 OUTS (outf, ")<<1"); 1334 } 1335 else if (opc == 7) 1336 { 1337 OUTS (outf, pregs (dst)); 1338 OUTS (outf, "=("); 1339 OUTS (outf, pregs (dst)); 1340 OUTS (outf, "+"); 1341 OUTS (outf, pregs (src)); 1342 OUTS (outf, ")<<2"); 1343 } 1344 else 1345 return 0; 1346 1347 return 2; 1348} 1349 1350static int 1351decode_LOGI2op_0 (TIword iw0, disassemble_info *outf) 1352{ 1353 /* LOGI2op 1354 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1355 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| 1356 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1357 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask); 1358 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask); 1359 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask); 1360 1361 if (opc == 0) 1362 { 1363 OUTS (outf, "CC = ! BITTST ("); 1364 OUTS (outf, dregs (dst)); 1365 OUTS (outf, ","); 1366 OUTS (outf, uimm5 (src)); 1367 OUTS (outf, ")"); 1368 } 1369 else if (opc == 1) 1370 { 1371 OUTS (outf, "CC = BITTST ("); 1372 OUTS (outf, dregs (dst)); 1373 OUTS (outf, ","); 1374 OUTS (outf, uimm5 (src)); 1375 OUTS (outf, ")"); 1376 } 1377 else if (opc == 2) 1378 { 1379 OUTS (outf, "BITSET ("); 1380 OUTS (outf, dregs (dst)); 1381 OUTS (outf, ","); 1382 OUTS (outf, uimm5 (src)); 1383 OUTS (outf, ")"); 1384 } 1385 else if (opc == 3) 1386 { 1387 OUTS (outf, "BITTGL ("); 1388 OUTS (outf, dregs (dst)); 1389 OUTS (outf, ","); 1390 OUTS (outf, uimm5 (src)); 1391 OUTS (outf, ")"); 1392 } 1393 else if (opc == 4) 1394 { 1395 OUTS (outf, "BITCLR ("); 1396 OUTS (outf, dregs (dst)); 1397 OUTS (outf, ","); 1398 OUTS (outf, uimm5 (src)); 1399 OUTS (outf, ")"); 1400 } 1401 else if (opc == 5) 1402 { 1403 OUTS (outf, dregs (dst)); 1404 OUTS (outf, ">>>="); 1405 OUTS (outf, uimm5 (src)); 1406 } 1407 else if (opc == 6) 1408 { 1409 OUTS (outf, dregs (dst)); 1410 OUTS (outf, ">>="); 1411 OUTS (outf, uimm5 (src)); 1412 } 1413 else if (opc == 7) 1414 { 1415 OUTS (outf, dregs (dst)); 1416 OUTS (outf, "<<="); 1417 OUTS (outf, uimm5 (src)); 1418 } 1419 else 1420 return 0; 1421 1422 return 2; 1423} 1424 1425static int 1426decode_COMP3op_0 (TIword iw0, disassemble_info *outf) 1427{ 1428 /* COMP3op 1429 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1430 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| 1431 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1432 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask); 1433 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask); 1434 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); 1435 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask); 1436 1437 if (opc == 5 && src1 == src0) 1438 { 1439 OUTS (outf, pregs (dst)); 1440 OUTS (outf, "="); 1441 OUTS (outf, pregs (src0)); 1442 OUTS (outf, "<<1"); 1443 } 1444 else if (opc == 1) 1445 { 1446 OUTS (outf, dregs (dst)); 1447 OUTS (outf, "="); 1448 OUTS (outf, dregs (src0)); 1449 OUTS (outf, "-"); 1450 OUTS (outf, dregs (src1)); 1451 } 1452 else if (opc == 2) 1453 { 1454 OUTS (outf, dregs (dst)); 1455 OUTS (outf, "="); 1456 OUTS (outf, dregs (src0)); 1457 OUTS (outf, "&"); 1458 OUTS (outf, dregs (src1)); 1459 } 1460 else if (opc == 3) 1461 { 1462 OUTS (outf, dregs (dst)); 1463 OUTS (outf, "="); 1464 OUTS (outf, dregs (src0)); 1465 OUTS (outf, "|"); 1466 OUTS (outf, dregs (src1)); 1467 } 1468 else if (opc == 4) 1469 { 1470 OUTS (outf, dregs (dst)); 1471 OUTS (outf, "="); 1472 OUTS (outf, dregs (src0)); 1473 OUTS (outf, "^"); 1474 OUTS (outf, dregs (src1)); 1475 } 1476 else if (opc == 5) 1477 { 1478 OUTS (outf, pregs (dst)); 1479 OUTS (outf, "="); 1480 OUTS (outf, pregs (src0)); 1481 OUTS (outf, "+"); 1482 OUTS (outf, pregs (src1)); 1483 } 1484 else if (opc == 6) 1485 { 1486 OUTS (outf, pregs (dst)); 1487 OUTS (outf, "="); 1488 OUTS (outf, pregs (src0)); 1489 OUTS (outf, "+("); 1490 OUTS (outf, pregs (src1)); 1491 OUTS (outf, "<<1)"); 1492 } 1493 else if (opc == 7) 1494 { 1495 OUTS (outf, pregs (dst)); 1496 OUTS (outf, "="); 1497 OUTS (outf, pregs (src0)); 1498 OUTS (outf, "+("); 1499 OUTS (outf, pregs (src1)); 1500 OUTS (outf, "<<2)"); 1501 } 1502 else if (opc == 0) 1503 { 1504 OUTS (outf, dregs (dst)); 1505 OUTS (outf, "="); 1506 OUTS (outf, dregs (src0)); 1507 OUTS (outf, "+"); 1508 OUTS (outf, dregs (src1)); 1509 } 1510 else 1511 return 0; 1512 1513 return 2; 1514} 1515 1516static int 1517decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf) 1518{ 1519 /* COMPI2opD 1520 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1521 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......| 1522 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1523 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask); 1524 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask); 1525 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask); 1526 1527 if (op == 0) 1528 { 1529 OUTS (outf, dregs (dst)); 1530 OUTS (outf, "="); 1531 OUTS (outf, imm7 (src)); 1532 OUTS (outf, "(x)"); 1533 } 1534 else if (op == 1) 1535 { 1536 OUTS (outf, dregs (dst)); 1537 OUTS (outf, "+="); 1538 OUTS (outf, imm7 (src)); 1539 } 1540 else 1541 return 0; 1542 1543 return 2; 1544} 1545 1546static int 1547decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf) 1548{ 1549 /* COMPI2opP 1550 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1551 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| 1552 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1553 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask); 1554 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask); 1555 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask); 1556 1557 if (op == 0) 1558 { 1559 OUTS (outf, pregs (dst)); 1560 OUTS (outf, "="); 1561 OUTS (outf, imm7 (src)); 1562 } 1563 else if (op == 1) 1564 { 1565 OUTS (outf, pregs (dst)); 1566 OUTS (outf, "+="); 1567 OUTS (outf, imm7 (src)); 1568 } 1569 else 1570 return 0; 1571 1572 return 2; 1573} 1574 1575static int 1576decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf) 1577{ 1578 /* LDSTpmod 1579 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1580 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| 1581 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1582 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask); 1583 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask); 1584 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask); 1585 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask); 1586 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask); 1587 1588 if (aop == 1 && W == 0 && idx == ptr) 1589 { 1590 OUTS (outf, dregs_lo (reg)); 1591 OUTS (outf, "=W["); 1592 OUTS (outf, pregs (ptr)); 1593 OUTS (outf, "]"); 1594 } 1595 else if (aop == 2 && W == 0 && idx == ptr) 1596 { 1597 OUTS (outf, dregs_hi (reg)); 1598 OUTS (outf, "=W["); 1599 OUTS (outf, pregs (ptr)); 1600 OUTS (outf, "]"); 1601 } 1602 else if (aop == 1 && W == 1 && idx == ptr) 1603 { 1604 OUTS (outf, "W["); 1605 OUTS (outf, pregs (ptr)); 1606 OUTS (outf, "]="); 1607 OUTS (outf, dregs_lo (reg)); 1608 } 1609 else if (aop == 2 && W == 1 && idx == ptr) 1610 { 1611 OUTS (outf, "W["); 1612 OUTS (outf, pregs (ptr)); 1613 OUTS (outf, "]="); 1614 OUTS (outf, dregs_hi (reg)); 1615 } 1616 else if (aop == 0 && W == 0) 1617 { 1618 OUTS (outf, dregs (reg)); 1619 OUTS (outf, "=["); 1620 OUTS (outf, pregs (ptr)); 1621 OUTS (outf, "++"); 1622 OUTS (outf, pregs (idx)); 1623 OUTS (outf, "]"); 1624 } 1625 else if (aop == 1 && W == 0) 1626 { 1627 OUTS (outf, dregs_lo (reg)); 1628 OUTS (outf, "=W["); 1629 OUTS (outf, pregs (ptr)); 1630 OUTS (outf, "++"); 1631 OUTS (outf, pregs (idx)); 1632 OUTS (outf, "]"); 1633 } 1634 else if (aop == 2 && W == 0) 1635 { 1636 OUTS (outf, dregs_hi (reg)); 1637 OUTS (outf, "=W["); 1638 OUTS (outf, pregs (ptr)); 1639 OUTS (outf, "++"); 1640 OUTS (outf, pregs (idx)); 1641 OUTS (outf, "]"); 1642 } 1643 else if (aop == 3 && W == 0) 1644 { 1645 OUTS (outf, dregs (reg)); 1646 OUTS (outf, "=W["); 1647 OUTS (outf, pregs (ptr)); 1648 OUTS (outf, "++"); 1649 OUTS (outf, pregs (idx)); 1650 OUTS (outf, "] (Z)"); 1651 } 1652 else if (aop == 3 && W == 1) 1653 { 1654 OUTS (outf, dregs (reg)); 1655 OUTS (outf, "=W["); 1656 OUTS (outf, pregs (ptr)); 1657 OUTS (outf, "++"); 1658 OUTS (outf, pregs (idx)); 1659 OUTS (outf, "](X)"); 1660 } 1661 else if (aop == 0 && W == 1) 1662 { 1663 OUTS (outf, "["); 1664 OUTS (outf, pregs (ptr)); 1665 OUTS (outf, "++"); 1666 OUTS (outf, pregs (idx)); 1667 OUTS (outf, "]="); 1668 OUTS (outf, dregs (reg)); 1669 } 1670 else if (aop == 1 && W == 1) 1671 { 1672 OUTS (outf, "W["); 1673 OUTS (outf, pregs (ptr)); 1674 OUTS (outf, "++"); 1675 OUTS (outf, pregs (idx)); 1676 OUTS (outf, "]="); 1677 OUTS (outf, dregs_lo (reg)); 1678 } 1679 else if (aop == 2 && W == 1) 1680 { 1681 OUTS (outf, "W["); 1682 OUTS (outf, pregs (ptr)); 1683 OUTS (outf, "++"); 1684 OUTS (outf, pregs (idx)); 1685 OUTS (outf, "]="); 1686 OUTS (outf, dregs_hi (reg)); 1687 } 1688 else 1689 return 0; 1690 1691 return 2; 1692} 1693 1694static int 1695decode_dagMODim_0 (TIword iw0, disassemble_info *outf) 1696{ 1697 /* dagMODim 1698 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1699 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| 1700 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1701 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask); 1702 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask); 1703 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask); 1704 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask); 1705 1706 if (op == 0 && br == 1) 1707 { 1708 OUTS (outf, iregs (i)); 1709 OUTS (outf, "+="); 1710 OUTS (outf, mregs (m)); 1711 OUTS (outf, "(BREV)"); 1712 } 1713 else if (op == 0) 1714 { 1715 OUTS (outf, iregs (i)); 1716 OUTS (outf, "+="); 1717 OUTS (outf, mregs (m)); 1718 } 1719 else if (op == 1) 1720 { 1721 OUTS (outf, iregs (i)); 1722 OUTS (outf, "-="); 1723 OUTS (outf, mregs (m)); 1724 } 1725 else 1726 return 0; 1727 1728 return 2; 1729} 1730 1731static int 1732decode_dagMODik_0 (TIword iw0, disassemble_info *outf) 1733{ 1734 /* dagMODik 1735 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1736 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| 1737 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1738 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask); 1739 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask); 1740 1741 if (op == 0) 1742 { 1743 OUTS (outf, iregs (i)); 1744 OUTS (outf, "+=2"); 1745 } 1746 else if (op == 1) 1747 { 1748 OUTS (outf, iregs (i)); 1749 OUTS (outf, "-=2"); 1750 } 1751 else if (op == 2) 1752 { 1753 OUTS (outf, iregs (i)); 1754 OUTS (outf, "+=4"); 1755 } 1756 else if (op == 3) 1757 { 1758 OUTS (outf, iregs (i)); 1759 OUTS (outf, "-=4"); 1760 } 1761 else 1762 return 0; 1763 1764 return 2; 1765} 1766 1767static int 1768decode_dspLDST_0 (TIword iw0, disassemble_info *outf) 1769{ 1770 /* dspLDST 1771 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1772 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| 1773 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1774 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask); 1775 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask); 1776 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask); 1777 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask); 1778 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask); 1779 1780 if (aop == 0 && W == 0 && m == 0) 1781 { 1782 OUTS (outf, dregs (reg)); 1783 OUTS (outf, "=["); 1784 OUTS (outf, iregs (i)); 1785 OUTS (outf, "++]"); 1786 } 1787 else if (aop == 0 && W == 0 && m == 1) 1788 { 1789 OUTS (outf, dregs_lo (reg)); 1790 OUTS (outf, "=W["); 1791 OUTS (outf, iregs (i)); 1792 OUTS (outf, "++]"); 1793 } 1794 else if (aop == 0 && W == 0 && m == 2) 1795 { 1796 OUTS (outf, dregs_hi (reg)); 1797 OUTS (outf, "=W["); 1798 OUTS (outf, iregs (i)); 1799 OUTS (outf, "++]"); 1800 } 1801 else if (aop == 1 && W == 0 && m == 0) 1802 { 1803 OUTS (outf, dregs (reg)); 1804 OUTS (outf, "=["); 1805 OUTS (outf, iregs (i)); 1806 OUTS (outf, "--]"); 1807 } 1808 else if (aop == 1 && W == 0 && m == 1) 1809 { 1810 OUTS (outf, dregs_lo (reg)); 1811 OUTS (outf, "=W["); 1812 OUTS (outf, iregs (i)); 1813 OUTS (outf, "--]"); 1814 } 1815 else if (aop == 1 && W == 0 && m == 2) 1816 { 1817 OUTS (outf, dregs_hi (reg)); 1818 OUTS (outf, "=W["); 1819 OUTS (outf, iregs (i)); 1820 OUTS (outf, "--]"); 1821 } 1822 else if (aop == 2 && W == 0 && m == 0) 1823 { 1824 OUTS (outf, dregs (reg)); 1825 OUTS (outf, "=["); 1826 OUTS (outf, iregs (i)); 1827 OUTS (outf, "]"); 1828 } 1829 else if (aop == 2 && W == 0 && m == 1) 1830 { 1831 OUTS (outf, dregs_lo (reg)); 1832 OUTS (outf, "=W["); 1833 OUTS (outf, iregs (i)); 1834 OUTS (outf, "]"); 1835 } 1836 else if (aop == 2 && W == 0 && m == 2) 1837 { 1838 OUTS (outf, dregs_hi (reg)); 1839 OUTS (outf, "=W["); 1840 OUTS (outf, iregs (i)); 1841 OUTS (outf, "]"); 1842 } 1843 else if (aop == 0 && W == 1 && m == 0) 1844 { 1845 OUTS (outf, "["); 1846 OUTS (outf, iregs (i)); 1847 OUTS (outf, "++]="); 1848 OUTS (outf, dregs (reg)); 1849 } 1850 else if (aop == 0 && W == 1 && m == 1) 1851 { 1852 OUTS (outf, "W["); 1853 OUTS (outf, iregs (i)); 1854 OUTS (outf, "++]="); 1855 OUTS (outf, dregs_lo (reg)); 1856 } 1857 else if (aop == 0 && W == 1 && m == 2) 1858 { 1859 OUTS (outf, "W["); 1860 OUTS (outf, iregs (i)); 1861 OUTS (outf, "++]="); 1862 OUTS (outf, dregs_hi (reg)); 1863 } 1864 else if (aop == 1 && W == 1 && m == 0) 1865 { 1866 OUTS (outf, "["); 1867 OUTS (outf, iregs (i)); 1868 OUTS (outf, "--]="); 1869 OUTS (outf, dregs (reg)); 1870 } 1871 else if (aop == 1 && W == 1 && m == 1) 1872 { 1873 OUTS (outf, "W["); 1874 OUTS (outf, iregs (i)); 1875 OUTS (outf, "--]="); 1876 OUTS (outf, dregs_lo (reg)); 1877 } 1878 else if (aop == 1 && W == 1 && m == 2) 1879 { 1880 OUTS (outf, "W["); 1881 OUTS (outf, iregs (i)); 1882 OUTS (outf, "--]="); 1883 OUTS (outf, dregs_hi (reg)); 1884 } 1885 else if (aop == 2 && W == 1 && m == 0) 1886 { 1887 OUTS (outf, "["); 1888 OUTS (outf, iregs (i)); 1889 OUTS (outf, "]="); 1890 OUTS (outf, dregs (reg)); 1891 } 1892 else if (aop == 2 && W == 1 && m == 1) 1893 { 1894 OUTS (outf, "W["); 1895 OUTS (outf, iregs (i)); 1896 OUTS (outf, "]="); 1897 OUTS (outf, dregs_lo (reg)); 1898 } 1899 else if (aop == 2 && W == 1 && m == 2) 1900 { 1901 OUTS (outf, "W["); 1902 OUTS (outf, iregs (i)); 1903 OUTS (outf, "]="); 1904 OUTS (outf, dregs_hi (reg)); 1905 } 1906 else if (aop == 3 && W == 0) 1907 { 1908 OUTS (outf, dregs (reg)); 1909 OUTS (outf, "=["); 1910 OUTS (outf, iregs (i)); 1911 OUTS (outf, "++"); 1912 OUTS (outf, mregs (m)); 1913 OUTS (outf, "]"); 1914 } 1915 else if (aop == 3 && W == 1) 1916 { 1917 OUTS (outf, "["); 1918 OUTS (outf, iregs (i)); 1919 OUTS (outf, "++"); 1920 OUTS (outf, mregs (m)); 1921 OUTS (outf, "]="); 1922 OUTS (outf, dregs (reg)); 1923 } 1924 else 1925 return 0; 1926 1927 return 2; 1928} 1929 1930static int 1931decode_LDST_0 (TIword iw0, disassemble_info *outf) 1932{ 1933 /* LDST 1934 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 1935 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| 1936 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 1937 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask); 1938 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask); 1939 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask); 1940 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask); 1941 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask); 1942 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask); 1943 1944 if (aop == 0 && sz == 0 && Z == 0 && W == 0) 1945 { 1946 OUTS (outf, dregs (reg)); 1947 OUTS (outf, "=["); 1948 OUTS (outf, pregs (ptr)); 1949 OUTS (outf, "++]"); 1950 } 1951 else if (aop == 0 && sz == 0 && Z == 1 && W == 0) 1952 { 1953 OUTS (outf, pregs (reg)); 1954 OUTS (outf, "=["); 1955 OUTS (outf, pregs (ptr)); 1956 OUTS (outf, "++]"); 1957 } 1958 else if (aop == 0 && sz == 1 && Z == 0 && W == 0) 1959 { 1960 OUTS (outf, dregs (reg)); 1961 OUTS (outf, "=W["); 1962 OUTS (outf, pregs (ptr)); 1963 OUTS (outf, "++] (Z)"); 1964 } 1965 else if (aop == 0 && sz == 1 && Z == 1 && W == 0) 1966 { 1967 OUTS (outf, dregs (reg)); 1968 OUTS (outf, "=W["); 1969 OUTS (outf, pregs (ptr)); 1970 OUTS (outf, "++](X)"); 1971 } 1972 else if (aop == 0 && sz == 2 && Z == 0 && W == 0) 1973 { 1974 OUTS (outf, dregs (reg)); 1975 OUTS (outf, "=B["); 1976 OUTS (outf, pregs (ptr)); 1977 OUTS (outf, "++] (Z)"); 1978 } 1979 else if (aop == 0 && sz == 2 && Z == 1 && W == 0) 1980 { 1981 OUTS (outf, dregs (reg)); 1982 OUTS (outf, "=B["); 1983 OUTS (outf, pregs (ptr)); 1984 OUTS (outf, "++](X)"); 1985 } 1986 else if (aop == 1 && sz == 0 && Z == 0 && W == 0) 1987 { 1988 OUTS (outf, dregs (reg)); 1989 OUTS (outf, "=["); 1990 OUTS (outf, pregs (ptr)); 1991 OUTS (outf, "--]"); 1992 } 1993 else if (aop == 1 && sz == 0 && Z == 1 && W == 0) 1994 { 1995 OUTS (outf, pregs (reg)); 1996 OUTS (outf, "=["); 1997 OUTS (outf, pregs (ptr)); 1998 OUTS (outf, "--]"); 1999 } 2000 else if (aop == 1 && sz == 1 && Z == 0 && W == 0) 2001 { 2002 OUTS (outf, dregs (reg)); 2003 OUTS (outf, "=W["); 2004 OUTS (outf, pregs (ptr)); 2005 OUTS (outf, "--] (Z)"); 2006 } 2007 else if (aop == 1 && sz == 1 && Z == 1 && W == 0) 2008 { 2009 OUTS (outf, dregs (reg)); 2010 OUTS (outf, "=W["); 2011 OUTS (outf, pregs (ptr)); 2012 OUTS (outf, "--](X)"); 2013 } 2014 else if (aop == 1 && sz == 2 && Z == 0 && W == 0) 2015 { 2016 OUTS (outf, dregs (reg)); 2017 OUTS (outf, "=B["); 2018 OUTS (outf, pregs (ptr)); 2019 OUTS (outf, "--] (Z)"); 2020 } 2021 else if (aop == 1 && sz == 2 && Z == 1 && W == 0) 2022 { 2023 OUTS (outf, dregs (reg)); 2024 OUTS (outf, "=B["); 2025 OUTS (outf, pregs (ptr)); 2026 OUTS (outf, "--](X)"); 2027 } 2028 else if (aop == 2 && sz == 0 && Z == 0 && W == 0) 2029 { 2030 OUTS (outf, dregs (reg)); 2031 OUTS (outf, "=["); 2032 OUTS (outf, pregs (ptr)); 2033 OUTS (outf, "]"); 2034 } 2035 else if (aop == 2 && sz == 0 && Z == 1 && W == 0) 2036 { 2037 OUTS (outf, pregs (reg)); 2038 OUTS (outf, "=["); 2039 OUTS (outf, pregs (ptr)); 2040 OUTS (outf, "]"); 2041 } 2042 else if (aop == 2 && sz == 1 && Z == 0 && W == 0) 2043 { 2044 OUTS (outf, dregs (reg)); 2045 OUTS (outf, "=W["); 2046 OUTS (outf, pregs (ptr)); 2047 OUTS (outf, "] (Z)"); 2048 } 2049 else if (aop == 2 && sz == 1 && Z == 1 && W == 0) 2050 { 2051 OUTS (outf, dregs (reg)); 2052 OUTS (outf, "=W["); 2053 OUTS (outf, pregs (ptr)); 2054 OUTS (outf, "](X)"); 2055 } 2056 else if (aop == 2 && sz == 2 && Z == 0 && W == 0) 2057 { 2058 OUTS (outf, dregs (reg)); 2059 OUTS (outf, "=B["); 2060 OUTS (outf, pregs (ptr)); 2061 OUTS (outf, "] (Z)"); 2062 } 2063 else if (aop == 2 && sz == 2 && Z == 1 && W == 0) 2064 { 2065 OUTS (outf, dregs (reg)); 2066 OUTS (outf, "=B["); 2067 OUTS (outf, pregs (ptr)); 2068 OUTS (outf, "](X)"); 2069 } 2070 else if (aop == 0 && sz == 0 && Z == 0 && W == 1) 2071 { 2072 OUTS (outf, "["); 2073 OUTS (outf, pregs (ptr)); 2074 OUTS (outf, "++]="); 2075 OUTS (outf, dregs (reg)); 2076 } 2077 else if (aop == 0 && sz == 0 && Z == 1 && W == 1) 2078 { 2079 OUTS (outf, "["); 2080 OUTS (outf, pregs (ptr)); 2081 OUTS (outf, "++]="); 2082 OUTS (outf, pregs (reg)); 2083 } 2084 else if (aop == 0 && sz == 1 && Z == 0 && W == 1) 2085 { 2086 OUTS (outf, "W["); 2087 OUTS (outf, pregs (ptr)); 2088 OUTS (outf, "++]="); 2089 OUTS (outf, dregs (reg)); 2090 } 2091 else if (aop == 0 && sz == 2 && Z == 0 && W == 1) 2092 { 2093 OUTS (outf, "B["); 2094 OUTS (outf, pregs (ptr)); 2095 OUTS (outf, "++]="); 2096 OUTS (outf, dregs (reg)); 2097 } 2098 else if (aop == 1 && sz == 0 && Z == 0 && W == 1) 2099 { 2100 OUTS (outf, "["); 2101 OUTS (outf, pregs (ptr)); 2102 OUTS (outf, "--]="); 2103 OUTS (outf, dregs (reg)); 2104 } 2105 else if (aop == 1 && sz == 0 && Z == 1 && W == 1) 2106 { 2107 OUTS (outf, "["); 2108 OUTS (outf, pregs (ptr)); 2109 OUTS (outf, "--]="); 2110 OUTS (outf, pregs (reg)); 2111 } 2112 else if (aop == 1 && sz == 1 && Z == 0 && W == 1) 2113 { 2114 OUTS (outf, "W["); 2115 OUTS (outf, pregs (ptr)); 2116 OUTS (outf, "--]="); 2117 OUTS (outf, dregs (reg)); 2118 } 2119 else if (aop == 1 && sz == 2 && Z == 0 && W == 1) 2120 { 2121 OUTS (outf, "B["); 2122 OUTS (outf, pregs (ptr)); 2123 OUTS (outf, "--]="); 2124 OUTS (outf, dregs (reg)); 2125 } 2126 else if (aop == 2 && sz == 0 && Z == 0 && W == 1) 2127 { 2128 OUTS (outf, "["); 2129 OUTS (outf, pregs (ptr)); 2130 OUTS (outf, "]="); 2131 OUTS (outf, dregs (reg)); 2132 } 2133 else if (aop == 2 && sz == 0 && Z == 1 && W == 1) 2134 { 2135 OUTS (outf, "["); 2136 OUTS (outf, pregs (ptr)); 2137 OUTS (outf, "]="); 2138 OUTS (outf, pregs (reg)); 2139 } 2140 else if (aop == 2 && sz == 1 && Z == 0 && W == 1) 2141 { 2142 OUTS (outf, "W["); 2143 OUTS (outf, pregs (ptr)); 2144 OUTS (outf, "]="); 2145 OUTS (outf, dregs (reg)); 2146 } 2147 else if (aop == 2 && sz == 2 && Z == 0 && W == 1) 2148 { 2149 OUTS (outf, "B["); 2150 OUTS (outf, pregs (ptr)); 2151 OUTS (outf, "]="); 2152 OUTS (outf, dregs (reg)); 2153 } 2154 else 2155 return 0; 2156 2157 return 2; 2158} 2159 2160static int 2161decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf) 2162{ 2163 /* LDSTiiFP 2164 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2165 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| 2166 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2167 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask); 2168 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask); 2169 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask); 2170 2171 if (W == 0) 2172 { 2173 OUTS (outf, dpregs (reg)); 2174 OUTS (outf, "=[FP"); 2175 OUTS (outf, negimm5s4 (offset)); 2176 OUTS (outf, "]"); 2177 } 2178 else if (W == 1) 2179 { 2180 OUTS (outf, "[FP"); 2181 OUTS (outf, negimm5s4 (offset)); 2182 OUTS (outf, "]="); 2183 OUTS (outf, dpregs (reg)); 2184 } 2185 else 2186 return 0; 2187 2188 return 2; 2189} 2190 2191static int 2192decode_LDSTii_0 (TIword iw0, disassemble_info *outf) 2193{ 2194 /* LDSTii 2195 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2196 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| 2197 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2198 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask); 2199 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask); 2200 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask); 2201 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask); 2202 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask); 2203 2204 if (W == 0 && op == 0) 2205 { 2206 OUTS (outf, dregs (reg)); 2207 OUTS (outf, "=["); 2208 OUTS (outf, pregs (ptr)); 2209 OUTS (outf, "+"); 2210 OUTS (outf, uimm4s4 (offset)); 2211 OUTS (outf, "]"); 2212 } 2213 else if (W == 0 && op == 1) 2214 { 2215 OUTS (outf, dregs (reg)); 2216 OUTS (outf, "=W["); 2217 OUTS (outf, pregs (ptr)); 2218 OUTS (outf, "+"); 2219 OUTS (outf, uimm4s2 (offset)); 2220 OUTS (outf, "] (Z)"); 2221 } 2222 else if (W == 0 && op == 2) 2223 { 2224 OUTS (outf, dregs (reg)); 2225 OUTS (outf, "=W["); 2226 OUTS (outf, pregs (ptr)); 2227 OUTS (outf, "+"); 2228 OUTS (outf, uimm4s2 (offset)); 2229 OUTS (outf, "](X)"); 2230 } 2231 else if (W == 0 && op == 3) 2232 { 2233 OUTS (outf, pregs (reg)); 2234 OUTS (outf, "=["); 2235 OUTS (outf, pregs (ptr)); 2236 OUTS (outf, "+"); 2237 OUTS (outf, uimm4s4 (offset)); 2238 OUTS (outf, "]"); 2239 } 2240 else if (W == 1 && op == 0) 2241 { 2242 OUTS (outf, "["); 2243 OUTS (outf, pregs (ptr)); 2244 OUTS (outf, "+"); 2245 OUTS (outf, uimm4s4 (offset)); 2246 OUTS (outf, "]="); 2247 OUTS (outf, dregs (reg)); 2248 } 2249 else if (W == 1 && op == 1) 2250 { 2251 OUTS (outf, "W"); 2252 OUTS (outf, "["); 2253 OUTS (outf, pregs (ptr)); 2254 OUTS (outf, "+"); 2255 OUTS (outf, uimm4s2 (offset)); 2256 OUTS (outf, "]"); 2257 OUTS (outf, "="); 2258 OUTS (outf, dregs (reg)); 2259 } 2260 else if (W == 1 && op == 3) 2261 { 2262 OUTS (outf, "["); 2263 OUTS (outf, pregs (ptr)); 2264 OUTS (outf, "+"); 2265 OUTS (outf, uimm4s4 (offset)); 2266 OUTS (outf, "]="); 2267 OUTS (outf, pregs (reg)); 2268 } 2269 else 2270 return 0; 2271 2272 return 2; 2273} 2274 2275static int 2276decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf) 2277{ 2278 /* LoopSetup 2279 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2280 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| 2281 |.reg...........| - | - |.eoffset...............................| 2282 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2283 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask); 2284 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask); 2285 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask); 2286 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask); 2287 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask); 2288 2289 if (rop == 0) 2290 { 2291 OUTS (outf, "LSETUP"); 2292 OUTS (outf, "("); 2293 OUTS (outf, pcrel4 (soffset)); 2294 OUTS (outf, ","); 2295 OUTS (outf, lppcrel10 (eoffset)); 2296 OUTS (outf, ")"); 2297 OUTS (outf, counters (c)); 2298 } 2299 else if (rop == 1) 2300 { 2301 OUTS (outf, "LSETUP"); 2302 OUTS (outf, "("); 2303 OUTS (outf, pcrel4 (soffset)); 2304 OUTS (outf, ","); 2305 OUTS (outf, lppcrel10 (eoffset)); 2306 OUTS (outf, ")"); 2307 OUTS (outf, counters (c)); 2308 OUTS (outf, "="); 2309 OUTS (outf, pregs (reg)); 2310 } 2311 else if (rop == 3) 2312 { 2313 OUTS (outf, "LSETUP"); 2314 OUTS (outf, "("); 2315 OUTS (outf, pcrel4 (soffset)); 2316 OUTS (outf, ","); 2317 OUTS (outf, lppcrel10 (eoffset)); 2318 OUTS (outf, ")"); 2319 OUTS (outf, counters (c)); 2320 OUTS (outf, "="); 2321 OUTS (outf, pregs (reg)); 2322 OUTS (outf, ">>1"); 2323 } 2324 else 2325 return 0; 2326 2327 return 4; 2328} 2329 2330static int 2331decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf) 2332{ 2333 /* LDIMMhalf 2334 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2335 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| 2336 |.hword.........................................................| 2337 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2338 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask); 2339 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask); 2340 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask); 2341 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask); 2342 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask); 2343 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask); 2344 2345 if (grp == 0 && H == 0 && S == 0 && Z == 0) 2346 { 2347 OUTS (outf, dregs_lo (reg)); 2348 OUTS (outf, "="); 2349 OUTS (outf, imm16 (hword)); 2350 } 2351 else if (grp == 0 && H == 1 && S == 0 && Z == 0) 2352 { 2353 OUTS (outf, dregs_hi (reg)); 2354 OUTS (outf, "="); 2355 OUTS (outf, imm16 (hword)); 2356 } 2357 else if (grp == 0 && H == 0 && S == 1 && Z == 0) 2358 { 2359 OUTS (outf, dregs (reg)); 2360 OUTS (outf, "="); 2361 OUTS (outf, imm16 (hword)); 2362 OUTS (outf, " (X)"); 2363 } 2364 else if (H == 0 && S == 1 && Z == 0) 2365 { 2366 OUTS (outf, regs (reg, grp)); 2367 OUTS (outf, "="); 2368 OUTS (outf, imm16 (hword)); 2369 OUTS (outf, " (X)"); 2370 } 2371 else if (H == 0 && S == 0 && Z == 1) 2372 { 2373 OUTS (outf, regs (reg, grp)); 2374 OUTS (outf, "="); 2375 OUTS (outf, luimm16 (hword)); 2376 OUTS (outf, "(Z)"); 2377 } 2378 else if (H == 0 && S == 0 && Z == 0) 2379 { 2380 OUTS (outf, regs_lo (reg, grp)); 2381 OUTS (outf, "="); 2382 OUTS (outf, luimm16 (hword)); 2383 } 2384 else if (H == 1 && S == 0 && Z == 0) 2385 { 2386 OUTS (outf, regs_hi (reg, grp)); 2387 OUTS (outf, "="); 2388 OUTS (outf, huimm16 (hword)); 2389 } 2390 else 2391 return 0; 2392 2393 return 4; 2394} 2395 2396static int 2397decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf) 2398{ 2399 /* CALLa 2400 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2401 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| 2402 |.lsw...........................................................| 2403 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2404 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask); 2405 int lsw = ((iw1 >> 0) & 0xffff); 2406 int msw = ((iw0 >> 0) & 0xff); 2407 2408 if (S == 1) 2409 OUTS (outf, "CALL "); 2410 else if (S == 0) 2411 OUTS (outf, "JUMP.L "); 2412 else 2413 return 0; 2414 2415 OUTS (outf, pcrel24 (((msw) << 16) | (lsw))); 2416 return 4; 2417} 2418 2419static int 2420decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf) 2421{ 2422 /* LDSTidxI 2423 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2424 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| 2425 |.offset........................................................| 2426 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2427 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask); 2428 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask); 2429 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask); 2430 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask); 2431 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask); 2432 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask); 2433 2434 if (W == 0 && sz == 0 && Z == 0) 2435 { 2436 OUTS (outf, dregs (reg)); 2437 OUTS (outf, "=["); 2438 OUTS (outf, pregs (ptr)); 2439 OUTS (outf, "+"); 2440 OUTS (outf, imm16s4 (offset)); 2441 OUTS (outf, "]"); 2442 } 2443 else if (W == 0 && sz == 0 && Z == 1) 2444 { 2445 OUTS (outf, pregs (reg)); 2446 OUTS (outf, "=["); 2447 OUTS (outf, pregs (ptr)); 2448 OUTS (outf, "+"); 2449 OUTS (outf, imm16s4 (offset)); 2450 OUTS (outf, "]"); 2451 } 2452 else if (W == 0 && sz == 1 && Z == 0) 2453 { 2454 OUTS (outf, dregs (reg)); 2455 OUTS (outf, "=W["); 2456 OUTS (outf, pregs (ptr)); 2457 OUTS (outf, "+"); 2458 OUTS (outf, imm16s2 (offset)); 2459 OUTS (outf, "] (Z)"); 2460 } 2461 else if (W == 0 && sz == 1 && Z == 1) 2462 { 2463 OUTS (outf, dregs (reg)); 2464 OUTS (outf, "=W["); 2465 OUTS (outf, pregs (ptr)); 2466 OUTS (outf, "+"); 2467 OUTS (outf, imm16s2 (offset)); 2468 OUTS (outf, "](X)"); 2469 } 2470 else if (W == 0 && sz == 2 && Z == 0) 2471 { 2472 OUTS (outf, dregs (reg)); 2473 OUTS (outf, "=B["); 2474 OUTS (outf, pregs (ptr)); 2475 OUTS (outf, "+"); 2476 OUTS (outf, imm16 (offset)); 2477 OUTS (outf, "] (Z)"); 2478 } 2479 else if (W == 0 && sz == 2 && Z == 1) 2480 { 2481 OUTS (outf, dregs (reg)); 2482 OUTS (outf, "=B["); 2483 OUTS (outf, pregs (ptr)); 2484 OUTS (outf, "+"); 2485 OUTS (outf, imm16 (offset)); 2486 OUTS (outf, "](X)"); 2487 } 2488 else if (W == 1 && sz == 0 && Z == 0) 2489 { 2490 OUTS (outf, "["); 2491 OUTS (outf, pregs (ptr)); 2492 OUTS (outf, "+"); 2493 OUTS (outf, imm16s4 (offset)); 2494 OUTS (outf, "]="); 2495 OUTS (outf, dregs (reg)); 2496 } 2497 else if (W == 1 && sz == 0 && Z == 1) 2498 { 2499 OUTS (outf, "["); 2500 OUTS (outf, pregs (ptr)); 2501 OUTS (outf, "+"); 2502 OUTS (outf, imm16s4 (offset)); 2503 OUTS (outf, "]="); 2504 OUTS (outf, pregs (reg)); 2505 } 2506 else if (W == 1 && sz == 1 && Z == 0) 2507 { 2508 OUTS (outf, "W["); 2509 OUTS (outf, pregs (ptr)); 2510 OUTS (outf, "+"); 2511 OUTS (outf, imm16s2 (offset)); 2512 OUTS (outf, "]="); 2513 OUTS (outf, dregs (reg)); 2514 } 2515 else if (W == 1 && sz == 2 && Z == 0) 2516 { 2517 OUTS (outf, "B["); 2518 OUTS (outf, pregs (ptr)); 2519 OUTS (outf, "+"); 2520 OUTS (outf, imm16 (offset)); 2521 OUTS (outf, "]="); 2522 OUTS (outf, dregs (reg)); 2523 } 2524 else 2525 return 0; 2526 2527 return 4; 2528} 2529 2530static int 2531decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf) 2532{ 2533 /* linkage 2534 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2535 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| 2536 |.framesize.....................................................| 2537 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2538 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask); 2539 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask); 2540 2541 if (R == 0) 2542 { 2543 OUTS (outf, "LINK "); 2544 OUTS (outf, uimm16s4 (framesize)); 2545 } 2546 else if (R == 1) 2547 OUTS (outf, "UNLINK"); 2548 else 2549 return 0; 2550 2551 return 4; 2552} 2553 2554static int 2555decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf) 2556{ 2557 /* dsp32mac 2558 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2559 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| 2560 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| 2561 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2562 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); 2563 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); 2564 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); 2565 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); 2566 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); 2567 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); 2568 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); 2569 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); 2570 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); 2571 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); 2572 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); 2573 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); 2574 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); 2575 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); 2576 2577 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) 2578 return 0; 2579 2580 if (op1 == 3 && MM) 2581 return 0; 2582 2583 if ((w1 || w0) && mmod == M_W32) 2584 return 0; 2585 2586 if (((1 << mmod) & (P ? 0x31b : 0x1b5f)) == 0) 2587 return 0; 2588 2589 if (w1 == 1 || op1 != 3) 2590 { 2591 if (w1) 2592 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst)); 2593 2594 if (op1 == 3) 2595 OUTS (outf, " = A1"); 2596 else 2597 { 2598 if (w1) 2599 OUTS (outf, " = ("); 2600 decode_macfunc (1, op1, h01, h11, src0, src1, outf); 2601 if (w1) 2602 OUTS (outf, ")"); 2603 } 2604 2605 if (w0 == 1 || op0 != 3) 2606 { 2607 if (MM) 2608 OUTS (outf, " (M)"); 2609 MM = 0; 2610 OUTS (outf, ", "); 2611 } 2612 } 2613 2614 if (w0 == 1 || op0 != 3) 2615 { 2616 if (w0) 2617 OUTS (outf, P ? dregs (dst) : dregs_lo (dst)); 2618 2619 if (op0 == 3) 2620 OUTS (outf, " = A0"); 2621 else 2622 { 2623 if (w0) 2624 OUTS (outf, " = ("); 2625 decode_macfunc (0, op0, h00, h10, src0, src1, outf); 2626 if (w0) 2627 OUTS (outf, ")"); 2628 } 2629 } 2630 2631 decode_optmode (mmod, MM, outf); 2632 2633 return 4; 2634} 2635 2636static int 2637decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf) 2638{ 2639 /* dsp32mult 2640 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2641 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| 2642 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| 2643 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2644 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); 2645 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); 2646 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); 2647 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); 2648 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); 2649 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); 2650 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); 2651 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); 2652 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); 2653 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); 2654 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); 2655 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); 2656 2657 if (w1 == 0 && w0 == 0) 2658 return 0; 2659 2660 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0) 2661 return 0; 2662 2663 if (w1) 2664 { 2665 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst)); 2666 OUTS (outf, " = "); 2667 decode_multfunc (h01, h11, src0, src1, outf); 2668 2669 if (w0) 2670 { 2671 if (MM) 2672 OUTS (outf, " (M)"); 2673 MM = 0; 2674 OUTS (outf, ", "); 2675 } 2676 } 2677 2678 if (w0) 2679 { 2680 OUTS (outf, dregs (dst)); 2681 OUTS (outf, " = "); 2682 decode_multfunc (h00, h10, src0, src1, outf); 2683 } 2684 2685 decode_optmode (mmod, MM, outf); 2686 return 4; 2687} 2688 2689static int 2690decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) 2691{ 2692 /* dsp32alu 2693 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2694 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| 2695 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| 2696 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2697 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask); 2698 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask); 2699 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask); 2700 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); 2701 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask); 2702 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask); 2703 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask); 2704 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask); 2705 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask); 2706 2707 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0) 2708 { 2709 OUTS (outf, "A0.L="); 2710 OUTS (outf, dregs_lo (src0)); 2711 } 2712 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0) 2713 { 2714 OUTS (outf, "A1.H="); 2715 OUTS (outf, dregs_hi (src0)); 2716 } 2717 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0) 2718 { 2719 OUTS (outf, "A1.L="); 2720 OUTS (outf, dregs_lo (src0)); 2721 } 2722 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0) 2723 { 2724 OUTS (outf, "A0.H="); 2725 OUTS (outf, dregs_hi (src0)); 2726 } 2727 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5) 2728 { 2729 OUTS (outf, dregs_hi (dst0)); 2730 OUTS (outf, "="); 2731 OUTS (outf, dregs (src0)); 2732 OUTS (outf, "-"); 2733 OUTS (outf, dregs (src1)); 2734 OUTS (outf, "(RND20)"); 2735 } 2736 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5) 2737 { 2738 OUTS (outf, dregs_hi (dst0)); 2739 OUTS (outf, "="); 2740 OUTS (outf, dregs (src0)); 2741 OUTS (outf, "+"); 2742 OUTS (outf, dregs (src1)); 2743 OUTS (outf, "(RND20)"); 2744 } 2745 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5) 2746 { 2747 OUTS (outf, dregs_lo (dst0)); 2748 OUTS (outf, "="); 2749 OUTS (outf, dregs (src0)); 2750 OUTS (outf, "-"); 2751 OUTS (outf, dregs (src1)); 2752 OUTS (outf, "(RND12)"); 2753 } 2754 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5) 2755 { 2756 OUTS (outf, dregs_lo (dst0)); 2757 OUTS (outf, "="); 2758 OUTS (outf, dregs (src0)); 2759 OUTS (outf, "+"); 2760 OUTS (outf, dregs (src1)); 2761 OUTS (outf, "(RND12)"); 2762 } 2763 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5) 2764 { 2765 OUTS (outf, dregs_lo (dst0)); 2766 OUTS (outf, "="); 2767 OUTS (outf, dregs (src0)); 2768 OUTS (outf, "-"); 2769 OUTS (outf, dregs (src1)); 2770 OUTS (outf, "(RND20)"); 2771 } 2772 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5) 2773 { 2774 OUTS (outf, dregs_hi (dst0)); 2775 OUTS (outf, "="); 2776 OUTS (outf, dregs (src0)); 2777 OUTS (outf, "+"); 2778 OUTS (outf, dregs (src1)); 2779 OUTS (outf, "(RND12)"); 2780 } 2781 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5) 2782 { 2783 OUTS (outf, dregs_lo (dst0)); 2784 OUTS (outf, "="); 2785 OUTS (outf, dregs (src0)); 2786 OUTS (outf, "+"); 2787 OUTS (outf, dregs (src1)); 2788 OUTS (outf, "(RND20)"); 2789 } 2790 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5) 2791 { 2792 OUTS (outf, dregs_hi (dst0)); 2793 OUTS (outf, "="); 2794 OUTS (outf, dregs (src0)); 2795 OUTS (outf, "-"); 2796 OUTS (outf, dregs (src1)); 2797 OUTS (outf, "(RND12)"); 2798 } 2799 else if (HL == 1 && aop == 0 && aopcde == 2) 2800 { 2801 OUTS (outf, dregs_hi (dst0)); 2802 OUTS (outf, "="); 2803 OUTS (outf, dregs_lo (src0)); 2804 OUTS (outf, "+"); 2805 OUTS (outf, dregs_lo (src1)); 2806 OUTS (outf, " "); 2807 amod1 (s, x, outf); 2808 } 2809 else if (HL == 1 && aop == 1 && aopcde == 2) 2810 { 2811 OUTS (outf, dregs_hi (dst0)); 2812 OUTS (outf, "="); 2813 OUTS (outf, dregs_lo (src0)); 2814 OUTS (outf, "+"); 2815 OUTS (outf, dregs_hi (src1)); 2816 OUTS (outf, " "); 2817 amod1 (s, x, outf); 2818 } 2819 else if (HL == 1 && aop == 2 && aopcde == 2) 2820 { 2821 OUTS (outf, dregs_hi (dst0)); 2822 OUTS (outf, "="); 2823 OUTS (outf, dregs_hi (src0)); 2824 OUTS (outf, "+"); 2825 OUTS (outf, dregs_lo (src1)); 2826 OUTS (outf, " "); 2827 amod1 (s, x, outf); 2828 } 2829 else if (HL == 1 && aop == 3 && aopcde == 2) 2830 { 2831 OUTS (outf, dregs_hi (dst0)); 2832 OUTS (outf, "="); 2833 OUTS (outf, dregs_hi (src0)); 2834 OUTS (outf, "+"); 2835 OUTS (outf, dregs_hi (src1)); 2836 OUTS (outf, " "); 2837 amod1 (s, x, outf); 2838 } 2839 else if (HL == 0 && aop == 0 && aopcde == 3) 2840 { 2841 OUTS (outf, dregs_lo (dst0)); 2842 OUTS (outf, "="); 2843 OUTS (outf, dregs_lo (src0)); 2844 OUTS (outf, "-"); 2845 OUTS (outf, dregs_lo (src1)); 2846 OUTS (outf, " "); 2847 amod1 (s, x, outf); 2848 } 2849 else if (HL == 0 && aop == 1 && aopcde == 3) 2850 { 2851 OUTS (outf, dregs_lo (dst0)); 2852 OUTS (outf, "="); 2853 OUTS (outf, dregs_lo (src0)); 2854 OUTS (outf, "-"); 2855 OUTS (outf, dregs_hi (src1)); 2856 OUTS (outf, " "); 2857 amod1 (s, x, outf); 2858 } 2859 else if (HL == 0 && aop == 3 && aopcde == 2) 2860 { 2861 OUTS (outf, dregs_lo (dst0)); 2862 OUTS (outf, "="); 2863 OUTS (outf, dregs_hi (src0)); 2864 OUTS (outf, "+"); 2865 OUTS (outf, dregs_hi (src1)); 2866 OUTS (outf, " "); 2867 amod1 (s, x, outf); 2868 } 2869 else if (HL == 1 && aop == 0 && aopcde == 3) 2870 { 2871 OUTS (outf, dregs_hi (dst0)); 2872 OUTS (outf, "="); 2873 OUTS (outf, dregs_lo (src0)); 2874 OUTS (outf, "-"); 2875 OUTS (outf, dregs_lo (src1)); 2876 OUTS (outf, " "); 2877 amod1 (s, x, outf); 2878 } 2879 else if (HL == 1 && aop == 1 && aopcde == 3) 2880 { 2881 OUTS (outf, dregs_hi (dst0)); 2882 OUTS (outf, "="); 2883 OUTS (outf, dregs_lo (src0)); 2884 OUTS (outf, "-"); 2885 OUTS (outf, dregs_hi (src1)); 2886 OUTS (outf, " "); 2887 amod1 (s, x, outf); 2888 } 2889 else if (HL == 1 && aop == 2 && aopcde == 3) 2890 { 2891 OUTS (outf, dregs_hi (dst0)); 2892 OUTS (outf, "="); 2893 OUTS (outf, dregs_hi (src0)); 2894 OUTS (outf, "-"); 2895 OUTS (outf, dregs_lo (src1)); 2896 OUTS (outf, " "); 2897 amod1 (s, x, outf); 2898 } 2899 else if (HL == 1 && aop == 3 && aopcde == 3) 2900 { 2901 OUTS (outf, dregs_hi (dst0)); 2902 OUTS (outf, "="); 2903 OUTS (outf, dregs_hi (src0)); 2904 OUTS (outf, "-"); 2905 OUTS (outf, dregs_hi (src1)); 2906 OUTS (outf, " "); 2907 amod1 (s, x, outf); 2908 } 2909 else if (HL == 0 && aop == 2 && aopcde == 2) 2910 { 2911 OUTS (outf, dregs_lo (dst0)); 2912 OUTS (outf, "="); 2913 OUTS (outf, dregs_hi (src0)); 2914 OUTS (outf, "+"); 2915 OUTS (outf, dregs_lo (src1)); 2916 OUTS (outf, " "); 2917 amod1 (s, x, outf); 2918 } 2919 else if (HL == 0 && aop == 1 && aopcde == 2) 2920 { 2921 OUTS (outf, dregs_lo (dst0)); 2922 OUTS (outf, "="); 2923 OUTS (outf, dregs_lo (src0)); 2924 OUTS (outf, "+"); 2925 OUTS (outf, dregs_hi (src1)); 2926 OUTS (outf, " "); 2927 amod1 (s, x, outf); 2928 } 2929 else if (HL == 0 && aop == 2 && aopcde == 3) 2930 { 2931 OUTS (outf, dregs_lo (dst0)); 2932 OUTS (outf, "="); 2933 OUTS (outf, dregs_hi (src0)); 2934 OUTS (outf, "-"); 2935 OUTS (outf, dregs_lo (src1)); 2936 OUTS (outf, " "); 2937 amod1 (s, x, outf); 2938 } 2939 else if (HL == 0 && aop == 3 && aopcde == 3) 2940 { 2941 OUTS (outf, dregs_lo (dst0)); 2942 OUTS (outf, "="); 2943 OUTS (outf, dregs_hi (src0)); 2944 OUTS (outf, "-"); 2945 OUTS (outf, dregs_hi (src1)); 2946 OUTS (outf, " "); 2947 amod1 (s, x, outf); 2948 } 2949 else if (HL == 0 && aop == 0 && aopcde == 2) 2950 { 2951 OUTS (outf, dregs_lo (dst0)); 2952 OUTS (outf, "="); 2953 OUTS (outf, dregs_lo (src0)); 2954 OUTS (outf, "+"); 2955 OUTS (outf, dregs_lo (src1)); 2956 OUTS (outf, " "); 2957 amod1 (s, x, outf); 2958 } 2959 else if (aop == 0 && aopcde == 9 && s == 1) 2960 { 2961 OUTS (outf, "A0="); 2962 OUTS (outf, dregs (src0)); 2963 } 2964 else if (aop == 3 && aopcde == 11 && s == 0) 2965 OUTS (outf, "A0-=A1"); 2966 2967 else if (aop == 3 && aopcde == 11 && s == 1) 2968 OUTS (outf, "A0-=A1(W32)"); 2969 2970 else if (aop == 3 && aopcde == 22 && HL == 1) 2971 { 2972 OUTS (outf, dregs (dst0)); 2973 OUTS (outf, "=BYTEOP2M("); 2974 OUTS (outf, dregs (src0 + 1)); 2975 OUTS (outf, ":"); 2976 OUTS (outf, imm5 (src0)); 2977 OUTS (outf, ","); 2978 OUTS (outf, dregs (src1 + 1)); 2979 OUTS (outf, ":"); 2980 OUTS (outf, imm5 (src1)); 2981 OUTS (outf, ")(TH"); 2982 if (s == 1) 2983 OUTS (outf, ", R)"); 2984 else 2985 OUTS (outf, ")"); 2986 } 2987 else if (aop == 3 && aopcde == 22 && HL == 0) 2988 { 2989 OUTS (outf, dregs (dst0)); 2990 OUTS (outf, "=BYTEOP2M("); 2991 OUTS (outf, dregs (src0 + 1)); 2992 OUTS (outf, ":"); 2993 OUTS (outf, imm5 (src0)); 2994 OUTS (outf, ","); 2995 OUTS (outf, dregs (src1 + 1)); 2996 OUTS (outf, ":"); 2997 OUTS (outf, imm5 (src1)); 2998 OUTS (outf, ")(TL"); 2999 if (s == 1) 3000 OUTS (outf, ", R)"); 3001 else 3002 OUTS (outf, ")"); 3003 } 3004 else if (aop == 2 && aopcde == 22 && HL == 1) 3005 { 3006 OUTS (outf, dregs (dst0)); 3007 OUTS (outf, "=BYTEOP2M("); 3008 OUTS (outf, dregs (src0 + 1)); 3009 OUTS (outf, ":"); 3010 OUTS (outf, imm5 (src0)); 3011 OUTS (outf, ","); 3012 OUTS (outf, dregs (src1 + 1)); 3013 OUTS (outf, ":"); 3014 OUTS (outf, imm5 (src1)); 3015 OUTS (outf, ")(RNDH"); 3016 if (s == 1) 3017 OUTS (outf, ", R)"); 3018 else 3019 OUTS (outf, ")"); 3020 } 3021 else if (aop == 2 && aopcde == 22 && HL == 0) 3022 { 3023 OUTS (outf, dregs (dst0)); 3024 OUTS (outf, "=BYTEOP2M("); 3025 OUTS (outf, dregs (src0 + 1)); 3026 OUTS (outf, ":"); 3027 OUTS (outf, imm5 (src0)); 3028 OUTS (outf, ","); 3029 OUTS (outf, dregs (src1 + 1)); 3030 OUTS (outf, ":"); 3031 OUTS (outf, imm5 (src1)); 3032 OUTS (outf, ")(RNDL"); 3033 if (s == 1) 3034 OUTS (outf, ", R)"); 3035 else 3036 OUTS (outf, ")"); 3037 } 3038 else if (aop == 1 && aopcde == 22 && HL == 1) 3039 { 3040 OUTS (outf, dregs (dst0)); 3041 OUTS (outf, "=BYTEOP2P("); 3042 OUTS (outf, dregs (src0 + 1)); 3043 OUTS (outf, ":"); 3044 OUTS (outf, imm5 (src0)); 3045 OUTS (outf, ","); 3046 OUTS (outf, dregs (src1 + 1)); 3047 OUTS (outf, ":"); 3048 OUTS (outf, imm5 (src1)); 3049 OUTS (outf, ")(TH"); 3050 if (s == 1) 3051 OUTS (outf, ", R)"); 3052 else 3053 OUTS (outf, ")"); 3054 } 3055 else if (aop == 1 && aopcde == 22 && HL == 0) 3056 { 3057 OUTS (outf, dregs (dst0)); 3058 OUTS (outf, "=BYTEOP2P("); 3059 OUTS (outf, dregs (src0 + 1)); 3060 OUTS (outf, ":"); 3061 OUTS (outf, imm5 (src0)); 3062 OUTS (outf, ","); 3063 OUTS (outf, dregs (src1 + 1)); 3064 OUTS (outf, ":"); 3065 OUTS (outf, imm5 (src1)); 3066 OUTS (outf, ")(TL"); 3067 if (s == 1) 3068 OUTS (outf, ", R)"); 3069 else 3070 OUTS (outf, ")"); 3071 } 3072 else if (aop == 0 && aopcde == 22 && HL == 1) 3073 { 3074 OUTS (outf, dregs (dst0)); 3075 OUTS (outf, "=BYTEOP2P("); 3076 OUTS (outf, dregs (src0 + 1)); 3077 OUTS (outf, ":"); 3078 OUTS (outf, imm5 (src0)); 3079 OUTS (outf, ","); 3080 OUTS (outf, dregs (src1 + 1)); 3081 OUTS (outf, ":"); 3082 OUTS (outf, imm5 (src1)); 3083 OUTS (outf, ")(RNDH"); 3084 if (s == 1) 3085 OUTS (outf, ", R)"); 3086 else 3087 OUTS (outf, ")"); 3088 } 3089 else if (aop == 0 && aopcde == 22 && HL == 0) 3090 { 3091 OUTS (outf, dregs (dst0)); 3092 OUTS (outf, "=BYTEOP2P("); 3093 OUTS (outf, dregs (src0 + 1)); 3094 OUTS (outf, ":"); 3095 OUTS (outf, imm5 (src0)); 3096 OUTS (outf, ","); 3097 OUTS (outf, dregs (src1 + 1)); 3098 OUTS (outf, ":"); 3099 OUTS (outf, imm5 (src1)); 3100 OUTS (outf, ")(RNDL"); 3101 if (s == 1) 3102 OUTS (outf, ", R)"); 3103 else 3104 OUTS (outf, ")"); 3105 } 3106 else if (aop == 0 && s == 0 && aopcde == 8) 3107 OUTS (outf, "A0=0"); 3108 3109 else if (aop == 0 && s == 1 && aopcde == 8) 3110 OUTS (outf, "A0=A0(S)"); 3111 3112 else if (aop == 1 && s == 0 && aopcde == 8) 3113 OUTS (outf, "A1=0"); 3114 3115 else if (aop == 1 && s == 1 && aopcde == 8) 3116 OUTS (outf, "A1=A1(S)"); 3117 3118 else if (aop == 2 && s == 0 && aopcde == 8) 3119 OUTS (outf, "A1=A0=0"); 3120 3121 else if (aop == 2 && s == 1 && aopcde == 8) 3122 OUTS (outf, "A1=A1(S),A0=A0(S)"); 3123 3124 else if (aop == 3 && s == 0 && aopcde == 8) 3125 OUTS (outf, "A0=A1"); 3126 3127 else if (aop == 3 && s == 1 && aopcde == 8) 3128 OUTS (outf, "A1=A0"); 3129 3130 else if (aop == 1 && aopcde == 9 && s == 0) 3131 { 3132 OUTS (outf, "A0.x="); 3133 OUTS (outf, dregs_lo (src0)); 3134 } 3135 else if (aop == 1 && HL == 0 && aopcde == 11) 3136 { 3137 OUTS (outf, dregs_lo (dst0)); 3138 OUTS (outf, "=(A0+=A1)"); 3139 } 3140 else if (aop == 3 && HL == 0 && aopcde == 16) 3141 OUTS (outf, "A1= ABS A0,A0= ABS A0"); 3142 3143 else if (aop == 0 && aopcde == 23 && HL == 1) 3144 { 3145 OUTS (outf, dregs (dst0)); 3146 OUTS (outf, "=BYTEOP3P("); 3147 OUTS (outf, dregs (src0 + 1)); 3148 OUTS (outf, ":"); 3149 OUTS (outf, imm5 (src0)); 3150 OUTS (outf, ","); 3151 OUTS (outf, dregs (src1 + 1)); 3152 OUTS (outf, ":"); 3153 OUTS (outf, imm5 (src1)); 3154 OUTS (outf, ")(HI"); 3155 if (s == 1) 3156 OUTS (outf, ", R)"); 3157 else 3158 OUTS (outf, ")"); 3159 } 3160 else if (aop == 3 && aopcde == 9 && s == 0) 3161 { 3162 OUTS (outf, "A1.x="); 3163 OUTS (outf, dregs_lo (src0)); 3164 } 3165 else if (aop == 1 && HL == 1 && aopcde == 16) 3166 OUTS (outf, "A1= ABS A1"); 3167 3168 else if (aop == 0 && HL == 1 && aopcde == 16) 3169 OUTS (outf, "A1= ABS A0"); 3170 3171 else if (aop == 2 && aopcde == 9 && s == 1) 3172 { 3173 OUTS (outf, "A1="); 3174 OUTS (outf, dregs (src0)); 3175 } 3176 else if (HL == 0 && aop == 3 && aopcde == 12) 3177 { 3178 OUTS (outf, dregs_lo (dst0)); 3179 OUTS (outf, "="); 3180 OUTS (outf, dregs (src0)); 3181 OUTS (outf, "(RND)"); 3182 } 3183 else if (aop == 1 && HL == 0 && aopcde == 16) 3184 OUTS (outf, "A0= ABS A1"); 3185 3186 else if (aop == 0 && HL == 0 && aopcde == 16) 3187 OUTS (outf, "A0= ABS A0"); 3188 3189 else if (aop == 3 && HL == 0 && aopcde == 15) 3190 { 3191 OUTS (outf, dregs (dst0)); 3192 OUTS (outf, "=-"); 3193 OUTS (outf, dregs (src0)); 3194 OUTS (outf, "(V)"); 3195 } 3196 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7) 3197 { 3198 OUTS (outf, dregs (dst0)); 3199 OUTS (outf, "=-"); 3200 OUTS (outf, dregs (src0)); 3201 OUTS (outf, "(S)"); 3202 } 3203 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7) 3204 { 3205 OUTS (outf, dregs (dst0)); 3206 OUTS (outf, "=-"); 3207 OUTS (outf, dregs (src0)); 3208 OUTS (outf, "(NS)"); 3209 } 3210 else if (aop == 1 && HL == 1 && aopcde == 11) 3211 { 3212 OUTS (outf, dregs_hi (dst0)); 3213 OUTS (outf, "=(A0+=A1)"); 3214 } 3215 else if (aop == 2 && aopcde == 11 && s == 0) 3216 OUTS (outf, "A0+=A1"); 3217 3218 else if (aop == 2 && aopcde == 11 && s == 1) 3219 OUTS (outf, "A0+=A1(W32)"); 3220 3221 else if (aop == 3 && HL == 0 && aopcde == 14) 3222 OUTS (outf, "A1=-A1,A0=-A0"); 3223 3224 else if (HL == 1 && aop == 3 && aopcde == 12) 3225 { 3226 OUTS (outf, dregs_hi (dst0)); 3227 OUTS (outf, "="); 3228 OUTS (outf, dregs (src0)); 3229 OUTS (outf, "(RND)"); 3230 } 3231 else if (aop == 0 && aopcde == 23 && HL == 0) 3232 { 3233 OUTS (outf, dregs (dst0)); 3234 OUTS (outf, "=BYTEOP3P("); 3235 OUTS (outf, dregs (src0 + 1)); 3236 OUTS (outf, ":"); 3237 OUTS (outf, imm5 (src0)); 3238 OUTS (outf, ","); 3239 OUTS (outf, dregs (src1 + 1)); 3240 OUTS (outf, ":"); 3241 OUTS (outf, imm5 (src1)); 3242 OUTS (outf, ")(LO"); 3243 if (s == 1) 3244 OUTS (outf, ", R)"); 3245 else 3246 OUTS (outf, ")"); 3247 } 3248 else if (aop == 0 && HL == 0 && aopcde == 14) 3249 OUTS (outf, "A0=-A0"); 3250 3251 else if (aop == 1 && HL == 0 && aopcde == 14) 3252 OUTS (outf, "A0=-A1"); 3253 3254 else if (aop == 0 && HL == 1 && aopcde == 14) 3255 OUTS (outf, "A1=-A0"); 3256 3257 else if (aop == 1 && HL == 1 && aopcde == 14) 3258 OUTS (outf, "A1=-A1"); 3259 3260 else if (aop == 0 && aopcde == 12) 3261 { 3262 OUTS (outf, dregs_hi (dst0)); 3263 OUTS (outf, "="); 3264 OUTS (outf, dregs_lo (dst0)); 3265 OUTS (outf, "=SIGN("); 3266 OUTS (outf, dregs_hi (src0)); 3267 OUTS (outf, ")*"); 3268 OUTS (outf, dregs_hi (src1)); 3269 OUTS (outf, "+SIGN("); 3270 OUTS (outf, dregs_lo (src0)); 3271 OUTS (outf, ")*"); 3272 OUTS (outf, dregs_lo (src1)); 3273 OUTS (outf, ")"); 3274 } 3275 else if (aop == 2 && aopcde == 0) 3276 { 3277 OUTS (outf, dregs (dst0)); 3278 OUTS (outf, "="); 3279 OUTS (outf, dregs (src0)); 3280 OUTS (outf, "-|+"); 3281 OUTS (outf, dregs (src1)); 3282 OUTS (outf, " "); 3283 amod0 (s, x, outf); 3284 } 3285 else if (aop == 1 && aopcde == 12) 3286 { 3287 OUTS (outf, dregs (dst1)); 3288 OUTS (outf, "=A1.L+A1.H,"); 3289 OUTS (outf, dregs (dst0)); 3290 OUTS (outf, "=A0.L+A0.H"); 3291 } 3292 else if (aop == 2 && aopcde == 4) 3293 { 3294 OUTS (outf, dregs (dst1)); 3295 OUTS (outf, "="); 3296 OUTS (outf, dregs (src0)); 3297 OUTS (outf, "+"); 3298 OUTS (outf, dregs (src1)); 3299 OUTS (outf, ","); 3300 OUTS (outf, dregs (dst0)); 3301 OUTS (outf, "="); 3302 OUTS (outf, dregs (src0)); 3303 OUTS (outf, "-"); 3304 OUTS (outf, dregs (src1)); 3305 OUTS (outf, " "); 3306 amod1 (s, x, outf); 3307 } 3308 else if (HL == 0 && aopcde == 1) 3309 { 3310 OUTS (outf, dregs (dst1)); 3311 OUTS (outf, "="); 3312 OUTS (outf, dregs (src0)); 3313 OUTS (outf, "+|+"); 3314 OUTS (outf, dregs (src1)); 3315 OUTS (outf, ","); 3316 OUTS (outf, dregs (dst0)); 3317 OUTS (outf, "="); 3318 OUTS (outf, dregs (src0)); 3319 OUTS (outf, "-|-"); 3320 OUTS (outf, dregs (src1)); 3321 amod0amod2 (s, x, aop, outf); 3322 } 3323 else if (aop == 0 && aopcde == 11) 3324 { 3325 OUTS (outf, dregs (dst0)); 3326 OUTS (outf, "=(A0+=A1)"); 3327 } 3328 else if (aop == 0 && aopcde == 10) 3329 { 3330 OUTS (outf, dregs_lo (dst0)); 3331 OUTS (outf, "=A0.x"); 3332 } 3333 else if (aop == 1 && aopcde == 10) 3334 { 3335 OUTS (outf, dregs_lo (dst0)); 3336 OUTS (outf, "=A1.x"); 3337 } 3338 else if (aop == 1 && aopcde == 0) 3339 { 3340 OUTS (outf, dregs (dst0)); 3341 OUTS (outf, "="); 3342 OUTS (outf, dregs (src0)); 3343 OUTS (outf, "+|-"); 3344 OUTS (outf, dregs (src1)); 3345 OUTS (outf, " "); 3346 amod0 (s, x, outf); 3347 } 3348 else if (aop == 3 && aopcde == 0) 3349 { 3350 OUTS (outf, dregs (dst0)); 3351 OUTS (outf, "="); 3352 OUTS (outf, dregs (src0)); 3353 OUTS (outf, "-|-"); 3354 OUTS (outf, dregs (src1)); 3355 OUTS (outf, " "); 3356 amod0 (s, x, outf); 3357 } 3358 else if (aop == 1 && aopcde == 4) 3359 { 3360 OUTS (outf, dregs (dst0)); 3361 OUTS (outf, "="); 3362 OUTS (outf, dregs (src0)); 3363 OUTS (outf, "-"); 3364 OUTS (outf, dregs (src1)); 3365 OUTS (outf, " "); 3366 amod1 (s, x, outf); 3367 } 3368 else if (aop == 0 && aopcde == 17) 3369 { 3370 OUTS (outf, dregs (dst1)); 3371 OUTS (outf, "=A1+A0,"); 3372 OUTS (outf, dregs (dst0)); 3373 OUTS (outf, "=A1-A0 "); 3374 amod1 (s, x, outf); 3375 } 3376 else if (aop == 1 && aopcde == 17) 3377 { 3378 OUTS (outf, dregs (dst1)); 3379 OUTS (outf, "=A0+A1,"); 3380 OUTS (outf, dregs (dst0)); 3381 OUTS (outf, "=A0-A1 "); 3382 amod1 (s, x, outf); 3383 } 3384 else if (aop == 0 && aopcde == 18) 3385 { 3386 OUTS (outf, "SAA("); 3387 OUTS (outf, dregs (src0 + 1)); 3388 OUTS (outf, ":"); 3389 OUTS (outf, imm5 (src0)); 3390 OUTS (outf, ","); 3391 OUTS (outf, dregs (src1 + 1)); 3392 OUTS (outf, ":"); 3393 OUTS (outf, imm5 (src1)); 3394 OUTS (outf, ") "); 3395 aligndir (s, outf); 3396 } 3397 else if (aop == 3 && aopcde == 18) 3398 OUTS (outf, "DISALGNEXCPT"); 3399 3400 else if (aop == 0 && aopcde == 20) 3401 { 3402 OUTS (outf, dregs (dst0)); 3403 OUTS (outf, "=BYTEOP1P("); 3404 OUTS (outf, dregs (src0 + 1)); 3405 OUTS (outf, ":"); 3406 OUTS (outf, imm5 (src0)); 3407 OUTS (outf, ","); 3408 OUTS (outf, dregs (src1 + 1)); 3409 OUTS (outf, ":"); 3410 OUTS (outf, imm5 (src1)); 3411 OUTS (outf, ")"); 3412 aligndir (s, outf); 3413 } 3414 else if (aop == 1 && aopcde == 20) 3415 { 3416 OUTS (outf, dregs (dst0)); 3417 OUTS (outf, "=BYTEOP1P("); 3418 OUTS (outf, dregs (src0 + 1)); 3419 OUTS (outf, ":"); 3420 OUTS (outf, imm5 (src0)); 3421 OUTS (outf, ","); 3422 OUTS (outf, dregs (src1 + 1)); 3423 OUTS (outf, ":"); 3424 OUTS (outf, imm5 (src1)); 3425 OUTS (outf, ")(T"); 3426 if (s == 1) 3427 OUTS (outf, ", R)"); 3428 else 3429 OUTS (outf, ")"); 3430 } 3431 else if (aop == 0 && aopcde == 21) 3432 { 3433 OUTS (outf, "("); 3434 OUTS (outf, dregs (dst1)); 3435 OUTS (outf, ","); 3436 OUTS (outf, dregs (dst0)); 3437 OUTS (outf, ")=BYTEOP16P("); 3438 OUTS (outf, dregs (src0 + 1)); 3439 OUTS (outf, ":"); 3440 OUTS (outf, imm5 (src0)); 3441 OUTS (outf, ","); 3442 OUTS (outf, dregs (src1 + 1)); 3443 OUTS (outf, ":"); 3444 OUTS (outf, imm5 (src1)); 3445 OUTS (outf, ") "); 3446 aligndir (s, outf); 3447 } 3448 else if (aop == 1 && aopcde == 21) 3449 { 3450 OUTS (outf, "("); 3451 OUTS (outf, dregs (dst1)); 3452 OUTS (outf, ","); 3453 OUTS (outf, dregs (dst0)); 3454 OUTS (outf, ")=BYTEOP16M("); 3455 OUTS (outf, dregs (src0 + 1)); 3456 OUTS (outf, ":"); 3457 OUTS (outf, imm5 (src0)); 3458 OUTS (outf, ","); 3459 OUTS (outf, dregs (src1 + 1)); 3460 OUTS (outf, ":"); 3461 OUTS (outf, imm5 (src1)); 3462 OUTS (outf, ") "); 3463 aligndir (s, outf); 3464 } 3465 else if (aop == 2 && aopcde == 7) 3466 { 3467 OUTS (outf, dregs (dst0)); 3468 OUTS (outf, "= ABS "); 3469 OUTS (outf, dregs (src0)); 3470 } 3471 else if (aop == 1 && aopcde == 7) 3472 { 3473 OUTS (outf, dregs (dst0)); 3474 OUTS (outf, "=MIN("); 3475 OUTS (outf, dregs (src0)); 3476 OUTS (outf, ","); 3477 OUTS (outf, dregs (src1)); 3478 OUTS (outf, ")"); 3479 } 3480 else if (aop == 0 && aopcde == 7) 3481 { 3482 OUTS (outf, dregs (dst0)); 3483 OUTS (outf, "=MAX("); 3484 OUTS (outf, dregs (src0)); 3485 OUTS (outf, ","); 3486 OUTS (outf, dregs (src1)); 3487 OUTS (outf, ")"); 3488 } 3489 else if (aop == 2 && aopcde == 6) 3490 { 3491 OUTS (outf, dregs (dst0)); 3492 OUTS (outf, "= ABS "); 3493 OUTS (outf, dregs (src0)); 3494 OUTS (outf, "(V)"); 3495 } 3496 else if (aop == 1 && aopcde == 6) 3497 { 3498 OUTS (outf, dregs (dst0)); 3499 OUTS (outf, "=MIN("); 3500 OUTS (outf, dregs (src0)); 3501 OUTS (outf, ","); 3502 OUTS (outf, dregs (src1)); 3503 OUTS (outf, ")(V)"); 3504 } 3505 else if (aop == 0 && aopcde == 6) 3506 { 3507 OUTS (outf, dregs (dst0)); 3508 OUTS (outf, "=MAX("); 3509 OUTS (outf, dregs (src0)); 3510 OUTS (outf, ","); 3511 OUTS (outf, dregs (src1)); 3512 OUTS (outf, ")(V)"); 3513 } 3514 else if (HL == 1 && aopcde == 1) 3515 { 3516 OUTS (outf, dregs (dst1)); 3517 OUTS (outf, "="); 3518 OUTS (outf, dregs (src0)); 3519 OUTS (outf, "+|-"); 3520 OUTS (outf, dregs (src1)); 3521 OUTS (outf, ","); 3522 OUTS (outf, dregs (dst0)); 3523 OUTS (outf, "="); 3524 OUTS (outf, dregs (src0)); 3525 OUTS (outf, "-|+"); 3526 OUTS (outf, dregs (src1)); 3527 amod0amod2 (s, x, aop, outf); 3528 } 3529 else if (aop == 0 && aopcde == 4) 3530 { 3531 OUTS (outf, dregs (dst0)); 3532 OUTS (outf, "="); 3533 OUTS (outf, dregs (src0)); 3534 OUTS (outf, "+"); 3535 OUTS (outf, dregs (src1)); 3536 OUTS (outf, " "); 3537 amod1 (s, x, outf); 3538 } 3539 else if (aop == 0 && aopcde == 0) 3540 { 3541 OUTS (outf, dregs (dst0)); 3542 OUTS (outf, "="); 3543 OUTS (outf, dregs (src0)); 3544 OUTS (outf, "+|+"); 3545 OUTS (outf, dregs (src1)); 3546 OUTS (outf, " "); 3547 amod0 (s, x, outf); 3548 } 3549 else if (aop == 0 && aopcde == 24) 3550 { 3551 OUTS (outf, dregs (dst0)); 3552 OUTS (outf, "=BYTEPACK("); 3553 OUTS (outf, dregs (src0)); 3554 OUTS (outf, ","); 3555 OUTS (outf, dregs (src1)); 3556 OUTS (outf, ")"); 3557 } 3558 else if (aop == 1 && aopcde == 24) 3559 { 3560 OUTS (outf, "("); 3561 OUTS (outf, dregs (dst1)); 3562 OUTS (outf, ","); 3563 OUTS (outf, dregs (dst0)); 3564 OUTS (outf, ") = BYTEUNPACK "); 3565 OUTS (outf, dregs (src0 + 1)); 3566 OUTS (outf, ":"); 3567 OUTS (outf, imm5 (src0)); 3568 OUTS (outf, " "); 3569 aligndir (s, outf); 3570 } 3571 else if (aopcde == 13) 3572 { 3573 OUTS (outf, "("); 3574 OUTS (outf, dregs (dst1)); 3575 OUTS (outf, ","); 3576 OUTS (outf, dregs (dst0)); 3577 OUTS (outf, ") = SEARCH "); 3578 OUTS (outf, dregs (src0)); 3579 OUTS (outf, "("); 3580 searchmod (aop, outf); 3581 OUTS (outf, ")"); 3582 } 3583 else 3584 return 0; 3585 3586 return 4; 3587} 3588 3589static int 3590decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) 3591{ 3592 /* dsp32shift 3593 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 3594 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| 3595 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| 3596 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 3597 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask); 3598 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask); 3599 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); 3600 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask); 3601 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask); 3602 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask); 3603 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1"; 3604 3605 if (HLs == 0 && sop == 0 && sopcde == 0) 3606 { 3607 OUTS (outf, dregs_lo (dst0)); 3608 OUTS (outf, "= ASHIFT "); 3609 OUTS (outf, dregs_lo (src1)); 3610 OUTS (outf, " BY "); 3611 OUTS (outf, dregs_lo (src0)); 3612 } 3613 else if (HLs == 1 && sop == 0 && sopcde == 0) 3614 { 3615 OUTS (outf, dregs_lo (dst0)); 3616 OUTS (outf, "= ASHIFT "); 3617 OUTS (outf, dregs_hi (src1)); 3618 OUTS (outf, " BY "); 3619 OUTS (outf, dregs_lo (src0)); 3620 } 3621 else if (HLs == 2 && sop == 0 && sopcde == 0) 3622 { 3623 OUTS (outf, dregs_hi (dst0)); 3624 OUTS (outf, "= ASHIFT "); 3625 OUTS (outf, dregs_lo (src1)); 3626 OUTS (outf, " BY "); 3627 OUTS (outf, dregs_lo (src0)); 3628 } 3629 else if (HLs == 3 && sop == 0 && sopcde == 0) 3630 { 3631 OUTS (outf, dregs_hi (dst0)); 3632 OUTS (outf, "= ASHIFT "); 3633 OUTS (outf, dregs_hi (src1)); 3634 OUTS (outf, " BY "); 3635 OUTS (outf, dregs_lo (src0)); 3636 } 3637 else if (HLs == 0 && sop == 1 && sopcde == 0) 3638 { 3639 OUTS (outf, dregs_lo (dst0)); 3640 OUTS (outf, "= ASHIFT "); 3641 OUTS (outf, dregs_lo (src1)); 3642 OUTS (outf, " BY "); 3643 OUTS (outf, dregs_lo (src0)); 3644 OUTS (outf, "(S)"); 3645 } 3646 else if (HLs == 1 && sop == 1 && sopcde == 0) 3647 { 3648 OUTS (outf, dregs_lo (dst0)); 3649 OUTS (outf, "= ASHIFT "); 3650 OUTS (outf, dregs_hi (src1)); 3651 OUTS (outf, " BY "); 3652 OUTS (outf, dregs_lo (src0)); 3653 OUTS (outf, "(S)"); 3654 } 3655 else if (HLs == 2 && sop == 1 && sopcde == 0) 3656 { 3657 OUTS (outf, dregs_hi (dst0)); 3658 OUTS (outf, "= ASHIFT "); 3659 OUTS (outf, dregs_lo (src1)); 3660 OUTS (outf, " BY "); 3661 OUTS (outf, dregs_lo (src0)); 3662 OUTS (outf, "(S)"); 3663 } 3664 else if (HLs == 3 && sop == 1 && sopcde == 0) 3665 { 3666 OUTS (outf, dregs_hi (dst0)); 3667 OUTS (outf, "= ASHIFT "); 3668 OUTS (outf, dregs_hi (src1)); 3669 OUTS (outf, " BY "); 3670 OUTS (outf, dregs_lo (src0)); 3671 OUTS (outf, "(S)"); 3672 } 3673 else if (sop == 2 && sopcde == 0) 3674 { 3675 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0)); 3676 OUTS (outf, "= LSHIFT "); 3677 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1)); 3678 OUTS (outf, " BY "); 3679 OUTS (outf, dregs_lo (src0)); 3680 } 3681 else if (sop == 0 && sopcde == 3) 3682 { 3683 OUTS (outf, acc01); 3684 OUTS (outf, "= ASHIFT "); 3685 OUTS (outf, acc01); 3686 OUTS (outf, " BY "); 3687 OUTS (outf, dregs_lo (src0)); 3688 } 3689 else if (sop == 1 && sopcde == 3) 3690 { 3691 OUTS (outf, acc01); 3692 OUTS (outf, "= LSHIFT "); 3693 OUTS (outf, acc01); 3694 OUTS (outf, " BY "); 3695 OUTS (outf, dregs_lo (src0)); 3696 } 3697 else if (sop == 2 && sopcde == 3) 3698 { 3699 OUTS (outf, acc01); 3700 OUTS (outf, "= ROT "); 3701 OUTS (outf, acc01); 3702 OUTS (outf, " BY "); 3703 OUTS (outf, dregs_lo (src0)); 3704 } 3705 else if (sop == 3 && sopcde == 3) 3706 { 3707 OUTS (outf, dregs (dst0)); 3708 OUTS (outf, "= ROT "); 3709 OUTS (outf, dregs (src1)); 3710 OUTS (outf, " BY "); 3711 OUTS (outf, dregs_lo (src0)); 3712 } 3713 else if (sop == 1 && sopcde == 1) 3714 { 3715 OUTS (outf, dregs (dst0)); 3716 OUTS (outf, "= ASHIFT "); 3717 OUTS (outf, dregs (src1)); 3718 OUTS (outf, " BY "); 3719 OUTS (outf, dregs_lo (src0)); 3720 OUTS (outf, "(V,S)"); 3721 } 3722 else if (sop == 0 && sopcde == 1) 3723 { 3724 OUTS (outf, dregs (dst0)); 3725 OUTS (outf, "= ASHIFT "); 3726 OUTS (outf, dregs (src1)); 3727 OUTS (outf, " BY "); 3728 OUTS (outf, dregs_lo (src0)); 3729 OUTS (outf, "(V)"); 3730 } 3731 else if (sop == 0 && sopcde == 2) 3732 { 3733 OUTS (outf, dregs (dst0)); 3734 OUTS (outf, "= ASHIFT "); 3735 OUTS (outf, dregs (src1)); 3736 OUTS (outf, " BY "); 3737 OUTS (outf, dregs_lo (src0)); 3738 } 3739 else if (sop == 1 && sopcde == 2) 3740 { 3741 OUTS (outf, dregs (dst0)); 3742 OUTS (outf, "= ASHIFT "); 3743 OUTS (outf, dregs (src1)); 3744 OUTS (outf, " BY "); 3745 OUTS (outf, dregs_lo (src0)); 3746 OUTS (outf, "(S)"); 3747 } 3748 else if (sop == 2 && sopcde == 2) 3749 { 3750 OUTS (outf, dregs (dst0)); 3751 OUTS (outf, "=SHIFT "); 3752 OUTS (outf, dregs (src1)); 3753 OUTS (outf, " BY "); 3754 OUTS (outf, dregs_lo (src0)); 3755 } 3756 else if (sop == 3 && sopcde == 2) 3757 { 3758 OUTS (outf, dregs (dst0)); 3759 OUTS (outf, "= ROT "); 3760 OUTS (outf, dregs (src1)); 3761 OUTS (outf, " BY "); 3762 OUTS (outf, dregs_lo (src0)); 3763 } 3764 else if (sop == 2 && sopcde == 1) 3765 { 3766 OUTS (outf, dregs (dst0)); 3767 OUTS (outf, "=SHIFT "); 3768 OUTS (outf, dregs (src1)); 3769 OUTS (outf, " BY "); 3770 OUTS (outf, dregs_lo (src0)); 3771 OUTS (outf, "(V)"); 3772 } 3773 else if (sop == 0 && sopcde == 4) 3774 { 3775 OUTS (outf, dregs (dst0)); 3776 OUTS (outf, "=PACK"); 3777 OUTS (outf, "("); 3778 OUTS (outf, dregs_lo (src1)); 3779 OUTS (outf, ","); 3780 OUTS (outf, dregs_lo (src0)); 3781 OUTS (outf, ")"); 3782 } 3783 else if (sop == 1 && sopcde == 4) 3784 { 3785 OUTS (outf, dregs (dst0)); 3786 OUTS (outf, "=PACK("); 3787 OUTS (outf, dregs_lo (src1)); 3788 OUTS (outf, ","); 3789 OUTS (outf, dregs_hi (src0)); 3790 OUTS (outf, ")"); 3791 } 3792 else if (sop == 2 && sopcde == 4) 3793 { 3794 OUTS (outf, dregs (dst0)); 3795 OUTS (outf, "=PACK("); 3796 OUTS (outf, dregs_hi (src1)); 3797 OUTS (outf, ","); 3798 OUTS (outf, dregs_lo (src0)); 3799 OUTS (outf, ")"); 3800 } 3801 else if (sop == 3 && sopcde == 4) 3802 { 3803 OUTS (outf, dregs (dst0)); 3804 OUTS (outf, "=PACK("); 3805 OUTS (outf, dregs_hi (src1)); 3806 OUTS (outf, ","); 3807 OUTS (outf, dregs_hi (src0)); 3808 OUTS (outf, ")"); 3809 } 3810 else if (sop == 0 && sopcde == 5) 3811 { 3812 OUTS (outf, dregs_lo (dst0)); 3813 OUTS (outf, "=SIGNBITS "); 3814 OUTS (outf, dregs (src1)); 3815 } 3816 else if (sop == 1 && sopcde == 5) 3817 { 3818 OUTS (outf, dregs_lo (dst0)); 3819 OUTS (outf, "=SIGNBITS "); 3820 OUTS (outf, dregs_lo (src1)); 3821 } 3822 else if (sop == 2 && sopcde == 5) 3823 { 3824 OUTS (outf, dregs_lo (dst0)); 3825 OUTS (outf, "=SIGNBITS "); 3826 OUTS (outf, dregs_hi (src1)); 3827 } 3828 else if (sop == 0 && sopcde == 6) 3829 { 3830 OUTS (outf, dregs_lo (dst0)); 3831 OUTS (outf, "=SIGNBITS A0"); 3832 } 3833 else if (sop == 1 && sopcde == 6) 3834 { 3835 OUTS (outf, dregs_lo (dst0)); 3836 OUTS (outf, "=SIGNBITS A1"); 3837 } 3838 else if (sop == 3 && sopcde == 6) 3839 { 3840 OUTS (outf, dregs_lo (dst0)); 3841 OUTS (outf, "=ONES "); 3842 OUTS (outf, dregs (src1)); 3843 } 3844 else if (sop == 0 && sopcde == 7) 3845 { 3846 OUTS (outf, dregs_lo (dst0)); 3847 OUTS (outf, "=EXPADJ ("); 3848 OUTS (outf, dregs (src1)); 3849 OUTS (outf, ","); 3850 OUTS (outf, dregs_lo (src0)); 3851 OUTS (outf, ")"); 3852 } 3853 else if (sop == 1 && sopcde == 7) 3854 { 3855 OUTS (outf, dregs_lo (dst0)); 3856 OUTS (outf, "=EXPADJ ("); 3857 OUTS (outf, dregs (src1)); 3858 OUTS (outf, ","); 3859 OUTS (outf, dregs_lo (src0)); 3860 OUTS (outf, ") (V)"); 3861 } 3862 else if (sop == 2 && sopcde == 7) 3863 { 3864 OUTS (outf, dregs_lo (dst0)); 3865 OUTS (outf, "=EXPADJ ("); 3866 OUTS (outf, dregs_lo (src1)); 3867 OUTS (outf, ","); 3868 OUTS (outf, dregs_lo (src0)); 3869 OUTS (outf, ")"); 3870 } 3871 else if (sop == 3 && sopcde == 7) 3872 { 3873 OUTS (outf, dregs_lo (dst0)); 3874 OUTS (outf, "=EXPADJ ("); 3875 OUTS (outf, dregs_hi (src1)); 3876 OUTS (outf, ","); 3877 OUTS (outf, dregs_lo (src0)); 3878 OUTS (outf, ")"); 3879 } 3880 else if (sop == 0 && sopcde == 8) 3881 { 3882 OUTS (outf, "BITMUX ("); 3883 OUTS (outf, dregs (src0)); 3884 OUTS (outf, ","); 3885 OUTS (outf, dregs (src1)); 3886 OUTS (outf, ",A0 )(ASR)"); 3887 } 3888 else if (sop == 1 && sopcde == 8) 3889 { 3890 OUTS (outf, "BITMUX ("); 3891 OUTS (outf, dregs (src0)); 3892 OUTS (outf, ","); 3893 OUTS (outf, dregs (src1)); 3894 OUTS (outf, ",A0 )(ASL)"); 3895 } 3896 else if (sop == 0 && sopcde == 9) 3897 { 3898 OUTS (outf, dregs_lo (dst0)); 3899 OUTS (outf, "=VIT_MAX ("); 3900 OUTS (outf, dregs (src1)); 3901 OUTS (outf, ") (ASL)"); 3902 } 3903 else if (sop == 1 && sopcde == 9) 3904 { 3905 OUTS (outf, dregs_lo (dst0)); 3906 OUTS (outf, "=VIT_MAX ("); 3907 OUTS (outf, dregs (src1)); 3908 OUTS (outf, ") (ASR)"); 3909 } 3910 else if (sop == 2 && sopcde == 9) 3911 { 3912 OUTS (outf, dregs (dst0)); 3913 OUTS (outf, "=VIT_MAX("); 3914 OUTS (outf, dregs (src1)); 3915 OUTS (outf, ","); 3916 OUTS (outf, dregs (src0)); 3917 OUTS (outf, ")(ASL)"); 3918 } 3919 else if (sop == 3 && sopcde == 9) 3920 { 3921 OUTS (outf, dregs (dst0)); 3922 OUTS (outf, "=VIT_MAX("); 3923 OUTS (outf, dregs (src1)); 3924 OUTS (outf, ","); 3925 OUTS (outf, dregs (src0)); 3926 OUTS (outf, ")(ASR)"); 3927 } 3928 else if (sop == 0 && sopcde == 10) 3929 { 3930 OUTS (outf, dregs (dst0)); 3931 OUTS (outf, "=EXTRACT("); 3932 OUTS (outf, dregs (src1)); 3933 OUTS (outf, ","); 3934 OUTS (outf, dregs_lo (src0)); 3935 OUTS (outf, ") (Z)"); 3936 } 3937 else if (sop == 1 && sopcde == 10) 3938 { 3939 OUTS (outf, dregs (dst0)); 3940 OUTS (outf, "=EXTRACT("); 3941 OUTS (outf, dregs (src1)); 3942 OUTS (outf, ","); 3943 OUTS (outf, dregs_lo (src0)); 3944 OUTS (outf, ")(X)"); 3945 } 3946 else if (sop == 2 && sopcde == 10) 3947 { 3948 OUTS (outf, dregs (dst0)); 3949 OUTS (outf, "=DEPOSIT("); 3950 OUTS (outf, dregs (src1)); 3951 OUTS (outf, ","); 3952 OUTS (outf, dregs (src0)); 3953 OUTS (outf, ")"); 3954 } 3955 else if (sop == 3 && sopcde == 10) 3956 { 3957 OUTS (outf, dregs (dst0)); 3958 OUTS (outf, "=DEPOSIT("); 3959 OUTS (outf, dregs (src1)); 3960 OUTS (outf, ","); 3961 OUTS (outf, dregs (src0)); 3962 OUTS (outf, ")(X)"); 3963 } 3964 else if (sop == 0 && sopcde == 11) 3965 { 3966 OUTS (outf, dregs_lo (dst0)); 3967 OUTS (outf, "=CC=BXORSHIFT(A0,"); 3968 OUTS (outf, dregs (src0)); 3969 OUTS (outf, ")"); 3970 } 3971 else if (sop == 1 && sopcde == 11) 3972 { 3973 OUTS (outf, dregs_lo (dst0)); 3974 OUTS (outf, "=CC=BXOR(A0,"); 3975 OUTS (outf, dregs (src0)); 3976 OUTS (outf, ")"); 3977 } 3978 else if (sop == 0 && sopcde == 12) 3979 OUTS (outf, "A0=BXORSHIFT(A0,A1 ,CC)"); 3980 3981 else if (sop == 1 && sopcde == 12) 3982 { 3983 OUTS (outf, dregs_lo (dst0)); 3984 OUTS (outf, "=CC=BXOR( A0,A1 ,CC )"); 3985 } 3986 else if (sop == 0 && sopcde == 13) 3987 { 3988 OUTS (outf, dregs (dst0)); 3989 OUTS (outf, "=ALIGN8("); 3990 OUTS (outf, dregs (src1)); 3991 OUTS (outf, ","); 3992 OUTS (outf, dregs (src0)); 3993 OUTS (outf, ")"); 3994 } 3995 else if (sop == 1 && sopcde == 13) 3996 { 3997 OUTS (outf, dregs (dst0)); 3998 OUTS (outf, "=ALIGN16("); 3999 OUTS (outf, dregs (src1)); 4000 OUTS (outf, ","); 4001 OUTS (outf, dregs (src0)); 4002 OUTS (outf, ")"); 4003 } 4004 else if (sop == 2 && sopcde == 13) 4005 { 4006 OUTS (outf, dregs (dst0)); 4007 OUTS (outf, "=ALIGN24("); 4008 OUTS (outf, dregs (src1)); 4009 OUTS (outf, ","); 4010 OUTS (outf, dregs (src0)); 4011 OUTS (outf, ")"); 4012 } 4013 else 4014 return 0; 4015 4016 return 4; 4017} 4018 4019static int 4020decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf) 4021{ 4022 /* dsp32shiftimm 4023 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 4024 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| 4025 |.sop...|.HLs...|.dst0......|.immag.................|.src1......| 4026 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 4027 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask); 4028 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask); 4029 int bit8 = ((iw1 >> 8) & 0x1); 4030 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask); 4031 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask); 4032 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask); 4033 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask); 4034 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask); 4035 4036 4037 if (sop == 0 && sopcde == 0) 4038 { 4039 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); 4040 OUTS (outf, " = "); 4041 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); 4042 OUTS (outf, " >>> "); 4043 OUTS (outf, uimm4 (newimmag)); 4044 } 4045 else if (sop == 1 && sopcde == 0 && bit8 == 0) 4046 { 4047 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); 4048 OUTS (outf, " = "); 4049 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); 4050 OUTS (outf, " << "); 4051 OUTS (outf, uimm4 (immag)); 4052 OUTS (outf, " (S)"); 4053 } 4054 else if (sop == 1 && sopcde == 0 && bit8 == 1) 4055 { 4056 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); 4057 OUTS (outf, " = "); 4058 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); 4059 OUTS (outf, " >>> "); 4060 OUTS (outf, uimm4 (newimmag)); 4061 OUTS (outf, " (S)"); 4062 } 4063 else if (sop == 2 && sopcde == 0 && bit8 == 0) 4064 { 4065 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); 4066 OUTS (outf, " = "); 4067 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); 4068 OUTS (outf, " << "); 4069 OUTS (outf, uimm4 (immag)); 4070 } 4071 else if (sop == 2 && sopcde == 0 && bit8 == 1) 4072 { 4073 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); 4074 OUTS (outf, " = "); 4075 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); 4076 OUTS (outf, " >> "); 4077 OUTS (outf, uimm4 (newimmag)); 4078 } 4079 else if (sop == 2 && sopcde == 3 && HLs == 1) 4080 { 4081 OUTS (outf, "A1= ROT A1 BY "); 4082 OUTS (outf, imm6 (immag)); 4083 } 4084 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0) 4085 { 4086 OUTS (outf, "A0=A0<<"); 4087 OUTS (outf, uimm5 (immag)); 4088 } 4089 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1) 4090 { 4091 OUTS (outf, "A0=A0>>>"); 4092 OUTS (outf, uimm5 (newimmag)); 4093 } 4094 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0) 4095 { 4096 OUTS (outf, "A1=A1<<"); 4097 OUTS (outf, uimm5 (immag)); 4098 } 4099 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1) 4100 { 4101 OUTS (outf, "A1=A1>>>"); 4102 OUTS (outf, uimm5 (newimmag)); 4103 } 4104 else if (sop == 1 && sopcde == 3 && HLs == 0) 4105 { 4106 OUTS (outf, "A0=A0>>"); 4107 OUTS (outf, uimm5 (newimmag)); 4108 } 4109 else if (sop == 1 && sopcde == 3 && HLs == 1) 4110 { 4111 OUTS (outf, "A1=A1>>"); 4112 OUTS (outf, uimm5 (newimmag)); 4113 } 4114 else if (sop == 2 && sopcde == 3 && HLs == 0) 4115 { 4116 OUTS (outf, "A0= ROT A0 BY "); 4117 OUTS (outf, imm6 (immag)); 4118 } 4119 else if (sop == 1 && sopcde == 1 && bit8 == 0) 4120 { 4121 OUTS (outf, dregs (dst0)); 4122 OUTS (outf, "="); 4123 OUTS (outf, dregs (src1)); 4124 OUTS (outf, "<<"); 4125 OUTS (outf, uimm5 (immag)); 4126 OUTS (outf, " (V, S)"); 4127 } 4128 else if (sop == 1 && sopcde == 1 && bit8 == 1) 4129 { 4130 OUTS (outf, dregs (dst0)); 4131 OUTS (outf, "="); 4132 OUTS (outf, dregs (src1)); 4133 OUTS (outf, ">>>"); 4134 OUTS (outf, imm5 (-immag)); 4135 OUTS (outf, " (V)"); 4136 } 4137 else if (sop == 2 && sopcde == 1 && bit8 == 1) 4138 { 4139 OUTS (outf, dregs (dst0)); 4140 OUTS (outf, "="); 4141 OUTS (outf, dregs (src1)); 4142 OUTS (outf, " >> "); 4143 OUTS (outf, uimm5 (newimmag)); 4144 OUTS (outf, " (V)"); 4145 } 4146 else if (sop == 2 && sopcde == 1 && bit8 == 0) 4147 { 4148 OUTS (outf, dregs (dst0)); 4149 OUTS (outf, "="); 4150 OUTS (outf, dregs (src1)); 4151 OUTS (outf, "<<"); 4152 OUTS (outf, imm5 (immag)); 4153 OUTS (outf, " (V)"); 4154 } 4155 else if (sop == 0 && sopcde == 1) 4156 { 4157 OUTS (outf, dregs (dst0)); 4158 OUTS (outf, "="); 4159 OUTS (outf, dregs (src1)); 4160 OUTS (outf, ">>>"); 4161 OUTS (outf, uimm5 (newimmag)); 4162 OUTS (outf, " (V)"); 4163 } 4164 else if (sop == 1 && sopcde == 2) 4165 { 4166 OUTS (outf, dregs (dst0)); 4167 OUTS (outf, "="); 4168 OUTS (outf, dregs (src1)); 4169 OUTS (outf, "<<"); 4170 OUTS (outf, uimm5 (immag)); 4171 OUTS (outf, "(S)"); 4172 } 4173 else if (sop == 2 && sopcde == 2 && bit8 == 1) 4174 { 4175 OUTS (outf, dregs (dst0)); 4176 OUTS (outf, "="); 4177 OUTS (outf, dregs (src1)); 4178 OUTS (outf, ">>"); 4179 OUTS (outf, uimm5 (newimmag)); 4180 } 4181 else if (sop == 2 && sopcde == 2 && bit8 == 0) 4182 { 4183 OUTS (outf, dregs (dst0)); 4184 OUTS (outf, "="); 4185 OUTS (outf, dregs (src1)); 4186 OUTS (outf, "<<"); 4187 OUTS (outf, uimm5 (immag)); 4188 } 4189 else if (sop == 3 && sopcde == 2) 4190 { 4191 OUTS (outf, dregs (dst0)); 4192 OUTS (outf, "= ROT "); 4193 OUTS (outf, dregs (src1)); 4194 OUTS (outf, " BY "); 4195 OUTS (outf, imm6 (immag)); 4196 } 4197 else if (sop == 0 && sopcde == 2) 4198 { 4199 OUTS (outf, dregs (dst0)); 4200 OUTS (outf, "="); 4201 OUTS (outf, dregs (src1)); 4202 OUTS (outf, ">>>"); 4203 OUTS (outf, uimm5 (newimmag)); 4204 } 4205 else 4206 return 0; 4207 4208 return 4; 4209} 4210 4211static int 4212decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf) 4213{ 4214 /* pseudoDEBUG 4215 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 4216 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| 4217 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 4218 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask); 4219 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask); 4220 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask); 4221 4222 if (reg == 0 && fn == 3) 4223 OUTS (outf, "DBG A0"); 4224 4225 else if (reg == 1 && fn == 3) 4226 OUTS (outf, "DBG A1"); 4227 4228 else if (reg == 3 && fn == 3) 4229 OUTS (outf, "ABORT"); 4230 4231 else if (reg == 4 && fn == 3) 4232 OUTS (outf, "HLT"); 4233 4234 else if (reg == 5 && fn == 3) 4235 OUTS (outf, "DBGHALT"); 4236 4237 else if (reg == 6 && fn == 3) 4238 { 4239 OUTS (outf, "DBGCMPLX("); 4240 OUTS (outf, dregs (grp)); 4241 OUTS (outf, ")"); 4242 } 4243 else if (reg == 7 && fn == 3) 4244 OUTS (outf, "DBG"); 4245 4246 else if (grp == 0 && fn == 2) 4247 { 4248 OUTS (outf, "OUTC"); 4249 OUTS (outf, dregs (reg)); 4250 } 4251 else if (fn == 0) 4252 { 4253 OUTS (outf, "DBG"); 4254 OUTS (outf, allregs (reg, grp)); 4255 } 4256 else if (fn == 1) 4257 { 4258 OUTS (outf, "PRNT"); 4259 OUTS (outf, allregs (reg, grp)); 4260 } 4261 else 4262 return 0; 4263 4264 return 2; 4265} 4266 4267static int 4268decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf) 4269{ 4270 /* pseudodbg_assert 4271 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 4272 | 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...| 4273 |.expected......................................................| 4274 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 4275 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask); 4276 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask); 4277 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask); 4278 4279 if (dbgop == 0) 4280 { 4281 OUTS (outf, "DBGA("); 4282 OUTS (outf, dregs_lo (regtest)); 4283 OUTS (outf, ","); 4284 OUTS (outf, uimm16 (expected)); 4285 OUTS (outf, ")"); 4286 } 4287 else if (dbgop == 1) 4288 { 4289 OUTS (outf, "DBGA("); 4290 OUTS (outf, dregs_hi (regtest)); 4291 OUTS (outf, ","); 4292 OUTS (outf, uimm16 (expected)); 4293 OUTS (outf, ")"); 4294 } 4295 else if (dbgop == 2) 4296 { 4297 OUTS (outf, "DBGAL("); 4298 OUTS (outf, dregs (regtest)); 4299 OUTS (outf, ","); 4300 OUTS (outf, uimm16 (expected)); 4301 OUTS (outf, ")"); 4302 } 4303 else if (dbgop == 3) 4304 { 4305 OUTS (outf, "DBGAH("); 4306 OUTS (outf, dregs (regtest)); 4307 OUTS (outf, ","); 4308 OUTS (outf, uimm16 (expected)); 4309 OUTS (outf, ")"); 4310 } 4311 else 4312 return 0; 4313 return 4; 4314} 4315 4316int 4317_print_insn_bfin (bfd_vma pc, disassemble_info *outf) 4318{ 4319 bfd_byte buf[4]; 4320 TIword iw0; 4321 TIword iw1; 4322 int status; 4323 int rv = 0; 4324 4325 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf); 4326 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf); 4327 4328 iw0 = bfd_getl16 (buf); 4329 iw1 = bfd_getl16 (buf + 2); 4330 4331 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800) 4332 { 4333 OUTS (outf, "mnop"); 4334 return 4; 4335 } 4336 else if ((iw0 & 0xff00) == 0x0000) 4337 rv = decode_ProgCtrl_0 (iw0, outf); 4338 else if ((iw0 & 0xffc0) == 0x0240) 4339 rv = decode_CaCTRL_0 (iw0, outf); 4340 else if ((iw0 & 0xff80) == 0x0100) 4341 rv = decode_PushPopReg_0 (iw0, outf); 4342 else if ((iw0 & 0xfe00) == 0x0400) 4343 rv = decode_PushPopMultiple_0 (iw0, outf); 4344 else if ((iw0 & 0xfe00) == 0x0600) 4345 rv = decode_ccMV_0 (iw0, outf); 4346 else if ((iw0 & 0xf800) == 0x0800) 4347 rv = decode_CCflag_0 (iw0, outf); 4348 else if ((iw0 & 0xffe0) == 0x0200) 4349 rv = decode_CC2dreg_0 (iw0, outf); 4350 else if ((iw0 & 0xff00) == 0x0300) 4351 rv = decode_CC2stat_0 (iw0, outf); 4352 else if ((iw0 & 0xf000) == 0x1000) 4353 rv = decode_BRCC_0 (iw0, pc, outf); 4354 else if ((iw0 & 0xf000) == 0x2000) 4355 rv = decode_UJUMP_0 (iw0, pc, outf); 4356 else if ((iw0 & 0xf000) == 0x3000) 4357 rv = decode_REGMV_0 (iw0, outf); 4358 else if ((iw0 & 0xfc00) == 0x4000) 4359 rv = decode_ALU2op_0 (iw0, outf); 4360 else if ((iw0 & 0xfe00) == 0x4400) 4361 rv = decode_PTR2op_0 (iw0, outf); 4362 else if ((iw0 & 0xf800) == 0x4800) 4363 rv = decode_LOGI2op_0 (iw0, outf); 4364 else if ((iw0 & 0xf000) == 0x5000) 4365 rv = decode_COMP3op_0 (iw0, outf); 4366 else if ((iw0 & 0xf800) == 0x6000) 4367 rv = decode_COMPI2opD_0 (iw0, outf); 4368 else if ((iw0 & 0xf800) == 0x6800) 4369 rv = decode_COMPI2opP_0 (iw0, outf); 4370 else if ((iw0 & 0xf000) == 0x8000) 4371 rv = decode_LDSTpmod_0 (iw0, outf); 4372 else if ((iw0 & 0xff60) == 0x9e60) 4373 rv = decode_dagMODim_0 (iw0, outf); 4374 else if ((iw0 & 0xfff0) == 0x9f60) 4375 rv = decode_dagMODik_0 (iw0, outf); 4376 else if ((iw0 & 0xfc00) == 0x9c00) 4377 rv = decode_dspLDST_0 (iw0, outf); 4378 else if ((iw0 & 0xf000) == 0x9000) 4379 rv = decode_LDST_0 (iw0, outf); 4380 else if ((iw0 & 0xfc00) == 0xb800) 4381 rv = decode_LDSTiiFP_0 (iw0, outf); 4382 else if ((iw0 & 0xe000) == 0xA000) 4383 rv = decode_LDSTii_0 (iw0, outf); 4384 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000) 4385 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf); 4386 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000) 4387 rv = decode_LDIMMhalf_0 (iw0, iw1, outf); 4388 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000) 4389 rv = decode_CALLa_0 (iw0, iw1, pc, outf); 4390 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000) 4391 rv = decode_LDSTidxI_0 (iw0, iw1, outf); 4392 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000) 4393 rv = decode_linkage_0 (iw0, iw1, outf); 4394 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000) 4395 rv = decode_dsp32mac_0 (iw0, iw1, outf); 4396 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000) 4397 rv = decode_dsp32mult_0 (iw0, iw1, outf); 4398 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000) 4399 rv = decode_dsp32alu_0 (iw0, iw1, outf); 4400 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000) 4401 rv = decode_dsp32shift_0 (iw0, iw1, outf); 4402 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000) 4403 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf); 4404 else if ((iw0 & 0xff00) == 0xf800) 4405 rv = decode_pseudoDEBUG_0 (iw0, outf); 4406#if 0 4407 else if ((iw0 & 0xFF00) == 0xF900) 4408 rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf); 4409#endif 4410 else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000) 4411 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf); 4412 4413 return rv; 4414} 4415 4416 4417int 4418print_insn_bfin (bfd_vma pc, disassemble_info *outf) 4419{ 4420 bfd_byte buf[2]; 4421 unsigned short iw0; 4422 int status; 4423 int count = 0; 4424 4425 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf); 4426 iw0 = bfd_getl16 (buf); 4427 4428 count += _print_insn_bfin (pc, outf); 4429 4430 /* Proper display of multiple issue instructions. */ 4431 4432 if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS) 4433 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ )) 4434 { 4435 outf->fprintf_func (outf->stream, " || "); 4436 count += _print_insn_bfin (pc + 4, outf); 4437 outf->fprintf_func (outf->stream, " || "); 4438 count += _print_insn_bfin (pc + 6, outf); 4439 } 4440 if (count == 0) 4441 { 4442 outf->fprintf_func (outf->stream, "ILLEGAL"); 4443 return 2; 4444 } 4445 outf->fprintf_func (outf->stream, ";"); 4446 return count; 4447} 4448