12007-01-08 Kazu Hirata <kazu@codesourcery.com> 2 3 * m68k.h (m68010up): OR fido_a. 4 52006-12-25 Kazu Hirata <kazu@codesourcery.com> 6 7 * m68k.h (fido_a): New. 8 92006-12-24 Kazu Hirata <kazu@codesourcery.com> 10 11 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, 12 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined 13 values. 14 152006-11-08 H.J. Lu <hongjiu.lu@intel.com> 16 17 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. 18 192006-10-31 Mei Ligang <ligang@sunnorth.com.cn> 20 21 * score-inst.h (enum score_insn_type): Add Insn_internal. 22 232006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> 24 Yukishige Shibata <shibata@rd.scei.sony.co.jp> 25 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> 26 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> 27 Alan Modra <amodra@bigpond.net.au> 28 29 * spu-insns.h: New file. 30 * spu.h: New file. 31 322006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> 33 34 * ppc.h (PPC_OPCODE_CELL): Define. 35 362006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 37 38 * i386.h : Modify opcode to support for the change in POPCNT opcode 39 in amdfam10 architecture. 40 412006-09-28 H.J. Lu <hongjiu.lu@intel.com> 42 43 * i386.h: Replace CpuMNI with CpuSSSE3. 44 452006-09-26 Mark Shinwell <shinwell@codesourcery.com> 46 Joseph Myers <joseph@codesourcery.com> 47 Ian Lance Taylor <ian@wasabisystems.com> 48 Ben Elliston <bje@wasabisystems.com> 49 50 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. 51 522006-09-17 Mei Ligang <ligang@sunnorth.com.cn> 53 54 * score-datadep.h: New file. 55 * score-inst.h: New file. 56 572006-07-14 H.J. Lu <hongjiu.lu@intel.com> 58 59 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, 60 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, 61 movdq2q and movq2dq. 62 632006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 64 Michael Meissner <michael.meissner@amd.com> 65 66 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). 67 682006-06-12 H.J. Lu <hongjiu.lu@intel.com> 69 70 * i386.h (i386_optab): Add "nop" with memory reference. 71 722006-06-12 H.J. Lu <hongjiu.lu@intel.com> 73 74 * i386.h (i386_optab): Update comment for 64bit NOP. 75 762006-06-06 Ben Elliston <bje@au.ibm.com> 77 Anton Blanchard <anton@samba.org> 78 79 * ppc.h (PPC_OPCODE_POWER6): Define. 80 Adjust whitespace. 81 822006-06-05 Thiemo Seufer <ths@mips.com> 83 84 * mips.h: Improve description of MT flags. 85 862006-05-25 Richard Sandiford <richard@codesourcery.com> 87 88 * m68k.h (mcf_mask): Define. 89 902006-05-05 Thiemo Seufer <ths@mips.com> 91 David Ung <davidu@mips.com> 92 93 * mips.h (enum): Add macro M_CACHE_AB. 94 952006-05-04 Thiemo Seufer <ths@mips.com> 96 Nigel Stephens <nigel@mips.com> 97 David Ung <davidu@mips.com> 98 99 * mips.h: Add INSN_SMARTMIPS define. 100 1012006-04-30 Thiemo Seufer <ths@mips.com> 102 David Ung <davidu@mips.com> 103 104 * mips.h: Defines udi bits and masks. Add description of 105 characters which may appear in the args field of udi 106 instructions. 107 1082006-04-26 Thiemo Seufer <ths@networkno.de> 109 110 * mips.h: Improve comments describing the bitfield instruction 111 fields. 112 1132006-04-26 Julian Brown <julian@codesourcery.com> 114 115 * arm.h (FPU_VFP_EXT_V3): Define constant. 116 (FPU_NEON_EXT_V1): Likewise. 117 (FPU_VFP_HARD): Update. 118 (FPU_VFP_V3): Define macro. 119 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. 120 1212006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> 122 123 * avr.h (AVR_ISA_PWMx): New. 124 1252006-03-28 Nathan Sidwell <nathan@codesourcery.com> 126 127 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, 128 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, 129 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, 130 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, 131 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. 132 1332006-03-10 Paul Brook <paul@codesourcery.com> 134 135 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. 136 1372006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 138 139 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come 140 first. Correct mask of bb "B" opcode. 141 1422006-02-27 H.J. Lu <hongjiu.lu@intel.com> 143 144 * i386.h (i386_optab): Support Intel Merom New Instructions. 145 1462006-02-24 Paul Brook <paul@codesourcery.com> 147 148 * arm.h: Add V7 feature bits. 149 1502006-02-23 H.J. Lu <hongjiu.lu@intel.com> 151 152 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. 153 1542006-01-31 Paul Brook <paul@codesourcery.com> 155 Richard Earnshaw <rearnsha@arm.com> 156 157 * arm.h: Use ARM_CPU_FEATURE. 158 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. 159 (arm_feature_set): Change to a structure. 160 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, 161 ARM_FEATURE): New macros. 162 1632005-12-07 Hans-Peter Nilsson <hp@axis.com> 164 165 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) 166 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. 167 (ADD_PC_INCR_OPCODE): Don't define. 168 1692005-12-06 H.J. Lu <hongjiu.lu@intel.com> 170 171 PR gas/1874 172 * i386.h (i386_optab): Add 64bit support for monitor and mwait. 173 1742005-11-14 David Ung <davidu@mips.com> 175 176 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore 177 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for 178 save/restore encoding of the args field. 179 1802005-10-28 Dave Brolley <brolley@redhat.com> 181 182 Contribute the following changes: 183 2005-02-16 Dave Brolley <brolley@redhat.com> 184 185 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename 186 cgen_isa_mask_* to cgen_bitset_*. 187 * cgen.h: Likewise. 188 189 2003-10-21 Richard Sandiford <rsandifo@redhat.com> 190 191 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. 192 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". 193 (CGEN_CPU_TABLE): Make isas a ponter. 194 195 2003-09-29 Dave Brolley <brolley@redhat.com> 196 197 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. 198 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. 199 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. 200 201 2002-12-13 Dave Brolley <brolley@redhat.com> 202 203 * cgen.h (symcat.h): #include it. 204 (cgen-bitset.h): #include it. 205 (CGEN_ATTR_VALUE_TYPE): Now a union. 206 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. 207 (CGEN_ATTR_ENTRY): 'value' now unsigned. 208 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). 209 * cgen-bitset.h: New file. 210 2112005-09-30 Catherine Moore <clm@cm00re.com> 212 213 * bfin.h: New file. 214 2152005-10-24 Jan Beulich <jbeulich@novell.com> 216 217 * ia64.h (enum ia64_opnd): Move memory operand out of set of 218 indirect operands. 219 2202005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 221 222 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. 223 Add FLAG_STRICT to pa10 ftest opcode. 224 2252005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 226 227 * hppa.h (pa_opcodes): Remove lha entries. 228 2292005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 230 231 * hppa.h (FLAG_STRICT): Revise comment. 232 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants 233 before corresponding pa11 opcodes. Add strict pa10 register-immediate 234 entries for "fdc". 235 2362005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 237 238 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. 239 2402005-09-06 Chao-ying Fu <fu@mips.com> 241 242 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, 243 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New 244 define. 245 Document !, $, *, &, g, +t, +T operand formats for MT instructions. 246 (INSN_ASE_MASK): Update to include INSN_MT. 247 (INSN_MT): New define for MT ASE. 248 2492005-08-25 Chao-ying Fu <fu@mips.com> 250 251 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, 252 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, 253 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, 254 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, 255 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. 256 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP 257 instructions. 258 (INSN_DSP): New define for DSP ASE. 259 2602005-08-18 Alan Modra <amodra@bigpond.net.au> 261 262 * a29k.h: Delete. 263 2642005-08-15 Daniel Jacobowitz <dan@codesourcery.com> 265 266 * ppc.h (PPC_OPCODE_E300): Define. 267 2682005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> 269 270 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. 271 2722005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 273 274 PR gas/336 275 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb 276 and pitlb. 277 2782005-07-27 Jan Beulich <jbeulich@novell.com> 279 280 * i386.h (i386_optab): Add comment to movd. Use LongMem for all 281 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. 282 Add movq-s as 64-bit variants of movd-s. 283 2842005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 285 286 * hppa.h: Fix punctuation in comment. 287 288 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for 289 implicit space-register addressing. Set space-register bits on opcodes 290 using implicit space-register addressing. Add various missing pa20 291 long-immediate opcodes. Remove various opcodes using implicit 3-bit 292 space-register addressing. Use "fE" instead of "fe" in various 293 fstw opcodes. 294 2952005-07-18 Jan Beulich <jbeulich@novell.com> 296 297 * i386.h (i386_optab): Operands of aam and aad are unsigned. 298 2992007-07-15 H.J. Lu <hongjiu.lu@intel.com> 300 301 * i386.h (i386_optab): Support Intel VMX Instructions. 302 3032005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 304 305 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. 306 3072005-07-05 Jan Beulich <jbeulich@novell.com> 308 309 * i386.h (i386_optab): Add new insns. 310 3112005-07-01 Nick Clifton <nickc@redhat.com> 312 313 * sparc.h: Add typedefs to structure declarations. 314 3152005-06-20 H.J. Lu <hongjiu.lu@intel.com> 316 317 PR 1013 318 * i386.h (i386_optab): Update comments for 64bit addressing on 319 mov. Allow 64bit addressing for mov and movq. 320 3212005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 322 323 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, 324 respectively, in various floating-point load and store patterns. 325 3262005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 327 328 * hppa.h (FLAG_STRICT): Correct comment. 329 (pa_opcodes): Update load and store entries to allow both PA 1.X and 330 PA 2.0 mneumonics when equivalent. Entries with cache control 331 completers now require PA 1.1. Adjust whitespace. 332 3332005-05-19 Anton Blanchard <anton@samba.org> 334 335 * ppc.h (PPC_OPCODE_POWER5): Define. 336 3372005-05-10 Nick Clifton <nickc@redhat.com> 338 339 * Update the address and phone number of the FSF organization in 340 the GPL notices in the following files: 341 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, 342 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, 343 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, 344 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, 345 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, 346 tic54x.h, tic80.h, v850.h, vax.h 347 3482005-05-09 Jan Beulich <jbeulich@novell.com> 349 350 * i386.h (i386_optab): Add ht and hnt. 351 3522005-04-18 Mark Kettenis <kettenis@gnu.org> 353 354 * i386.h: Insert hyphens into selected VIA PadLock extensions. 355 Add xcrypt-ctr. Provide aliases without hyphens. 356 3572005-04-13 H.J. Lu <hongjiu.lu@intel.com> 358 359 Moved from ../ChangeLog 360 361 2005-04-12 Paul Brook <paul@codesourcery.com> 362 * m88k.h: Rename psr macros to avoid conflicts. 363 364 2005-03-12 Zack Weinberg <zack@codesourcery.com> 365 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. 366 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, 367 and ARM_ARCH_V6ZKT2. 368 369 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> 370 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. 371 Remove redundant instruction types. 372 (struct argument): X_op - new field. 373 (struct cst4_entry): Remove. 374 (no_op_insn): Declare. 375 376 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> 377 * crx.h (enum argtype): Rename types, remove unused types. 378 379 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> 380 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. 381 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. 382 (enum operand_type): Rearrange operands, edit comments. 383 replace us<N> with ui<N> for unsigned immediate. 384 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped 385 displacements (respectively). 386 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. 387 (instruction type): Add NO_TYPE_INS. 388 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. 389 (operand_entry): New field - 'flags'. 390 (operand flags): New. 391 392 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> 393 * crx.h (operand_type): Remove redundant types i3, i4, 394 i5, i8, i12. 395 Add new unsigned immediate types us3, us4, us5, us16. 396 3972005-04-12 Mark Kettenis <kettenis@gnu.org> 398 399 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and 400 adjust them accordingly. 401 4022005-04-01 Jan Beulich <jbeulich@novell.com> 403 404 * i386.h (i386_optab): Add rdtscp. 405 4062005-03-29 H.J. Lu <hongjiu.lu@intel.com> 407 408 * i386.h (i386_optab): Don't allow the `l' suffix for moving 409 between memory and segment register. Allow movq for moving between 410 general-purpose register and segment register. 411 4122005-02-09 Jan Beulich <jbeulich@novell.com> 413 414 PR gas/707 415 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and 416 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and 417 fnstsw. 418 4192006-02-07 Nathan Sidwell <nathan@codesourcery.com> 420 421 * m68k.h (m68008, m68ec030, m68882): Remove. 422 (m68k_mask): New. 423 (cpu_m68k, cpu_cf): New. 424 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, 425 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. 426 4272005-01-25 Alexandre Oliva <aoliva@redhat.com> 428 429 2004-11-10 Alexandre Oliva <aoliva@redhat.com> 430 * cgen.h (enum cgen_parse_operand_type): Add 431 CGEN_PARSE_OPERAND_SYMBOLIC. 432 4332005-01-21 Fred Fish <fnf@specifixinc.com> 434 435 * mips.h: Change INSN_ALIAS to INSN2_ALIAS. 436 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. 437 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. 438 4392005-01-19 Fred Fish <fnf@specifixinc.com> 440 441 * mips.h (struct mips_opcode): Add new pinfo2 member. 442 (INSN_ALIAS): New define for opcode table entries that are 443 specific instances of another entry, such as 'move' for an 'or' 444 with a zero operand. 445 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. 446 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. 447 4482004-12-09 Ian Lance Taylor <ian@wasabisystems.com> 449 450 * mips.h (CPU_RM9000): Define. 451 (OPCODE_IS_MEMBER): Handle CPU_RM9000. 452 4532004-11-25 Jan Beulich <jbeulich@novell.com> 454 455 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves 456 to/from test registers are illegal in 64-bit mode. Add missing 457 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix 458 (previously one had to explicitly encode a rex64 prefix). Re-enable 459 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings 460 support it there. Add cmpxchg16b as per Intel's 64-bit documentation. 461 4622004-11-23 Jan Beulich <jbeulich@novell.com> 463 464 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are 465 available only with SSE2. Change the MMX additions introduced by SSE 466 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A 467 instructions by their now designated identifier (since combining i686 468 and 3DNow! does not really imply 3DNow!A). 469 4702004-11-19 Alan Modra <amodra@bigpond.net.au> 471 472 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, 473 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. 474 4752004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> 476 Vineet Sharma <vineets@noida.hcltech.com> 477 478 * maxq.h: New file: Disassembly information for the maxq port. 479 4802004-11-05 H.J. Lu <hongjiu.lu@intel.com> 481 482 * i386.h (i386_optab): Put back "movzb". 483 4842004-11-04 Hans-Peter Nilsson <hp@axis.com> 485 486 * cris.h (enum cris_insn_version_usage): Tweak formatting and 487 comments. Remove member cris_ver_sim. Add members 488 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, 489 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. 490 (struct cris_support_reg, struct cris_cond15): New types. 491 (cris_conds15): Declare. 492 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) 493 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) 494 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. 495 (NOP_Z_BITS): Define in terms of NOP_OPCODE. 496 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and 497 SIZE_FIELD_UNSIGNED. 498 4992004-11-04 Jan Beulich <jbeulich@novell.com> 500 501 * i386.h (sldx_Suf): Remove. 502 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. 503 (q_FP): Define, implying no REX64. 504 (x_FP, sl_FP): Imply FloatMF. 505 (i386_optab): Split reg and mem forms of moving from segment registers 506 so that the memory forms can ignore the 16-/32-bit operand size 507 distinction. Adjust a few others for Intel mode. Remove *FP uses from 508 all non-floating-point instructions. Unite 32- and 64-bit forms of 509 movsx, movzx, and movd. Adjust floating point operations for the above 510 changes to the *FP macros. Add DefaultSize to floating point control 511 insns operating on larger memory ranges. Remove left over comments 512 hinting at certain insns being Intel-syntax ones where the ones 513 actually meant are already gone. 514 5152004-10-07 Tomer Levi <Tomer.Levi@nsc.com> 516 517 * crx.h: Add COPS_REG_INS - Coprocessor Special register 518 instruction type. 519 5202004-09-30 Paul Brook <paul@codesourcery.com> 521 522 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. 523 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. 524 5252004-09-11 Theodore A. Roth <troth@openavr.org> 526 527 * avr.h: Add support for 528 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. 529 5302004-09-09 Segher Boessenkool <segher@kernel.crashing.org> 531 532 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. 533 5342004-08-24 Dmitry Diky <diwil@spec.ru> 535 536 * msp430.h (msp430_opc): Add new instructions. 537 (msp430_rcodes): Declare new instructions. 538 (msp430_hcodes): Likewise.. 539 5402004-08-13 Nick Clifton <nickc@redhat.com> 541 542 PR/301 543 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX 544 processors. 545 5462004-08-30 Michal Ludvig <mludvig@suse.cz> 547 548 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. 549 5502004-07-22 H.J. Lu <hongjiu.lu@intel.com> 551 552 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. 553 5542004-07-21 Jan Beulich <jbeulich@novell.com> 555 556 * i386.h: Adjust instruction descriptions to better match the 557 specification. 558 5592004-07-16 Richard Earnshaw <rearnsha@arm.com> 560 561 * arm.h: Remove all old content. Replace with architecture defines 562 from gas/config/tc-arm.c. 563 5642004-07-09 Andreas Schwab <schwab@suse.de> 565 566 * m68k.h: Fix comment. 567 5682004-07-07 Tomer Levi <Tomer.Levi@nsc.com> 569 570 * crx.h: New file. 571 5722004-06-24 Alan Modra <amodra@bigpond.net.au> 573 574 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. 575 5762004-05-24 Peter Barada <peter@the-baradas.com> 577 578 * m68k.h: Add 'size' to m68k_opcode. 579 5802004-05-05 Peter Barada <peter@the-baradas.com> 581 582 * m68k.h: Switch from ColdFire chip name to core variant. 583 5842004-04-22 Peter Barada <peter@the-baradas.com> 585 586 * m68k.h: Add mcfmac/mcfemac definitions. Update operand 587 descriptions for new EMAC cases. 588 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly 589 handle Motorola MAC syntax. 590 Allow disassembly of ColdFire V4e object files. 591 5922004-03-16 Alan Modra <amodra@bigpond.net.au> 593 594 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. 595 5962004-03-12 Jakub Jelinek <jakub@redhat.com> 597 598 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. 599 6002004-03-12 Michal Ludvig <mludvig@suse.cz> 601 602 * i386.h (i386_optab): Added xstore as an alias for xstorerng. 603 6042004-03-12 Michal Ludvig <mludvig@suse.cz> 605 606 * i386.h (i386_optab): Added xstore/xcrypt insns. 607 6082004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> 609 610 * h8300.h (32bit ldc/stc): Add relaxing support. 611 6122004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> 613 614 * h8300.h (BITOP): Pass MEMRELAX flag. 615 6162004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> 617 618 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 619 except for the H8S. 620 621For older changes see ChangeLog-9103 622 623Local Variables: 624mode: change-log 625left-margin: 8 626fill-column: 74 627version-control: never 628End: 629