1/*
2 * Copyright © 2009 Apple Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1.  Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
11 * 2.  Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 * 3.  Neither the name of Apple Inc. ("Apple") nor the names of its
15 * contributors may be used to endorse or promote products derived from this
16 * software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY APPLE AND ITS CONTRIBUTORS "AS IS" AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL APPLE OR ITS CONTRIBUTORS BE LIABLE FOR ANY
22 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * @APPLE_LICENSE_HEADER_END@
30 */
31/*
32 * This file contains the i386 disassembler routine used at NeXT Computer, Inc.
33 * to match the the assembler used at NeXT.  It was addapted from a set of
34 * source files with the following copyright which is retained below.
35 */
36/*
37  Copyright 1988, 1989 by Intel Corporation, Santa Clara, California.
38
39		All Rights Reserved
40
41Permission to use, copy, modify, and distribute this software and
42its documentation for any purpose and without fee is hereby
43granted, provided that the above copyright notice appears in all
44copies and that both the copyright notice and this permission notice
45appear in supporting documentation, and that the name of Intel
46not be used in advertising or publicity pertaining to distribution
47of the software without specific, written prior permission.
48
49INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
50INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
51IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
52CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
53LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
54NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
55WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56*/
57#include <stdio.h>
58#include <string.h>
59#include <mach-o/loader.h>
60#include <mach-o/nlist.h>
61#include <mach-o/reloc.h>
62#include <mach-o/x86_64/reloc.h>
63#include "stuff/symbol.h"
64#include "stuff/bytesex.h"
65#include "stuff/llvm.h"
66#include "otool.h"
67#include "ofile_print.h"
68#include "i386_disasm.h"
69
70#define MAX_MNEMONIC	16	/* Maximum number of chars per mnemonic, plus a byte for '\0' */
71#define MAX_RESULT	14	/* Maximum number of char in a register */
72				/*  result expression "(%ebx,%ecx,8)" */
73
74#define WBIT(x)	(x & 0x1)		/* to get w bit	*/
75#define REGNO(x) (x & 0x7)		/* to get 3 bit register */
76#define VBIT(x)	((x)>>1 & 0x1)		/* to get 'v' bit */
77#define OPSIZE(data16,wbit,maybe64) ((wbit) ? ((data16) ? 2: ((maybe64) ? 8 : 4)) : 1 )
78#define REX_W(x) (((x) & 0x8) == 0x8)	/* true if the REX.W bit is set --> 64-bit operand size */
79#define REX_R(x) (((x) & 0x4) == 0x4)	/* true if the REX.R bit is set --> ModRM reg extension */
80#define REX_X(x) (((x) & 0x2) == 0x2)	/* true if the REX.X bit is set --> SIB index extension */
81#define REX_B(x) (((x) & 0x1) == 0x1)	/* true if the REX.B bit is set --> ModRM r/m, SIB base, or opcode reg extension */
82
83#define REG_ONLY 3	/* mode indicates a single register with	*/
84			/* no displacement is an operand		*/
85#define BYTEOPERAND 0	/* value of the w-bit indicating a byte		*/
86			/* operand (1-byte)				*/
87#define LONGOPERAND 1	/* value of the w-bit indicating a long		*/
88			/* operand (2-bytes or 4-bytes)			*/
89#define EBP 5
90#define ESP 4
91
92/*
93 * This is the structure that is used for storing all the op code information.
94 */
95struct instable {
96    char name[MAX_MNEMONIC];
97    const struct instable *indirect;
98    unsigned adr_mode;
99    int flags;
100    const struct instable *arch64;
101};
102#define	TERM	0	/* used to indicate that the 'indirect' field of the */
103			/* 'instable' terminates - no pointer.	*/
104#define	INVALID	{"",TERM,UNKNOWN,0}
105/*
106 * These are defined this way to make the initializations in the tables simpler
107 * and more readable for differences between 32-bit and 64-bit architectures.
108 */
109#define	INVALID_32 "",TERM,UNKNOWN,0
110static const struct instable op_invalid_64 = {"",TERM,/* UNKNOWN */0,0};
111#define INVALID_64 (&op_invalid_64)
112
113/* Flags */
114#define HAS_SUFFIX			0x1	/* For instructions which may have a 'w', 'l', or 'q' suffix */
115#define IS_POINTER_SIZED	0x2	/* For instructions which implicitly have operands which are sizeof(void *) */
116
117static void get_operand(
118    const char **symadd,
119    const char **symsub,
120    uint32_t *value,
121    uint32_t *value_size,
122    char *result,
123    const cpu_type_t cputype,
124    const uint32_t mode,
125    const uint32_t r_m,
126    const uint32_t wbit,
127    const enum bool data16,
128    const enum bool addr16,
129    const enum bool sse2,
130    const enum bool mmx,
131	const unsigned int rex,
132    const char *sect,
133    uint32_t sect_addr,
134    uint32_t *length,
135    uint32_t *left,
136    const uint32_t addr,
137    const struct relocation_info *sorted_relocs,
138    const uint32_t nsorted_relocs,
139    const struct nlist *symbols,
140    const struct nlist_64 *symbols64,
141    const uint32_t nsymbols,
142    const char *strings,
143    const uint32_t strings_size,
144    const struct symbol *sorted_symbols,
145    const uint32_t nsorted_symbols,
146    const enum bool verbose);
147
148static void immediate(
149    const char **symadd,
150    const char **symsub,
151    uint64_t *value,
152    uint32_t value_size,
153    const char *sect,
154    uint32_t sect_addr,
155    uint32_t *length,
156    uint32_t *left,
157    const cpu_type_t cputype,
158    const uint32_t addr,
159    const struct relocation_info *sorted_relocs,
160    const uint32_t nsorted_relocs,
161    const struct nlist *symbols,
162    const struct nlist_64 *symbols64,
163    const uint32_t nsymbols,
164    const char *strings,
165    const uint32_t strings_size,
166    const struct symbol *sorted_symbols,
167    const uint32_t nsorted_symbols,
168    const enum bool verbose);
169
170static void displacement(
171    const char **symadd,
172    const char **symsub,
173    uint64_t *value,
174    const uint32_t value_size,
175    const char *sect,
176    uint64_t sect_addr,
177    uint32_t *length,
178    uint32_t *left,
179    const uint32_t filetype,
180    const cpu_type_t cputype,
181    const uint64_t addr,
182    const struct relocation_info *sorted_relocs,
183    const uint32_t nsorted_relocs,
184    const struct nlist *symbols,
185    const struct nlist_64 *symbols64,
186    const uint32_t nsymbols,
187    const char *strings,
188    const uint32_t strings_size,
189    const struct symbol *sorted_symbols,
190    const uint32_t nsorted_symbols,
191    const enum bool verbose);
192
193static void get_symbol(
194    const char **symadd,
195    const char **symsub,
196    uint64_t *offset,
197    const cpu_type_t cputype,
198    const uint32_t sect_offset,
199    const uint64_t value,
200    const struct relocation_info *relocs,
201    const uint32_t nrelocs,
202    const struct nlist *symbols,
203    const struct nlist_64 *symbols64,
204    const uint32_t nsymbols,
205    const char *strings,
206    const uint32_t strings_size,
207    const struct symbol *sorted_symbols,
208    const uint32_t nsorted_symbols,
209    const enum bool verbose);
210
211static void print_operand(
212    const char *seg,
213    const char *symadd,
214    const char *symsub,
215    uint64_t value,
216    unsigned int value_size,
217    const char *result,
218    const char *tail);
219
220static uint64_t get_value(
221    const uint32_t size,
222    const char *sect,
223    uint32_t *length,
224    uint32_t *left);
225
226static void modrm_byte(
227    uint32_t *mode,
228    uint32_t *reg,
229    uint32_t *r_m,
230    unsigned char byte);
231
232#define GET_OPERAND(symadd, symsub, value, value_size, result) \
233	get_operand((symadd), (symsub), (value), (value_size), (result), \
234		    cputype, mode, r_m, wbit, data16, addr16, sse2, mmx, rex, \
235		    sect, sect_addr, &length, &left, addr, sorted_relocs, \
236		    nsorted_relocs, symbols, symbols64, nsymbols, strings, \
237		    strings_size, sorted_symbols, nsorted_symbols, verbose)
238
239#define DISPLACEMENT(symadd, symsub, value, value_size) \
240	displacement((symadd), (symsub), (value), (value_size), sect, \
241		     sect_addr, &length, &left, filetype, cputype, addr, \
242		     sorted_relocs, nsorted_relocs, symbols, symbols64, \
243		     nsymbols, strings, strings_size, sorted_symbols, \
244		     nsorted_symbols, verbose)
245
246#define IMMEDIATE(symadd, symsub, value, value_size) \
247	immediate((symadd), (symsub), (value), (value_size), sect, sect_addr, \
248		  &length, &left, cputype, addr, sorted_relocs, \
249		  nsorted_relocs, symbols, symbols64, nsymbols, strings, \
250		  strings_size, sorted_symbols, nsorted_symbols, verbose)
251
252#define GET_SYMBOL(symadd, symsub, offset, sect_offset, value) \
253	get_symbol((symadd), (symsub), (offset), cputype, (sect_offset), \
254		   (value), sorted_relocs, nsorted_relocs, symbols, symbols64, \
255		   nsymbols, strings, strings_size, sorted_symbols, \
256		   nsorted_symbols, verbose)
257
258#define GUESS_SYMBOL(value) \
259	guess_symbol((value), sorted_symbols, nsorted_symbols, verbose)
260
261/*
262 * These are the instruction formats as they appear in the disassembly tables.
263 * Here they are given numerical values for use in the actual disassembly of
264 * an instruction.
265 */
266#define UNKNOWN	0
267#define MRw	2
268#define IMlw	3
269#define IMw	4
270#define IR	5
271#define OA	6
272#define AO	7
273#define MS	8
274#define SM	9
275#define Mv	10
276#define Mw	11
277#define M	12
278#define R	13
279#define RA	14
280#define SEG	15
281#define MR	16
282#define IA	17
283#define MA	18
284#define SD	19
285#define AD	20
286#define SA	21
287#define D	22
288#define INM	23
289#define SO	24
290#define BD	25
291#define I	26
292#define P	27
293#define V	28
294#define DSHIFT	29 /* for double shift that has an 8-bit immediate */
295#define U	30
296#define OVERRIDE 31
297#define GO_ON	32
298#define O	33	/* for call	*/
299#define JTAB	34	/* jump table (not used at NeXT) */
300#define IMUL	35	/* for 186 iimul instr  */
301#define CBW 36 /* so that data16 can be evaluated for cbw and its variants */
302#define MvI	37	/* for 186 logicals */
303#define ENTER	38	/* for 186 enter instr  */
304#define RMw	39	/* for 286 arpl instr */
305#define Ib	40	/* for push immediate byte */
306#define F	41	/* for 287 instructions */
307#define FF	42	/* for 287 instructions */
308#define DM	43	/* 16-bit data */
309#define AM	44	/* 16-bit addr */
310#define LSEG	45	/* for 3-bit seg reg encoding */
311#define MIb	46	/* for 386 logicals */
312#define SREG	47	/* for 386 special registers */
313#define PREFIX	48	/* an instruction prefix like REP, LOCK */
314#define INT3	49	/* The int 3 instruction, which has a fake operand */
315#define DSHIFTcl 50	/* for double shift that implicitly uses %cl */
316#define CWD	51	/* so that data16 can be evaluated for cwd and vars */
317#define RET	52	/* single immediate 16-bit operand */
318#define MOVZ	53	/* for movs and movz, with different size operands */
319#define XINST	54	/* for cmpxchg and xadd */
320#define BSWAP	55	/* for bswap */
321#define Pi	56
322#define Po	57
323#define Vi	58
324#define Vo	59
325#define Mb	60
326#define INMl	61
327#define SSE2	62	/* SSE2 instruction with possible 3rd opcode byte */
328#define SSE2i	63	/* SSE2 instruction with 8-bit immediate */
329#define SSE2i1	64	/* SSE2 with one operand and 8-bit immediate */
330#define SSE2tm	65	/* SSE2 with dest to memory */
331#define SSE2tfm	66	/* SSE2 with dest to memory or memory to dest */
332#define PFCH	67	/* prefetch instructions */
333#define SFEN	68	/* sfence & clflush */
334#define Mnol	69	/* no 'l' suffix, fildl, fistpl */
335#define AMD3DNOW       70  /* 3DNow! instruction (SSE2 format with a suffix) */
336#define PFCH3DNOW      71  /* 3DNow! prefetch instruction */
337#define REX	72		/* 64-bit REX prefix */
338#define IR64 73		/* IR with a 64-bit immediate if REX.W is set */
339#define MNI 74		/* MNI instruction, differentiated by 2nd and 3rd opcode bytes */
340#define MNIi 75		/* MNI instruction with 8-bit immediate, differentiated by 2nd and 3rd opcode bytes */
341#define SSE4	76	/* SSE4 instruction with 3rd & 4th opcode bytes */
342#define SSE4i	77	/* SSE4 instruction with 8-bit immediate */
343#define SSE4itm	78	/* SSE4 with dest to memory and 8-bit immediate */
344#define SSE4ifm	79	/* SSE4 with src from memory and 8-bit immediate */
345#define SSE4MRw	80	/* SSE4.2 memory or register operand to register */
346#define SSE4CRC	81	/* SSE4.2 crc memory or register operand to register */
347#define SSE4CRCb	82	/* SSE4.2 crc byte memory or register operand to register */
348
349/*
350 * In 16-bit addressing mode:
351 * Register operands may be indicated by a distinguished field.
352 * An '8' bit register is selected if the 'w' bit is equal to 0,
353 * and a '16' bit register is selected if the 'w' bit is equal to
354 * 1 and also if there is no 'w' bit.
355 */
356static const char * const REG16[8][2] = {
357/* w bit		0		1		*/
358/* reg bits */
359/* 000	*/		{"%al",		"%ax"},
360/* 001  */		{"%cl",		"%cx"},
361/* 010  */		{"%dl",		"%dx"},
362/* 011	*/		{"%bl",		"%bx"},
363/* 100	*/		{"%ah",		"%sp"},
364/* 101	*/		{"%ch",		"%bp"},
365/* 110	*/		{"%dh",		"%si"},
366/* 111	*/		{"%bh",		"%di"}
367};
368
369/*
370 * In 32-bit or 64-bit addressing mode:
371 * Register operands may be indicated by a distinguished field.
372 * An '8' bit register is selected if the 'w' bit is equal to 0,
373 * and a '32' bit register is selected if the 'w' bit is equal to
374 * 1 and also if there is no 'w' bit.
375 */
376static const char * const REG32[16][3] = {
377/* w bit		0				1			1 + REX.W	*/
378/* reg bits */
379/* 0000	*/		{"%al",			"%eax",			"%rax"},
380/* 0001  */		{"%cl",			"%ecx",			"%rcx"},
381/* 0010  */		{"%dl",			"%edx",			"%rdx"},
382/* 0011	*/		{"%bl",			"%ebx",			"%rbx"},
383/* 0100	*/		{"%ah",			"%esp",			"%rsp"},
384/* 0101	*/		{"%ch",			"%ebp",			"%rbp"},
385/* 0110	*/		{"%dh",			"%esi",			"%rsi"},
386/* 0111	*/		{"%bh",			"%edi",			"%rdi"},
387/* 1000	*/		{"%r8b",		"%r8d",			"%r8"},
388/* 1001 */		{"%r9b",		"%r9d",			"%r9"},
389/* 1010 */		{"%r10b",		"%r10d",		"%r10"},
390/* 1011	*/		{"%r11b",		"%r11d",		"%r11"},
391/* 1100	*/		{"%r12b",		"%r12d",		"%r12"},
392/* 1101	*/		{"%r13b",		"%r13d",		"%r13"},
393/* 1110	*/		{"%r14b",		"%r14d",		"%r14"},
394/* 1111	*/		{"%r15b",		"%r15d",		"%r15"}
395};
396
397/* For SSE4CRCb (i.e. crc32) instruction the byte regs when there is a REX */
398static const char * const REG64_BYTE[16] = {
399/* 0 */ "%al",
400/* 1 */ "%cl",
401/* 2 */ "%dl",
402/* 3 */ "%bl",
403/* 4 */ "%spl",
404/* 5 */ "%bpl",
405/* 6 */ "%sil",
406/* 7 */ "%dil",
407/* 8 */ "%r8b",
408/* 9 */ "%r9b",
409/* 10 */"%r10b",
410/* 11 */"%r11b",
411/* 12 */"%r12b",
412/* 13 */"%r13b",
413/* 14 */"%r14b",
414/* 15 */"%r15b"
415};
416
417/*
418 * In 16-bit mode:
419 * This initialized array will be indexed by the 'r/m' and 'mod'
420 * fields, to determine the size of the displacement in each mode.
421 */
422static const char dispsize16 [8][4] = {
423/* mod		00	01	10	11 */
424/* r/m */
425/* 000 */	{0,	1,	2,	0},
426/* 001 */	{0,	1,	2,	0},
427/* 010 */	{0,	1,	2,	0},
428/* 011 */	{0,	1,	2,	0},
429/* 100 */	{0,	1,	2,	0},
430/* 101 */	{0,	1,	2,	0},
431/* 110 */	{2,	1,	2,	0},
432/* 111 */	{0,	1,	2,	0}
433};
434
435/*
436 * In 32-bit mode:
437 * This initialized array will be indexed by the 'r/m' and 'mod'
438 * fields, to determine the size of the displacement in this mode.
439 */
440static const char dispsize32 [8][4] = {
441/* mod		00	01	10	11 */
442/* r/m */
443/* 000 */	{0,	1,	4,	0},
444/* 001 */	{0,	1,	4,	0},
445/* 010 */	{0,	1,	4,	0},
446/* 011 */	{0,	1,	4,	0},
447/* 100 */	{0,	1,	4,	0},
448/* 101 */	{4,	1,	4,	0},
449/* 110 */	{0,	1,	4,	0},
450/* 111 */	{0,	1,	4,	0}
451};
452
453/*
454 * When data16 has been specified, the following array specifies the registers
455 * for the different addressing modes.  Indexed first by mode, then by register
456 * number.
457 */
458static const char * const regname16[4][8] = {
459/*reg  000        001        010        011        100    101   110     111 */
460/*mod*/
461/*00*/{"%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "",    "%bx"},
462/*01*/{"%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"},
463/*10*/{"%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"},
464/*11*/{"%ax",     "%cx",     "%dx",     "%bx",     "%sp", "%bp", "%si", "%di"}
465};
466
467/*
468 * When data16 has not been specified, fields, to determine the addressing mode,
469 * and will also provide strings for printing.
470 */
471static const char * const regname32[4][8] = {
472/*reg   000     001     010     011     100     101    110     111 */
473/*mod*/
474/*00 */{"%eax", "%ecx", "%edx", "%ebx", "%esp", "",     "%esi", "%edi"},
475/*01 */{"%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi"},
476/*10 */{"%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi"},
477/*11 */{"%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi"}
478};
479
480/*
481 * When data16 has not been specified, fields, to determine the addressing mode,
482 * and will also provide strings for printing.
483 */
484static const char * const regname64[4][16] = {
485/*reg   0000    0001    0010    0011    0100    0101    0110    0111    1000    1001    1010    1011    1100    1101    1110    1111 */
486/*mod*/
487/*00 */{"%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"},
488/*01 */{"%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"},
489/*10 */{"%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"},
490/*11 */{"%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"}
491};
492
493/*
494 * If r/m==100 then the following byte (the s-i-b byte) must be decoded
495 */
496static const char * const scale_factor[4] = {
497    "1",
498    "2",
499    "4",
500    "8"
501};
502
503static const char * const indexname[8] = {
504    ",%eax",
505    ",%ecx",
506    ",%edx",
507    ",%ebx",
508    "",
509    ",%ebp",
510    ",%esi",
511    ",%edi"
512};
513
514static const char * const indexname64[16] = {
515    ",%rax",
516    ",%rcx",
517    ",%rdx",
518    ",%rbx",
519    "",
520    ",%rbp",
521    ",%rsi",
522    ",%rdi",
523	",%r8",
524	",%r9",
525	",%r10",
526	",%r11",
527	",%r12",
528	",%r13",
529	",%r14",
530	",%r15"
531};
532
533/*
534 * Segment registers are selected by a two or three bit field.
535 */
536static const char * const SEGREG[8] = {
537/* 000 */	"%es",
538/* 001 */	"%cs",
539/* 010 */	"%ss",
540/* 011 */	"%ds",
541/* 100 */	"%fs",
542/* 101 */	"%gs",
543/* 110 */	"%?6",
544/* 111 */	"%?7",
545};
546
547/*
548 * Special Registers
549 */
550static const char * const DEBUGREG[] = {
551	"%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7",
552	"%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
553};
554
555static const char * const LLVM_MC_DEBUGREG[] = {
556	"%dr0", "%dr1", "%dr2", "%dr3", "%dr4", "%dr5", "%dr6", "%dr7",
557	"%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
558};
559
560static const char * const CONTROLREG[] = {
561	"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
562	"%cr8", "%cr9", "%cr10", "%cr11", "%cr12", "%cr13", "%cr14", "%cr15"
563};
564
565static const char * const LLVM_MC_32_CONTROLREG[] = {
566	"%ecr0", "%ecr1", "%ecr2", "%ecr3", "%ecr4", "%ecr5", "%ecr6", "%ecr7",
567	"%ecr8", "%ecr9", "%ecr10", "%ecr11", "%ecr12", "%ecr13", "%ecr14",
568	"%ecr15"
569};
570
571static const char * const LLVM_MC_64_CONTROLREG[] = {
572	"%rcr0", "%rcr1", "%rcr2", "%rcr3", "%rcr4", "%rcr5", "%rcr6", "%rcr7",
573	"%rcr8", "%rcr9", "%rcr10", "%rcr11", "%rcr12", "%rcr13", "%rcr14",
574	"%rcr15"
575};
576
577static const char * const TESTREG[8] = {
578    "%tr0", "%tr1", "%tr2", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
579};
580
581/*
582 * Decode table for 0x0F00 opcodes
583 */
584static const struct instable op0F00[8] = {
585/*  [0]  */	{"sldt",TERM,M,0},	{"str",TERM,M,0},
586		{"lldt",TERM,M,0},	{"ltr",TERM,M,0},
587/*  [4]  */	{"verr",TERM,M,0},	{"verw",TERM,M,0},
588		INVALID,		INVALID,
589};
590
591
592/*
593 * Decode table for 0x0F01 opcodes
594 */
595static const struct instable op0F01[8] = {
596/*  [0]  */	{"sgdt",TERM,M,1},	{"sidt",TERM,M,1},
597		{"lgdt",TERM,M,1},	{"lidt",TERM,M,1},
598/*  [4]  */	{"smsw",TERM,M,0},	INVALID,
599		{"lmsw",TERM,M,0},	{"invlpg",TERM,M,0},
600};
601
602/*
603 * Decode table for 0x0F38 opcodes
604 */
605static const struct instable op0F38[256] = {
606/*  [00]  */	{"pshufb",TERM,MNI,0},	{"phaddw",TERM,MNI,0},
607		{"phaddd",TERM,MNI,0},	{"phaddsw",TERM,MNI,0},
608/*  [04]  */	{"pmaddubsw",TERM,MNI,0},	{"phsubw",TERM,MNI,0},
609		{"phsubd",TERM,MNI,0},	{"phsubsw",TERM,MNI,0},
610/*  [08]  */	{"psignb",TERM,MNI,0},	{"psignw",TERM,MNI,0},
611		{"psignd",TERM,MNI,0},	{"pmulhrsw",TERM,MNI,0},
612/*  [0C]  */	INVALID,	INVALID,
613		INVALID,	INVALID,
614/*  [10]  */	{"pblendvb",TERM,SSE4,0},	INVALID,
615		INVALID,	INVALID,
616/*  [14]  */	{"blendvps",TERM,SSE4,0},{"blendvpd",TERM,SSE4,0},
617		INVALID,	{"ptest",TERM,SSE4,0},
618/*  [18]  */	INVALID,	INVALID,
619		INVALID,	INVALID,
620/*  [1C]  */	{"pabsb",TERM,MNI,0},	{"pabsw",TERM,MNI,0},
621		{"pabsd",TERM,MNI,0},	INVALID,
622/*  [20]  */	{"pmovsxbw",TERM,SSE4,0},	{"pmovsxbd",TERM,SSE4,0},
623		{"pmovsxbq",TERM,SSE4,0},	{"pmovsxwd",TERM,SSE4,0},
624/*  [24]  */	{"pmovsxwq",TERM,SSE4,0},	{"pmovsxdq",TERM,SSE4,0},
625		INVALID,	INVALID,
626/*  [28]  */	{"pmuldq",TERM,SSE4,0},		{"pcmpeqq",TERM,SSE4,0},
627		{"movntdqa",TERM,SSE4,0},	{"packusdw",TERM,SSE4,0},
628/*  [2C]  */	INVALID,	INVALID,
629		INVALID,	INVALID,
630/*  [30]  */	{"pmovzxbw",TERM,SSE4,0},	{"pmovzxbd",TERM,SSE4,0},
631		{"pmovzxbq",TERM,SSE4,0},	{"pmovzxwd",TERM,SSE4,0},
632/*  [34]  */	{"pmovzxwq",TERM,SSE4,0},	{"pmovzxdq",TERM,SSE4,0},
633		INVALID,	{"pcmpgtq",TERM,SSE4,0},
634/*  [38]  */	{"pminsb",TERM,SSE4,0},	{"pminsd",TERM,SSE4,0},
635		{"pminuw",TERM,SSE4,0},	{"pminud",TERM,SSE4,0},
636/*  [3C]  */	{"pmaxsb",TERM,SSE4,0},	{"pmaxsd",TERM,SSE4,0},
637		{"pmaxuw",TERM,SSE4,0},	{"pmaxud",TERM,SSE4,0},
638/*  [40]  */	{"pmulld",TERM,SSE4,0},	{"phminposuw",TERM,SSE4,0},
639		INVALID,	INVALID,
640/*  [44]  */	INVALID,	INVALID,
641		INVALID,	INVALID,
642/*  [48]  */	INVALID,	INVALID,
643		INVALID,	INVALID,
644/*  [4C]  */	INVALID,	INVALID,
645		INVALID,	INVALID,
646/*  [50]  */	INVALID,	INVALID,
647		INVALID,	INVALID,
648/*  [54]  */	INVALID,	INVALID,
649		INVALID,	INVALID,
650/*  [58]  */	INVALID,	INVALID,
651		INVALID,	INVALID,
652/*  [5C]  */	INVALID,	INVALID,
653		INVALID,	INVALID,
654/*  [60]  */	INVALID,	INVALID,
655		INVALID,	INVALID,
656/*  [64]  */	INVALID,	INVALID,
657		INVALID,	INVALID,
658/*  [68]  */	INVALID,	INVALID,
659		INVALID,	INVALID,
660/*  [6C]  */	INVALID,	INVALID,
661		INVALID,	INVALID,
662/*  [70]  */	INVALID,	INVALID,
663		INVALID,	INVALID,
664/*  [74]  */	INVALID,	INVALID,
665		INVALID,	INVALID,
666/*  [78]  */	INVALID,	INVALID,
667		INVALID,	INVALID,
668/*  [7C]  */	INVALID,	INVALID,
669		INVALID,	INVALID,
670/*  [80]  */	{"invept",TERM,MR,0}, {"invvpid",TERM,MR,0},
671		INVALID,	INVALID,
672/*  [84]  */	INVALID,	INVALID,
673		INVALID,	INVALID,
674/*  [88]  */	INVALID,	INVALID,
675		INVALID,	INVALID,
676/*  [8C]  */	INVALID,	INVALID,
677		INVALID,	INVALID,
678/*  [90]  */	INVALID,	INVALID,
679		INVALID,	INVALID,
680/*  [94]  */	INVALID,	INVALID,
681		INVALID,	INVALID,
682/*  [98]  */	INVALID,	INVALID,
683		INVALID,	INVALID,
684/*  [9C]  */	INVALID,	INVALID,
685		INVALID,	INVALID,
686/*  [A0]  */	INVALID,	INVALID,
687		INVALID,	INVALID,
688/*  [A4]  */	INVALID,	INVALID,
689		INVALID,	INVALID,
690/*  [A8]  */	INVALID,	INVALID,
691		INVALID,	INVALID,
692/*  [AC]  */	INVALID,	INVALID,
693		INVALID,	INVALID,
694/*  [B0]  */	INVALID,	INVALID,
695		INVALID,	INVALID,
696/*  [B4]  */	INVALID,	INVALID,
697		INVALID,	INVALID,
698/*  [B8]  */	INVALID,	INVALID,
699		INVALID,	INVALID,
700/*  [BC]  */	INVALID,	INVALID,
701		INVALID,	INVALID,
702/*  [C0]  */	INVALID,	INVALID,
703		INVALID,	INVALID,
704/*  [C4]  */	INVALID,	INVALID,
705		INVALID,	INVALID,
706/*  [C8]  */	INVALID,	INVALID,
707		INVALID,	INVALID,
708/*  [CC]  */	INVALID,	INVALID,
709		INVALID,	INVALID,
710/*  [D0]  */	INVALID,	INVALID,
711		INVALID,	INVALID,
712/*  [D4]  */	INVALID,	INVALID,
713		INVALID,	INVALID,
714/*  [D8]  */	INVALID,	INVALID,
715		INVALID,	{"aesimc",TERM,SSE4,0},
716/*  [DC]  */	{"aesenc",TERM,SSE4,0}, {"aesenclast",TERM,SSE4,0},
717		{"aesdec",TERM,SSE4,0},	{"aesdeclast",TERM,SSE4,0},
718/*  [E0]  */	INVALID,	INVALID,
719		INVALID,	INVALID,
720/*  [E4]  */	INVALID,	INVALID,
721		INVALID,	INVALID,
722/*  [E8]  */	INVALID,	INVALID,
723		INVALID,	INVALID,
724/*  [EC]  */	INVALID,	INVALID,
725		INVALID,	INVALID,
726/*  [F0]  */	{"crc32b",TERM,SSE4CRCb,0},	{"crc32",TERM,SSE4CRC,1},
727		INVALID,	INVALID,
728/*  [F4]  */	INVALID,	INVALID,
729		INVALID,	INVALID,
730/*  [F8]  */	INVALID,	INVALID,
731		INVALID,	INVALID,
732/*  [FC]  */	INVALID,	INVALID,
733		INVALID,	INVALID,
734};
735
736/*
737 * Decode table for 0x0F3A opcodes
738 */
739static const struct instable op0F3A[224] = {
740/*  [00]  */	INVALID,	INVALID,
741		INVALID,	INVALID,
742/*  [04]  */	INVALID,	INVALID,
743		INVALID,	INVALID,
744/*  [08]  */	{"roundps",TERM,SSE4i,0},	{"roundpd",TERM,SSE4i,0},
745		{"roundss",TERM,SSE4i,0},	{"roundsd",TERM,SSE4i,0},
746/*  [0C]  */	{"blendps",TERM,SSE4i,0},	{"blendpd",TERM,SSE4i,0},
747		{"pblendw",TERM,SSE4i,0},	{"palignr",TERM,MNIi,0},
748/*  [10]  */	INVALID,	INVALID,
749		INVALID,	INVALID,
750/*  [14]  */	{"pextrb",TERM,SSE4itm,0},	{"pextrw",TERM,SSE4itm,0},
751		{"pextr",TERM,SSE4itm,0},	{"extractps",TERM,SSE4itm,0},
752/*  [18]  */	INVALID,	INVALID,
753		INVALID,	INVALID,
754/*  [1C]  */	INVALID,	INVALID,
755		INVALID,	INVALID,
756/*  [20]  */	{"pinsrb",TERM,SSE4ifm,0},	{"insertps",TERM,SSE4i,0},
757		{"pinsr",TERM,SSE4ifm,0},	INVALID,
758/*  [24]  */	INVALID,	INVALID,
759		INVALID,	INVALID,
760/*  [28]  */	INVALID,	INVALID,
761		INVALID,	INVALID,
762/*  [2C]  */	INVALID,	INVALID,
763		INVALID,	INVALID,
764/*  [30]  */	INVALID,	INVALID,
765		INVALID,	INVALID,
766/*  [34]  */	INVALID,	INVALID,
767		INVALID,	INVALID,
768/*  [38]  */	INVALID,	INVALID,
769		INVALID,	INVALID,
770/*  [3C]  */	INVALID,	INVALID,
771		INVALID,	INVALID,
772/*  [40]  */	{"dpps",TERM,SSE4i,0},	{"dppd",TERM,SSE4i,0},
773		{"mpsadbw",TERM,SSE4i,0},	INVALID,
774/*  [44]  */	INVALID,	INVALID,
775		INVALID,	INVALID,
776/*  [48]  */	INVALID,	INVALID,
777		INVALID,	INVALID,
778/*  [4C]  */	INVALID,	INVALID,
779		INVALID,	INVALID,
780/*  [50]  */	INVALID,	INVALID,
781		INVALID,	INVALID,
782/*  [54]  */	INVALID,	INVALID,
783		INVALID,	INVALID,
784/*  [58]  */	INVALID,	INVALID,
785		INVALID,	INVALID,
786/*  [5C]  */	INVALID,	INVALID,
787		INVALID,	INVALID,
788/*  [60]  */	{"pcmpestrm",TERM,SSE4i,0},	{"pcmpestri",TERM,SSE4i,0},
789		{"pcmpistrm",TERM,SSE4i,0},	{"pcmpistri",TERM,SSE4i,0},
790/*  [64]  */	INVALID,	INVALID,
791		INVALID,	INVALID,
792/*  [68]  */	INVALID,	INVALID,
793		INVALID,	INVALID,
794/*  [6C]  */	INVALID,	INVALID,
795		INVALID,	INVALID,
796/*  [70]  */	INVALID,	INVALID,
797		INVALID,	INVALID,
798/*  [74]  */	INVALID,	INVALID,
799		INVALID,	INVALID,
800/*  [78]  */	INVALID,	INVALID,
801		INVALID,	INVALID,
802/*  [7C]  */	INVALID,	INVALID,
803		INVALID,	INVALID,
804/*  [80]  */	INVALID,	INVALID,
805		INVALID,	INVALID,
806/*  [84]  */	INVALID,	INVALID,
807		INVALID,	INVALID,
808/*  [88]  */	INVALID,	INVALID,
809		INVALID,	INVALID,
810/*  [8C]  */	INVALID,	INVALID,
811		INVALID,	INVALID,
812/*  [90]  */	INVALID,	INVALID,
813		INVALID,	INVALID,
814/*  [94]  */	INVALID,	INVALID,
815		INVALID,	INVALID,
816/*  [98]  */	INVALID,	INVALID,
817		INVALID,	INVALID,
818/*  [9C]  */	INVALID,	INVALID,
819		INVALID,	INVALID,
820/*  [A0]  */	INVALID,	INVALID,
821		INVALID,	INVALID,
822/*  [A4]  */	INVALID,	INVALID,
823		INVALID,	INVALID,
824/*  [A8]  */	INVALID,	INVALID,
825		INVALID,	INVALID,
826/*  [AC]  */	INVALID,	INVALID,
827		INVALID,	INVALID,
828/*  [B0]  */	INVALID,	INVALID,
829		INVALID,	INVALID,
830/*  [B4]  */	INVALID,	INVALID,
831		INVALID,	INVALID,
832/*  [B8]  */	INVALID,	INVALID,
833		INVALID,	INVALID,
834/*  [BC]  */	INVALID,	INVALID,
835		INVALID,	INVALID,
836/*  [C0]  */	INVALID,	INVALID,
837		INVALID,	INVALID,
838/*  [C4]  */	INVALID,	INVALID,
839		INVALID,	INVALID,
840/*  [C8]  */	INVALID,	INVALID,
841		INVALID,	INVALID,
842/*  [CC]  */	INVALID,	INVALID,
843		INVALID,	INVALID,
844/*  [D0]  */	INVALID,	INVALID,
845		INVALID,	INVALID,
846/*  [D4]  */	INVALID,	INVALID,
847		INVALID,	INVALID,
848/*  [D8]  */	INVALID,	INVALID,
849		INVALID,	INVALID,
850/*  [DC]  */	INVALID,	INVALID,
851		INVALID,	{"aeskeygenassist",TERM,SSE4i,0},
852};
853
854static const struct instable op_monitor = {"monitor",TERM,GO_ON,0};
855static const struct instable op_mwait   = {"mwait",TERM,GO_ON,0};
856static const struct instable op_rdtscp   = {"rdtscp",TERM,GO_ON,0};
857
858/* These opcode tables entries are only used for the 64-bit architecture */
859static const struct instable op_swapgs = {"swapgs",TERM,GO_ON,0};
860static const struct instable op_syscall = {"syscall",TERM,GO_ON,0};
861static const struct instable op_sysret = {"sysret",TERM,GO_ON,0};
862static const struct instable opREX = {"",TERM,REX,0};
863static const struct instable op_movsl = {"movsl",TERM,MOVZ,1};
864
865/*
866 * Decode table for 0x0F0F opcodes
867 * Unlike the other decode tables, this one maps suffixes.
868 */
869static const struct instable op0F0F[16][16] = {
870/*  [00]  */ {  INVALID,       INVALID,
871               INVALID,        INVALID,
872/*  [04]  */   INVALID,        INVALID,
873               INVALID,        INVALID,
874/*  [08]  */   INVALID,        INVALID,
875               INVALID,        INVALID,
876/*  [0C]  */   {"pi2fw",TERM,AMD3DNOW,0},      {"pi2fd",TERM,AMD3DNOW,0},
877               INVALID,        INVALID },
878/*  [10]  */ {  INVALID,       INVALID,
879               INVALID,        INVALID,
880/*  [14]  */   INVALID,        INVALID,
881               INVALID,        INVALID,
882/*  [18]  */   INVALID,        INVALID,
883               INVALID,        INVALID,
884/*  [1C]  */   {"pf2iw",TERM,AMD3DNOW,0},      {"pf2id",TERM,AMD3DNOW,0},
885               INVALID,        INVALID },
886/*  [20]  */ {  INVALID,       INVALID,
887               INVALID,        INVALID,
888/*  [24]  */   INVALID,        INVALID,
889               INVALID,        INVALID,
890/*  [28]  */   INVALID,        INVALID,
891               INVALID,        INVALID,
892/*  [2C]  */   INVALID,        INVALID,
893               INVALID,        INVALID, },
894/*  [30]  */ {  INVALID,       INVALID,
895               INVALID,        INVALID,
896/*  [34]  */   INVALID,        INVALID,
897               INVALID,        INVALID,
898/*  [38]  */   INVALID,        INVALID,
899               INVALID,        INVALID,
900/*  [3C]  */   INVALID,        INVALID,
901               INVALID,        INVALID },
902/*  [40]  */ {  INVALID,       INVALID,
903               INVALID,        INVALID,
904/*  [44]  */   INVALID,        INVALID,
905               INVALID,        INVALID,
906/*  [48]  */   INVALID,        INVALID,
907               INVALID,        INVALID,
908/*  [4C]  */   INVALID,        INVALID,
909               INVALID,        INVALID },
910/*  [50]  */ {  INVALID,       INVALID,
911               INVALID,        INVALID,
912/*  [54]  */   INVALID,        INVALID,
913               INVALID,        INVALID,
914/*  [58]  */   INVALID,        INVALID,
915               INVALID,        INVALID,
916/*  [5C]  */   INVALID,        INVALID,
917               INVALID,        INVALID, },
918/*  [60]  */ {  INVALID,       INVALID,
919               INVALID,        INVALID,
920/*  [64]  */   INVALID,        INVALID,
921               INVALID,        INVALID,
922/*  [68]  */   INVALID,        INVALID,
923               INVALID,        INVALID,
924/*  [6C]  */   INVALID,        INVALID,
925               INVALID,        INVALID },
926/*  [70]  */ {  INVALID,       INVALID,
927               INVALID,        INVALID,
928/*  [74]  */   INVALID,        INVALID,
929               INVALID,        INVALID,
930/*  [78]  */   INVALID,        INVALID,
931               INVALID,        INVALID,
932/*  [7C]  */   INVALID,        INVALID,
933               INVALID,        INVALID },
934/*  [80]  */ {  INVALID,       INVALID,
935               INVALID,        INVALID,
936/*  [84]  */   INVALID,        INVALID,
937               INVALID,        INVALID,
938/*  [88]  */   INVALID,        INVALID,
939               {"pfnacc",TERM,AMD3DNOW,0},     INVALID,
940/*  [8C]  */   INVALID,        INVALID,
941               {"pfpnacc",TERM,AMD3DNOW,0},    INVALID },
942/*  [90]  */ {  {"pfcmpge",TERM,AMD3DNOW,0},   INVALID,
943               INVALID,        INVALID,
944/*  [94]  */   {"pfmin",TERM,AMD3DNOW,0},      INVALID,
945               {"pfrcp",TERM,AMD3DNOW,0},      {"pfrsqrt",TERM,AMD3DNOW,0},
946/*  [98]  */   INVALID,        INVALID,
947               {"pfsub",TERM,AMD3DNOW,0},      INVALID,
948/*  [9C]  */   INVALID,        INVALID,
949               {"pfadd",TERM,AMD3DNOW,0},      INVALID },
950/*  [A0]  */ {  {"pfcmpgt",TERM,AMD3DNOW,0},   INVALID,
951               INVALID,        INVALID,
952/*  [A4]  */   {"pfmax",TERM,AMD3DNOW,0},      INVALID,
953               {"pfrcpit1",TERM,AMD3DNOW,0},   {"pfrsqit1",TERM,AMD3DNOW,0},
954/*  [A8]  */   INVALID,        INVALID,
955               {"pfsubr",TERM,AMD3DNOW,0},     INVALID,
956/*  [AC]  */   INVALID,        INVALID,
957               {"pfacc",TERM,AMD3DNOW,0},      INVALID },
958/*  [B0]  */ {  {"pfcmpeq",TERM,AMD3DNOW,0},   INVALID,
959               INVALID,        INVALID,
960/*  [B4]  */   {"pfmul",TERM,AMD3DNOW,0},      INVALID,
961               {"pfrcpit2",TERM,AMD3DNOW,0},   {"pmulhrw",TERM,AMD3DNOW,0},
962/*  [B8]  */   INVALID,        INVALID,
963               INVALID,        {"pswapd",TERM,AMD3DNOW,0},
964/*  [BC]  */   INVALID,        INVALID,
965               INVALID,        {"pavgusb",TERM,AMD3DNOW,0} },
966/*  [C0]  */ {  INVALID,       INVALID,
967               INVALID,        INVALID,
968/*  [C4]  */   INVALID,        INVALID,
969               INVALID,        INVALID,
970/*  [C8]  */   INVALID,        INVALID,
971               INVALID,        INVALID,
972/*  [CC]  */   INVALID,        INVALID,
973               INVALID,        INVALID },
974/*  [D0]  */ {  INVALID,       INVALID,
975               INVALID,        INVALID,
976/*  [D4]  */   INVALID,        INVALID,
977               INVALID,        INVALID,
978/*  [D8]  */   INVALID,        INVALID,
979               INVALID,        INVALID,
980/*  [DC]  */   INVALID,        INVALID,
981               INVALID,        INVALID },
982/*  [E0]  */ {  INVALID,       INVALID,
983               INVALID,        INVALID,
984/*  [E4]  */   INVALID,        INVALID,
985               INVALID,        INVALID,
986/*  [E8]  */   INVALID,        INVALID,
987               INVALID,        INVALID,
988/*  [EC]  */   INVALID,        INVALID,
989               INVALID,        INVALID },
990/*  [F0]  */ {  INVALID,       INVALID,
991               INVALID,        INVALID,
992/*  [F4]  */   INVALID,        INVALID,
993               INVALID,        INVALID,
994/*  [F8]  */   INVALID,        INVALID,
995               INVALID,        INVALID,
996/*  [FC]  */   INVALID,        INVALID,
997               INVALID,        INVALID },
998};
999
1000/*
1001 * Decode table for 0x0FBA opcodes
1002 */
1003static const struct instable op0FBA[8] = {
1004/*  [0]  */	INVALID,		INVALID,
1005		INVALID,		INVALID,
1006/*  [4]  */	{"bt",TERM,MIb,1},	{"bts",TERM,MIb,1},
1007		{"btr",TERM,MIb,1},	{"btc",TERM,MIb,1},
1008};
1009
1010/*
1011 * Decode table for 0x0FAE opcodes
1012 */
1013static const struct instable op0FAE[8] = {
1014/*  [0]  */	{"fxsave",TERM,M,0},	{"fxrstor",TERM,M,0},
1015		{"ldmxcsr",TERM,M,0},	{"stmxcsr",TERM,M,0},
1016/*  [4]  */	INVALID,		{"lfence",TERM,GO_ON,0},
1017		{"mfence",TERM,GO_ON,0},{"clflush",TERM,SFEN,0},
1018};
1019
1020/*
1021 * Decode table for 0x0F opcodes
1022 */
1023static const struct instable op0F[16][16] = {
1024/*  [00]  */ {  {"",op0F00,TERM,0},	{"",op0F01,TERM,0},
1025		{"lar",TERM,MR,0},	{"lsl",TERM,MR,0},
1026/*  [04]  */	INVALID,		{INVALID_32,&op_syscall},
1027		{"clts",TERM,GO_ON,0},  {INVALID_32,&op_sysret},
1028/*  [08]  */	{"invd",TERM,GO_ON,0},	{"wbinvd",TERM,GO_ON,0},
1029		INVALID,		{"ud2",TERM,GO_ON,0},
1030/*  [0C]  */	INVALID,                {"prefetch",TERM,PFCH3DNOW,1},
1031		{"femms",TERM,GO_ON,0},
1032				{"",(const struct instable *)op0F0F,TERM,0} },
1033/*  [10]  */ {  {"mov",TERM,SSE2,0},	{"mov",TERM,SSE2tm,0},
1034		{"mov",TERM,SSE2,0},	{"movl",TERM,SSE2tm,0},
1035/*  [14]  */	{"unpckl",TERM,SSE2,0},	{"unpckh",TERM,SSE2,0},
1036		{"mov",TERM,SSE2,0},	{"movh",TERM,SSE2tm,0},
1037/*  [18]  */	{"prefetch",TERM,PFCH,1},INVALID,
1038		INVALID,		INVALID,
1039/*  [1C]  */	INVALID,		INVALID,
1040		INVALID,		{"nop",TERM,M,1} },
1041/*  [20]  */ {  {"mov",TERM,SREG,0x03},	{"mov",TERM,SREG,0x03},
1042		{"mov",TERM,SREG,0x03},	{"mov",TERM,SREG,0x03},
1043/*  [24]  */	{"mov",TERM,SREG,0x03},	INVALID,
1044		{"mov",TERM,SREG,0x03},	INVALID,
1045/*  [28]  */	{"mova",TERM,SSE2,0},	{"mova",TERM,SSE2tm,0},
1046		{"cvt",TERM,SSE2,0},	{"movnt",TERM,SSE2tm,0},
1047/*  [2C]  */	{"cvt",TERM,SSE2,0},	{"cvt",TERM,SSE2,0} ,
1048		{"ucomi",TERM,SSE2,0},	{"comi",TERM,SSE2,0} },
1049/*  [30]  */ {  {"wrmsr",TERM,GO_ON,0},	{"rdtsc",TERM,GO_ON,0},
1050		{"rdmsr",TERM,GO_ON,0},	{"rdpmc",TERM,GO_ON,0},
1051/*  [34]  */	{"sysenter",TERM,GO_ON,0},{"sysexit",TERM,GO_ON,0},
1052		INVALID,		INVALID,
1053/*  [38]  */	{"",op0F38,TERM,0},		INVALID,
1054		{"",op0F3A,TERM,0},		INVALID,
1055/*  [3C]  */	INVALID,		INVALID,
1056		INVALID,		INVALID },
1057/*  [40]  */ {  {"cmovo",TERM,MRw,1},	{"cmovno",TERM,MRw,1},
1058		{"cmovb",TERM,MRw,1},	{"cmovae",TERM,MRw,1},
1059/*  [44]  */	{"cmove",TERM,MRw,1},	{"cmovne",TERM,MRw,1},
1060		{"cmovbe",TERM,MRw,1},	{"cmova",TERM,MRw,1},
1061/*  [48]  */	{"cmovs",TERM,MRw,1},	{"cmovns",TERM,MRw,1},
1062		{"cmovp",TERM,MRw,1},	{"cmovnp",TERM,MRw,1},
1063/*  [4C]  */	{"cmovl",TERM,MRw,1},	{"cmovge",TERM,MRw,1},
1064		{"cmovle",TERM,MRw,1},	{"cmovg",TERM,MRw,1} },
1065/*  [50]  */ {  {"movmsk",TERM,SSE2,0},	{"sqrt",TERM,SSE2,0},
1066		{"rsqrt",TERM,SSE2,0},	{"rcp",TERM,SSE2,0},
1067/*  [54]  */	{"and",TERM,SSE2,0},	{"andn",TERM,SSE2,0},
1068		{"or",TERM,SSE2,0},	{"xor",TERM,SSE2,0},
1069/*  [58]  */	{"add",TERM,SSE2,0},	{"mul",TERM,SSE2,0},
1070		{"cvt",TERM,SSE2,0},	{"cvt",TERM,SSE2,0},
1071/*  [5C]  */	{"sub",TERM,SSE2,0},	{"min",TERM,SSE2,0},
1072		{"div",TERM,SSE2,0},	{"max",TERM,SSE2,0} },
1073/*  [60]  */ {  {"punpcklbw",TERM,SSE2,0},{"punpcklwd",TERM,SSE2,0},
1074		{"punpckldq",TERM,SSE2,0},{"packsswb",TERM,SSE2,0},
1075/*  [64]  */	{"pcmpgtb",TERM,SSE2,0},{"pcmpgtw",TERM,SSE2,0},
1076		{"pcmpgtd",TERM,SSE2,0},{"packuswb",TERM,SSE2,0},
1077/*  [68]  */	{"punpckhbw",TERM,SSE2,0},{"punpckhwd",TERM,SSE2,0},
1078		{"punpckhdq",TERM,SSE2,0},{"packssdw",TERM,SSE2,0},
1079/*  [6C]  */	{"punpckl",TERM,SSE2,0},{"punpckh",TERM,SSE2,0},
1080		{"movd",TERM,SSE2,0},	{"mov",TERM,SSE2,0} },
1081/*  [70]  */ {  {"pshu",TERM,SSE2i,0},	{"ps",TERM,SSE2i1,0},
1082		{"ps",TERM,SSE2i1,0},	{"ps",TERM,SSE2i1,0},
1083/*  [74]  */	{"pcmpeqb",TERM,SSE2,0},{"pcmpeqw",TERM,SSE2,0},
1084		{"pcmpeqd",TERM,SSE2,0},{"emms",TERM,GO_ON,0},
1085/*  [78]  */	{"vmread",TERM,RMw,0},  {"vmwrite",TERM,MRw,0},
1086		INVALID,		INVALID,
1087/*  [7C]  */	{"haddp",TERM,SSE2,0},  {"hsubp",TERM,SSE2,0},
1088		{"mov",TERM,SSE2tfm,0},	{"mov",TERM,SSE2tm,0} },
1089/*  [80]  */ {  {"jo",TERM,D,0x02},	{"jno",TERM,D,0x02},
1090		{"jb",TERM,D,0x02},	{"jae",TERM,D,0x02},
1091/*  [84]  */	{"je",TERM,D,0x02},	{"jne",TERM,D,0x02},
1092		{"jbe",TERM,D,0x02},	{"ja",TERM,D,0x02},
1093/*  [88]  */	{"js",TERM,D,0x02},	{"jns",TERM,D,0x02},
1094		{"jp",TERM,D,0x02},	{"jnp",TERM,D,0x02},
1095/*  [8C]  */	{"jl",TERM,D,0x02},	{"jge",TERM,D,0x02},
1096		{"jle",TERM,D,0x02},	{"jg",TERM,D,0x02} },
1097/*  [90]  */ {  {"seto",TERM,Mb,0},	{"setno",TERM,Mb,0},
1098		{"setb",TERM,Mb,0},	{"setae",TERM,Mb,0},
1099/*  [94]  */	{"sete",TERM,Mb,0},	{"setne",TERM,Mb,0},
1100		{"setbe",TERM,Mb,0},	{"seta",TERM,Mb,0},
1101/*  [98]  */	{"sets",TERM,Mb,0},	{"setns",TERM,Mb,0},
1102		{"setp",TERM,Mb,0},	{"setnp",TERM,Mb,0},
1103/*  [9C]  */	{"setl",TERM,Mb,0},	{"setge",TERM,Mb,0},
1104		{"setle",TERM,Mb,0},	{"setg",TERM,Mb,0} },
1105/*  [A0]  */ {  {"push",TERM,LSEG,0x03},{"pop",TERM,LSEG,0x03},
1106		{"cpuid",TERM,GO_ON,0},	{"bt",TERM,RMw,1},
1107/*  [A4]  */	{"shld",TERM,DSHIFT,1},	{"shld",TERM,DSHIFTcl,1},
1108		INVALID,		INVALID,
1109/*  [A8]  */	{"push",TERM,LSEG,0x03},{"pop",TERM,LSEG,0x03},
1110		{"rsm",TERM,GO_ON,0, INVALID_64}, {"bts",TERM,RMw,1},
1111/*  [AC]  */	{"shrd",TERM,DSHIFT,1},	{"shrd",TERM,DSHIFTcl,1},
1112		{"",op0FAE,TERM,0},	{"imul",TERM,MRw,1} },
1113/*  [B0]  */ {  {"cmpxchgb",TERM,XINST,0},{"cmpxchg",TERM,XINST,1},
1114		{"lss",TERM,MR,0},	{"btr",TERM,RMw,1},
1115/*  [B4]  */	{"lfs",TERM,MR,0},	{"lgs",TERM,MR,0},
1116		{"movzb",TERM,MOVZ,1},	{"movzw",TERM,MOVZ,1},
1117/*  [B8]  */	{"popcnt",TERM,SSE4MRw,0},		INVALID,
1118		{"",op0FBA,TERM,0},	{"btc",TERM,RMw,1},
1119/*  [BC]  */	{"bsf",TERM,MRw,1},	{"bsr",TERM,MRw,1},
1120		{"movsb",TERM,MOVZ,1},	{"movsw",TERM,MOVZ,1} },
1121/*  [C0]  */ {  {"xaddb",TERM,XINST,0},	{"xadd",TERM,XINST,1},
1122		{"cmp",TERM,SSE2i,0},	{"movnti",TERM,RMw,0},
1123/*  [C4]  */	{"pinsrw",TERM,SSE2i,0},{"pextrw",TERM,SSE2i,0},
1124		{"shuf",TERM,SSE2i,0},	{"cmpxchg8b",TERM,M,0},
1125/*  [C8]  */	{"bswap",TERM,BSWAP,0},	{"bswap",TERM,BSWAP,0},
1126		{"bswap",TERM,BSWAP,0},	{"bswap",TERM,BSWAP,0},
1127/*  [CC]  */	{"bswap",TERM,BSWAP,0},	{"bswap",TERM,BSWAP,0},
1128		{"bswap",TERM,BSWAP,0},	{"bswap",TERM,BSWAP,0} },
1129/*  [D0]  */ {  {"addsubp",TERM,SSE2,0},{"psrlw",TERM,SSE2,0},
1130		{"psrld",TERM,SSE2,0},	{"psrlq",TERM,SSE2,0},
1131/*  [D4]  */	{"paddq",TERM,SSE2,0},	{"pmullw",TERM,SSE2,0},
1132		{"mov",TERM,SSE2tm,0},	{"pmovmskb",TERM,SSE2,0},
1133/*  [D8]  */	{"psubusb",TERM,SSE2,0},{"psubusw",TERM,SSE2,0},
1134		{"pminub",TERM,SSE2,0},	{"pand",TERM,SSE2,0},
1135/*  [DC]  */	{"paddusb",TERM,SSE2,0},{"paddusw",TERM,SSE2,0},
1136		{"pmaxub",TERM,SSE2,0},	{"pandn",TERM,SSE2,0} },
1137/*  [E0]  */ {  {"pavgb",TERM,SSE2,0},	{"psraw",TERM,SSE2,0},
1138		{"psrad",TERM,SSE2,0},	{"pavgw",TERM,SSE2,0},
1139/*  [E4]  */	{"pmulhuw",TERM,SSE2,0},{"pmulhw",TERM,SSE2,0},
1140		{"cvt",TERM,SSE2,0},	{"movn",TERM,SSE2tm,0},
1141/*  [E8]  */	{"psubsb",TERM,SSE2,0},	{"psubsw",TERM,SSE2,0},
1142		{"pminsw",TERM,SSE2,0},	{"por",TERM,SSE2,0},
1143/*  [EC]  */	{"paddsb",TERM,SSE2,0},	{"paddsw",TERM,SSE2,0},
1144		{"pmaxsw",TERM,SSE2,0},	{"pxor",TERM,SSE2,0} },
1145/*  [F0]  */ {  {"lddqu",TERM,SSE2,0},	{"psllw",TERM,SSE2,0},
1146		{"pslld",TERM,SSE2,0},	{"psllq",TERM,SSE2,0},
1147/*  [F4]  */	{"pmuludq",TERM,SSE2,0},{"pmaddwd",TERM,SSE2,0},
1148		{"psadbw",TERM,SSE2,0},	{"maskmov",TERM,SSE2,0},
1149/*  [F8]  */	{"psubb",TERM,SSE2,0},	{"psubw",TERM,SSE2,0},
1150		{"psubd",TERM,SSE2,0},	{"psubq",TERM,SSE2,0},
1151/*  [FC]  */	{"paddb",TERM,SSE2,0},	{"paddw",TERM,SSE2,0},
1152		{"paddd",TERM,SSE2,0},	INVALID },
1153};
1154
1155/*
1156 * Decode table for 0x80 opcodes
1157 */
1158static const struct instable op80[8] = {
1159/*  [0]  */	{"addb",TERM,IMlw,0},	{"orb",TERM,IMw,0},
1160		{"adcb",TERM,IMlw,0},	{"sbbb",TERM,IMlw,0},
1161/*  [4]  */	{"andb",TERM,IMw,0},	{"subb",TERM,IMlw,0},
1162		{"xorb",TERM,IMw,0},	{"cmpb",TERM,IMlw,0},
1163};
1164
1165/*
1166 * Decode table for 0x81 opcodes.
1167 */
1168static const struct instable op81[8] = {
1169/*  [0]  */	{"add",TERM,IMlw,1},	{"or",TERM,IMw,1},
1170		{"adc",TERM,IMlw,1},	{"sbb",TERM,IMlw,1},
1171/*  [4]  */	{"and",TERM,IMw,1},	{"sub",TERM,IMlw,1},
1172		{"xor",TERM,IMw,1},	{"cmp",TERM,IMlw,1},
1173};
1174
1175/*
1176 * Decode table for 0x82 opcodes.
1177 */
1178static const struct instable op82[8] = {
1179/*  [0]  */	{"addb",TERM,IMlw,0},	INVALID,
1180		{"adcb",TERM,IMlw,0},	{"sbbb",TERM,IMlw,0},
1181/*  [4]  */	INVALID,		{"subb",TERM,IMlw,0},
1182		INVALID,		{"cmpb",TERM,IMlw,0},
1183};
1184
1185/*
1186 * Decode table for 0x83 opcodes.
1187 */
1188static const struct instable op83[8] = {
1189/*  [0]  */	{"add",TERM,IMlw,1},	{"or",TERM,IMlw,1},
1190		{"adc",TERM,IMlw,1},	{"sbb",TERM,IMlw,1},
1191/*  [4]  */	{"and",TERM,IMlw,1},	{"sub",TERM,IMlw,1},
1192		{"xor",TERM,IMlw,1},	{"cmp",TERM,IMlw,1},
1193};
1194
1195/*
1196 * Decode table for 0xC0 opcodes.
1197 */
1198static const struct instable opC0[8] = {
1199/*  [0]  */	{"rolb",TERM,MvI,0},	{"rorb",TERM,MvI,0},
1200		{"rclb",TERM,MvI,0},	{"rcrb",TERM,MvI,0},
1201/*  [4]  */	{"shlb",TERM,MvI,0},	{"shrb",TERM,MvI,0},
1202		INVALID,		{"sarb",TERM,MvI,0},
1203};
1204
1205/*
1206 * Decode table for 0xD0 opcodes.
1207 */
1208static const struct instable opD0[8] = {
1209/*  [0]  */	{"rolb",TERM,Mv,0},	{"rorb",TERM,Mv,0},
1210		{"rclb",TERM,Mv,0},	{"rcrb",TERM,Mv,0},
1211/*  [4]  */	{"shlb",TERM,Mv,0},	{"shrb",TERM,Mv,0},
1212		INVALID,		{"sarb",TERM,Mv,0},
1213};
1214
1215/*
1216 * Decode table for 0xC1 opcodes.
1217 * 186 instruction set
1218 */
1219static const struct instable opC1[8] = {
1220/*  [0]  */	{"rol",TERM,MvI,1},	{"ror",TERM,MvI,1},
1221		{"rcl",TERM,MvI,1},	{"rcr",TERM,MvI,1},
1222/*  [4]  */	{"shl",TERM,MvI,1},	{"shr",TERM,MvI,1},
1223		INVALID,		{"sar",TERM,MvI,1},
1224};
1225
1226/*
1227 * Decode table for 0xD1 opcodes.
1228 */
1229static const struct instable opD1[8] = {
1230/*  [0]  */	{"rol",TERM,Mv,1},	{"ror",TERM,Mv,1},
1231		{"rcl",TERM,Mv,1},	{"rcr",TERM,Mv,1},
1232/*  [4]  */	{"shl",TERM,Mv,1},	{"shr",TERM,Mv,1},
1233		INVALID,		{"sar",TERM,Mv,1},
1234};
1235
1236/*
1237 * Decode table for 0xD2 opcodes.
1238 */
1239static const struct instable opD2[8] = {
1240/*  [0]  */	{"rolb",TERM,Mv,0},	{"rorb",TERM,Mv,0},
1241		{"rclb",TERM,Mv,0},	{"rcrb",TERM,Mv,0},
1242/*  [4]  */	{"shlb",TERM,Mv,0},	{"shrb",TERM,Mv,0},
1243		INVALID,		{"sarb",TERM,Mv,0},
1244};
1245
1246/*
1247 * Decode table for 0xD3 opcodes.
1248 */
1249static const struct instable opD3[8] = {
1250/*  [0]  */	{"rol",TERM,Mv,1},	{"ror",TERM,Mv,1},
1251		{"rcl",TERM,Mv,1},	{"rcr",TERM,Mv,1},
1252/*  [4]  */	{"shl",TERM,Mv,1},	{"shr",TERM,Mv,1},
1253		INVALID,		{"sar",TERM,Mv,1},
1254};
1255
1256/*
1257 * Decode table for 0xF6 opcodes.
1258 */
1259static const struct instable opF6[8] = {
1260/*  [0]  */	{"testb",TERM,IMw,0},	INVALID,
1261		{"notb",TERM,Mw,0},	{"negb",TERM,Mw,0},
1262/*  [4]  */	{"mulb",TERM,MA,0},	{"imulb",TERM,MA,0},
1263		{"divb",TERM,MA,0},	{"idivb",TERM,MA,0},
1264};
1265
1266/*
1267 * Decode table for 0xF7 opcodes.
1268 */
1269static const struct instable opF7[8] = {
1270/*  [0]  */	{"test",TERM,IMw,1},	INVALID,
1271		{"not",TERM,Mw,1},	{"neg",TERM,Mw,1},
1272/*  [4]  */	{"mul",TERM,MA,1},	{"imul",TERM,MA,1},
1273		{"div",TERM,MA,1},	{"idiv",TERM,MA,1},
1274};
1275
1276/*
1277 * Decode table for 0xFE opcodes.
1278 */
1279static const struct instable opFE[8] = {
1280/*  [0]  */	{"incb",TERM,Mw,0},	{"decb",TERM,Mw,0},
1281		INVALID,		INVALID,
1282/*  [4]  */	INVALID,		INVALID,
1283		INVALID,		INVALID,
1284};
1285
1286/*
1287 * Decode table for 0xFF opcodes.
1288 */
1289static const struct instable opFF[8] = {
1290/*  [0]  */	{"inc",TERM,Mw,1},	{"dec",TERM,Mw,1},
1291		{"call",TERM,INM,1},	{"lcall",TERM,INMl,1},
1292/*  [4]  */	{"jmp",TERM,INM,1},	{"ljmp",TERM,INMl,1},
1293		{"push",TERM,M,0x03},	INVALID,
1294};
1295
1296/* for 287 instructions, which are a mess to decode */
1297static const struct instable opFP1n2[8][8] = {
1298/* bit pattern:	1101 1xxx MODxx xR/M */
1299/*  [0,0]  */ { {"fadds",TERM,M,0},	{"fmuls",TERM,M,0},
1300		{"fcoms",TERM,M,0},	{"fcomps",TERM,M,0},
1301/*  [0,4]  */	{"fsubs",TERM,M,0},	{"fsubrs",TERM,M,0},
1302		{"fdivs",TERM,M,0},	{"fdivrs",TERM,M,0} },
1303/*  [1,0]  */ { {"flds",TERM,M,0},	INVALID,
1304		{"fsts",TERM,M,0},	{"fstps",TERM,M,0},
1305/*  [1,4]  */	{"fldenv",TERM,M,1},	{"fldcw",TERM,M,0},
1306		{"fnstenv",TERM,M,1},	{"fnstcw",TERM,M,0} },
1307/*  [2,0]  */ { {"fiaddl",TERM,M,0},	{"fimull",TERM,M,0},
1308		{"ficoml",TERM,M,0},	{"ficompl",TERM,M,0},
1309/*  [2,4]  */	{"fisubl",TERM,M,0},	{"fisubrl",TERM,M,0},
1310		{"fidivl",TERM,M,0},	{"fidivrl",TERM,M,0} },
1311/*  [3,0]  */ { {"fildl",TERM,Mnol,0},	{"fisttpl",TERM,M,0},
1312		{"fistl",TERM,M,0},	{"fistpl",TERM,Mnol,0},
1313/*  [3,4]  */	INVALID,		{"fldt",TERM,M,0},
1314		INVALID,		{"fstpt",TERM,M,0} },
1315/*  [4,0]  */ { {"faddl",TERM,M,0},	{"fmull",TERM,M,0},
1316		{"fcoml",TERM,M,0},	{"fcompl",TERM,M,0},
1317/*  [4,1]  */	{"fsubl",TERM,M,0},	{"fsubrl",TERM,M,0},
1318		{"fdivl",TERM,M,0},	{"fdivrl",TERM,M,0} },
1319/*  [5,0]  */ { {"fldl",TERM,M,0},	{"fisttpll",TERM,M,0},
1320		{"fstl",TERM,M,0},	{"fstpl",TERM,M,0},
1321/*  [5,4]  */	{"frstor",TERM,M,1},	INVALID,
1322		{"fnsave",TERM,M,1},	{"fnstsw",TERM,M,0} },
1323/*  [6,0]  */ { {"fiadds",TERM,M,0},	{"fimuls",TERM,M,0},
1324		{"ficoms",TERM,M,0},	{"ficomps",TERM,M,0},
1325/*  [6,4]  */	{"fisubs",TERM,M,0},	{"fisubrs",TERM,M,0},
1326		{"fidivs",TERM,M,0},	{"fidivrs",TERM,M,0} },
1327/*  [7,0]  */ { {"filds",TERM,M,0},	{"fisttps",TERM,M,0},
1328		{"fists",TERM,M,0},	{"fistps",TERM,M,0},
1329/*  [7,4]  */	{"fbld",TERM,M,0},	{"fildq",TERM,M,0},
1330		{"fbstp",TERM,M,0},	{"fistpq",TERM,M,0} },
1331};
1332
1333static const struct instable opFP3[8][8] = {
1334/* bit  pattern:	1101 1xxx 11xx xREG */
1335/*  [0,0]  */ { {"fadd",TERM,FF,0},	{"fmul",TERM,FF,0},
1336		{"fcom",TERM,F,0},	{"fcomp",TERM,F,0},
1337/*  [0,4]  */	{"fsub",TERM,FF,0},	{"fsubr",TERM,FF,0},
1338		{"fdiv",TERM,FF,0},	{"fdivr",TERM,FF,0} },
1339/*  [1,0]  */ { {"fld",TERM,F,0},	{"fxch",TERM,F,0},
1340		{"fnop",TERM,GO_ON,0},	{"fstp",TERM,F,0},
1341/*  [1,4]  */	INVALID,		INVALID,
1342		INVALID,		INVALID },
1343/*  [2,0]  */ { {"fcmovb",TERM,FF,0},	{"fcmove",TERM,FF,0},
1344		{"fcmovbe",TERM,FF,0},	{"fcmovu",TERM,FF,0},
1345/*  [2,4]  */	INVALID,		{"fucompp",TERM,GO_ON,0},
1346		INVALID,		INVALID },
1347/*  [3,0]  */ { {"fcmovnb",TERM,FF,0},	{"fcmovne",TERM,FF,0},
1348		{"fcmovnbe",TERM,FF,0},	{"fcmovnu",TERM,FF,0},
1349/*  [3,4]  */	INVALID,		{"fucomi",TERM,FF,0},
1350		{"fcomi",TERM,FF,0},	INVALID },
1351/*  [4,0]  */ { {"fadd",TERM,FF,0},	{"fmul",TERM,FF,0},
1352		{"fcom",TERM,F,0},	{"fcomp",TERM,F,0},
1353/*  [4,4]  */	{"fsub",TERM,FF,0},	{"fsubr",TERM,FF,0},
1354		{"fdiv",TERM,FF,0},	{"fdivr",TERM,FF,0} },
1355/*  [5,0]  */ { {"ffree",TERM,F,0},	{"fxch",TERM,F,0},
1356		{"fst",TERM,F,0},	{"fstp",TERM,F,0},
1357/*  [5,4]  */	{"fucom",TERM,F,0},	{"fucomp",TERM,F,0},
1358		INVALID,		INVALID },
1359/*  [6,0]  */ { {"faddp",TERM,FF,0},	{"fmulp",TERM,FF,0},
1360		{"fcomp",TERM,F,0},	{"fcompp",TERM,GO_ON,0},
1361/*  [6,4]  */	{"fsubp",TERM,FF,0},	{"fsubrp",TERM,FF,0},
1362		{"fdivp",TERM,FF,0},	{"fdivrp",TERM,FF,0} },
1363/*  [7,0]  */ { {"ffreep",TERM,F,0},	{"fxch",TERM,F,0},
1364		{"fstp",TERM,F,0},	{"fstp",TERM,F,0},
1365/*  [7,4]  */	{"fnstsw",TERM,M,0},	{"fucomip",TERM,FF,0},
1366		{"fcomip",TERM,FF,0},	INVALID },
1367};
1368
1369static const struct instable opFP4[4][8] = {
1370/* bit pattern:	1101 1001 111x xxxx */
1371/*  [0,0]  */ { {"fchs",TERM,GO_ON,0},	{"fabs",TERM,GO_ON,0},
1372		INVALID,		INVALID,
1373/*  [0,4]  */	{"ftst",TERM,GO_ON,0},	{"fxam",TERM,GO_ON,0},
1374		INVALID,		INVALID },
1375/*  [1,0]  */ { {"fld1",TERM,GO_ON,0},	{"fldl2t",TERM,GO_ON,0},
1376		{"fldl2e",TERM,GO_ON,0},{"fldpi",TERM,GO_ON,0},
1377/*  [1,4]  */	{"fldlg2",TERM,GO_ON,0},{"fldln2",TERM,GO_ON,0},
1378		{"fldz",TERM,GO_ON,0},	INVALID },
1379/*  [2,0]  */ { {"f2xm1",TERM,GO_ON,0},	{"fyl2x",TERM,GO_ON,0},
1380		{"fptan",TERM,GO_ON,0},	{"fpatan",TERM,GO_ON,0},
1381/*  [2,4]  */	{"fxtract",TERM,GO_ON,0},{"fprem1",TERM,GO_ON,0},
1382		{"fdecstp",TERM,GO_ON,0},{"fincstp",TERM,GO_ON,0} },
1383/*  [3,0]  */ { {"fprem",TERM,GO_ON,0},	{"fyl2xp1",TERM,GO_ON,0},
1384		{"fsqrt",TERM,GO_ON,0},	{"fsincos",TERM,GO_ON,0},
1385/*  [3,4]  */	{"frndint",TERM,GO_ON,0},{"fscale",TERM,GO_ON,0},
1386		{"fsin",TERM,GO_ON,0},	{"fcos",TERM,GO_ON,0} },
1387};
1388
1389static const struct instable opFP5[8] = {
1390/* bit pattern:	1101 1011 1110 0xxx */
1391/*  [0]  */	INVALID,		INVALID,
1392		{"fnclex",TERM,GO_ON,0},{"fninit",TERM,GO_ON,0},
1393/*  [4]  */	{"fsetpm",TERM,GO_ON,0},INVALID,
1394		INVALID,		INVALID,
1395};
1396
1397/*
1398 * Main decode table for the op codes.  The first two nibbles
1399 * will be used as an index into the table.  If there is a
1400 * a need to further decode an instruction, the array to be
1401 * referenced is indicated with the other two entries being
1402 * empty.
1403 */
1404static const struct instable distable[16][16] = {
1405/* [0,0] */  {  {"addb",TERM,RMw,0},	{"add",TERM,RMw,1},
1406		{"addb",TERM,MRw,0},	{"add",TERM,MRw,1},
1407/* [0,4] */	{"addb",TERM,IA,0},	{"add",TERM,IA,1},
1408		{"push",TERM,SEG,0x03,INVALID_64},
1409					{"pop",TERM,SEG,0x03,INVALID_64},
1410/* [0,8] */	{"orb",TERM,RMw,0},	{"or",TERM,RMw,1},
1411		{"orb",TERM,MRw,0},	{"or",TERM,MRw,1},
1412/* [0,C] */	{"orb",TERM,IA,0},	{"or",TERM,IA,1},
1413		{"push",TERM,SEG,0x03,INVALID_64},
1414				    {"",(const struct instable *)op0F,TERM,0} },
1415/* [1,0] */  {  {"adcb",TERM,RMw,0},	{"adc",TERM,RMw,1},
1416		{"adcb",TERM,MRw,0},	{"adc",TERM,MRw,1},
1417/* [1,4] */	{"adcb",TERM,IA,0},	{"adc",TERM,IA,1},
1418		{"push",TERM,SEG,0x03,INVALID_64},
1419					{"pop",TERM,SEG,0x03,INVALID_64},
1420/* [1,8] */	{"sbbb",TERM,RMw,0},	{"sbb",TERM,RMw,1},
1421		{"sbbb",TERM,MRw,0},	{"sbb",TERM,MRw,1},
1422/* [1,C] */	{"sbbb",TERM,IA,0},	{"sbb",TERM,IA,1},
1423		{"push",TERM,SEG,0x03,INVALID_64},
1424					{"pop",TERM,SEG,0x03,INVALID_64} },
1425/* [2,0] */  {  {"andb",TERM,RMw,0},	{"and",TERM,RMw,1},
1426		{"andb",TERM,MRw,0},	{"and",TERM,MRw,1},
1427/* [2,4] */	{"andb",TERM,IA,0},	{"and",TERM,IA,1},
1428		{"%es:",TERM,OVERRIDE,0},
1429					{"daa",TERM,GO_ON,0,INVALID_64},
1430/* [2,8] */	{"subb",TERM,RMw,0},	{"sub",TERM,RMw,1},
1431		{"subb",TERM,MRw,0},	{"sub",TERM,MRw,1},
1432/* [2,C] */	{"subb",TERM,IA,0},	{"sub",TERM,IA,1},
1433		{"%cs:",TERM,OVERRIDE,0},
1434					{"das",TERM,GO_ON,0,INVALID_64} },
1435/* [3,0] */  {  {"xorb",TERM,RMw,0},	{"xor",TERM,RMw,1},
1436		{"xorb",TERM,MRw,0},	{"xor",TERM,MRw,1},
1437/* [3,4] */	{"xorb",TERM,IA,0},	{"xor",TERM,IA,1},
1438		{"%ss:",TERM,OVERRIDE,0},
1439					{"aaa",TERM,GO_ON,0,INVALID_64},
1440/* [3,8] */	{"cmpb",TERM,RMw,0},	{"cmp",TERM,RMw,1},
1441		{"cmpb",TERM,MRw,0},	{"cmp",TERM,MRw,1},
1442/* [3,C] */	{"cmpb",TERM,IA,0},	{"cmp",TERM,IA,1},
1443		{"%ds:",TERM,OVERRIDE,0},
1444					{"aas",TERM,GO_ON,0,INVALID_64} },
1445/* [4,0] */  {  {"inc",TERM,R,1,&opREX},{"inc",TERM,R,1,&opREX},
1446		{"inc",TERM,R,1,&opREX},{"inc",TERM,R,1,&opREX},
1447/* [4,4] */	{"inc",TERM,R,1,&opREX},{"inc",TERM,R,1,&opREX},
1448		{"inc",TERM,R,1,&opREX},{"inc",TERM,R,1,&opREX},
1449/* [4,8] */	{"dec",TERM,R,1,&opREX},{"dec",TERM,R,1,&opREX},
1450		{"dec",TERM,R,1,&opREX},{"dec",TERM,R,1,&opREX},
1451/* [4,C] */	{"dec",TERM,R,1,&opREX},{"dec",TERM,R,1,&opREX},
1452		{"dec",TERM,R,1,&opREX},{"dec",TERM,R,1,&opREX} },
1453/* [5,0] */  {  {"push",TERM,R,0x03},	{"push",TERM,R,0x03},
1454		{"push",TERM,R,0x03},	{"push",TERM,R,0x03},
1455/* [5,4] */	{"push",TERM,R,0x03},	{"push",TERM,R,0x03},
1456		{"push",TERM,R,0x03},	{"push",TERM,R,0x03},
1457/* [5,8] */	{"pop",TERM,R,0x03},	{"pop",TERM,R,0x03},
1458		{"pop",TERM,R,0x03},	{"pop",TERM,R,0x03},
1459/* [5,C] */	{"pop",TERM,R,0x03},	{"pop",TERM,R,0x03},
1460		{"pop",TERM,R,0x03},	{"pop",TERM,R,0x03} },
1461/* [6,0] */  {  {"pusha",TERM,GO_ON,1,INVALID_64},
1462					{"popa",TERM,GO_ON,1,INVALID_64},
1463		{"bound",TERM,MR,0,INVALID_64},
1464					{"arpl",TERM,RMw,0,&op_movsl},
1465/* [6,4] */	{"%fs:",TERM,OVERRIDE,0},
1466					{"%gs:",TERM,OVERRIDE,0},
1467		{"data16",TERM,DM,0},	{"addr16",TERM,AM,0},
1468/* [6,8] */	{"push",TERM,I,0x03},	{"imul",TERM,IMUL,1},
1469		{"push",TERM,Ib,0x03},	{"imul",TERM,IMUL,1},
1470/* [6,C] */	{"insb",TERM,GO_ON,0},	{"ins",TERM,GO_ON,1},
1471		{"outsb",TERM,GO_ON,0},	{"outs",TERM,GO_ON,1} },
1472/* [7,0] */  {  {"jo",TERM,BD,0},	{"jno",TERM,BD,0},
1473		{"jb",TERM,BD,0},	{"jae",TERM,BD,0},
1474/* [7,4] */	{"je",TERM,BD,0},	{"jne",TERM,BD,0},
1475		{"jbe",TERM,BD,0},	{"ja",TERM,BD,0},
1476/* [7,8] */	{"js",TERM,BD,0},	{"jns",TERM,BD,0},
1477		{"jp",TERM,BD,0},	{"jnp",TERM,BD,0},
1478/* [7,C] */	{"jl",TERM,BD,0},	{"jge",TERM,BD,0},
1479		{"jle",TERM,BD,0},	{"jg",TERM,BD,0} },
1480/* [8,0] */  {  {"",op80,TERM,0},	{"",op81,TERM,0},
1481		{"",op82,TERM,0},	{"",op83,TERM,0},
1482/* [8,4] */	{"testb",TERM,MRw,0},	{"test",TERM,MRw,1},
1483		{"xchgb",TERM,MRw,0},	{"xchg",TERM,MRw,1},
1484/* [8,8] */	{"movb",TERM,RMw,0},	{"mov",TERM,RMw,1},
1485		{"movb",TERM,MRw,0},	{"mov",TERM,MRw,1},
1486/* [8,C] */	{"mov",TERM,SM,1},	{"lea",TERM,MR,1},
1487		{"mov",TERM,MS,1},	{"pop",TERM,M,0x03} },
1488/* [9,0] */  {  {"nop",TERM,GO_ON,0},	{"xchg",TERM,RA,1},
1489		{"xchg",TERM,RA,1},	{"xchg",TERM,RA,1},
1490/* [9,4] */	{"xchg",TERM,RA,1},	{"xchg",TERM,RA,0},
1491		{"xchg",TERM,RA,1},	{"xchg",TERM,RA,1},
1492/* [9,8] */	{"",TERM,CBW,0},	{"",TERM,CWD,0},
1493		{"lcall",TERM,SO,0},	{"wait/",TERM,PREFIX,0},
1494/* [9,C] */	{"pushf",TERM,GO_ON,0},	{"popf",TERM,GO_ON,0},
1495		{"sahf",TERM,GO_ON,0},	{"lahf",TERM,GO_ON,0} },
1496/* [A,0] */  {  {"movb",TERM,OA,0},	{"mov",TERM,OA,1},
1497		{"movb",TERM,AO,0},	{"mov",TERM,AO,1},
1498/* [A,4] */	{"movsb",TERM,SD,0},	{"movs",TERM,SD,1},
1499		{"cmpsb",TERM,SD,0},	{"cmps",TERM,SD,1},
1500/* [A,8] */	{"testb",TERM,IA,0},	{"test",TERM,IA,1},
1501		{"stosb",TERM,AD,0},	{"stos",TERM,AD,1},
1502/* [A,C] */	{"lodsb",TERM,SA,0},	{"lods",TERM,SA,1},
1503		{"scasb",TERM,AD,0},	{"scas",TERM,AD,1} },
1504/* [B,0] */  {  {"movb",TERM,IR,0},	{"movb",TERM,IR,0},
1505		{"movb",TERM,IR,0},	{"movb",TERM,IR,0},
1506/* [B,4] */	{"movb",TERM,IR,0},	{"movb",TERM,IR,0},
1507		{"movb",TERM,IR,0},	{"movb",TERM,IR,0},
1508/* [B,8] */	{"mov",TERM,IR64,1},	{"mov",TERM,IR64,1},
1509		{"mov",TERM,IR64,1},	{"mov",TERM,IR64,1},
1510/* [B,C] */	{"mov",TERM,IR64,1},	{"mov",TERM,IR64,1},
1511		{"mov",TERM,IR64,1},	{"mov",TERM,IR64,1} },
1512/* [C,0] */  {  {"",opC0,TERM,0},	{"",opC1,TERM,0},
1513		{"ret",TERM,RET,1},	{"ret",TERM,GO_ON,0},
1514/* [C,4] */	{"les",TERM,MR,0,INVALID_64},
1515					{"lds",TERM,MR,0,INVALID_64},
1516		{"movb",TERM,IMw,0},	{"mov",TERM,IMw,1},
1517/* [C,8] */	{"enter",TERM,ENTER,0},	{"leave",TERM,GO_ON,0},
1518		{"lret",TERM,RET,1},	{"lret",TERM,GO_ON,0},
1519/* [C,C] */	{"int",TERM,INT3,0},	{"int",TERM,Ib,0},
1520		{"into",TERM,GO_ON,0,INVALID_64},
1521					{"iret",TERM,GO_ON,0} },
1522/* [D,0] */  {  {"",opD0,TERM,0},	{"",opD1,TERM,0},
1523		{"",opD2,TERM,0},	{"",opD3,TERM,0},
1524/* [D,4] */	{"aam",TERM,U,0,INVALID_64},
1525					{"aad",TERM,U,0,INVALID_64},
1526		{"falc",TERM,GO_ON,0},	{"xlat",TERM,GO_ON,0},
1527/* 287 instructions.  Note that although the indirect field		*/
1528/* indicates opFP1n2 for further decoding, this is not necessarily	*/
1529/* the case since the opFP arrays are not partitioned according to key1	*/
1530/* and key2.  opFP1n2 is given only to indicate that we haven't		*/
1531/* finished decoding the instruction.					*/
1532/* [D,8] */	{"",(const struct instable *)opFP1n2,TERM,0},
1533		{"",(const struct instable *)opFP1n2,TERM,0},
1534		{"",(const struct instable *)opFP1n2,TERM,0},
1535		{"",(const struct instable *)opFP1n2,TERM,0},
1536/* [D,C] */	{"",(const struct instable *)opFP1n2,TERM,0},
1537		{"",(const struct instable *)opFP1n2,TERM,0},
1538		{"",(const struct instable *)opFP1n2,TERM,0},
1539		{"",(const struct instable *)opFP1n2,TERM,0} },
1540/* [E,0] */  {  {"loopnz",TERM,BD,0},	{"loopz",TERM,BD,0},
1541		{"loop",TERM,BD,0},	{"jcxz",TERM,BD,0},
1542/* [E,4] */	{"inb",TERM,Pi,0},	{"in",TERM,Pi,1},
1543		{"outb",TERM,Po,0},	{"out",TERM,Po,1},
1544/* [E,8] */	{"call",TERM,D,0x03},	{"jmp",TERM,D,0x02},
1545		{"ljmp",TERM,SO,0},	{"jmp",TERM,BD,0},
1546/* [E,C] */	{"inb",TERM,Vi,0},	{"in",TERM,Vi,1},
1547		{"outb",TERM,Vo,0},	{"out",TERM,Vo,1} },
1548/* [F,0] */  {  {"lock/",TERM,PREFIX,0}, INVALID,
1549		{"repnz/",TERM,PREFIX,0}, {"repz/",TERM,PREFIX,0},
1550/* [F,4] */	{"hlt",TERM,GO_ON,0},	{"cmc",TERM,GO_ON,0},
1551		{"",opF6,TERM,0},	{"",opF7,TERM,0},
1552/* [F,8] */	{"clc",TERM,GO_ON,0},	{"stc",TERM,GO_ON,0},
1553		{"cli",TERM,GO_ON,0},	{"sti",TERM,GO_ON,0},
1554/* [F,C] */	{"cld",TERM,GO_ON,0},	{"std",TERM,GO_ON,0},
1555		{"",opFE,TERM,0},	{"",opFF,TERM,0} },
1556};
1557
1558static const char *get_reg_name(int reg, int wbit, int data16, int rex)
1559{
1560	const char *reg_name;
1561
1562	// A REX prefix takes precedent over a 66h prefix.
1563	if (rex != 0) {
1564		reg_name = REG32[reg + (REX_R(rex) << 3)][wbit + REX_W(rex)];
1565	} else if (data16) {
1566		reg_name = REG16[reg][wbit];
1567	} else {
1568		reg_name = REG32[reg][wbit];
1569	}
1570
1571	return reg_name;
1572}
1573
1574static const char *get_r_m_name(int r_m, int wbit, int data16, int rex)
1575{
1576	const char *reg_name;
1577
1578	// A REX prefix takes precedent over a 66h prefix.
1579	if (rex != 0) {
1580		reg_name = REG32[r_m + (REX_B(rex) << 3)][wbit + REX_W(rex)];
1581	} else if (data16) {
1582		reg_name = REG16[r_m][wbit];
1583	} else {
1584		reg_name = REG32[r_m][wbit];
1585	}
1586
1587	return reg_name;
1588}
1589
1590// Returns the xmm register number referenced by reg and rex.
1591static unsigned int xmm_reg(int reg, int rex)
1592{
1593	return (reg + (REX_R(rex) << 3));
1594}
1595
1596// Returns the xmm register number referenced by r_m and rex.
1597static unsigned int xmm_rm(int r_m, int rex)
1598{
1599	return (r_m + (REX_B(rex) << 3));
1600}
1601
1602/*
1603 * This is passed to the llvm disassembler.
1604 */
1605struct disassemble_info {
1606  enum bool verbose;
1607  /* Relocation information.  */
1608  struct relocation_info *sorted_relocs;
1609  uint32_t nsorted_relocs;
1610  /* Symbol table.  */
1611  struct nlist *symbols;
1612  struct nlist_64 *symbols64;
1613  uint32_t nsymbols;
1614  /* Symbols sorted by address.  */
1615  struct symbol *sorted_symbols;
1616  uint32_t nsorted_symbols;
1617  /* String table.  */
1618  char *strings;
1619  uint32_t strings_size;
1620  /* Other useful info.  */
1621  uint32_t ncmds;
1622  uint32_t sizeofcmds;
1623  struct load_command *load_commands;
1624  enum byte_sex object_byte_sex;
1625  uint32_t *indirect_symbols;
1626  uint32_t nindirect_symbols;
1627  char *sect;
1628  uint32_t left;
1629  uint32_t addr;
1630  uint32_t sect_addr;
1631  cpu_type_t cputype;
1632  LLVMDisasmContextRef i386_dc;
1633  LLVMDisasmContextRef x86_64_dc;
1634  char *object_addr;
1635  uint32_t object_size;
1636  struct inst *inst;
1637  struct inst *insts;
1638  uint32_t ninsts;
1639  uint32_t filetype;
1640} dis_info;
1641
1642/*
1643 * i386_disassemble()
1644 */
1645uint32_t
1646i386_disassemble(
1647char *sect,
1648uint32_t left,
1649uint64_t addr,
1650uint64_t sect_addr,
1651enum byte_sex object_byte_sex,
1652struct relocation_info *sorted_relocs,
1653uint32_t nsorted_relocs,
1654struct nlist *symbols,
1655struct nlist_64 *symbols64,
1656uint32_t nsymbols,
1657struct symbol *sorted_symbols,
1658uint32_t nsorted_symbols,
1659char *strings,
1660uint32_t strings_size,
1661uint32_t *indirect_symbols,
1662uint32_t nindirect_symbols,
1663cpu_type_t cputype,
1664struct load_command *load_commands,
1665uint32_t ncmds,
1666uint32_t sizeofcmds,
1667enum bool verbose,
1668enum bool llvm_mc,
1669LLVMDisasmContextRef i386_dc,
1670LLVMDisasmContextRef x86_64_dc,
1671char *object_addr,
1672uint32_t object_size,
1673struct inst *inst,
1674struct inst *insts,
1675uint32_t ninsts,
1676uint32_t filetype)
1677{
1678    char mnemonic[MAX_MNEMONIC+2]; /* one extra for suffix */
1679    const char *seg;
1680    const char *symbol0, *symbol1;
1681    const char *symadd0, *symsub0, *symadd1, *symsub1;
1682    uint32_t value0, value1;
1683    uint64_t imm0, imm1;
1684    uint32_t value0_size, value1_size;
1685    char result0[MAX_RESULT], result1[MAX_RESULT];
1686    const char *indirect_symbol_name;
1687
1688    uint32_t i, length;
1689    unsigned char byte;
1690       unsigned char opcode_suffix;
1691    /* nibbles (4 bits) of the opcode */
1692    unsigned opcode1, opcode2, opcode3, opcode4, opcode5, prefix_byte;
1693    const struct instable *dp, *prefix_dp;
1694    uint32_t wbit, vbit;
1695    enum bool got_modrm_byte;
1696    uint32_t mode, reg, r_m;
1697    const char *reg_name;
1698    enum bool data16;		/* 16- or 32-bit data */
1699    enum bool addr16;		/* 16- or 32-bit addressing */
1700    enum bool sse2;		/* sse2 instruction using xmmreg's */
1701    enum bool mmx;		/* mmx instruction using mmreg's */
1702    unsigned char rex;		/* x86-64 REX prefix */
1703
1704	if(left == 0){
1705	   printf("(end of section)\n");
1706	   return(0);
1707	}
1708
1709	/* Use the llvm disassembler with the -q flag. */
1710	if(qflag || gflag){
1711	    LLVMDisasmContextRef dc;
1712	    char dst[4096];
1713
1714	    dst[4095] = '\0';
1715	    dis_info.verbose = verbose;
1716	    dis_info.sorted_relocs = sorted_relocs;
1717	    dis_info.nsorted_relocs = nsorted_relocs;
1718	    dis_info.symbols = symbols;
1719	    dis_info.symbols64 = symbols64;
1720	    dis_info.nsymbols = nsymbols;
1721	    dis_info.sorted_symbols = sorted_symbols;
1722	    dis_info.nsorted_symbols = nsorted_symbols;
1723	    dis_info.strings = strings;
1724	    dis_info.strings_size = strings_size;
1725	    dis_info.load_commands = load_commands;
1726	    dis_info.object_byte_sex = object_byte_sex;
1727	    dis_info.indirect_symbols = indirect_symbols;
1728	    dis_info.nindirect_symbols = nindirect_symbols;
1729	    dis_info.ncmds = ncmds;
1730	    dis_info.sizeofcmds = sizeofcmds;
1731	    dis_info.sect = sect;
1732	    dis_info.left = left;
1733	    dis_info.addr = addr;
1734	    dis_info.sect_addr = sect_addr;
1735	    dis_info.cputype = cputype;
1736	    dis_info.object_addr = object_addr;
1737	    dis_info.object_size = object_size;
1738	    dis_info.inst = inst;
1739	    dis_info.insts = insts;
1740	    dis_info.ninsts = ninsts;
1741	    dis_info.filetype = filetype;
1742	    if(cputype == CPU_TYPE_I386)
1743		dc = i386_dc;
1744	    else
1745		dc = x86_64_dc;
1746	    length = llvm_disasm_instruction(dc, (uint8_t *)sect, left,
1747					     addr, dst, 4095);
1748	    if(length != 0){
1749		if(inst == NULL || inst->print)
1750		    printf("%s\n", dst);
1751	    }
1752	    else{
1753		if(inst == NULL || inst->print)
1754		    printf("\t.byte 0x%02x #bad opcode\n", 0xff & sect[0]);
1755		length = 1;
1756	    }
1757	    return(length);
1758	}
1759
1760	memset(mnemonic, '\0', sizeof(mnemonic));
1761	seg = "";
1762	symbol0 = NULL;
1763	symbol1 = NULL;
1764	value0 = 0;
1765	value1 = 0;
1766	value0_size = 0;
1767	value1_size = 0;
1768	memset(result0, '\0', sizeof(result0));
1769	memset(result1, '\0', sizeof(result1));
1770	data16 = FALSE;
1771	addr16 = FALSE;
1772	sse2 = FALSE;
1773	mmx = FALSE;
1774	rex = 0;
1775	reg_name = NULL;
1776	wbit = 0;
1777
1778	length = 0;
1779	byte = 0;
1780	opcode4 = 0; /* to remove a compiler warning only */
1781	opcode5 = 0; /* to remove a compiler warning only */
1782	r_m = 0;
1783	reg = 0;
1784	mode = 0;
1785	opcode3 = 0;
1786
1787	/*
1788	 * As long as there is a prefix, the default segment register,
1789	 * addressing-mode, or data-mode in the instruction will be overridden.
1790	 * This may be more general than the chip actually is.
1791	 */
1792	prefix_dp = NULL;
1793	prefix_byte = 0;
1794	for(;;){
1795	    byte = get_value(sizeof(char), sect, &length, &left);
1796	    opcode1 = byte >> 4 & 0xf;
1797	    opcode2 = byte & 0xf;
1798
1799	    dp = &distable[opcode1][opcode2];
1800	    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64 &&
1801	       dp->arch64 != NULL)
1802		dp = dp->arch64;
1803
1804	    if(dp->adr_mode == PREFIX){
1805		if(prefix_dp != NULL)
1806		    printf("%s", dp->name);
1807		else if(llvm_mc == TRUE && byte == 0x9b){
1808		    printf("wait\n");
1809		    return(length);
1810		}
1811		prefix_dp = dp;
1812		prefix_byte = byte;
1813	    }
1814	    else if(dp->adr_mode == AM){
1815		addr16 = !addr16;
1816		prefix_byte = byte;
1817	    }
1818	    else if(dp->adr_mode == DM){
1819		data16 = !data16;
1820		prefix_byte = byte;
1821	    }
1822	    else if(dp->adr_mode == OVERRIDE){
1823		seg = dp->name;
1824		prefix_byte = byte;
1825	    }
1826	    else if(dp->adr_mode == REX){
1827		rex = byte;
1828		/*
1829		 * REX is a prefix, but we don't set prefix_byte here because
1830		 * we use that to detect things related to the other prefixes
1831		 * and we don't want the existence of those bytes to be hidden
1832		 * by the presence of a REX prefix.
1833		 */
1834	    }
1835	    else
1836		break;
1837	}
1838
1839	got_modrm_byte = FALSE;
1840
1841	/*
1842	 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
1843	 * byte so we need to perform a table indirection.
1844	 */
1845	if(dp->indirect == (const struct instable *)op0F){
1846	    byte = get_value(sizeof(char), sect, &length, &left);
1847	    opcode4 = byte >> 4 & 0xf;
1848	    opcode5 = byte & 0xf;
1849	    dp = &op0F[opcode4][opcode5];
1850	    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64 &&
1851	       dp->arch64 != NULL)
1852		dp = dp->arch64;
1853	    if(dp->indirect == op0F38 || dp->indirect == op0F3A){
1854		/*
1855		 * MNI instructions are SSE2ish instructions with an
1856		 * extra byte.  Do the extra indirection here.
1857		 */
1858		byte = get_value(sizeof(char), sect, &length, &left);
1859		dp = &dp->indirect[byte];
1860	    }
1861	    /*
1862	     * SSE and SSE2 instructions have 3 bytes of opcode and the
1863	     * "third opcode byte" is before the other two (where the prefix
1864	     * byte would be).  This is why the prefix byte is saved above and
1865	     * the printing of the last prefix is delayed.
1866	     */
1867	    if(dp->adr_mode == SSE2 ||
1868	       dp->adr_mode == SSE2i ||
1869	       dp->adr_mode == SSE2i1 ||
1870	       dp->adr_mode == SSE2tm ||
1871	       dp->adr_mode == SSE2tfm ||
1872	       dp->adr_mode == SSE4 ||
1873	       dp->adr_mode == SSE4i ||
1874	       dp->adr_mode == SSE4MRw ||
1875	       dp->adr_mode == SSE4CRC ||
1876	       dp->adr_mode == SSE4CRCb ||
1877	       (byte == 0xc7 && prefix_byte == 0xf3)){ /* for vmxon */
1878		prefix_dp = NULL;
1879	    }
1880	    else{
1881		/*
1882		 * 3DNow! instructions have 2 bytes of opcode followed by their
1883		 * operands and then an instruction-specific suffix byte.
1884		 */
1885		if(dp->indirect == (const struct instable *)op0F0F){
1886		    data16 = FALSE;
1887		    mmx = TRUE;
1888		    if(got_modrm_byte == FALSE){
1889			got_modrm_byte = TRUE;
1890			byte = get_value(sizeof(char), sect, &length, &left);
1891			modrm_byte(&mode, &reg, &r_m, byte);
1892		    }
1893		    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size,
1894				result0);
1895		    opcode_suffix = get_value(sizeof(char), sect, &length,
1896					      &left);
1897		    dp = &op0F0F[opcode_suffix >> 4][opcode_suffix & 0x0F];
1898		}
1899		else if(dp->indirect == (const struct instable *)op0F01){
1900		    if(got_modrm_byte == FALSE){
1901			got_modrm_byte = TRUE;
1902			byte = get_value(sizeof(char), sect, &length, &left);
1903			modrm_byte(&mode, &reg, &r_m, byte);
1904			opcode3 = reg;
1905		    }
1906		    if(byte == 0xc8){
1907			data16 = FALSE;
1908			mmx = TRUE;
1909			dp = &op_monitor;
1910		    }
1911		    else if(byte == 0xc9){
1912			data16 = FALSE;
1913			mmx = TRUE;
1914			dp = &op_mwait;
1915		    }
1916		    else if(byte == 0xf9){
1917			data16 = FALSE;
1918			mmx = TRUE;
1919			dp = &op_rdtscp;
1920		    }
1921		    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64){
1922			if(opcode3 == 0x7 && got_modrm_byte &&
1923			   mode == REG_ONLY && r_m == 0) {
1924			    dp = &op_swapgs;
1925			}
1926		    }
1927		    /*
1928		     * To get the 'q' suffix on all 0F 01 /0-3 opcodes in 64
1929		     * bit mode we set the REX_W here.
1930		     */
1931		    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64 &&
1932		       (opcode3 == 0 || opcode3 == 1 || opcode3 == 2 ||
1933			opcode3 == 3))
1934			rex |= 0x8;
1935		}
1936		else{
1937		    /*
1938		     * Since the opcode is not an SSE or SSE2 instruction that
1939		     * uses the prefix byte as the "third opcode byte" print the
1940		     * delayed last prefix if any.
1941		     */
1942		    if(prefix_dp != NULL)
1943			printf("%s", prefix_dp->name);
1944		}
1945            }
1946	}
1947	else{
1948	    /*
1949	     * The "pause" Spin Loop Hint instruction is a "repz" prefix
1950	     * followed by a nop (0x90).
1951	     */
1952	    if(prefix_dp != NULL && prefix_byte == 0xf3 &&
1953	       opcode1 == 0x9 && opcode2 == 0x0){
1954		printf("pause\n");
1955		return(length);
1956	    }
1957	    /*
1958	     * Since the opcode is not an SSE or SSE2 instruction print the
1959	     * delayed last prefix if any.
1960	     */
1961	    if(prefix_dp != NULL){
1962		/*
1963		 * If the prefix is "repz" and the instruction is ins, outs,
1964		 * movs, lods, or stos then the name used is "rep".
1965		 */
1966		if(strcmp(prefix_dp->name, "repz/") == 0 &&
1967		   (byte == 0x6c || byte == 0x6d || /* ins */
1968		    byte == 0x6e || byte == 0x6f || /* outs */
1969		    byte == 0xa4 || byte == 0xa5 || /* movs */
1970		    byte == 0xac || byte == 0xad || /* lods */
1971		    byte == 0xaa || byte == 0xab))  /* stos */
1972		    printf("rep/");
1973		else
1974		    printf("%s", prefix_dp->name);
1975	    }
1976	}
1977
1978	if(dp->indirect != TERM){
1979	    /*
1980	     * This must have been an opcode for which several instructions
1981	     * exist.  The opcode3 field further decodes the instruction.
1982	     */
1983	    if(got_modrm_byte == FALSE){
1984		got_modrm_byte = TRUE;
1985		byte = get_value(sizeof(char), sect, &length, &left);
1986		modrm_byte(&mode, (uint32_t *)&opcode3, &r_m, byte);
1987	    }
1988	    /*
1989	     * decode 287 instructions (D8-DF) from opcodeN
1990	     */
1991	    if(opcode1 == 0xD && opcode2 >= 0x8){
1992		/* instruction form 5 */
1993		if(opcode2 == 0xB && mode == 0x3 && opcode3 == 4)
1994		    dp = &opFP5[r_m];
1995		else if(opcode2 == 0xB && mode == 0x3 && opcode3 > 6){
1996		    printf(".byte 0x%01x%01x, 0x%01x%01x 0x%02x #bad opcode\n",
1997			   (unsigned int)opcode1, (unsigned int)opcode2,
1998			   (unsigned int)opcode4, (unsigned int)opcode5,
1999			   (unsigned int)byte);
2000		    return(length);
2001		}
2002		/* instruction form 4 */
2003		else if(opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4)
2004		    dp = &opFP4[opcode3-4][r_m];
2005		/* instruction form 3 */
2006		else if(mode == 0x3)
2007		    dp = &opFP3[opcode2-8][opcode3];
2008		else /* instruction form 1 and 2 */
2009		    dp = &opFP1n2[opcode2-8][opcode3];
2010	    }
2011	    else
2012		dp = dp->indirect + opcode3;
2013		/* now dp points the proper subdecode table entry */
2014	}
2015
2016	if(dp->indirect != TERM){
2017	    printf(".byte 0x%02x #bad opcode\n", (unsigned int)byte);
2018	    return(length);
2019	}
2020
2021	/*
2022	 * Some addressing modes are implicitly 64-bit.  Set REX.W for those
2023	 * so we don't have to change the logic for them later.
2024	 */
2025	if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64){
2026	    if((dp->flags & IS_POINTER_SIZED) != 0){
2027		rex |= 0x8;	/* Set REX.W if it isn't already set */
2028	    }
2029	}
2030
2031	/* setup the mnemonic with a possible suffix */
2032	if(dp->adr_mode != CBW && dp->adr_mode != CWD){
2033	    if((dp->flags & HAS_SUFFIX) != 0){
2034		if(data16 == TRUE)
2035		    sprintf(mnemonic, "%sw", dp->name);
2036		else{
2037		    if(dp->adr_mode == Mnol || dp->adr_mode == INM ||
2038		       dp->adr_mode == SM || dp->adr_mode == MS)
2039			sprintf(mnemonic, "%s", dp->name);
2040		    else if(REX_W(rex) != 0)
2041			sprintf(mnemonic, "%sq", dp->name);
2042		    else
2043			sprintf(mnemonic, "%sl", dp->name);
2044		}
2045	    }
2046	    else{
2047		sprintf(mnemonic, "%s", dp->name);
2048	    }
2049	    if(dp->adr_mode == BD){
2050		if(strcmp(seg, "%cs:") == 0){
2051		    sprintf(mnemonic, "%s,pn", mnemonic);
2052		    seg = "";
2053		}
2054		else if(strcmp(seg, "%ds:") == 0){
2055		    sprintf(mnemonic, "%s,pt", mnemonic);
2056		    seg = "";
2057		}
2058	    }
2059	}
2060
2061	/*
2062	 * Each instruction has a particular instruction syntax format
2063	 * stored in the disassembly tables.  The assignment of formats
2064	 * to instructions was made by the author.  Individual formats
2065	 * are explained as they are encountered in the following
2066	 * switch construct.
2067	 */
2068	switch(dp -> adr_mode){
2069
2070	case BSWAP:
2071	    reg = opcode5 & 0x7;
2072	    if(rex)
2073		reg_name = REG32[reg + (REX_B(rex) << 3)][1 + REX_W(rex)];
2074	    else
2075		reg_name = get_reg_name(reg, 1, data16, rex);
2076	    printf("%s\t%s\n", mnemonic, reg_name);
2077	    return(length);
2078
2079	case XINST:
2080	    wbit = WBIT(opcode5);
2081	    if(got_modrm_byte == FALSE){
2082		got_modrm_byte = TRUE;
2083		byte = get_value(sizeof(char), sect, &length, &left);
2084		modrm_byte(&mode, &reg, &r_m, byte);
2085	    }
2086	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2087		reg_name = get_reg_name(reg, wbit, data16, rex);
2088	    printf("%s\t%s,", mnemonic, reg_name);
2089	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
2090			  "\n");
2091	    return(length);
2092
2093	/* movsbl movsbw (0x0FBE) or movswl (0x0FBF) */
2094	/* movzbl movzbw (0x0FB6) or mobzwl (0x0FB7) */
2095	/* wbit lives in 2nd byte, note that operands are different sized */
2096	case MOVZ:
2097	    /* Get second operand first so data16 can be destroyed */
2098	    if(got_modrm_byte == FALSE){
2099		got_modrm_byte = TRUE;
2100		byte = get_value(sizeof(char), sect, &length, &left);
2101		modrm_byte(&mode, &reg, &r_m, byte);
2102	    }
2103	    reg_name = get_reg_name(reg, LONGOPERAND, data16, rex);
2104	    wbit = WBIT(opcode5);
2105	    data16 = 1;
2106	    /* movslq (0x63) Move doubleword to quadword with sign-extension */
2107	    if(opcode1 != 0x6 && opcode2 != 0x3)
2108	        rex = 0;
2109	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2110	    printf("%s\t", mnemonic);
2111	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
2112			  ",");
2113	    printf("%s\n", reg_name);
2114	    return(length);
2115
2116	/* imul instruction, with either 8-bit or longer immediate */
2117	case IMUL:
2118	    if(got_modrm_byte == FALSE){
2119		got_modrm_byte = TRUE;
2120		byte = get_value(sizeof(char), sect, &length, &left);
2121		modrm_byte(&mode, &reg, &r_m, byte);
2122	    }
2123	    wbit = LONGOPERAND;
2124	    GET_OPERAND(&symadd1, &symsub1, &value1, &value1_size, result1);
2125	    /* opcode 0x6B for byte, sign-extended displacement,
2126		0x69 for word(s) */
2127	    value0_size = OPSIZE(data16, opcode2 == 0x9, 0);
2128	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
2129	    reg_name = get_reg_name(reg, wbit, data16, rex);
2130	    printf("%s\t$", mnemonic);
2131	    print_operand("", symadd0, symsub0, imm0, value0_size, "", ",");
2132	    print_operand(seg, symadd1, symsub1, value1, value1_size, result1,
2133			  ",");
2134	    printf("%s\n", reg_name);
2135	    return(length);
2136
2137	/* memory or register operand to register, with 'w' bit	*/
2138	case MRw:
2139	case SSE4MRw:
2140	    /*
2141	     * If this is vmwrite in a 64-bit object the 0F 79
2142	     * opcode it results in a 64-bit operand.
2143	     * So to get the 64-bit register names in the disassembly we
2144	     * set the REX.W bit to indicate 64-bit operand size.
2145	     */
2146	    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64 &&
2147	       opcode1 == 0x0 && opcode2 == 0xf &&
2148	       opcode4 == 0x7 && opcode5 == 0x9)
2149		rex |= 0x8;
2150	    wbit = WBIT(opcode2);
2151	    if(got_modrm_byte == FALSE){
2152		got_modrm_byte = TRUE;
2153		byte = get_value(sizeof(char), sect, &length, &left);
2154		modrm_byte(&mode, &reg, &r_m, byte);
2155	    }
2156	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2157	    reg_name = get_reg_name(reg, wbit, data16, rex);
2158	    printf("%s\t", mnemonic);
2159	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
2160			  ",");
2161	    printf("%s\n", reg_name);
2162	    return(length);
2163
2164	/* register to memory or register operand, with 'w' bit	*/
2165	/* arpl happens to fit here also because it is odd */
2166	case RMw:
2167	    /*
2168	     * If this is vmread in a 64-bit object the 0F 78
2169	     * opcode it results in a 64-bit operand.
2170	     * So to get the 64-bit register names in the disassembly we
2171	     * set the REX.W bit to indicate 64-bit operand size.
2172	     */
2173	    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64 &&
2174	       opcode1 == 0x0 && opcode2 == 0xf &&
2175	       opcode4 == 0x7 && opcode5 == 0x8)
2176		rex |= 0x8;
2177	    /* arpl, 0x63, always uses r16's */
2178	    if(opcode1 == 0x6 && opcode2 == 0x3)
2179		data16 = 1;
2180	    wbit = WBIT(opcode2);
2181	    if(got_modrm_byte == FALSE){
2182		got_modrm_byte = TRUE;
2183		byte = get_value(sizeof(char), sect, &length, &left);
2184		modrm_byte(&mode, &reg, &r_m, byte);
2185	    }
2186	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2187	    reg_name = get_reg_name(reg, wbit, data16, rex);
2188	    printf("%s\t%s,", mnemonic, reg_name);
2189	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
2190			  "\n");
2191	    return(length);
2192
2193	/* SSE2 instructions with further prefix decoding dest to memory or
2194	   memory to dest depending on the opcode */
2195	case SSE2tfm:
2196	    data16 = FALSE;
2197	    if(got_modrm_byte == FALSE){
2198		got_modrm_byte = TRUE;
2199		byte = get_value(sizeof(char), sect, &length, &left);
2200		modrm_byte(&mode, &reg, &r_m, byte);
2201	    }
2202	    switch(opcode4 << 4 | opcode5){
2203	    case 0x7e: /* movq & movd */
2204		if(prefix_byte == 0x66){
2205		    /* movd from xmm to r/m32 */
2206		    printf("%sd\t%%xmm%u,", mnemonic, xmm_reg(reg, rex));
2207		    wbit = LONGOPERAND;
2208		    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size,
2209				result0);
2210		    print_operand(seg, symadd0, symsub0, value0, value0_size,
2211				  result0, "\n");
2212		}
2213		else if(prefix_byte == 0xf0){
2214		    /* movq from mm to mm/m64 */
2215		    printf("%sd\t%%mm%u,", mnemonic, reg);
2216		    mmx = TRUE;
2217		    GET_OPERAND(&symadd1, &symsub1, &value1, &value1_size,
2218				result1);
2219		    print_operand(seg, symadd1, symsub1, value1, value1_size,
2220				  result1, "\n");
2221		}
2222		else if(prefix_byte == 0xf3){
2223		    /* movq from xmm2/mem64 to xmm1 */
2224		    printf("%sq\t", mnemonic);
2225		    sse2 = TRUE;
2226		    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size,
2227				result0);
2228		    print_operand(seg, symadd0, symsub0, value0, value0_size,
2229				  result0, ",");
2230		    printf("%%xmm%u\n", xmm_reg(reg, rex));
2231		}
2232		else{ /* no prefix_byte */
2233		    /* movd from mm to r/m32 */
2234		    printf("%sd\t%%mm%u,", mnemonic, reg);
2235		    wbit = LONGOPERAND;
2236		    GET_OPERAND(&symadd1, &symsub1, &value1, &value1_size,
2237				result1);
2238		    print_operand(seg, symadd1, symsub1, value1, value1_size,
2239				  result1, "\n");
2240		}
2241	    }
2242	    return(length);
2243
2244	/* SSE2 instructions with further prefix decoding dest to memory */
2245	case SSE2tm:
2246	    data16 = FALSE;
2247	    if(got_modrm_byte == FALSE){
2248		got_modrm_byte = TRUE;
2249		byte = get_value(sizeof(char), sect, &length, &left);
2250		modrm_byte(&mode, &reg, &r_m, byte);
2251	    }
2252	    sprintf(result0, "%%xmm%u", xmm_reg(reg, rex));
2253	    switch(opcode4 << 4 | opcode5){
2254	    case 0x11: /* movupd &         movups */
2255		       /*          movsd &        movss */
2256		sse2 = TRUE;
2257		if(prefix_byte == 0x66)
2258		    printf("%supd\t", mnemonic);
2259		else if(prefix_byte == 0xf2)
2260		    printf("%ssd\t", mnemonic);
2261		else if(prefix_byte == 0xf3)
2262		    printf("%sss\t", mnemonic);
2263		else /* no prefix_byte */
2264		    printf("%sups\t", mnemonic);
2265		break;
2266	    case 0x13: /*  movlpd &          movlps */
2267	    case 0x17: /*  movhpd &          movhps */
2268	    case 0x29: /*  movapd &  movasd */
2269	    case 0x2b: /* movntpd & movntsd */
2270		sse2 = TRUE;
2271		if(prefix_byte == 0x66)
2272		    printf("%spd\t", mnemonic);
2273		else if(prefix_byte == 0xf2)
2274		    printf("%ssd\t", mnemonic);
2275		else if(prefix_byte == 0xf3)
2276		    printf("%sss\t", mnemonic);
2277		else /* no prefix_byte */
2278		    printf("%sps\t", mnemonic);
2279		break;
2280	    case 0xd6: /* movq */
2281		if(prefix_byte == 0x66){
2282		    sse2 = TRUE;
2283		    printf("%sq\t", mnemonic);
2284		}
2285		else if(prefix_byte == 0xf2){
2286		    printf("%sdq2q\t", mnemonic);
2287		    sse2 = TRUE;
2288		    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size,
2289				result0);
2290		    print_operand(seg, symadd0, symsub0, value0, value0_size,
2291				  result0, ",");
2292		    sprintf(result1, "%%mm%u", reg);
2293		    printf("%s\n", result1);
2294		    return(length);
2295		}
2296		else if(prefix_byte == 0xf3){
2297		    printf("%sq2dq\t", mnemonic);
2298		    mmx = TRUE;
2299		    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size,
2300				result0);
2301		    print_operand(seg, symadd0, symsub0, value0, value0_size,
2302				  result0, ",");
2303		    sprintf(result1, "%%xmm%u", reg);
2304		    printf("%s\n", result1);
2305		    return(length);
2306		}
2307		break;
2308	    case 0x7f: /* movdqa, movdqu, movq */
2309		sse2 = TRUE;
2310		if(prefix_byte == 0x66)
2311		    printf("%sdqa\t", mnemonic);
2312		else if(prefix_byte == 0xf3)
2313		    printf("%sdqu\t", mnemonic);
2314		else{
2315		    sprintf(result0, "%%mm%u", reg);
2316		    printf("%sq\t", mnemonic);
2317		    mmx = TRUE;
2318		}
2319		break;
2320	    case 0xe7: /* movntdq & movntq */
2321		if(prefix_byte == 0x66){
2322		    printf("%stdq\t", mnemonic);
2323		}
2324		else{ /* no prefix_byte */
2325		    sprintf(result0, "%%mm%u", reg);
2326		    printf("%stq\t", mnemonic);
2327		    mmx = TRUE;
2328		}
2329		break;
2330	    }
2331	    printf("%s,", result0);
2332	    GET_OPERAND(&symadd1, &symsub1, &value1, &value1_size, result1);
2333	    print_operand(seg, symadd1, symsub1, value1, value1_size,
2334			  result1, "\n");
2335	    return(length);
2336
2337	/* MNI instructions */
2338	case MNI:
2339	    data16 = FALSE;
2340	    if(got_modrm_byte == FALSE){
2341		got_modrm_byte = TRUE;
2342		byte = get_value(sizeof(char), sect, &length, &left);
2343		modrm_byte(&mode, &reg, &r_m, byte);
2344	    }
2345	    if(prefix_byte == 0x66){
2346		sse2 = TRUE;
2347		sprintf(result1, "%%xmm%u", xmm_reg(reg, rex));
2348	    }
2349	    else{ /* no prefix byte */
2350		mmx = TRUE;
2351		sprintf(result1, "%%mm%u", reg);
2352	    }
2353	    printf("%s\t", mnemonic);
2354	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2355	    print_operand(seg, symadd0, symsub0, value0, value0_size,
2356			  result0, ",");
2357	    printf("%s\n", result1);
2358		return length;
2359
2360	/* MNI instructions with 8-bit immediate */
2361	case MNIi:
2362	    data16 = FALSE;
2363	    if (got_modrm_byte == FALSE) {
2364			got_modrm_byte = TRUE;
2365			byte = get_value(sizeof(char), sect, &length, &left);
2366			modrm_byte(&mode, &reg, &r_m, byte);
2367	    }
2368	    if(prefix_byte == 0x66){
2369		sse2 = TRUE;
2370		sprintf(result1, "%%xmm%u", xmm_reg(reg, rex));
2371	    }
2372	    else{ /* no prefix byte */
2373		mmx = TRUE;
2374		sprintf(result1, "%%mm%u", reg);
2375	    }
2376	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2377	    byte = get_value(sizeof(char), sect, &length, &left);
2378		printf("%s\t$0x%x,", mnemonic, byte);
2379
2380	    print_operand(seg, symadd0, symsub0, value0, value0_size,
2381			  result0, ",");
2382	    printf("%s\n", result1);
2383		return length;
2384
2385	/* SSE2 instructions with further prefix decoding */
2386	case SSE2:
2387	    data16 = FALSE;
2388	    if(got_modrm_byte == FALSE){
2389		got_modrm_byte = TRUE;
2390		byte = get_value(sizeof(char), sect, &length, &left);
2391		modrm_byte(&mode, &reg, &r_m, byte);
2392	    }
2393	    sprintf(result1, "%%xmm%u", xmm_reg(reg, rex));
2394	    switch(opcode4 << 4 | opcode5){
2395	    case 0x14: /* unpcklpd &                 unpcklps */
2396	    case 0x15: /* unpckhpd &                 unpckhps */
2397	    case 0x28: /*   movapd & movasd */
2398	    case 0x51: /*   sqrtpd,  sqrtsd, sqrtss &  sqrtps */
2399	    case 0x52: /*                   rsqrtss & rsqrtps */
2400	    case 0x53: /*                     rcpss &   rcpps */
2401	    case 0x54: /*    andpd &  andsd */
2402	    case 0x55: /*   andnpd & andnsd */
2403	    case 0x56: /*     orpd &                    orps */
2404	    case 0x57: /*    xorpd &                   xorps */
2405	    case 0x58: /*    addpd &  addsd */
2406	    case 0x59: /*    mulpd,   mulsd,  mulss &   mulps */
2407	    case 0x5c: /*    subpd,   subsd,  subss &   subps */
2408	    case 0x5d: /*    minpd,   minsd,  minss &   minps */
2409	    case 0x5e: /*    divpd,   divsd,  divss &   divps */
2410	    case 0x5f: /*    maxpd,   maxsd,  maxss &   maxps */
2411		sse2 = TRUE;
2412		if(prefix_byte == 0x66)
2413		    printf("%spd\t", mnemonic);
2414		else if(prefix_byte == 0xf2)
2415		    printf("%ssd\t", mnemonic);
2416		else if(prefix_byte == 0xf3)
2417		    printf("%sss\t", mnemonic);
2418		else /* no prefix_byte */
2419		    printf("%sps\t", mnemonic);
2420		break;
2421	    case 0x12: /*   movlpd, movlps & movhlps */
2422		sse2 = TRUE;
2423		if(prefix_byte == 0x66)
2424		    printf("%slpd\t", mnemonic);
2425		else if(prefix_byte == 0xf2)
2426		    printf("movddup\t");
2427		else if(prefix_byte == 0xf3)
2428		    printf("movsldup\t");
2429		else{ /* no prefix_byte */
2430		    if(mode == REG_ONLY)
2431			printf("%shlps\t", mnemonic);
2432		    else
2433			printf("%slps\t", mnemonic);
2434		}
2435		break;
2436	    case 0x16: /*   movhpd, movhps & movlhps */
2437		sse2 = TRUE;
2438		if(prefix_byte == 0x66)
2439		    printf("%shpd\t", mnemonic);
2440		else if(prefix_byte == 0xf2)
2441		    printf("%shsd\t", mnemonic);
2442		else if(prefix_byte == 0xf3)
2443		    printf("movshdup\t");
2444		else{ /* no prefix_byte */
2445		    if(mode == REG_ONLY)
2446			printf("%slhps\t", mnemonic);
2447		    else
2448			printf("%shps\t", mnemonic);
2449		}
2450		break;
2451	    case 0x50: /* movmskpd &                 movmskps */
2452		sse2 = TRUE;
2453		reg_name = get_reg_name(reg, 1, data16, rex);
2454		strcpy(result1, reg_name);
2455		if(prefix_byte == 0x66)
2456		    printf("%spd\t", mnemonic);
2457		else /* no prefix_byte */
2458		    printf("%sps\t", mnemonic);
2459		break;
2460	    case 0x10: /*   movupd &                  movups */
2461		       /*             movsd & movss */
2462		sse2 = TRUE;
2463		if(prefix_byte == 0x66)
2464		    printf("%supd\t", mnemonic);
2465		else if(prefix_byte == 0xf2)
2466		    printf("%ssd\t", mnemonic);
2467		else if(prefix_byte == 0xf3)
2468		    printf("%sss\t", mnemonic);
2469		else /* no prefix_byte */
2470		    printf("%sups\t", mnemonic);
2471		break;
2472	    case 0x2a: /* cvtpi2pd, cvtsi2sd, cvtsi2ss & cvtpi2ps */
2473		if(prefix_byte == 0x66){
2474		    mmx = TRUE;
2475		    printf("%spi2pd\t", mnemonic);
2476		}
2477		else if(prefix_byte == 0xf2){
2478		    wbit = LONGOPERAND;
2479		    printf("%ssi2sd\t", mnemonic);
2480		}
2481		else if(prefix_byte == 0xf3){
2482		    wbit = LONGOPERAND;
2483		    printf("%ssi2ss\t", mnemonic);
2484		}
2485		else{ /* no prefix_byte */
2486		    mmx = TRUE;
2487		    printf("%spi2ps\t", mnemonic);
2488		}
2489		break;
2490	    case 0x2c: /* cvttpd2pi, cvttsd2si, cvttss2si & cvttps2pi */
2491		if(prefix_byte == 0x66){
2492		    sse2 = TRUE;
2493		    printf("%stpd2pi\t", mnemonic);
2494		    sprintf(result1, "%%mm%u", reg);
2495		}
2496		else if(prefix_byte == 0xf2){
2497		    sse2 = TRUE;
2498		    printf("%stsd2si\t", mnemonic);
2499		    reg_name = get_reg_name(reg, 1, data16, rex);
2500		    strcpy(result1, reg_name);
2501		}
2502		else if(prefix_byte == 0xf3){
2503		    sse2 = TRUE;
2504		    printf("%stss2si\t", mnemonic);
2505		    reg_name = get_reg_name(reg, 1, data16, rex);
2506		    strcpy(result1, reg_name);
2507		}
2508		else{ /* no prefix_byte */
2509		    sse2 = TRUE;
2510		    printf("%stps2pi\t", mnemonic);
2511		    sprintf(result1, "%%mm%u", reg);
2512		}
2513		break;
2514	    case 0x2d: /* cvtpd2pi, cvtsd2si, cvtss2si & cvtps2pi */
2515		if(prefix_byte == 0x66){
2516		    sse2 = TRUE;
2517		    printf("%spd2pi\t", mnemonic);
2518		    sprintf(result1, "%%mm%u", reg);
2519		}
2520		else if(prefix_byte == 0xf2){
2521		    sse2 = TRUE;
2522		    printf("%ssd2si\t", mnemonic);
2523		    reg_name = get_reg_name(reg, 1, data16, rex);
2524		    strcpy(result1, reg_name);
2525		}
2526		else if(prefix_byte == 0xf3){
2527		    sse2 = TRUE;
2528		    printf("%sss2si\t", mnemonic);
2529		    reg_name = get_reg_name(reg, 1, data16, rex);
2530		    strcpy(result1, reg_name);
2531		}
2532		else{ /* no prefix_byte */
2533		    sse2 = TRUE;
2534		    printf("%sps2pi\t", mnemonic);
2535		    sprintf(result1, "%%mm%u", reg);
2536		}
2537		break;
2538	    case 0x2e: /* ucomisd & ucomiss */
2539	    case 0x2f: /*  comisd &  comiss */
2540		sse2 = TRUE;
2541		if(prefix_byte == 0x66)
2542		    printf("%ssd\t", mnemonic);
2543		else /* no prefix_byte */
2544		    printf("%sss\t", mnemonic);
2545		break;
2546	    case 0xe0: /* pavgb */
2547	    case 0xe3: /* pavgw */
2548		if(prefix_byte == 0x66){
2549		    sse2 = TRUE;
2550		    printf("%s\t", mnemonic);
2551		}
2552		else{ /* no prefix_byte */
2553		    sprintf(result1, "%%mm%u", reg);
2554		    printf("%s\t", mnemonic);
2555		    mmx = TRUE;
2556		}
2557		break;
2558	    case 0xe6: /* cvttpd2dq, cvtdq2pd & cvtpd2dq */
2559		sse2 = TRUE;
2560		if(prefix_byte == 0x66)
2561		    printf("%stpd2dq\t", mnemonic);
2562		if(prefix_byte == 0xf3)
2563		    printf("%sdq2pd\t", mnemonic);
2564		else if(prefix_byte == 0xf2)
2565		    printf("%spd2dq\t", mnemonic);
2566		break;
2567	    case 0x5a: /* cvtpd2ps, cvtsd2ss, cvtss2sd & cvtps2pd */
2568		sse2 = TRUE;
2569		if(prefix_byte == 0x66)
2570		    printf("%spd2ps\t", mnemonic);
2571		else if(prefix_byte == 0xf2)
2572		    printf("%ssd2ss\t", mnemonic);
2573		else if(prefix_byte == 0xf3)
2574		    printf("%sss2sd\t", mnemonic);
2575		else /* no prefix_byte */
2576		    printf("%sps2pd\t", mnemonic);
2577		break;
2578	    case 0x5b: /* cvtdq2ps, cvttps2dq & cvtps2dq */
2579		sse2 = TRUE;
2580		if(prefix_byte == 0x66)
2581		    printf("%sps2dq\t", mnemonic);
2582		else if(prefix_byte == 0xf3)
2583		    printf("%stps2dq\t", mnemonic);
2584		else /* no prefix_byte */
2585		    printf("%sdq2ps\t", mnemonic);
2586		break;
2587	    case 0x60: /* punpcklbw */
2588	    case 0x61: /* punpcklwd */
2589	    case 0x62: /* punpckldq */
2590	    case 0x63: /* packsswb */
2591	    case 0x64: /* pcmpgtb */
2592	    case 0x65: /* pcmpgtw */
2593	    case 0x66: /* pcmpgtd */
2594	    case 0x67: /* packuswb */
2595	    case 0x68: /* punpckhbw */
2596	    case 0x69: /* punpckhwd */
2597	    case 0x6a: /* punpckhdq */
2598	    case 0x6b: /* packssdw */
2599	    case 0x74: /* pcmpeqb */
2600	    case 0x75: /* pcmpeqw */
2601	    case 0x76: /* pcmpeqd */
2602	    case 0xd1: /* psrlw */
2603	    case 0xd2: /* psrld */
2604	    case 0xd3: /* psrlq */
2605	    case 0xd4: /* paddq */
2606	    case 0xd5: /* pmullw */
2607	    case 0xd8: /* psubusb */
2608	    case 0xd9: /* psubusw */
2609	    case 0xdb: /* pand */
2610	    case 0xdc: /* paddusb */
2611	    case 0xdd: /* paddusw */
2612	    case 0xdf: /* pandn */
2613	    case 0xe1: /* psraw */
2614	    case 0xe2: /* psrad */
2615	    case 0xe5: /* pmulhw */
2616	    case 0xe8: /* psubsb */
2617	    case 0xe9: /* psubsw */
2618	    case 0xeb: /* por */
2619	    case 0xec: /* paddsb */
2620	    case 0xed: /* paddsw */
2621	    case 0xef: /* pxor */
2622	    case 0xf1: /* psllw */
2623	    case 0xf2: /* pslld */
2624	    case 0xf3: /* psllq */
2625	    case 0xf5: /* pmaddwd */
2626	    case 0xf8: /* psubb */
2627	    case 0xf9: /* psubw */
2628	    case 0xfa: /* psubd */
2629	    case 0xfb: /* psubq */
2630	    case 0xfc: /* paddb */
2631	    case 0xfd: /* paddw */
2632	    case 0xfe: /* paddd */
2633		if(prefix_byte == 0x66){
2634		    printf("%s\t", mnemonic);
2635		    sse2 = TRUE;
2636		}
2637		else{ /* no prefix_byte */
2638		    sprintf(result1, "%%mm%u", reg);
2639		    printf("%s\t", mnemonic);
2640		    mmx = TRUE;
2641		}
2642		break;
2643	    case 0x6c: /* punpcklqdq */
2644	    case 0x6d: /* punpckhqdq */
2645		sse2 = TRUE;
2646		if(prefix_byte == 0x66)
2647		    printf("%sqdq\t", mnemonic);
2648		break;
2649	    case 0x6f: /* movdqa, movdqu & movq */
2650		if(prefix_byte == 0x66){
2651		    sse2 = TRUE;
2652		    printf("%sdqa\t", mnemonic);
2653		}
2654		else if(prefix_byte == 0xf3){
2655		    sse2 = TRUE;
2656		    printf("%sdqu\t", mnemonic);
2657		}
2658		else{ /* no prefix_byte */
2659		    sprintf(result1, "%%mm%u", reg);
2660		    printf("%sq\t", mnemonic);
2661		    mmx = TRUE;
2662		}
2663		break;
2664	    case 0xd6: /* movdq2q & movq2dq */
2665		if(prefix_byte == 0xf2){
2666		    sprintf(result1, "%%mm%u", reg);
2667		    printf("%sdq2q\t", mnemonic);
2668		    sse2 = TRUE;
2669		}
2670		else if(prefix_byte == 0xf3){
2671		    printf("%sq2dq\t", mnemonic);
2672		    mmx = TRUE;
2673		}
2674		break;
2675	    case 0x6e: /* movd */
2676		if(prefix_byte == 0x66){
2677		    printf("%s\t", mnemonic);
2678		    wbit = LONGOPERAND;
2679		}
2680		else{ /* no prefix_byte */
2681		    sprintf(result1, "%%mm%u", reg);
2682		    printf("%s\t", mnemonic);
2683		    wbit = LONGOPERAND;
2684		}
2685		break;
2686	    case 0xd0: /* addsubpd */
2687	    case 0x7c: /* haddp */
2688	    case 0x7d: /* hsubp */
2689		if(prefix_byte == 0x66){
2690		    printf("%sd\t", mnemonic);
2691		    sse2 = TRUE;
2692		}
2693		else if(prefix_byte == 0xf2){
2694		    printf("%ss\t", mnemonic);
2695		    sse2 = TRUE;
2696		}
2697		else{ /* no prefix_byte */
2698		    sprintf(result1, "%%mm%u", reg);
2699		    printf("%s\t", mnemonic);
2700		    mmx = TRUE;
2701		}
2702		break;
2703	    case 0xd7: /* pmovmskb */
2704		if(prefix_byte == 0x66){
2705		    reg_name = get_reg_name(reg, 1, data16, rex);
2706		    printf("%s\t%%xmm%u,%s\n", mnemonic, xmm_rm(r_m, rex),
2707			   reg_name);
2708		    return(length);
2709		}
2710		else{ /* no prefix_byte */
2711		    reg_name = get_reg_name(reg, 1, data16, rex);
2712		    printf("%s\t%%mm%u,%s\n", mnemonic, r_m, reg_name);
2713		    return(length);
2714		}
2715		break;
2716	    case 0xda: /* pminub */
2717	    case 0xde: /* pmaxub */
2718	    case 0xe4: /* pmulhuw */
2719	    case 0xea: /* pminsw */
2720	    case 0xee: /* pmaxsw */
2721	    case 0xf4: /* pmuludq */
2722	    case 0xf6: /* psadbw */
2723		if(prefix_byte == 0x66){
2724		    sse2 = TRUE;
2725		    printf("%s\t", mnemonic);
2726		}
2727		else{ /* no prefix_byte */
2728		    sprintf(result1, "%%mm%u", reg);
2729		    printf("%s\t", mnemonic);
2730		    mmx = TRUE;
2731		}
2732		break;
2733	    case 0xf0: /* lddqu */
2734		printf("%s\t", mnemonic);
2735		sse2 = TRUE;
2736		break;
2737	    case 0xf7: /* maskmovdqu & maskmovq */
2738		sse2 = TRUE;
2739		if(prefix_byte == 0x66)
2740		    printf("%sdqu\t", mnemonic);
2741		else{ /* no prefix_byte */
2742		    printf("%sq\t%%mm%u,%%mm%u\n", mnemonic, r_m, reg);
2743		    return(length);
2744		}
2745		break;
2746	    }
2747	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2748	    print_operand(seg, symadd0, symsub0, value0, value0_size,
2749			  result0, ",");
2750	    printf("%s\n", result1);
2751	    return(length);
2752
2753	/* SSE4 instructions */
2754	case SSE4:
2755	    sse2 = TRUE;
2756	    data16 = FALSE;
2757	    wbit = LONGOPERAND;
2758	    if(got_modrm_byte == FALSE){
2759		got_modrm_byte = TRUE;
2760		byte = get_value(sizeof(char), sect, &length, &left);
2761		modrm_byte(&mode, &reg, &r_m, byte);
2762	    }
2763	    printf("%s\t", mnemonic);
2764	    sprintf(result1, "%%xmm%u", xmm_reg(reg, rex));
2765	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2766	    print_operand(seg, symadd0, symsub0, value0, value0_size,
2767			  result0, ",");
2768	    printf("%s\n", result1);
2769	    return(length);
2770
2771	/* SSE4 instructions with 8 bit immediate */
2772	case SSE4i:
2773	    sse2 = TRUE;
2774	    data16 = FALSE;
2775	    wbit = LONGOPERAND;
2776	    if(got_modrm_byte == FALSE){
2777		got_modrm_byte = TRUE;
2778		byte = get_value(sizeof(char), sect, &length, &left);
2779		modrm_byte(&mode, &reg, &r_m, byte);
2780	    }
2781	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2782	    byte = get_value(sizeof(char), sect, &length, &left);
2783	    printf("%s\t$0x%x,", mnemonic, byte);
2784	    print_operand(seg, symadd0, symsub0, value0, value0_size,
2785			  result0, ",");
2786	    printf("%%xmm%u\n", xmm_reg(reg, rex));
2787	    return(length);
2788
2789	/* SSE4 instructions with dest to memory and 8-bit immediate */
2790	case SSE4itm:
2791	    sse2 = FALSE;
2792	    data16 = FALSE;
2793	    wbit = LONGOPERAND;
2794	    if(got_modrm_byte == FALSE){
2795		got_modrm_byte = TRUE;
2796		byte = get_value(sizeof(char), sect, &length, &left);
2797		modrm_byte(&mode, &reg, &r_m, byte);
2798	    }
2799	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2800	    byte = get_value(sizeof(char), sect, &length, &left);
2801	    if(dp == &op0F3A[0x16]){
2802		if(rex != 0)
2803		    printf("%sq\t$0x%x,", mnemonic, byte);
2804		else
2805		    printf("%sd\t$0x%x,", mnemonic, byte);
2806	    }
2807	    else
2808		printf("%s\t$0x%x,", mnemonic, byte);
2809	    printf("%%xmm%u,", xmm_reg(reg, rex));
2810	    print_operand(seg, symadd0, symsub0, value0, value0_size,
2811			  result0, "\n");
2812	    return(length);
2813
2814	/* SSE4 instructions with src from memory and 8-bit immediate */
2815	case SSE4ifm:
2816	    sse2 = FALSE;
2817	    data16 = FALSE;
2818	    wbit = LONGOPERAND;
2819	    if(got_modrm_byte == FALSE){
2820		got_modrm_byte = TRUE;
2821		byte = get_value(sizeof(char), sect, &length, &left);
2822		modrm_byte(&mode, &reg, &r_m, byte);
2823	    }
2824	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2825	    byte = get_value(sizeof(char), sect, &length, &left);
2826	    if(dp == &op0F3A[0x22]){
2827		if(rex != 0)
2828		    printf("%sq\t$0x%x,", mnemonic, byte);
2829		else
2830		    printf("%sd\t$0x%x,", mnemonic, byte);
2831	    }
2832	    else
2833		printf("%s\t$0x%x,", mnemonic, byte);
2834	    print_operand(seg, symadd0, symsub0, value0, value0_size,
2835			  result0, ",");
2836	    printf("%%xmm%u\n", xmm_reg(reg, rex));
2837	    return(length);
2838
2839	/* SSE4.2 instructions memory or register operand to register */
2840	case SSE4CRCb:
2841	    wbit = 0;
2842	    if(got_modrm_byte == FALSE){
2843		got_modrm_byte = TRUE;
2844		byte = get_value(sizeof(char), sect, &length, &left);
2845		modrm_byte(&mode, &reg, &r_m, byte);
2846	    }
2847	    /*
2848	     * This is to get the byte register names for SSE4CRCb opcodes.
2849	     */
2850	    if(mode == REG_ONLY){
2851		strcpy(result0, REG64_BYTE[(REX_B(rex) << 3) | r_m]);
2852		symadd0 = NULL;
2853		symsub0 = NULL;
2854		value0 = 0;
2855		value0_size = 0;
2856	    }
2857	    else
2858		GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2859	    reg_name = get_reg_name(reg, 1 /* wbit */, 0 /* data16 */, rex);
2860	    printf("%s\t", mnemonic);
2861	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
2862			  ",");
2863	    printf("%s\n", reg_name);
2864	    return(length);
2865
2866	case SSE4CRC:
2867	    wbit = 1;
2868	    if(got_modrm_byte == FALSE){
2869		got_modrm_byte = TRUE;
2870		byte = get_value(sizeof(char), sect, &length, &left);
2871		modrm_byte(&mode, &reg, &r_m, byte);
2872	    }
2873	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2874	    reg_name = get_reg_name(reg, 1 /* wbit */, 0 /* data16 */, rex);
2875	    printf("%s\t", mnemonic);
2876	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
2877			  ",");
2878	    printf("%s\n", reg_name);
2879	    return(length);
2880
2881	/* SSE2 instructions with 8 bit immediate with further prefix decoding*/
2882	case SSE2i:
2883	    data16 = FALSE;
2884	    if(got_modrm_byte == FALSE){
2885		got_modrm_byte = TRUE;
2886		byte = get_value(sizeof(char), sect, &length, &left);
2887		modrm_byte(&mode, &reg, &r_m, byte);
2888	    }
2889	    /* pshufw */
2890	    if((opcode4 << 4 | opcode5) == 0x70 && prefix_byte == 0)
2891		mmx = TRUE;
2892	    /* pinsrw */
2893	    else if((opcode4 << 4 | opcode5) == 0xc4)
2894		wbit = LONGOPERAND;
2895	    else
2896		sse2 = TRUE;
2897	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
2898	    byte = get_value(sizeof(char), sect, &length, &left);
2899
2900	    switch(opcode4 << 4 | opcode5){
2901	    case 0x70: /* pshufd, pshuflw, pshufhw & pshufw */
2902		if(prefix_byte == 0x66)
2903		    printf("%sfd\t$0x%x,", mnemonic, byte);
2904		else if(prefix_byte == 0xf2)
2905		    printf("%sflw\t$0x%x,", mnemonic, byte);
2906		else if(prefix_byte == 0xf3)
2907		    printf("%sfhw\t$0x%x,", mnemonic, byte);
2908		else{ /* no prefix_byte */
2909		    printf("%sfw\t$0x%x,", mnemonic, byte);
2910		    print_operand(seg, symadd0, symsub0, value0, value0_size,
2911				  result0, ",");
2912		    printf("%%mm%u\n", reg);
2913		    return(length);
2914		}
2915		break;
2916	    case 0xc4: /* pinsrw */
2917		if(prefix_byte == 0x66){
2918		    printf("%s\t$0x%x,", mnemonic, byte);
2919		}
2920		else{ /* no prefix_byte */
2921		    printf("%s\t$0x%x,", mnemonic, byte);
2922		    print_operand(seg, symadd0, symsub0, value0, value0_size,
2923				  result0, ",");
2924		    printf("%%mm%u\n", reg);
2925		    return(length);
2926		}
2927		break;
2928	    case 0xc5: /* pextrw */
2929		if(prefix_byte == 0x66){
2930		    reg_name = get_reg_name(reg, 1, data16, rex);
2931		    printf("%s\t$0x%x,%%xmm%u,%s\n", mnemonic, byte,
2932			   xmm_rm(r_m, rex), reg_name);
2933		    return(length);
2934		}
2935		else{ /* no prefix_byte */
2936		    reg_name = get_reg_name(reg, 1, data16, rex);
2937		    printf("%s\t$0x%x,%%mm%u,%s\n", mnemonic, byte, r_m,
2938			   reg_name);
2939		    return(length);
2940		}
2941		break;
2942	    default:
2943		if(prefix_byte == 0x66)
2944		    printf("%spd\t$0x%x,", mnemonic, byte);
2945		else if(prefix_byte == 0xf2)
2946		    printf("%ssd\t$0x%x,", mnemonic, byte);
2947		else if(prefix_byte == 0xf3)
2948		    printf("%sss\t$0x%x,", mnemonic, byte);
2949		else /* no prefix_byte */
2950		    printf("%sps\t$0x%x,", mnemonic, byte);
2951		break;
2952	    }
2953	    print_operand(seg, symadd0, symsub0, value0, value0_size,
2954			  result0, ",");
2955	    printf("%%xmm%u\n", xmm_reg(reg, rex));
2956	    return(length);
2957
2958	/* SSE2 instructions with 8 bit immediate and only 1 reg */
2959	case SSE2i1:
2960	    if(got_modrm_byte == FALSE){
2961		got_modrm_byte = TRUE;
2962		byte = get_value(sizeof(char), sect, &length, &left);
2963		modrm_byte(&mode, &reg, &r_m, byte);
2964	    }
2965	    byte = get_value(sizeof(char), sect, &length, &left);
2966	    switch(opcode4 << 4 | opcode5){
2967	    case 0x71: /* psrlw, psllw, psraw & psrld */
2968		if(prefix_byte == 0x66){
2969		    if(reg == 0x2)
2970			printf("%srlw\t$0x%x,", mnemonic, byte);
2971		    else if(reg == 0x4)
2972			printf("%sraw\t$0x%x,", mnemonic, byte);
2973		    else if(reg == 0x6)
2974			printf("%sllw\t$0x%x,", mnemonic, byte);
2975		}
2976		else{ /* no prefix_byte */
2977		    if(reg == 0x2)
2978			printf("%srlw\t$0x%x,", mnemonic, byte);
2979		    else if(reg == 0x4)
2980			printf("%sraw\t$0x%x,", mnemonic, byte);
2981		    else if(reg == 0x6)
2982			printf("%sllw\t$0x%x,", mnemonic, byte);
2983		    printf("%%mm%u\n", r_m);
2984		    return(length);
2985		}
2986		break;
2987	    case 0x72: /* psrld, pslld & psrad */
2988		if(prefix_byte == 0x66){
2989		    if(reg == 0x2)
2990			printf("%srld\t$0x%x,", mnemonic, byte);
2991		    else if(reg == 0x4)
2992			printf("%srad\t$0x%x,", mnemonic, byte);
2993		    else if(reg == 0x6)
2994			printf("%slld\t$0x%x,", mnemonic, byte);
2995		}
2996		else{ /* no prefix_byte */
2997		    if(reg == 0x2)
2998			printf("%srld\t$0x%x,", mnemonic, byte);
2999		    else if(reg == 0x4)
3000			printf("%srad\t$0x%x,", mnemonic, byte);
3001		    else if(reg == 0x6)
3002			printf("%slld\t$0x%x,", mnemonic, byte);
3003		    printf("%%mm%u\n", r_m);
3004		    return(length);
3005		}
3006		break;
3007	    case 0x73: /* pslldq & psrldq, psrlq & psllq */
3008		if(prefix_byte == 0x66){
3009		    if(reg == 0x7)
3010			printf("%slldq\t$0x%x,", mnemonic, byte);
3011		    else if(reg == 0x3)
3012			printf("%srldq\t$0x%x,", mnemonic, byte);
3013		    else if(reg == 0x2)
3014			printf("%srlq\t$0x%x,", mnemonic, byte);
3015		    else if(reg == 0x6)
3016			printf("%sllq\t$0x%x,", mnemonic, byte);
3017		}
3018		else{ /* no prefix_byte */
3019		    if(reg == 0x2)
3020			printf("%srlq\t$0x%x,", mnemonic, byte);
3021		    else if(reg == 0x6)
3022			printf("%sllq\t$0x%x,", mnemonic, byte);
3023		    printf("%%mm%u\n", r_m);
3024		    return(length);
3025		}
3026		break;
3027	    }
3028	    printf("%%xmm%u\n", xmm_rm(r_m, rex));
3029	    return(length);
3030
3031       /* 3DNow instructions */
3032       case AMD3DNOW:
3033               printf("%s\t", mnemonic);
3034           sprintf(result1, "%%mm%u", reg);
3035           print_operand(seg, symadd0, symsub0, value0, value0_size,
3036                         result0, ",");
3037           printf("%s\n", result1);
3038           return(length);
3039
3040	/* prefetch instructions */
3041	case PFCH:
3042	    if(got_modrm_byte == FALSE){
3043		got_modrm_byte = TRUE;
3044		byte = get_value(sizeof(char), sect, &length, &left);
3045		modrm_byte(&mode, &reg, &r_m, byte);
3046	    }
3047	    switch(reg){
3048	    case 0:
3049		printf("%snta", dp->name);
3050		break;
3051	    case 1:
3052		printf("%st0", dp->name);
3053		break;
3054	    case 2:
3055		printf("%st1", dp->name);
3056		break;
3057	    case 3:
3058		printf("%st2", dp->name);
3059		break;
3060	    }
3061	    if(data16 == TRUE)
3062		printf("w");
3063	    printf("\t");
3064           GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3065           print_operand(seg, symadd0, symsub0, value0, value0_size,
3066                         result0, "\n");
3067           return(length);
3068
3069       /* 3DNow! prefetch instructions */
3070       case PFCH3DNOW:
3071           if(got_modrm_byte == FALSE){
3072               got_modrm_byte = TRUE;
3073               byte = get_value(sizeof(char), sect, &length, &left);
3074               modrm_byte(&mode, &reg, &r_m, byte);
3075           }
3076           switch(reg){
3077           case 0:
3078               printf("%s\t", dp->name);
3079               break;
3080           case 1:
3081               printf("%sw\t", dp->name);
3082               break;
3083           }
3084	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3085	    print_operand(seg, symadd0, symsub0, value0, value0_size,
3086			  result0, "\n");
3087	    return(length);
3088
3089	/* sfence & clflush */
3090	case SFEN:
3091	    if(mode == REG_ONLY && r_m == 0){
3092		printf("sfence\n");
3093		return(length);
3094	    }
3095	    printf("%s\t", mnemonic);
3096	    reg = opcode3;
3097	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3098	    print_operand(seg, symadd0, symsub0, value0, value0_size,
3099			  result0, "\n");
3100	    return(length);
3101
3102	/* Double shift. Has immediate operand specifying the shift. */
3103	case DSHIFT:
3104	    if(got_modrm_byte == FALSE){
3105		got_modrm_byte = TRUE;
3106		byte = get_value(sizeof(char), sect, &length, &left);
3107		modrm_byte(&mode, &reg, &r_m, byte);
3108	    }
3109	    wbit = LONGOPERAND;
3110	    GET_OPERAND(&symadd1, &symsub1, &value1, &value1_size, result1);
3111	    value0_size = sizeof(char);
3112	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3113	    reg_name = get_reg_name(reg, wbit, data16, rex);
3114	    printf("%s\t$", mnemonic);
3115	    print_operand("", symadd0, symsub0, imm0, value0_size, "", ",");
3116	    printf("%s,", reg_name);
3117	    print_operand(seg, symadd1, symsub1, value1, value1_size, result1,
3118			  "\n");
3119	    return(length);
3120
3121	/* Double shift. With no immediate operand, specifies using %cl. */
3122	case DSHIFTcl:
3123	    if(got_modrm_byte == FALSE){
3124		got_modrm_byte = TRUE;
3125		byte = get_value(sizeof(char), sect, &length, &left);
3126		modrm_byte(&mode, &reg, &r_m, byte);
3127	    }
3128	    wbit = LONGOPERAND;
3129	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3130	    reg_name = get_reg_name(reg, wbit, data16, rex);
3131	    printf("%s\t%%cl,%s,", mnemonic, reg_name);
3132	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3133			  "\n");
3134	    return(length);
3135
3136	/* immediate to memory or register operand */
3137	case IMlw:
3138	    wbit = WBIT(opcode2);
3139	    GET_OPERAND(&symadd1, &symsub1, &value1, &value1_size, result1);
3140	    /* A long immediate is expected for opcode 0x81, not 0x80 & 0x83 */
3141	    value0_size = OPSIZE(data16, opcode2 == 1, 0);
3142	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3143	    printf("%s\t$", mnemonic);
3144	    print_operand("", symadd0, symsub0, imm0, value0_size, "", ",");
3145	    print_operand(seg, symadd1, symsub1, value1, value1_size, result1,
3146			  "\n");
3147	    return(length);
3148
3149	/* immediate to memory or register operand with the 'w' bit present */
3150	case IMw:
3151	    if(got_modrm_byte == FALSE){
3152		got_modrm_byte = TRUE;
3153		byte = get_value(sizeof(char), sect, &length, &left);
3154		modrm_byte(&mode, &reg, &r_m, byte);
3155	    }
3156	    wbit = WBIT(opcode2);
3157	    GET_OPERAND(&symadd1, &symsub1, &value1, &value1_size, result1);
3158	    value0_size = OPSIZE(data16, wbit, 0);
3159	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3160	    printf("%s\t$", mnemonic);
3161	    print_operand("", symadd0, symsub0, imm0, value0_size, "", ",");
3162	    print_operand(seg, symadd1, symsub1, value1, value1_size, result1,
3163			  "\n");
3164	    return(length);
3165
3166	/* immediate to register with register in low 3 bits of op code */
3167	case IR:
3168	    wbit = (opcode2 >> 3) & 0x1; /* w-bit here (with regs) is bit 3 */
3169	    reg = REGNO(opcode2);
3170	    value0_size = OPSIZE(data16, wbit, 0);
3171	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3172	    reg_name = get_r_m_name(reg, wbit, data16, rex);
3173	    printf("%s\t$", mnemonic);
3174	    print_operand("", symadd0, symsub0, imm0, value0_size, "", ",");
3175	    printf("%s\n", reg_name);
3176	    return(length);
3177
3178	/* immediate to register with register in low 3 bits of op code,
3179	   possibly with a 64-bit immediate */
3180	case IR64:
3181	    wbit = (opcode2 >> 3) & 0x1; /* w-bit here (with regs) is bit 3 */
3182	    reg = REGNO(opcode2);
3183	    value0_size = OPSIZE(data16, wbit, REX_W(rex));
3184	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3185	    reg_name = get_r_m_name(reg, wbit, data16, rex);
3186	    printf("%s\t$", mnemonic);
3187	    print_operand("", symadd0, symsub0, imm0, value0_size, "", ",");
3188	    printf("%s\n", reg_name);
3189	    return(length);
3190
3191	/* memory operand to accumulator */
3192	case OA:
3193	    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64){
3194		value0_size = OPSIZE(addr16, LONGOPERAND, 1);
3195		if(opcode1 == 0xa && opcode2 == 0x0)
3196		    strcpy(mnemonic, "movabsb");
3197		else if(opcode1 == 0xa && opcode2 == 0x1){
3198		    if(rex != 0)
3199			strcpy(mnemonic, "movabsq");
3200		    else if(data16 == TRUE)
3201			strcpy(mnemonic, "movabsw");
3202		    else
3203			strcpy(mnemonic, "movabsl");
3204		}
3205	    }
3206	    else
3207		value0_size = OPSIZE(addr16, LONGOPERAND, 0);
3208	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3209	    printf("%s\t", mnemonic);
3210	    print_operand(seg, symadd0, symsub0, imm0, value0_size, "", ",");
3211	    wbit = WBIT(opcode2);
3212	    reg_name = get_reg_name(0, wbit, data16, rex);
3213	    printf("%s\n", reg_name);
3214	    return(length);
3215
3216	/* accumulator to memory operand */
3217	case AO:
3218	    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64){
3219		value0_size = OPSIZE(addr16, LONGOPERAND, 1);
3220		if(opcode1 == 0xa && opcode2 == 0x2)
3221		    strcpy(mnemonic, "movabsb");
3222		else if(opcode1 == 0xa && opcode2 == 0x3){
3223		    if(rex != 0)
3224			strcpy(mnemonic, "movabsq");
3225		    else if(data16 == TRUE)
3226			strcpy(mnemonic, "movabsw");
3227		    else
3228			strcpy(mnemonic, "movabsl");
3229		}
3230	    }
3231	    else
3232		value0_size = OPSIZE(addr16, LONGOPERAND, 0);
3233	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3234	    wbit = WBIT(opcode2);
3235	    reg_name = get_reg_name(0, wbit, data16, rex);
3236	    printf("%s\t%s,", mnemonic, reg_name);
3237	    print_operand(seg, symadd0, symsub0, imm0, value0_size, "", "\n");
3238	    return(length);
3239
3240	/* memory or register operand to segment register */
3241	case MS:
3242	    if(got_modrm_byte == FALSE){
3243		got_modrm_byte = TRUE;
3244		byte = get_value(sizeof(char), sect, &length, &left);
3245		modrm_byte(&mode, &reg, &r_m, byte);
3246	    }
3247	    wbit = LONGOPERAND;
3248	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3249	    printf("%s\t", mnemonic);
3250	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3251			  ",");
3252	    printf("%s\n", SEGREG[reg]);
3253	    return(length);
3254
3255	/* segment register to memory or register operand	*/
3256	case SM:
3257	    if(got_modrm_byte == FALSE){
3258		got_modrm_byte = TRUE;
3259		byte = get_value(sizeof(char), sect, &length, &left);
3260		modrm_byte(&mode, &reg, &r_m, byte);
3261	    }
3262	    wbit = LONGOPERAND;
3263	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3264	    printf("%s\t%s,", mnemonic, SEGREG[reg]);
3265	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3266			  "\n");
3267	    return(length);
3268
3269	/* rotate or shift instrutions, which may shift by 1 or */
3270	/* consult the cl register, depending on the 'v' bit	*/
3271	case Mv:
3272	    vbit = VBIT(opcode2);
3273	    wbit = WBIT(opcode2);
3274	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3275	    /* When vbit is set, register is an operand, otherwise just $0x1 */
3276	    reg_name = vbit ? "%cl," : "" ;
3277	    printf("%s\t%s", mnemonic, reg_name);
3278	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3279			  "\n");
3280	    return(length);
3281
3282	/* immediate rotate or shift instrutions, which may or */
3283	/* may not consult the cl register, depending on the 'v' bit */
3284	case MvI:
3285	    vbit = VBIT(opcode2);
3286	    wbit = WBIT(opcode2);
3287	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3288	    value1_size = sizeof(char);
3289	    IMMEDIATE(&symadd1, &symsub1, &imm0, value1_size);
3290	    /* When vbit is set, register is an operand, otherwise just $0x1 */
3291	    reg_name = vbit ? "%cl," : "" ;
3292	    printf("%s\t$", mnemonic);
3293	    print_operand("", symadd1, symsub1, imm0, value1_size, "", ",");
3294	    printf("%s", reg_name);
3295	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3296			  "\n");
3297	    return(length);
3298
3299	case MIb:
3300	    wbit = LONGOPERAND;
3301	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3302	    value1_size = sizeof(char);
3303	    IMMEDIATE(&symadd1, &symsub1, &imm0, value1_size);
3304	    printf("%s\t$", mnemonic);
3305	    print_operand("", symadd1, symsub1, imm0, value1_size, "", ",");
3306	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3307			  "\n");
3308	    return(length);
3309
3310	/* single memory or register operand with 'w' bit present */
3311	case Mw:
3312	    wbit = WBIT(opcode2);
3313	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3314	    printf("%s\t", mnemonic);
3315	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3316			  "\n");
3317	    return(length);
3318
3319	/* single memory or register operand but don't use 'l' suffix */
3320	case Mnol:
3321	/* single memory or register operand */
3322	case M:
3323	    if(opcode1 == 0x0 && opcode2 == 0xf &&
3324	       opcode4 == 0x0 && opcode5 == 0x1){
3325		switch(byte){
3326		case 0xc1:
3327		    printf("vmcall\n");
3328		    return(length);
3329		case 0xc2:
3330		    printf("vmlaunch\n");
3331		    return(length);
3332		case 0xc3:
3333		    printf("vmresume\n");
3334		    return(length);
3335		case 0xc4:
3336		    printf("vmxoff\n");
3337		    return(length);
3338		}
3339	    }
3340	    if(opcode1 == 0x0 && opcode2 == 0xf && byte == 0xc7){
3341		if(prefix_byte == 0x66)
3342		    sprintf(mnemonic, "vmclear");
3343		else if(prefix_byte == 0xf3)
3344		    sprintf(mnemonic, "vmxon");
3345		else{
3346		    if(got_modrm_byte == FALSE){
3347			got_modrm_byte = TRUE;
3348			byte = get_value(sizeof(char), sect, &length, &left);
3349			modrm_byte(&mode, &reg, &r_m, byte);
3350		    }
3351		    if(reg == 6)
3352			sprintf(mnemonic, "vmptrld");
3353		    else if(reg == 7)
3354			sprintf(mnemonic, "vmptrst");
3355		    else if(reg == 1 && REX_W(rex))
3356			sprintf(mnemonic, "cmpxchg16b");
3357		}
3358	    }
3359	    /*
3360	     * Hacks for lldt, lmsw, ltr, verr and verw which take only a
3361	     * r/m16 operands.
3362	     */
3363	    if(opcode1 == 0 && opcode2 == 0xf && opcode4 == 0 && opcode5 == 1 &&
3364	       (opcode3 == 6))
3365		data16 = TRUE;
3366	    if(opcode1 == 0 && opcode2 == 0xf && opcode4 == 0 && opcode5 == 0 &&
3367	       (opcode3 == 2 || opcode3 == 3 || opcode3 == 4 || opcode3 == 5))
3368		data16 = TRUE;
3369	    /*
3370	     * Hacks for fnstsw which take only a r/m16 operand.
3371	     */
3372	    if((opcode1 == 0xd && opcode2 == 0xf && byte == 0xe0) ||
3373	       (opcode1 == 0xd && opcode2 == 0xd && opcode3 == 0x7))
3374		data16 = TRUE;
3375	    if(got_modrm_byte == FALSE){
3376		got_modrm_byte = TRUE;
3377		byte = get_value(sizeof(char), sect, &length, &left);
3378		modrm_byte(&mode, &reg, &r_m, byte);
3379	    }
3380	    wbit = LONGOPERAND;
3381	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3382	    printf("%s\t", mnemonic);
3383	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3384			  "\n");
3385	    return(length);
3386
3387	/* single memory or register operand */
3388	case Mb:
3389	    if(got_modrm_byte == FALSE){
3390		got_modrm_byte = TRUE;
3391		byte = get_value(sizeof(char), sect, &length, &left);
3392		modrm_byte(&mode, &reg, &r_m, byte);
3393	    }
3394	    wbit = BYTEOPERAND;
3395	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3396	    printf("%s\t", mnemonic);
3397	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3398			  "\n");
3399	    return(length);
3400
3401	case SREG: /* special register */
3402	    byte = get_value(sizeof(char), sect, &length, &left);
3403	    modrm_byte(&mode, &reg, &r_m, byte);
3404	    vbit = 0;
3405	    switch(opcode5){
3406	    case 2:
3407		vbit = 1;
3408		/* fall thru */
3409	    case 0:
3410		if(llvm_mc == TRUE){
3411		    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64)
3412		        reg_name = LLVM_MC_64_CONTROLREG[reg+(REX_R(rex) << 3)];
3413		    else
3414		        reg_name = LLVM_MC_32_CONTROLREG[reg+(REX_R(rex) << 3)];
3415		}
3416		else{
3417		    reg_name = CONTROLREG[reg + (REX_R(rex) << 3)];
3418		}
3419		break;
3420	    case 3:
3421		vbit = 1;
3422		/* fall thru */
3423	    case 1:
3424		if(llvm_mc == TRUE)
3425		    reg_name = LLVM_MC_DEBUGREG[reg + (REX_R(rex) << 3)];
3426		else
3427		    reg_name = DEBUGREG[reg + (REX_R(rex) << 3)];
3428		break;
3429	    case 6:
3430		vbit = 1;
3431		/* fall thru */
3432	    case 4:
3433		reg_name = TESTREG[reg];
3434		break;
3435	    }
3436	    if(vbit){
3437		printf("%s\t%s,%s\n", mnemonic, get_r_m_name(r_m, 1, data16,
3438		       rex), reg_name);
3439	    }
3440	    else{
3441		printf("%s\t%s,%s\n", mnemonic, reg_name, get_r_m_name(r_m, 1,
3442		       data16, rex));
3443	    }
3444	    return(length);
3445
3446	/* single register operand with register in the low 3	*/
3447	/* bits of op code					*/
3448	case R:
3449	    reg = REGNO(opcode2);
3450	    reg_name = get_r_m_name(reg, LONGOPERAND, data16, rex);
3451	    printf("%s\t%s\n", mnemonic, reg_name);
3452	    return(length);
3453
3454	/* register to accumulator with register in the low 3	*/
3455	/* bits of op code, xchg instructions                   */
3456	case RA:
3457	    reg = REGNO(opcode2);
3458	    if(rex)
3459		reg_name = REG32[reg + (REX_B(rex) << 3)]
3460				[LONGOPERAND + REX_W(rex)];
3461	    else
3462		reg_name = get_reg_name(reg, LONGOPERAND, data16, rex);
3463	    if(rex)
3464		printf("%s\t%s,%s\n", mnemonic, reg_name, "%rax");
3465	    else
3466		printf("%s\t%s,%s\n", mnemonic, reg_name, (data16 ?
3467							  "%ax" : "%eax"));
3468	    return(length);
3469
3470	/* single segment register operand, with reg in bits 3-4 of op code */
3471	case SEG:
3472	    reg = byte >> 3 & 0x3; /* segment register */
3473	    printf("%s\t%s\n", mnemonic, SEGREG[reg]);
3474	    return(length);
3475
3476	/* single segment register operand, with register in	*/
3477	/* bits 3-5 of op code					*/
3478	case LSEG:
3479	    reg = byte >> 3 & 0x7; /* long seg reg from opcode */
3480	    printf("%s\t%s\n", mnemonic, SEGREG[reg]);
3481	    return(length);
3482
3483	/* memory or register operand to register */
3484	case MR:
3485	    /*
3486	     * invvpid and invept outside 64-bit mode the register operand is
3487	     * always 32 bits, since this is encoded with 0x66 (operand-size
3488	     * override) it would have set data16. So clear that to get the
3489	     * correct value from reg_name().
3490	     */
3491	    if((opcode1 == 0x0 && opcode2 == 0xf &&
3492	        opcode4 == 0x3 && opcode5 == 0x8 && prefix_byte == 0x66) &&
3493		(byte == 0x81 || byte == 0x80) &&
3494		(cputype & CPU_ARCH_ABI64) != CPU_ARCH_ABI64)
3495		data16 = FALSE;
3496	    if(got_modrm_byte == FALSE){
3497		got_modrm_byte = TRUE;
3498		byte = get_value(sizeof(char), sect, &length, &left);
3499		modrm_byte(&mode, &reg, &r_m, byte);
3500	    }
3501	    wbit = LONGOPERAND;
3502	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3503	    reg_name = get_reg_name(reg, wbit, data16, rex);
3504	    printf("%s\t", mnemonic);
3505	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3506			  ",");
3507	    printf("%s\n", reg_name);
3508	    return(length);
3509
3510	/* immediate operand to accumulator */
3511	case IA:
3512	    value0_size = OPSIZE(data16, WBIT(opcode2), 0);
3513	    switch(value0_size) {
3514		case 1: reg_name = "%al"; break;
3515		case 2: reg_name = "%ax"; break;
3516		case 4: reg_name = "%eax"; break;
3517	    }
3518	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3519	    printf("%s\t$", mnemonic);
3520	    print_operand("", symadd0, symsub0, imm0, value0_size, "", ",");
3521	    printf("%s\n", reg_name);
3522	    return(length);
3523
3524	/* memory or register operand to accumulator */
3525	case MA:
3526	    wbit = WBIT(opcode2);
3527	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3528	    printf("%s\t", mnemonic);
3529	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3530			  "\n");
3531	    return(length);
3532
3533	/* si register to di register */
3534	case SD:
3535	    if(addr16 == TRUE)
3536		printf("%s\t%s(%%si),(%%di)\n", mnemonic, seg);
3537	    else
3538		printf("%s\t%s(%%esi),(%%edi)\n", mnemonic, seg);
3539	    return(length);
3540
3541	/* accumulator to di register */
3542	case AD:
3543	    wbit = WBIT(opcode2);
3544	    reg_name = get_reg_name(0, wbit, data16, rex);
3545	    if(addr16 == TRUE)
3546		printf("%s\t%s,%s(%%di)\n", mnemonic, reg_name, seg);
3547	    else
3548		printf("%s\t%s,%s(%%edi)\n", mnemonic, reg_name, seg);
3549	    return(length);
3550
3551	/* si register to accumulator */
3552	case SA:
3553	    wbit = WBIT(opcode2);
3554	    reg_name = get_reg_name(0, wbit, data16, rex);
3555	    if(addr16 == TRUE)
3556		printf("%s\t%s(%%si),%s\n", mnemonic, seg, reg_name);
3557	    else
3558		printf("%s\t%s(%%esi),%s\n", mnemonic, seg, reg_name);
3559	    return(length);
3560
3561	/* single operand, a 16/32 bit displacement */
3562	case D:
3563	    value0_size = OPSIZE(data16, LONGOPERAND, 0);
3564	    DISPLACEMENT(&symadd0, &symsub0, &imm0, value0_size);
3565	    printf("%s\t", mnemonic);
3566	    print_operand(seg, symadd0, symsub0, imm0, value0_size, "", "");
3567	    if(verbose){
3568		indirect_symbol_name = guess_indirect_symbol(imm0,
3569		    ncmds, sizeofcmds, load_commands, object_byte_sex,
3570		    indirect_symbols, nindirect_symbols, symbols, symbols64,
3571		    nsymbols, strings,strings_size);
3572		if(indirect_symbol_name != NULL)
3573		    printf("\t; symbol stub for: %s", indirect_symbol_name);
3574	    }
3575	    printf("\n");
3576	    return(length);
3577
3578	/* indirect to memory or register operand */
3579	case INM:
3580	    /*
3581	     * If this is call (near) in a 64-bit object the FF /2 opcode
3582	     * results in a 64-bit operand even without a rex prefix byte.
3583	     * So to get the 64-bit register names in the disassembly we
3584	     * set the REX.W bit to indicate 64-bit operand size.
3585	     */
3586	    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64 &&
3587	       opcode1 == 0xf && opcode2 == 0xf &&
3588	       (opcode3 == 2 || opcode3 == 4))
3589		rex |= 0x8;
3590	    wbit = LONGOPERAND;
3591	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3592	    if((mode == 0 && (r_m == 5 || r_m == 4)) || mode == 1 ||
3593		mode == 2 || mode == 3)
3594		printf("%s\t*", mnemonic);
3595	    else
3596		printf("%s\t", mnemonic);
3597	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3598			  "\n");
3599	    return(length);
3600
3601	/* indirect to memory or register operand (for lcall and ljmp) */
3602	case INMl:
3603	    wbit = LONGOPERAND;
3604	    GET_OPERAND(&symadd0, &symsub0, &value0, &value0_size, result0);
3605	    printf("%s\t*", mnemonic);
3606	    print_operand(seg, symadd0, symsub0, value0, value0_size, result0,
3607			  "\n");
3608	    return(length);
3609
3610	/*
3611	 * For long jumps and long calls -- a new code segment
3612	 * register and an offset in IP -- stored in object
3613	 * code in reverse order
3614	 */
3615	case SO:
3616	    value1_size = OPSIZE(data16, LONGOPERAND, 0);
3617	    IMMEDIATE(&symadd1, &symsub1, &imm1, value1_size);
3618	    value0_size = sizeof(short);
3619	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3620	    printf("%s\t$", mnemonic);
3621	    print_operand("", symadd0, symsub0, imm0, value0_size, "", ",$");
3622	    print_operand(seg, symadd1, symsub1, imm1, value1_size, "", "\n");
3623	    return(length);
3624
3625	/* jmp/call. single operand, 8 bit displacement */
3626	case BD:
3627	    /*
3628	     * The "Jump if rCX Zero" instruction is 0xe3 but is "jcxz" as in
3629	     * the table only in 32-bit mode with a Address-size override
3630	     * prefix.  Without a prefix it is "jecxz" in 32-bit mode.  In
3631	     * 64-bit mode with a prefix it is "jecxz" and without it is
3632	     * "jrcxz".
3633	     */
3634	    if(opcode1 == 0xe && opcode2 == 0x3){
3635		if((cputype & CPU_ARCH_ABI64) != CPU_ARCH_ABI64){
3636		   if(addr16 == FALSE)
3637			sprintf(mnemonic, "jecxz");
3638		}
3639		else if ((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64){
3640		   if(addr16 == TRUE)
3641			sprintf(mnemonic, "jecxz");
3642		   else
3643			sprintf(mnemonic, "jrcxz");
3644		}
3645	    }
3646	    value0_size = sizeof(char);
3647	    DISPLACEMENT(&symadd0, &symsub0, &imm0, value0_size);
3648	    printf("%s\t", mnemonic);
3649	    print_operand(seg, symadd0, symsub0, imm0, sizeof(int32_t), "",
3650			  "\n");
3651	    return(length);
3652
3653	/* single 32/16 bit immediate operand */
3654	case I:
3655	    value0_size = OPSIZE(data16, LONGOPERAND, 0);
3656	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3657	    printf("%s\t$", mnemonic);
3658	    print_operand("", symadd0, symsub0, imm0, value0_size, "", "\n");
3659	    return(length);
3660
3661	/* single 8 bit immediate operand */
3662	case Ib:
3663	    value0_size = sizeof(char);
3664	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3665	    printf("%s\t$", mnemonic);
3666	    print_operand("", symadd0, symsub0, imm0, value0_size, "", "\n");
3667	    return(length);
3668
3669	case ENTER:
3670	    value0_size = sizeof(short);
3671	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3672	    value1_size = sizeof(char);
3673	    IMMEDIATE(&symadd1, &symsub1, &imm1, value1_size);
3674	    printf("%s\t$", mnemonic);
3675	    print_operand("", symadd0, symsub0, imm0, value0_size, "", ",$");
3676	    print_operand("", symadd1, symsub1, imm1, value1_size, "", "\n");
3677	    return(length);
3678
3679	/* 16-bit immediate operand */
3680	case RET:
3681	    value0_size = sizeof(short);
3682	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3683	    printf("%s\t$", mnemonic);
3684	    print_operand("", symadd0, symsub0, imm0, value0_size, "", "\n");
3685	    return(length);
3686
3687	/* single 8 bit port operand */
3688	case P:
3689	    value0_size = sizeof(char);
3690	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3691	    printf("%s\t$", mnemonic);
3692	    print_operand(seg, symadd0, symsub0, imm0, value0_size, "", "\n");
3693	    return(length);
3694
3695	/* single 8 bit (input) port operand				*/
3696	case Pi:
3697	    value0_size = sizeof(char);
3698	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3699	    printf("%s\t$", mnemonic);
3700	    if(opcode2 == 4)
3701		print_operand(seg, symadd0, symsub0, imm0, value0_size, "",
3702			      ",%al\n");
3703	    else if(data16)
3704		print_operand(seg, symadd0, symsub0, imm0, value0_size, "",
3705			      ",%ax\n");
3706	    else
3707		print_operand(seg, symadd0, symsub0, imm0, value0_size, "",
3708			      ",%eax\n");
3709	    return(length);
3710
3711	/* single 8 bit (output) port operand				*/
3712	case Po:
3713	    value0_size = sizeof(char);
3714	    IMMEDIATE(&symadd0, &symsub0, &imm0, value0_size);
3715	    if(opcode2 == 0x6)
3716		printf("%s\t%%al,$", mnemonic);
3717	    else if(data16)
3718		printf("%s\t%%ax,$", mnemonic);
3719	    else
3720		printf("%s\t%%eax,$", mnemonic);
3721	    print_operand(seg, symadd0, symsub0, imm0, value0_size, "", "\n");
3722	    return(length);
3723
3724	/* single operand, dx register (variable port instruction) */
3725	case V:
3726	    printf("%s\t%s(%%dx)\n", mnemonic, seg);
3727	    return(length);
3728
3729	/* single operand, dx register (variable (input) port instruction) */
3730	case Vi:
3731	    if(opcode2 == 0xc)
3732		printf("%s\t%s%%dx,%%al\n", mnemonic, seg);
3733	    else if(data16)
3734		printf("%s\t%s%%dx,%%ax\n", mnemonic, seg);
3735	    else
3736		printf("%s\t%s%%dx,%%eax\n", mnemonic, seg);
3737	    return(length);
3738
3739	/* single operand, dx register (variable (output) port instruction)*/
3740	case Vo:
3741	    if(opcode2 == 0xe)
3742		printf("%s\t%s%%al,%%dx\n", mnemonic, seg);
3743	    else if(data16)
3744		printf("%s\t%s%%ax,%%dx\n", mnemonic, seg);
3745	    else
3746		printf("%s\t%s%%eax,%%dx\n", mnemonic, seg);
3747	    return(length);
3748
3749	/* The int instruction, which has two forms: int 3 (breakpoint) or  */
3750	/* int n, where n is indicated in the subsequent byte (format Ib).  */
3751	/* The int 3 instruction (opcode 0xCC), where, although the 3 looks */
3752	/* like an operand, it is implied by the opcode. It must be converted */
3753	/* to the correct base and output. */
3754	case INT3:
3755	    printf("%s\t$0x3\n", mnemonic);
3756	    return(length);
3757
3758	/* just an opcode and an unused byte that must be discarded */
3759	case U:
3760	    byte = get_value(sizeof(char), sect, &length, &left);
3761	    if(opcode1 == 0xd && (opcode2 == 0x5 || opcode2 == 0x4) &&
3762	       byte != 0xa)
3763		printf("%s\t$0x%x\n", mnemonic, byte);
3764	    else
3765		printf("%s\n", mnemonic);
3766	    return(length);
3767
3768	case CBW:
3769	    if(rex != 0)
3770		printf("cdqe\n");
3771	    else if(data16 == TRUE)
3772		printf("cbtw\n");
3773	    else
3774		printf("cwtl\n");
3775	    return(length);
3776
3777	case CWD:
3778	    if(rex != 0)
3779		printf("cqto\n");
3780	    else if(data16 == TRUE)
3781		printf("cwtd\n");
3782	    else
3783		printf("cltd\n");
3784	    return(length);
3785
3786	/* no disassembly, the mnemonic was all there was so go on */
3787	case GO_ON:
3788	    printf("%s\n", mnemonic);
3789	    return(length);
3790
3791	/* float reg */
3792	case F:
3793	    printf("%s\t%%st(%1.1u)\n", mnemonic, r_m);
3794	    return(length);
3795
3796	/* float reg to float reg, with ret bit present */
3797	case FF:
3798	    /* return result bit for 287 instructions */
3799	    if(((opcode2 >> 2) & 0x1) == 0x1 && opcode2 != 0xf)
3800		printf("%s\t%%st,%%st(%1.1u)\n", mnemonic, r_m);
3801	    else
3802		printf("%s\t%%st(%1.1u),%%st\n", mnemonic, r_m);
3803	    return(length);
3804
3805	/* an invalid op code */
3806	case AM:
3807	case DM:
3808	case OVERRIDE:
3809	case PREFIX:
3810	case UNKNOWN:
3811	default:
3812	    printf(".byte 0x%02x", 0xff & sect[0]);
3813	    for(i = 1; i < length; i++)
3814		printf(", 0x%02x", 0xff & sect[i]);
3815	    printf(" #bad opcode\n");
3816	    return(length);
3817	} /* end switch */
3818}
3819
3820/*
3821 * get_operand() is used to return the symbolic operand for an operand that is
3822 * encoded with a mod r/m byte.
3823 */
3824static
3825void
3826get_operand(
3827const char **symadd,
3828const char **symsub,
3829uint32_t *value,
3830uint32_t *value_size,
3831char *result,
3832
3833const cpu_type_t cputype,
3834const uint32_t mode,
3835const uint32_t r_m,
3836const uint32_t wbit,
3837const enum bool data16,
3838const enum bool addr16,
3839const enum bool sse2,
3840const enum bool mmx,
3841const unsigned int rex,
3842
3843const char *sect,
3844uint32_t sect_addr,
3845uint32_t *length,
3846uint32_t *left,
3847
3848const uint32_t addr,
3849const struct relocation_info *sorted_relocs,
3850const uint32_t nsorted_relocs,
3851const struct nlist *symbols,
3852const struct nlist_64 *symbols64,
3853const uint32_t nsymbols,
3854const char *strings,
3855const uint32_t strings_size,
3856
3857const struct symbol *sorted_symbols,
3858const uint32_t nsorted_symbols,
3859const enum bool verbose)
3860{
3861    enum bool s_i_b;		/* flag presence of scale-index-byte */
3862    unsigned char byte;		/* the scale-index-byte */
3863    uint32_t ss;		/* scale-factor from scale-index-byte */
3864    uint32_t index; 		/* index register number from scale-index-byte*/
3865    uint32_t base;  		/* base register number from scale-index-byte */
3866    uint32_t sect_offset;
3867    uint64_t offset;
3868
3869	*symadd = NULL;
3870	*symsub = NULL;
3871	*value = 0;
3872	*result = '\0';
3873	base = 0;
3874	index = 0;
3875	ss = 0;
3876
3877	/* check for the presence of the s-i-b byte */
3878	if(r_m == ESP && mode != REG_ONLY &&
3879	   (((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64) || addr16 == FALSE)){
3880	    s_i_b = TRUE;
3881	    byte = get_value(sizeof(char), sect, length, left);
3882	    modrm_byte(&ss, &index, &base, byte);
3883	}
3884	else
3885	    s_i_b = FALSE;
3886
3887	if(addr16 && (cputype & CPU_ARCH_ABI64) != CPU_ARCH_ABI64)
3888	    *value_size = dispsize16[r_m][mode];
3889	else
3890	    *value_size = dispsize32[r_m][mode];
3891
3892	if(s_i_b == TRUE && mode == 0 && base == EBP)
3893	    *value_size = sizeof(int32_t);
3894
3895	if(*value_size != 0){
3896	    sect_offset = addr + *length - sect_addr;
3897	    *value = get_value(*value_size, sect, length, left);
3898	    GET_SYMBOL(symadd, symsub, &offset, sect_offset, *value);
3899	    if(*symadd != NULL){
3900		*value = offset;
3901	    }
3902	    else{
3903		*symadd = GUESS_SYMBOL(*value);
3904		if(*symadd != NULL)
3905		    *value = 0;
3906	    }
3907	}
3908
3909	if(s_i_b == TRUE){
3910	    if(((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64) && !addr16){
3911		/* If the scale factor is 1, don't display it. */
3912		if(ss == 0){
3913		    /*
3914		     * If mode is 0 and base is 5 (regardless of the rex bit)
3915		     * there is no base register, and if the index is
3916		     * also 4 then the operand is just a displacement.
3917		     */
3918		    if(mode == 0 && base == 5 && index == 4){
3919			result = "";
3920		    }
3921		    else{
3922			sprintf(result, "(%s%s)", regname64[mode][base +
3923				(REX_B(rex) << 3)], indexname64[index +
3924				(REX_X(rex) << 3)]);
3925		    }
3926		}
3927		else{
3928		    /*
3929		     * If mode is 0 and base is 5 (regardless of the rex bit)
3930		     * there is no base register.
3931		     */
3932		    if(mode == 0 && base == 5){
3933			sprintf(result, "(%s,%s)", indexname64[index +
3934				(REX_X(rex) << 3)], scale_factor[ss]);
3935		    }
3936		    else{
3937			sprintf(result, "(%s%s,%s)", regname64[mode][base +
3938				(REX_B(rex) << 3)], indexname64[index +
3939				(REX_X(rex) << 3)], scale_factor[ss]);
3940		    }
3941		}
3942	    }
3943	    else{
3944		/* If the scale factor is 1, don't display it. */
3945		if(ss == 0){
3946		    /*
3947		     * If mode is 0 and base is 5 it there is no base register,
3948		     * and if the index is also 4 then the operand is just a
3949		     * displacement.
3950		     */
3951		    if(mode == 0 && base == 5 && index == 4){
3952			result = "";
3953		    }
3954		    else{
3955			sprintf(result, "(%s%s)", regname32[mode][base],
3956				indexname[index]);
3957		    }
3958		}
3959		else{
3960		    sprintf(result, "(%s%s,%s)", regname32[mode][base],
3961			    indexname[index], scale_factor[ss]);
3962		}
3963	    }
3964	}
3965	else{ /* no s-i-b */
3966	    if(mode == REG_ONLY){
3967		if(sse2 == TRUE)
3968		    sprintf(result, "%%xmm%u", xmm_rm(r_m, rex));
3969		else if(mmx == TRUE)
3970		    sprintf(result, "%%mm%u", r_m);
3971		else if (data16 == FALSE || rex != 0)
3972		    /* The presence of a REX byte overrides 66h. */
3973		    strcpy(result, REG32[r_m + (REX_B(rex) << 3)][wbit +
3974			   REX_W(rex)]);
3975		else
3976		    strcpy(result, REG16[r_m][wbit]);
3977	    }
3978	    else{ /* Modes 00, 01, or 10 */
3979		if(r_m == EBP && mode == 0){ /* displacement only */
3980		    if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64)
3981			/*
3982			 * In 64-bit mode, mod=00 and r/m=101 defines
3983			 * RIP-relative addressing with a 32-bit displacement.
3984			 * In 32-bit mode, it's just a 32-bit displacement. See
3985			 * section 2.2.1.6 ("RIP-Relative Addressing") of Volume
3986			 * 2A of the Intel IA-32 manual.
3987			 */
3988			sprintf(result, "(%%rip)");
3989		    else
3990			*result = '\0';
3991		}
3992		else {
3993		    /* Modes 00, 01, or 10, not displacement only, no s-i-b */
3994		    if(addr16 == TRUE) {
3995			if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64)
3996			    /*
3997			     *  In 64-bit mode, the address size prefix drops us
3998			     * down to 32-bit, not 16-bit.
3999			     */
4000			    sprintf(result, "(%s)", regname32[mode][r_m]);
4001			else
4002			    sprintf(result, "(%s)", regname16[mode][r_m]);
4003		    }
4004		    else{
4005			if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64)
4006			    sprintf(result, "(%s)", regname64[mode][r_m +
4007				    (REX_B(rex) << 3)]);
4008			else
4009			    sprintf(result, "(%s)", regname32[mode][r_m]);
4010		    }
4011		}
4012	    }
4013	}
4014}
4015
4016/*
4017 * immediate() is used to return the symbolic operand for an immediate operand.
4018 */
4019static
4020void
4021immediate(
4022const char **symadd,
4023const char **symsub,
4024uint64_t *value,
4025uint32_t value_size,
4026
4027const char *sect,
4028uint32_t sect_addr,
4029uint32_t *length,
4030uint32_t *left,
4031
4032const cpu_type_t cputype,
4033const uint32_t addr,
4034const struct relocation_info *sorted_relocs,
4035const uint32_t nsorted_relocs,
4036const struct nlist *symbols,
4037const struct nlist_64 *symbols64,
4038const uint32_t nsymbols,
4039const char *strings,
4040const uint32_t strings_size,
4041
4042const struct symbol *sorted_symbols,
4043const uint32_t nsorted_symbols,
4044const enum bool verbose)
4045{
4046    uint32_t sect_offset;
4047	uint64_t offset;
4048
4049	sect_offset = addr + *length - sect_addr;
4050	*value = get_value(value_size, sect, length, left);
4051	GET_SYMBOL(symadd, symsub, &offset, sect_offset, *value);
4052	if(*symadd == NULL){
4053	    *symadd = GUESS_SYMBOL(*value);
4054	    if(*symadd != NULL)
4055		*value = 0;
4056	}
4057	else if(*symsub != NULL){
4058	    *value = offset;
4059	}
4060}
4061
4062/*
4063 * displacement() is used to return the symbolic operand for an operand that is
4064 * encoded as a displacement from the program counter.
4065 */
4066static
4067void
4068displacement(
4069const char **symadd,
4070const char **symsub,
4071uint64_t *value,
4072const uint32_t value_size,
4073
4074const char *sect,
4075uint64_t sect_addr,
4076uint32_t *length,
4077uint32_t *left,
4078
4079const uint32_t filetype,
4080const cpu_type_t cputype,
4081const uint64_t addr,
4082const struct relocation_info *sorted_relocs,
4083const uint32_t nsorted_relocs,
4084const struct nlist *symbols,
4085const struct nlist_64 *symbols64,
4086const uint32_t nsymbols,
4087const char *strings,
4088const uint32_t strings_size,
4089
4090const struct symbol *sorted_symbols,
4091const uint32_t nsorted_symbols,
4092const enum bool verbose)
4093{
4094    uint32_t sect_offset;
4095	uint64_t offset;
4096	uint64_t guess_addr;
4097
4098	sect_offset = addr + *length;
4099	if(filetype != MH_KEXT_BUNDLE)
4100	    sect_offset -= sect_addr;
4101	*value = get_value(value_size, sect, length, left);
4102	switch(value_size){
4103	case 1:
4104	    if((*value) & 0x80)
4105		*value = *value | 0xffffffffffffff00ULL;
4106	    break;
4107	case 2:
4108	    if((*value) & 0x8000)
4109		*value = *value | 0xffffffffffff0000ULL;
4110	    break;
4111	case 4:
4112	    if((*value) & 0x80000000)
4113		*value = *value | 0xffffffff00000000ULL;
4114	    break;
4115	}
4116	if((cputype & CPU_ARCH_ABI64) != CPU_ARCH_ABI64)
4117	    *value += addr + *length;
4118
4119	GET_SYMBOL(symadd, symsub, &offset, sect_offset, *value);
4120	if(*symadd == NULL){
4121	    if((cputype & CPU_ARCH_ABI64) != CPU_ARCH_ABI64){
4122		*symadd = GUESS_SYMBOL(*value);
4123		if(*symadd != NULL)
4124		    *value = 0;
4125	    }
4126	    else{
4127		guess_addr = *value;
4128		if((*value) & 0x80000000)
4129		    guess_addr |= 0xffffffff00000000ULL;
4130		guess_addr += addr + *length;
4131		*symadd = GUESS_SYMBOL(guess_addr);
4132		if(*symadd != NULL)
4133		    *value = 0;
4134		else
4135		    *value += addr + *length;
4136	    }
4137	}
4138	else if(*symsub != NULL){
4139	    *value = offset;
4140	}
4141	if((cputype & CPU_ARCH_ABI64) != CPU_ARCH_ABI64)
4142	    *value = *value & 0x00000000ffffffffULL;
4143}
4144
4145/*
4146 * get_symbol() returns the name of a symbol (or NULL) based on the relocation
4147 * information at the specified address.
4148 */
4149static
4150void
4151get_symbol(
4152const char **symadd,
4153const char **symsub,
4154uint64_t *offset,
4155
4156const cpu_type_t cputype,
4157const uint32_t sect_offset,
4158const uint64_t value,
4159const struct relocation_info *relocs,
4160const uint32_t nrelocs,
4161const struct nlist *symbols,
4162const struct nlist_64 *symbols64,
4163const uint32_t nsymbols,
4164const char *strings,
4165const uint32_t strings_size,
4166const struct symbol *sorted_symbols,
4167const uint32_t nsorted_symbols,
4168const enum bool verbose)
4169{
4170    uint32_t i;
4171    unsigned int r_symbolnum;
4172    uint32_t n_strx;
4173    struct scattered_relocation_info *sreloc, *pair;
4174    const char *name, *add, *sub;
4175
4176    static char add_buffer[11]; /* max is "0x1234678\0" */
4177    static char sub_buffer[11];
4178
4179	*symadd = NULL;
4180	*symsub = NULL;
4181	*offset = value;
4182
4183	if(verbose == FALSE)
4184	    return;
4185
4186	for(i = 0; i < nrelocs; i++){
4187	    if((cputype & CPU_ARCH_ABI64) != CPU_ARCH_ABI64 &&
4188	       ((relocs[i].r_address) & R_SCATTERED) != 0){
4189		sreloc = (struct scattered_relocation_info *)(relocs + i);
4190		if(sreloc->r_type == GENERIC_RELOC_PAIR){
4191		    fprintf(stderr, "Stray GENERIC_RELOC_PAIR relocation entry "
4192			    "%u\n", i);
4193		    continue;
4194		}
4195		if(sreloc->r_type == GENERIC_RELOC_VANILLA){
4196		    if(sreloc->r_address == sect_offset){
4197			name = guess_symbol(sreloc->r_value,
4198					    sorted_symbols,
4199					    nsorted_symbols,
4200					    verbose);
4201			if(name != NULL){
4202			    *symadd = name;
4203			    *offset = value - sreloc->r_value;
4204			    return;
4205			}
4206		    }
4207		    continue;
4208		}
4209		if(sreloc->r_type != GENERIC_RELOC_SECTDIFF &&
4210		   sreloc->r_type != GENERIC_RELOC_LOCAL_SECTDIFF){
4211		    fprintf(stderr, "Unknown relocation r_type for entry "
4212			    "%u\n", i);
4213		    continue;
4214		}
4215		if(i + 1 < nrelocs){
4216		    pair = (struct scattered_relocation_info *)(relocs + i + 1);
4217		    if(pair->r_scattered == 0 ||
4218		       pair->r_type != GENERIC_RELOC_PAIR){
4219			fprintf(stderr, "No GENERIC_RELOC_PAIR relocation "
4220				"entry after entry %u\n", i);
4221			continue;
4222		    }
4223		}
4224		else{
4225		    fprintf(stderr, "No GENERIC_RELOC_PAIR relocation entry "
4226			    "after entry %u\n", i);
4227		    continue;
4228		}
4229		i++; /* skip the pair reloc */
4230
4231		if(sreloc->r_address == sect_offset){
4232		    add = guess_symbol(sreloc->r_value, sorted_symbols,
4233				       nsorted_symbols, verbose);
4234		    sub = guess_symbol(pair->r_value, sorted_symbols,
4235				       nsorted_symbols, verbose);
4236		    if(add == NULL){
4237			sprintf(add_buffer, "0x%x",
4238				(unsigned int)sreloc->r_value);
4239			add = add_buffer;
4240		    }
4241		    if(sub == NULL){
4242			sprintf(sub_buffer, "0x%x",
4243				(unsigned int)pair->r_value);
4244			sub = sub_buffer;
4245		    }
4246		    *symadd = add;
4247		    *symsub = sub;
4248		    *offset = value - (sreloc->r_value - pair->r_value);
4249		    return;
4250		}
4251	    }
4252	    else{
4253		if((uint32_t)relocs[i].r_address == sect_offset){
4254		    r_symbolnum = relocs[i].r_symbolnum;
4255		    if(relocs[i].r_extern){
4256		        if(r_symbolnum >= nsymbols)
4257			    return;
4258			if(symbols != NULL)
4259			    n_strx = symbols[r_symbolnum].n_un.n_strx;
4260			else
4261			    n_strx = symbols64[r_symbolnum].n_un.n_strx;
4262			if(n_strx <= 0 || n_strx >= strings_size)
4263			    return;
4264			if((cputype & CPU_ARCH_ABI64) == CPU_ARCH_ABI64 &&
4265			   relocs[i].r_type == X86_64_RELOC_SUBTRACTOR &&
4266			   i+1 < nrelocs &&
4267			   relocs[i+1].r_type == X86_64_RELOC_UNSIGNED &&
4268			   relocs[i+1].r_extern == 1 &&
4269			   relocs[i+1].r_symbolnum < nsymbols){
4270			    *symsub = strings + n_strx;
4271			    r_symbolnum = relocs[i+1].r_symbolnum;
4272			    if(symbols64 == NULL)
4273				return;
4274			    n_strx = symbols64[r_symbolnum].n_un.n_strx;
4275			    if(n_strx <= 0 || n_strx >= strings_size)
4276				return;
4277			}
4278			*symadd = strings + n_strx;
4279			return;
4280		    }
4281		    break;
4282		}
4283	    }
4284	}
4285}
4286
4287/*
4288 * print_operand() prints an operand from it's broken out symbolic
4289 * representation.
4290 */
4291static
4292void
4293print_operand(
4294const char *seg,
4295const char *symadd,
4296const char *symsub,
4297uint64_t value,
4298unsigned int value_size,
4299const char *result,
4300const char *tail)
4301{
4302	if(symadd != NULL){
4303	    if(symsub != NULL){
4304		if(value_size != 0){
4305		    if(value != 0)
4306			printf("%s%s-%s+0x%0*llx%s%s", seg, symadd, symsub,
4307			       (int)value_size * 2, value, result, tail);
4308		    else
4309			printf("%s%s-%s%s%s",seg, symadd, symsub, result, tail);
4310		}
4311		else{
4312		    printf("%s%s%s%s", seg, symadd, result, tail);
4313		}
4314	    }
4315	    else{
4316		if(value_size != 0){
4317		    if(value != 0)
4318			printf("%s%s+0x%0*llx%s%s", seg, symadd,
4319			       (int)value_size * 2, value, result, tail);
4320		    else
4321			printf("%s%s%s%s", seg, symadd, result, tail);
4322		}
4323		else{
4324		    printf("%s%s%s%s", seg, symadd, result, tail);
4325		}
4326	    }
4327	}
4328	else{
4329	    if(value_size != 0){
4330		printf("%s0x%0*llx%s%s", seg, (int)value_size *2, value, result,
4331		       tail);
4332	    }
4333	    else{
4334		printf("%s%s%s", seg, result, tail);
4335	    }
4336	}
4337}
4338
4339/*
4340 * get_value() gets a value of size from sect + length and decrease left by the
4341 * size and increase length by size.  The size of the value can be 1, 2, 4, or 8
4342 * bytes and the value is in little endian byte order.  The value is always
4343 * returned as a uint64_t and is not sign extended.
4344 */
4345static
4346uint64_t
4347get_value(
4348const uint32_t size,	/* size of the value to get as a number of bytes (in)*/
4349const char *sect,	/* pointer to the raw data of the section (in) */
4350uint32_t *length,	/* number of bytes taken from the sect (in/out) */
4351uint32_t *left)		/* number of bytes left in sect after length (in/out) */
4352{
4353    uint32_t i;
4354    uint64_t value;
4355    unsigned char byte;
4356
4357	if(left == 0)
4358	    return(0);
4359
4360	value = 0;
4361	for(i = 0; i < size; i++) {
4362	    byte = 0;
4363	    if(*left > 0){
4364		byte = sect[*length];
4365		(*length)++;
4366		(*left)--;
4367	    }
4368	    value |= (uint64_t)byte << (8*i);
4369	}
4370	return(value);
4371}
4372
4373/*
4374 * modrm_byte() breaks a byte out into its mode, reg and r/m bits.
4375 */
4376static
4377void
4378modrm_byte(
4379uint32_t *mode,
4380uint32_t *reg,
4381uint32_t *r_m,
4382unsigned char byte)
4383{
4384	*r_m = byte & 0x7; /* r/m field from the byte */
4385	*reg = byte >> 3 & 0x7; /* register field from the byte */
4386	*mode = byte >> 6 & 0x3; /* mode field from the byte */
4387}
4388
4389/*
4390 * i386GetOpInfo() is the operand information call back function for i386 code.
4391 * This is called to get the symbolic information for an operand of an i386
4392 * instruction.  This is done from the relocation information, symbol table,
4393 * etc.  That block of information is a pointer to the struct disassemble_info
4394 * that was passed when the disassembler context was created and passed to back
4395 * to i386GetOpInfo() when called back by LLVMDisasmInstruction().  The address
4396 * of the instruction containing operand is at the Pc parameter.  The immediate
4397 * for the operand is at Offset past the start of the instruction and has a byte
4398 * Width of 1, 2 or 4.  The information is returned in TagBuf is the
4399 * LLVMOpInfo1 struct defined in "llvm-c/Disassembler.h".  The value of TagType
4400 * is currently 1 (for the LLVMOpInfo1 struct). If symbolic information is
4401 * returned then this function returns 1 else it returns 0.
4402 */
4403static
4404int
4405i386GetOpInfo(
4406void *DisInfo,
4407uint64_t Pc,
4408uint64_t Offset,
4409uint64_t Width,
4410int TagType,     /* should currently always be passed as 1 */
4411void *TagBuf)
4412{
4413    struct disassemble_info *info;
4414    struct LLVMOpInfo1 *op_info;
4415    unsigned int value;
4416    int32_t reloc_found, offset;
4417    uint32_t sect_offset, i, r_address, r_symbolnum, r_type, r_extern, r_length,
4418	     r_value, r_scattered, pair_r_type, pair_r_value;
4419    uint32_t other_half;
4420    const char *strings, *name, *add, *sub;
4421    struct relocation_info *relocs, *rp, *pairp;
4422    struct scattered_relocation_info *srp, *spairp;
4423    uint32_t nrelocs, strings_size, n_strx;
4424    struct nlist *symbols;
4425
4426	info = (struct disassemble_info *)DisInfo;
4427
4428	op_info = (struct LLVMOpInfo1 *)TagBuf;
4429	value = op_info->Value;
4430	/* make sure all feilds returned are zero if we don't set them */
4431	memset(op_info, '\0', sizeof(struct LLVMOpInfo1));
4432	op_info->Value = value;
4433
4434	if((Width != 1 && Width != 2 && Width != 4) || TagType != 1 ||
4435	   info->verbose == FALSE)
4436	    return(0);
4437
4438	sect_offset = (Pc + Offset);
4439	if(info->filetype != MH_KEXT_BUNDLE)
4440	    sect_offset -= info->sect_addr;
4441	relocs = info->sorted_relocs;
4442	nrelocs = info->nsorted_relocs;
4443	symbols = info->symbols;
4444	strings = info->strings;
4445	strings_size = info->strings_size;
4446
4447	r_symbolnum = 0;
4448	r_type = 0;
4449	r_extern = 0;
4450	r_value = 0;
4451	r_scattered = 0;
4452	other_half = 0;
4453	pair_r_value = 0;
4454	n_strx = 0;
4455	r_length = 0;
4456
4457	/*
4458	 * When searching for a relocation entry for this sect_offset we simply
4459	 * return if we run into errors.
4460	 */
4461	reloc_found = 0;
4462	for(i = 0; i < nrelocs; i++){
4463	    rp = &relocs[i];
4464	    if(rp->r_address & R_SCATTERED){
4465		srp = (struct scattered_relocation_info *)rp;
4466		r_scattered = 1;
4467		r_address = srp->r_address;
4468		r_extern = 0;
4469		r_length = srp->r_length;
4470		r_type = srp->r_type;
4471		r_value = srp->r_value;
4472	    }
4473	    else{
4474		r_scattered = 0;
4475		r_address = rp->r_address;
4476		r_symbolnum = rp->r_symbolnum;
4477		r_extern = rp->r_extern;
4478		r_length = rp->r_length;
4479		r_type = rp->r_type;
4480	    }
4481	    if(r_type == GENERIC_RELOC_PAIR){
4482		/* Error stray GENERIC_RELOC_PAIR relocation entry. */
4483		return(0);
4484	    }
4485	    if(r_address == sect_offset){
4486		if(r_type == GENERIC_RELOC_SECTDIFF ||
4487		   r_type == GENERIC_RELOC_LOCAL_SECTDIFF){
4488		    if(i+1 < nrelocs){
4489			pairp = &rp[1];
4490			if(pairp->r_address & R_SCATTERED){
4491			    spairp = (struct scattered_relocation_info *)
4492				     pairp;
4493			    pair_r_type = spairp->r_type;
4494			    pair_r_value = spairp->r_value;
4495			}
4496			else{
4497			    pair_r_type = pairp->r_type;
4498			}
4499			if(pair_r_type != GENERIC_RELOC_PAIR){
4500			    /* Error missing GENERIC_RELOC_PAIR relocation. */
4501			    return(0);
4502			}
4503		    }
4504		}
4505		reloc_found = 1;
4506		break;
4507	    }
4508	    if(r_type == GENERIC_RELOC_SECTDIFF ||
4509	       r_type == GENERIC_RELOC_LOCAL_SECTDIFF){
4510		if(i+1 < nrelocs){
4511		    pairp = &rp[1];
4512		    if(pairp->r_address & R_SCATTERED){
4513			spairp = (struct scattered_relocation_info *)pairp;
4514			pair_r_type = spairp->r_type;
4515		    }
4516		    else{
4517			pair_r_type = pairp->r_type;
4518		    }
4519		    if(pair_r_type == GENERIC_RELOC_PAIR)
4520			i++;
4521		    else{
4522			/* Error missing GENERIC_RELOC_PAIR relocation. */
4523			return(0);
4524		    }
4525		}
4526	    }
4527	}
4528
4529	if(reloc_found && r_extern == 1){
4530	    if(symbols != NULL)
4531		n_strx = symbols[r_symbolnum].n_un.n_strx;
4532	    if(n_strx >= strings_size){
4533		/* Error bad string offset. */
4534		return(0);
4535	    }
4536	    name = strings + n_strx;
4537	    op_info->AddSymbol.Present = 1;
4538	    op_info->AddSymbol.Name = name;
4539	    /*
4540	     * For i386 extern relocation entries the value in the instrucion is
4541	     * the offset from the symbol.
4542	     */
4543	    op_info->Value = value;
4544	    return(1);
4545	}
4546
4547	if(reloc_found &&
4548	   (r_type == GENERIC_RELOC_SECTDIFF ||
4549	    r_type == GENERIC_RELOC_LOCAL_SECTDIFF)){
4550	    add = guess_symbol(r_value, info->sorted_symbols,
4551			       info->nsorted_symbols, info->verbose);
4552	    sub = guess_symbol(pair_r_value, info->sorted_symbols,
4553			       info->nsorted_symbols, info->verbose);
4554	    offset = value - (r_value - pair_r_value);
4555	    op_info->AddSymbol.Present = 1;
4556	    if(add != NULL)
4557		op_info->AddSymbol.Name = add;
4558	    else
4559		op_info->AddSymbol.Value = r_value;
4560	    op_info->SubtractSymbol.Present = 1;
4561	    if(sub != NULL)
4562		op_info->SubtractSymbol.Name = sub;
4563	    else
4564		op_info->SubtractSymbol.Value = pair_r_value;
4565	    op_info->Value = offset;
4566	    return(1);
4567	}
4568
4569	/* We found no symbolic info so just return zero indicating that. */
4570	return(0);
4571}
4572
4573/*
4574 * x86_64GetOpInfo() is the operand information call back function for x86_64
4575 * code.  This is called to get the symbolic information for an operand of an
4576 * x86_64 instruction.  This is done from the relocation information, symbol
4577 * table, etc.  That block of information is a pointer to the struct
4578 * disassemble_info that was passed when the disassembler context was created
4579 * and passed to back to x86_64GetOpInfo() when called back by
4580 * LLVMDisasmInstruction().  The address of the instruction containing operand
4581 * is at the Pc parameter.  The immediate for the operand is at Offset past the
4582 * start of the instruction and has a byte Width of 1, 2 or 4.  The information
4583 * is returned in TagBuf is the LLVMOpInfo1 struct defined in
4584 * "llvm-c/Disassembler.h".  The value of TagType is currently 1 (for the
4585 * LLVMOpInfo1 struct). If symbolic information is returned then this function
4586 * returns 1 else it returns 0.
4587 */
4588static
4589int
4590x86_64GetOpInfo(
4591void *DisInfo,
4592uint64_t Pc,
4593uint64_t Offset,
4594uint64_t Width,
4595int TagType,     /* should currently always be passed as 1 */
4596void *TagBuf)
4597{
4598    struct disassemble_info *info;
4599    struct LLVMOpInfo1 *op_info;
4600    unsigned int value;
4601    int32_t reloc_found;
4602    uint32_t sect_offset, i;
4603    const char *strings, *name;
4604    struct relocation_info *relocs;
4605    uint32_t nrelocs, strings_size, n_strx;
4606    struct nlist_64 *symbols;
4607
4608	info = (struct disassemble_info *)DisInfo;
4609
4610	op_info = (struct LLVMOpInfo1 *)TagBuf;
4611	value = op_info->Value;
4612	/* make sure all fields returned are zero if we don't set them */
4613	memset(op_info, '\0', sizeof(struct LLVMOpInfo1));
4614	op_info->Value = value;
4615
4616	if((Width != 1 && Width != 2 && Width != 4 && Width != 0) ||
4617	   TagType != 1 ||
4618	   info->verbose == FALSE)
4619	    return(0);
4620
4621	sect_offset = (Pc + Offset);
4622	if(info->filetype != MH_KEXT_BUNDLE)
4623	    sect_offset -= info->sect_addr;
4624	relocs = info->sorted_relocs;
4625	nrelocs = info->nsorted_relocs;
4626	symbols = info->symbols64;
4627	strings = info->strings;
4628	strings_size = info->strings_size;
4629
4630	reloc_found = 0;
4631	for(i = 0; i < nrelocs; i++){
4632	    /* We could also check the Width matches the r_length. */
4633	    if(relocs[i].r_address == sect_offset){
4634		reloc_found = 1;
4635		break;
4636	    }
4637	}
4638
4639	if(reloc_found && relocs[i].r_extern == 1){
4640	    /*
4641	     * The Value passed in will be adjusted by the Pc if the instruction
4642	     * adds the Pc.  But for x86_64 external relocation entries the
4643	     * Value is the offset from the external symbol.
4644	     */
4645	    if(relocs[i].r_pcrel == 1)
4646		op_info->Value -= Pc + Offset + Width;
4647	    if(symbols != NULL)
4648		n_strx = symbols[relocs[i].r_symbolnum].n_un.n_strx;
4649	    else
4650		return(0);
4651	    if(n_strx >= strings_size)
4652		return(0);
4653	    name = strings + n_strx;
4654	    if(relocs[i].r_type == X86_64_RELOC_SUBTRACTOR &&
4655	       i+1 < nrelocs &&
4656	       relocs[i+1].r_type == X86_64_RELOC_UNSIGNED &&
4657	       relocs[i+1].r_extern == 1){
4658		op_info->SubtractSymbol.Present = 1;
4659		op_info->SubtractSymbol.Name = name;
4660		if(symbols != NULL)
4661		    n_strx = symbols[relocs[i+1].r_symbolnum].n_un.n_strx;
4662		if(n_strx >= strings_size)
4663		    return(0);
4664		name = strings + n_strx;
4665	    }
4666	    op_info->AddSymbol.Present = 1;
4667	    op_info->AddSymbol.Name = name;
4668	    return(1);
4669	}
4670
4671	/* We found no symbolic info so just return zero indicating that. */
4672	return(0);
4673}
4674
4675/*
4676 * guess_cstring_pointer() is passed the address of what might be a pointer to a
4677 * literal string in a cstring section.  If that address is in a cstring section
4678 * it returns a pointer to that string.  Else it returns NULL.
4679 */
4680static
4681const char *
4682guess_cstring_pointer(
4683const uint64_t value,
4684const uint32_t ncmds,
4685const uint32_t sizeofcmds,
4686const struct load_command *load_commands,
4687const enum byte_sex load_commands_byte_sex,
4688const char *object_addr,
4689const uint64_t object_size)
4690{
4691    enum byte_sex host_byte_sex;
4692    enum bool swapped;
4693    uint32_t i, j, section_type;
4694    uint64_t sect_offset, object_offset;
4695    const struct load_command *lc;
4696    struct load_command l;
4697    struct segment_command_64 sg64;
4698    struct section_64 s64;
4699    char *p;
4700    uint64_t big_load_end;
4701    const char *name;
4702
4703	host_byte_sex = get_host_byte_sex();
4704	swapped = host_byte_sex != load_commands_byte_sex;
4705
4706	lc = load_commands;
4707	big_load_end = 0;
4708	for(i = 0 ; i < ncmds; i++){
4709	    memcpy((char *)&l, (char *)lc, sizeof(struct load_command));
4710	    if(swapped)
4711		swap_load_command(&l, host_byte_sex);
4712	    if(l.cmdsize % sizeof(int32_t) != 0)
4713		return(NULL);
4714	    big_load_end += l.cmdsize;
4715	    if(big_load_end > sizeofcmds)
4716		return(NULL);
4717	    switch(l.cmd){
4718	    case LC_SEGMENT_64:
4719		memcpy((char *)&sg64, (char *)lc,
4720		       sizeof(struct segment_command_64));
4721		if(swapped)
4722		    swap_segment_command_64(&sg64, host_byte_sex);
4723		p = (char *)lc + sizeof(struct segment_command_64);
4724		for(j = 0 ; j < sg64.nsects ; j++){
4725		    memcpy((char *)&s64, p, sizeof(struct section_64));
4726		    p += sizeof(struct section_64);
4727		    if(swapped)
4728			swap_section_64(&s64, 1, host_byte_sex);
4729		    section_type = s64.flags & SECTION_TYPE;
4730		    if(section_type == S_CSTRING_LITERALS &&
4731		       value >= s64.addr && value < s64.addr + s64.size){
4732			sect_offset = value - s64.addr;
4733			object_offset = s64.offset + sect_offset;
4734			if(object_offset < object_size){
4735			    name = object_addr + object_offset;
4736			    return(name);
4737			}
4738			else
4739			    return(NULL);
4740		    }
4741		}
4742		break;
4743	    }
4744	    if(l.cmdsize == 0){
4745		return(NULL);
4746	    }
4747	    lc = (struct load_command *)((char *)lc + l.cmdsize);
4748	    if((char *)lc > (char *)load_commands + sizeofcmds)
4749		return(NULL);
4750	}
4751	return(NULL);
4752}
4753
4754/*
4755 * guess_literal_pointer() returns a pointer to a literal string if the value
4756 * passed in is the address of a literal pointer and the literal pointer's value
4757 * is and address of a cstring.
4758 */
4759static
4760const char *
4761guess_literal_pointer(
4762uint64_t value,	  	  /* the value of the reference */
4763const uint64_t pc,	  /* pc of the referencing instruction */
4764uint64_t *reference_type, /* type returned, symbol name or string literal*/
4765struct disassemble_info *info)
4766{
4767    uint32_t reloc_found, sect_offset, i, nrelocs, ncmds, sizeofcmds;
4768    struct relocation_info *relocs;
4769    struct nlist_64 *symbols;
4770    struct load_command *load_commands;
4771    enum byte_sex object_byte_sex;
4772    char *object_addr;
4773    uint64_t object_size;
4774    const char *name;
4775
4776	/*
4777	 * First see if there is a relocation entry.
4778	 */
4779	sect_offset = pc - info->sect_addr;
4780	relocs = info->sorted_relocs;
4781	nrelocs = info->nsorted_relocs;
4782	symbols = info->symbols64;
4783
4784	reloc_found = 0;
4785	for(i = 0; i < nrelocs; i++){
4786	    if(relocs[i].r_address == sect_offset){
4787		reloc_found = 1;
4788		break;
4789	    }
4790	}
4791
4792	/*
4793	 * If there is an external relocation entry for a symbol in a section
4794	 * then used that symbol's value for the value of the reference.
4795	 */
4796	if(reloc_found && relocs[i].r_extern == 1){
4797	    if(relocs[i].r_pcrel == 1 &&
4798	       relocs[i].r_type == X86_64_RELOC_SIGNED &&
4799	       relocs[i].r_symbolnum < info->nsymbols &&
4800	       symbols != NULL &&
4801	       (symbols[relocs[i].r_symbolnum].n_type & N_TYPE) == N_SECT){
4802		value = symbols[relocs[i].r_symbolnum].n_value;
4803	    }
4804	}
4805
4806	ncmds = info->ncmds;
4807	sizeofcmds = info->sizeofcmds;
4808	load_commands = info->load_commands;
4809	object_byte_sex = info->object_byte_sex;
4810	object_addr = info->object_addr;
4811	object_size = info->object_size;
4812
4813	/*
4814	 * See if the value is pointing to a cstring.
4815	 */
4816	name = guess_cstring_pointer(value, ncmds, sizeofcmds, load_commands,
4817				     object_byte_sex, object_addr, object_size);
4818	if(name != NULL){
4819	    *reference_type =
4820	        LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr;
4821	    return(name);
4822	}
4823
4824	return(NULL);
4825}
4826
4827/*
4828 * The symbol lookup function passed to LLVMCreateDisasm().  It looks up the
4829 * SymbolValue using the info passed vis the pointer to the struct
4830 * disassemble_info that was passed when disassembler context is created and
4831 * returns the symbol name that matches or NULL if none.
4832 *
4833 * When this is called to get a symbol name for a branch target then the
4834 * ReferenceType can be LLVMDisassembler_ReferenceType_In_Branch and then
4835 * SymbolValue will be looked for in the indirect symbol table to determine if
4836 * it is an address for a symbol stub.  If so then the symbol name for that
4837 * stub is returned indirectly through ReferenceName and then ReferenceType is
4838 * set to LLVMDisassembler_ReferenceType_Out_SymbolStub.
4839 */
4840static
4841const char *
4842SymbolLookUp(
4843void *DisInfo,
4844uint64_t SymbolValue,
4845uint64_t *ReferenceType,
4846uint64_t ReferencePC,
4847const char **ReferenceName)
4848{
4849    struct disassemble_info *info;
4850    const char *SymbolName;
4851    uint32_t i;
4852
4853	info = (struct disassemble_info *)DisInfo;
4854	if(info->verbose == FALSE){
4855	    *ReferenceName = NULL;
4856	    *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
4857	    return(NULL);
4858	}
4859	SymbolName = guess_symbol(SymbolValue, info->sorted_symbols,
4860				  info->nsorted_symbols, TRUE);
4861	if(SymbolName == NULL && info->insts != NULL && info->ninsts != 0){
4862	    for(i = 0; i < info->ninsts; i++){
4863		if(info->insts[i].address == SymbolValue){
4864		    SymbolName = info->insts[i].tmp_label;
4865		    break;
4866		}
4867	    }
4868	}
4869
4870	if(*ReferenceType == LLVMDisassembler_ReferenceType_In_Branch){
4871	    *ReferenceName = guess_indirect_symbol(SymbolValue,
4872		    info->ncmds, info->sizeofcmds, info->load_commands,
4873		    info->object_byte_sex, info->indirect_symbols,
4874		    info->nindirect_symbols, info->symbols, info->symbols64,
4875		    info->nsymbols, info->strings, info->strings_size);
4876	    if(*ReferenceName != NULL)
4877		*ReferenceType = LLVMDisassembler_ReferenceType_Out_SymbolStub;
4878	    else
4879		*ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
4880	    if(info->inst != NULL && SymbolName == NULL){
4881		info->inst->has_raw_target_address = TRUE;
4882		info->inst->raw_target_address = SymbolValue;
4883	    }
4884	}
4885	else if(*ReferenceType == LLVMDisassembler_ReferenceType_In_PCrel_Load){
4886	    *ReferenceName = guess_literal_pointer(SymbolValue, ReferencePC,
4887						   ReferenceType, info);
4888	    if(*ReferenceName == NULL)
4889		*ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
4890	}
4891	else{
4892	    *ReferenceName = NULL;
4893	    *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
4894	}
4895	return(SymbolName);
4896}
4897
4898LLVMDisasmContextRef
4899create_i386_llvm_disassembler(
4900void)
4901{
4902    LLVMDisasmContextRef dc;
4903
4904	dc = llvm_create_disasm("i386-apple-darwin10", mcpu, &dis_info, 1,
4905				i386GetOpInfo, SymbolLookUp);
4906	return(dc);
4907}
4908
4909void
4910delete_i386_llvm_disassembler(
4911LLVMDisasmContextRef dc)
4912{
4913	llvm_disasm_dispose(dc);
4914}
4915
4916LLVMDisasmContextRef
4917create_x86_64_llvm_disassembler(
4918void)
4919{
4920    LLVMDisasmContextRef dc;
4921
4922	dc = llvm_create_disasm("x86_64-apple-darwin10", mcpu, &dis_info, 1,
4923				x86_64GetOpInfo, SymbolLookUp);
4924	return(dc);
4925}
4926
4927void
4928delete_x86_64_llvm_disassembler(
4929LLVMDisasmContextRef dc)
4930{
4931	llvm_disasm_dispose(dc);
4932}
4933