1/* 2 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28/* 29 * @OSF_COPYRIGHT@ 30 */ 31/* 32 * Mach Operating System 33 * Copyright (c) 1991 Carnegie Mellon University 34 * All Rights Reserved. 35 * 36 * Permission to use, copy, modify and distribute this software and its 37 * documentation is hereby granted, provided that both the copyright 38 * notice and this permission notice appear in all copies of the 39 * software, derivative works or modified versions, and any portions 40 * thereof, and that both notices appear in supporting documentation. 41 * 42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 45 * 46 * Carnegie Mellon requests users of this software to return to 47 * 48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 49 * School of Computer Science 50 * Carnegie Mellon University 51 * Pittsburgh PA 15213-3890 52 * 53 * any improvements or extensions that they make and grant Carnegie Mellon 54 * the rights to redistribute these changes. 55 */ 56 57#ifndef _I386_FPU_H_ 58#define _I386_FPU_H_ 59 60/* 61 * Macro definitions for routines to manipulate the 62 * floating-point processor. 63 */ 64#include <kern/thread.h> 65#include <i386/thread.h> 66#include <kern/kern_types.h> 67#include <mach/i386/kern_return.h> 68#include <mach/i386/thread_status.h> 69#include <i386/proc_reg.h> 70 71extern int fp_kind; 72 73extern void init_fpu(void); 74extern void fpu_module_init(void); 75extern void fpu_free( 76 struct x86_fpsave_state * fps); 77extern kern_return_t fpu_set_fxstate( 78 thread_t thr_act, 79 thread_state_t state); 80extern kern_return_t fpu_get_fxstate( 81 thread_t thr_act, 82 thread_state_t state); 83extern void fpu_dup_fxstate( 84 thread_t parent, 85 thread_t child); 86extern void fpnoextflt(void); 87extern void fpextovrflt(void); 88extern void fpexterrflt(void); 89extern void fpSSEexterrflt(void); 90extern void fpflush(thread_t); 91extern void fp_setvalid(boolean_t); 92extern void fxsave64(struct x86_fx_save *); 93extern void fxrstor64(struct x86_fx_save *); 94 95/* 96 * FPU instructions. 97 */ 98#define fninit() \ 99 __asm__ volatile("fninit") 100 101#define fnstcw(control) \ 102 __asm__("fnstcw %0" : "=m" (*(unsigned short *)(control))) 103 104#define fldcw(control) \ 105 __asm__ volatile("fldcw %0" : : "m" (*(unsigned short *) &(control)) ) 106 107static inline unsigned short 108fnstsw(void) 109{ 110 unsigned short status; 111 __asm__ volatile("fnstsw %0" : "=ma" (status)); 112 return(status); 113} 114 115#define fnclex() \ 116 __asm__ volatile("fnclex") 117 118#define fnsave(state) \ 119 __asm__ volatile("fnsave %0" : "=m" (*state)) 120 121#define frstor(state) \ 122 __asm__ volatile("frstor %0" : : "m" (state)) 123 124#define fwait() \ 125 __asm__("fwait"); 126 127#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 128#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 129 130#define FXSAFE() (fp_kind == FP_FXSR) 131 132 133static inline void clear_fpu(void) 134{ 135 set_ts(); 136} 137 138/* 139 * Save thread`s FPU context. 140 */ 141 142static inline void fpu_save_context(thread_t thread) 143{ 144 struct x86_fpsave_state *ifps; 145 146 assert(ml_get_interrupts_enabled() == FALSE); 147 ifps = (thread)->machine.pcb->ifps; 148 if (ifps != 0 && !ifps->fp_valid) { 149 /* Clear CR0.TS in preparation for the FP context save. In 150 * theory, this shouldn't be necessary since a live FPU should 151 * indicate that TS is clear. However, various routines 152 * (such as sendsig & sigreturn) manipulate TS directly. 153 */ 154 clear_ts(); 155 /* registers are in FPU - save to memory */ 156 ifps->fp_valid = TRUE; 157 158 if (!thread_is_64bit(thread) || is_saved_state32(thread->machine.pcb->iss)) { 159 /* save the compatibility/legacy mode XMM+x87 state */ 160 fxsave(&ifps->fx_save_state); 161 ifps->fp_save_layout = FXSAVE32; 162 } 163 else { 164 /* Execute a brief jump to 64-bit mode to save the 64 165 * bit state 166 */ 167 fxsave64(&ifps->fx_save_state); 168 ifps->fp_save_layout = FXSAVE64; 169 } 170 } 171 set_ts(); 172} 173 174#endif /* _I386_FPU_H_ */ 175