1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of a target 11// register file for a code generator. It uses instances of the Register, 12// RegisterAliases, and RegisterClass classes to gather this information. 13// 14//===----------------------------------------------------------------------===// 15 16#include "CodeGenRegisters.h" 17#include "CodeGenTarget.h" 18#include "SequenceToOffsetTable.h" 19#include "llvm/ADT/BitVector.h" 20#include "llvm/ADT/STLExtras.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/ADT/Twine.h" 23#include "llvm/Support/Format.h" 24#include "llvm/TableGen/Error.h" 25#include "llvm/TableGen/Record.h" 26#include "llvm/TableGen/TableGenBackend.h" 27#include <algorithm> 28#include <set> 29#include <vector> 30using namespace llvm; 31 32namespace { 33class RegisterInfoEmitter { 34 RecordKeeper &Records; 35public: 36 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {} 37 38 // runEnums - Print out enum values for all of the registers. 39 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 40 41 // runMCDesc - Print out MC register descriptions. 42 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 43 44 // runTargetHeader - Emit a header fragment for the register info emitter. 45 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 46 CodeGenRegBank &Bank); 47 48 // runTargetDesc - Output the target register and register file descriptions. 49 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 50 CodeGenRegBank &Bank); 51 52 // run - Output the register file description. 53 void run(raw_ostream &o); 54 55private: 56 void EmitRegMapping(raw_ostream &o, 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor); 58 void EmitRegMappingTables(raw_ostream &o, 59 const std::vector<CodeGenRegister*> &Regs, 60 bool isCtor); 61 void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target); 62 63 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 64 const std::string &ClassName); 65 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 66 const std::string &ClassName); 67}; 68} // End anonymous namespace 69 70// runEnums - Print out enum values for all of the registers. 71void RegisterInfoEmitter::runEnums(raw_ostream &OS, 72 CodeGenTarget &Target, CodeGenRegBank &Bank) { 73 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); 74 75 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 76 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 77 78 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); 79 80 emitSourceFileHeader("Target Register Enum Values", OS); 81 82 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 83 OS << "#undef GET_REGINFO_ENUM\n"; 84 85 OS << "namespace llvm {\n\n"; 86 87 OS << "class MCRegisterClass;\n" 88 << "extern const MCRegisterClass " << Namespace 89 << "MCRegisterClasses[];\n\n"; 90 91 if (!Namespace.empty()) 92 OS << "namespace " << Namespace << " {\n"; 93 OS << "enum {\n NoRegister,\n"; 94 95 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 96 OS << " " << Registers[i]->getName() << " = " << 97 Registers[i]->EnumValue << ",\n"; 98 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && 99 "Register enum value mismatch!"); 100 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 101 OS << "};\n"; 102 if (!Namespace.empty()) 103 OS << "}\n"; 104 105 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses(); 106 if (!RegisterClasses.empty()) { 107 108 // RegisterClass enums are stored as uint16_t in the tables. 109 assert(RegisterClasses.size() <= 0xffff && 110 "Too many register classes to fit in tables"); 111 112 OS << "\n// Register classes\n"; 113 if (!Namespace.empty()) 114 OS << "namespace " << Namespace << " {\n"; 115 OS << "enum {\n"; 116 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 117 if (i) OS << ",\n"; 118 OS << " " << RegisterClasses[i]->getName() << "RegClassID"; 119 OS << " = " << i; 120 } 121 OS << "\n };\n"; 122 if (!Namespace.empty()) 123 OS << "}\n"; 124 } 125 126 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices(); 127 // If the only definition is the default NoRegAltName, we don't need to 128 // emit anything. 129 if (RegAltNameIndices.size() > 1) { 130 OS << "\n// Register alternate name indices\n"; 131 if (!Namespace.empty()) 132 OS << "namespace " << Namespace << " {\n"; 133 OS << "enum {\n"; 134 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 135 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 136 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 137 OS << "};\n"; 138 if (!Namespace.empty()) 139 OS << "}\n"; 140 } 141 142 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices(); 143 if (!SubRegIndices.empty()) { 144 OS << "\n// Subregister indices\n"; 145 std::string Namespace = 146 SubRegIndices[0]->getNamespace(); 147 if (!Namespace.empty()) 148 OS << "namespace " << Namespace << " {\n"; 149 OS << "enum {\n NoSubRegister,\n"; 150 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 151 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; 152 OS << " NUM_TARGET_SUBREGS\n};\n"; 153 if (!Namespace.empty()) 154 OS << "}\n"; 155 } 156 157 OS << "} // End llvm namespace \n"; 158 OS << "#endif // GET_REGINFO_ENUM\n\n"; 159} 160 161void RegisterInfoEmitter:: 162EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 163 const std::string &ClassName) { 164 unsigned NumRCs = RegBank.getRegClasses().size(); 165 unsigned NumSets = RegBank.getNumRegPressureSets(); 166 167 OS << "/// Get the weight in units of pressure for this register class.\n" 168 << "const RegClassWeight &" << ClassName << "::\n" 169 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 170 << " static const RegClassWeight RCWeightTable[] = {\n"; 171 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 172 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; 173 const CodeGenRegister::Set &Regs = RC.getMembers(); 174 if (Regs.empty()) 175 OS << " {0, 0"; 176 else { 177 std::vector<unsigned> RegUnits; 178 RC.buildRegUnitSet(RegUnits); 179 OS << " {" << (*Regs.begin())->getWeight(RegBank) 180 << ", " << RegBank.getRegUnitSetWeight(RegUnits); 181 } 182 OS << "}, \t// " << RC.getName() << "\n"; 183 } 184 OS << " {0, 0} };\n" 185 << " return RCWeightTable[RC->getID()];\n" 186 << "}\n\n"; 187 188 OS << "\n" 189 << "// Get the number of dimensions of register pressure.\n" 190 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 191 << " return " << NumSets << ";\n}\n\n"; 192 193 OS << "// Get the name of this register unit pressure set.\n" 194 << "const char *" << ClassName << "::\n" 195 << "getRegPressureSetName(unsigned Idx) const {\n" 196 << " static const char *PressureNameTable[] = {\n"; 197 for (unsigned i = 0; i < NumSets; ++i ) { 198 OS << " \"" << RegBank.getRegPressureSet(i).Name << "\",\n"; 199 } 200 OS << " 0 };\n" 201 << " return PressureNameTable[Idx];\n" 202 << "}\n\n"; 203 204 OS << "// Get the register unit pressure limit for this dimension.\n" 205 << "// This limit must be adjusted dynamically for reserved registers.\n" 206 << "unsigned " << ClassName << "::\n" 207 << "getRegPressureSetLimit(unsigned Idx) const {\n" 208 << " static const unsigned PressureLimitTable[] = {\n"; 209 for (unsigned i = 0; i < NumSets; ++i ) { 210 const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i); 211 OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units) 212 << ", \t// " << i << ": " << RegUnits.Name << "\n"; 213 } 214 OS << " 0 };\n" 215 << " return PressureLimitTable[Idx];\n" 216 << "}\n\n"; 217 218 OS << "/// Get the dimensions of register pressure " 219 << "impacted by this register class.\n" 220 << "/// Returns a -1 terminated array of pressure set IDs\n" 221 << "const int* " << ClassName << "::\n" 222 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n" 223 << " static const int RCSetsTable[] = {\n "; 224 std::vector<unsigned> RCSetStarts(NumRCs); 225 for (unsigned i = 0, StartIdx = 0, e = NumRCs; i != e; ++i) { 226 RCSetStarts[i] = StartIdx; 227 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 228 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 229 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 230 OS << *PSetI << ", "; 231 ++StartIdx; 232 } 233 OS << "-1, \t// " << RegBank.getRegClasses()[i]->getName() << "\n "; 234 ++StartIdx; 235 } 236 OS << "-1 };\n"; 237 OS << " static const unsigned RCSetStartTable[] = {\n "; 238 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 239 OS << RCSetStarts[i] << ","; 240 } 241 OS << "0 };\n" 242 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n" 243 << " return &RCSetsTable[SetListStart];\n" 244 << "}\n\n"; 245} 246 247void 248RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS, 249 const std::vector<CodeGenRegister*> &Regs, 250 bool isCtor) { 251 // Collect all information about dwarf register numbers 252 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 253 DwarfRegNumsMapTy DwarfRegNums; 254 255 // First, just pull all provided information to the map 256 unsigned maxLength = 0; 257 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 258 Record *Reg = Regs[i]->TheDef; 259 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 260 maxLength = std::max((size_t)maxLength, RegNums.size()); 261 if (DwarfRegNums.count(Reg)) 262 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 263 getQualifiedName(Reg) + "specified multiple times"); 264 DwarfRegNums[Reg] = RegNums; 265 } 266 267 if (!maxLength) 268 return; 269 270 // Now we know maximal length of number list. Append -1's, where needed 271 for (DwarfRegNumsMapTy::iterator 272 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 273 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 274 I->second.push_back(-1); 275 276 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 277 278 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 279 280 // Emit reverse information about the dwarf register numbers. 281 for (unsigned j = 0; j < 2; ++j) { 282 for (unsigned i = 0, e = maxLength; i != e; ++i) { 283 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 284 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 285 OS << i << "Dwarf2L[]"; 286 287 if (!isCtor) { 288 OS << " = {\n"; 289 290 // Store the mapping sorted by the LLVM reg num so lookup can be done 291 // with a binary search. 292 std::map<uint64_t, Record*> Dwarf2LMap; 293 for (DwarfRegNumsMapTy::iterator 294 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 295 int DwarfRegNo = I->second[i]; 296 if (DwarfRegNo < 0) 297 continue; 298 Dwarf2LMap[DwarfRegNo] = I->first; 299 } 300 301 for (std::map<uint64_t, Record*>::iterator 302 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 303 OS << " { " << I->first << "U, " << getQualifiedName(I->second) 304 << " },\n"; 305 306 OS << "};\n"; 307 } else { 308 OS << ";\n"; 309 } 310 311 // We have to store the size in a const global, it's used in multiple 312 // places. 313 OS << "extern const unsigned " << Namespace 314 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 315 if (!isCtor) 316 OS << " = sizeof(" << Namespace 317 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 318 << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n"; 319 else 320 OS << ";\n\n"; 321 } 322 } 323 324 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 325 Record *Reg = Regs[i]->TheDef; 326 const RecordVal *V = Reg->getValue("DwarfAlias"); 327 if (!V || !V->getValue()) 328 continue; 329 330 DefInit *DI = dynamic_cast<DefInit*>(V->getValue()); 331 Record *Alias = DI->getDef(); 332 DwarfRegNums[Reg] = DwarfRegNums[Alias]; 333 } 334 335 // Emit information about the dwarf register numbers. 336 for (unsigned j = 0; j < 2; ++j) { 337 for (unsigned i = 0, e = maxLength; i != e; ++i) { 338 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 339 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 340 OS << i << "L2Dwarf[]"; 341 if (!isCtor) { 342 OS << " = {\n"; 343 // Store the mapping sorted by the Dwarf reg num so lookup can be done 344 // with a binary search. 345 for (DwarfRegNumsMapTy::iterator 346 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 347 int RegNo = I->second[i]; 348 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 349 continue; 350 351 OS << " { " << getQualifiedName(I->first) << ", " << RegNo 352 << "U },\n"; 353 } 354 OS << "};\n"; 355 } else { 356 OS << ";\n"; 357 } 358 359 // We have to store the size in a const global, it's used in multiple 360 // places. 361 OS << "extern const unsigned " << Namespace 362 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 363 if (!isCtor) 364 OS << " = sizeof(" << Namespace 365 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 366 << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n"; 367 else 368 OS << ";\n\n"; 369 } 370 } 371} 372 373void 374RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS, 375 const std::vector<CodeGenRegister*> &Regs, 376 bool isCtor) { 377 // Emit the initializer so the tables from EmitRegMappingTables get wired up 378 // to the MCRegisterInfo object. 379 unsigned maxLength = 0; 380 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 381 Record *Reg = Regs[i]->TheDef; 382 maxLength = std::max((size_t)maxLength, 383 Reg->getValueAsListOfInts("DwarfNumbers").size()); 384 } 385 386 if (!maxLength) 387 return; 388 389 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 390 391 // Emit reverse information about the dwarf register numbers. 392 for (unsigned j = 0; j < 2; ++j) { 393 OS << " switch ("; 394 if (j == 0) 395 OS << "DwarfFlavour"; 396 else 397 OS << "EHFlavour"; 398 OS << ") {\n" 399 << " default:\n" 400 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 401 402 for (unsigned i = 0, e = maxLength; i != e; ++i) { 403 OS << " case " << i << ":\n"; 404 OS << " "; 405 if (!isCtor) 406 OS << "RI->"; 407 std::string Tmp; 408 raw_string_ostream(Tmp) << Namespace 409 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 410 << "Dwarf2L"; 411 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 412 if (j == 0) 413 OS << "false"; 414 else 415 OS << "true"; 416 OS << ");\n"; 417 OS << " break;\n"; 418 } 419 OS << " }\n"; 420 } 421 422 // Emit information about the dwarf register numbers. 423 for (unsigned j = 0; j < 2; ++j) { 424 OS << " switch ("; 425 if (j == 0) 426 OS << "DwarfFlavour"; 427 else 428 OS << "EHFlavour"; 429 OS << ") {\n" 430 << " default:\n" 431 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 432 433 for (unsigned i = 0, e = maxLength; i != e; ++i) { 434 OS << " case " << i << ":\n"; 435 OS << " "; 436 if (!isCtor) 437 OS << "RI->"; 438 std::string Tmp; 439 raw_string_ostream(Tmp) << Namespace 440 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 441 << "L2Dwarf"; 442 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 443 if (j == 0) 444 OS << "false"; 445 else 446 OS << "true"; 447 OS << ");\n"; 448 OS << " break;\n"; 449 } 450 OS << " }\n"; 451 } 452} 453 454// Print a BitVector as a sequence of hex numbers using a little-endian mapping. 455// Width is the number of bits per hex number. 456static void printBitVectorAsHex(raw_ostream &OS, 457 const BitVector &Bits, 458 unsigned Width) { 459 assert(Width <= 32 && "Width too large"); 460 unsigned Digits = (Width + 3) / 4; 461 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 462 unsigned Value = 0; 463 for (unsigned j = 0; j != Width && i + j != e; ++j) 464 Value |= Bits.test(i + j) << j; 465 OS << format("0x%0*x, ", Digits, Value); 466 } 467} 468 469// Helper to emit a set of bits into a constant byte array. 470class BitVectorEmitter { 471 BitVector Values; 472public: 473 void add(unsigned v) { 474 if (v >= Values.size()) 475 Values.resize(((v/8)+1)*8); // Round up to the next byte. 476 Values[v] = true; 477 } 478 479 void print(raw_ostream &OS) { 480 printBitVectorAsHex(OS, Values, 8); 481 } 482}; 483 484static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 485 OS << getEnumName(VT); 486} 487 488static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 489 OS << Idx->EnumValue; 490} 491 492// Differentially encoded register and regunit lists allow for better 493// compression on regular register banks. The sequence is computed from the 494// differential list as: 495// 496// out[0] = InitVal; 497// out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 498// 499// The initial value depends on the specific list. The list is terminated by a 500// 0 differential which means we can't encode repeated elements. 501 502typedef SmallVector<uint16_t, 4> DiffVec; 503 504// Differentially encode a sequence of numbers into V. The starting value and 505// terminating 0 are not added to V, so it will have the same size as List. 506static 507DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) { 508 assert(V.empty() && "Clear DiffVec before diffEncode."); 509 uint16_t Val = uint16_t(InitVal); 510 for (unsigned i = 0; i != List.size(); ++i) { 511 uint16_t Cur = List[i]; 512 V.push_back(Cur - Val); 513 Val = Cur; 514 } 515 return V; 516} 517 518template<typename Iter> 519static 520DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 521 assert(V.empty() && "Clear DiffVec before diffEncode."); 522 uint16_t Val = uint16_t(InitVal); 523 for (Iter I = Begin; I != End; ++I) { 524 uint16_t Cur = (*I)->EnumValue; 525 V.push_back(Cur - Val); 526 Val = Cur; 527 } 528 return V; 529} 530 531static void printDiff16(raw_ostream &OS, uint16_t Val) { 532 OS << Val; 533} 534 535// Try to combine Idx's compose map into Vec if it is compatible. 536// Return false if it's not possible. 537static bool combine(const CodeGenSubRegIndex *Idx, 538 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 539 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 540 for (CodeGenSubRegIndex::CompMap::const_iterator 541 I = Map.begin(), E = Map.end(); I != E; ++I) { 542 CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1]; 543 if (Entry && Entry != I->second) 544 return false; 545 } 546 547 // All entries are compatible. Make it so. 548 for (CodeGenSubRegIndex::CompMap::const_iterator 549 I = Map.begin(), E = Map.end(); I != E; ++I) 550 Vec[I->first->EnumValue - 1] = I->second; 551 return true; 552} 553 554static const char *getMinimalTypeForRange(uint64_t Range) { 555 assert(Range < 0xFFFFFFFFULL && "Enum too large"); 556 if (Range > 0xFFFF) 557 return "uint32_t"; 558 if (Range > 0xFF) 559 return "uint16_t"; 560 return "uint8_t"; 561} 562 563void 564RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 565 CodeGenRegBank &RegBank, 566 const std::string &ClName) { 567 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 568 OS << "unsigned " << ClName 569 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 570 571 // Many sub-register indexes are composition-compatible, meaning that 572 // 573 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 574 // 575 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 576 // The illegal entries can be use as wildcards to compress the table further. 577 578 // Map each Sub-register index to a compatible table row. 579 SmallVector<unsigned, 4> RowMap; 580 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 581 582 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 583 unsigned Found = ~0u; 584 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 585 if (combine(SubRegIndices[i], Rows[r])) { 586 Found = r; 587 break; 588 } 589 } 590 if (Found == ~0u) { 591 Found = Rows.size(); 592 Rows.resize(Found + 1); 593 Rows.back().resize(SubRegIndices.size()); 594 combine(SubRegIndices[i], Rows.back()); 595 } 596 RowMap.push_back(Found); 597 } 598 599 // Output the row map if there is multiple rows. 600 if (Rows.size() > 1) { 601 OS << " static const " << getMinimalTypeForRange(Rows.size()) 602 << " RowMap[" << SubRegIndices.size() << "] = {\n "; 603 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 604 OS << RowMap[i] << ", "; 605 OS << "\n };\n"; 606 } 607 608 // Output the rows. 609 OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1) 610 << " Rows[" << Rows.size() << "][" << SubRegIndices.size() << "] = {\n"; 611 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 612 OS << " { "; 613 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 614 if (Rows[r][i]) 615 OS << Rows[r][i]->EnumValue << ", "; 616 else 617 OS << "0, "; 618 OS << "},\n"; 619 } 620 OS << " };\n\n"; 621 622 OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n" 623 << " --IdxB; assert(IdxB < " << SubRegIndices.size() << ");\n"; 624 if (Rows.size() > 1) 625 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 626 else 627 OS << " return Rows[0][IdxB];\n"; 628 OS << "}\n\n"; 629} 630 631// 632// runMCDesc - Print out MC register descriptions. 633// 634void 635RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 636 CodeGenRegBank &RegBank) { 637 emitSourceFileHeader("MC Register Information", OS); 638 639 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 640 OS << "#undef GET_REGINFO_MC_DESC\n"; 641 642 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 643 644 // The lists of sub-registers, super-registers, and overlaps all go in the 645 // same array. That allows us to share suffixes. 646 typedef std::vector<const CodeGenRegister*> RegVec; 647 648 // Differentially encoded lists. 649 SequenceToOffsetTable<DiffVec> DiffSeqs; 650 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 651 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 652 SmallVector<DiffVec, 4> OverlapLists(Regs.size()); 653 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 654 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 655 656 // Keep track of sub-register names as well. These are not differentially 657 // encoded. 658 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 659 SequenceToOffsetTable<SubRegIdxVec> SubRegIdxSeqs; 660 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 661 662 SequenceToOffsetTable<std::string> RegStrings; 663 664 // Precompute register lists for the SequenceToOffsetTable. 665 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 666 const CodeGenRegister *Reg = Regs[i]; 667 668 RegStrings.add(Reg->getName()); 669 670 // Compute the ordered sub-register list. 671 SetVector<const CodeGenRegister*> SR; 672 Reg->addSubRegsPreOrder(SR, RegBank); 673 diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end()); 674 DiffSeqs.add(SubRegLists[i]); 675 676 // Compute the corresponding sub-register indexes. 677 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 678 for (unsigned j = 0, je = SR.size(); j != je; ++j) 679 SRIs.push_back(Reg->getSubRegIndex(SR[j])); 680 SubRegIdxSeqs.add(SRIs); 681 682 // Super-registers are already computed. 683 const RegVec &SuperRegList = Reg->getSuperRegs(); 684 diffEncode(SuperRegLists[i], Reg->EnumValue, 685 SuperRegList.begin(), SuperRegList.end()); 686 DiffSeqs.add(SuperRegLists[i]); 687 688 // The list of overlaps doesn't need to have any particular order, and Reg 689 // itself must be omitted. 690 DiffVec &OverlapList = OverlapLists[i]; 691 CodeGenRegister::Set OSet; 692 Reg->computeOverlaps(OSet, RegBank); 693 OSet.erase(Reg); 694 diffEncode(OverlapList, Reg->EnumValue, OSet.begin(), OSet.end()); 695 DiffSeqs.add(OverlapList); 696 697 // Differentially encode the register unit list, seeded by register number. 698 // First compute a scale factor that allows more diff-lists to be reused: 699 // 700 // D0 -> (S0, S1) 701 // D1 -> (S2, S3) 702 // 703 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 704 // value for the differential decoder is the register number multiplied by 705 // the scale. 706 // 707 // Check the neighboring registers for arithmetic progressions. 708 unsigned ScaleA = ~0u, ScaleB = ~0u; 709 ArrayRef<unsigned> RUs = Reg->getNativeRegUnits(); 710 if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size()) 711 ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front(); 712 if (i+1 != Regs.size() && 713 Regs[i+1]->getNativeRegUnits().size() == RUs.size()) 714 ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front(); 715 unsigned Scale = std::min(ScaleB, ScaleA); 716 // Default the scale to 0 if it can't be encoded in 4 bits. 717 if (Scale >= 16) 718 Scale = 0; 719 RegUnitInitScale[i] = Scale; 720 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs)); 721 } 722 723 // Compute the final layout of the sequence table. 724 DiffSeqs.layout(); 725 SubRegIdxSeqs.layout(); 726 727 OS << "namespace llvm {\n\n"; 728 729 const std::string &TargetName = Target.getName(); 730 731 // Emit the shared table of differential lists. 732 OS << "extern const uint16_t " << TargetName << "RegDiffLists[] = {\n"; 733 DiffSeqs.emit(OS, printDiff16); 734 OS << "};\n\n"; 735 736 // Emit the table of sub-register indexes. 737 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 738 SubRegIdxSeqs.emit(OS, printSubRegIndex); 739 OS << "};\n\n"; 740 741 // Emit the string table. 742 RegStrings.layout(); 743 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 744 RegStrings.emit(OS, printChar); 745 OS << "};\n\n"; 746 747 OS << "extern const MCRegisterDesc " << TargetName 748 << "RegDesc[] = { // Descriptors\n"; 749 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 750 751 // Emit the register descriptors now. 752 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 753 const CodeGenRegister *Reg = Regs[i]; 754 OS << " { " << RegStrings.get(Reg->getName()) << ", " 755 << DiffSeqs.get(OverlapLists[i]) << ", " 756 << DiffSeqs.get(SubRegLists[i]) << ", " 757 << DiffSeqs.get(SuperRegLists[i]) << ", " 758 << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 759 << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n"; 760 } 761 OS << "};\n\n"; // End of register descriptors... 762 763 // Emit the table of register unit roots. Each regunit has one or two root 764 // registers. 765 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n"; 766 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 767 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 768 assert(!Roots.empty() && "All regunits must have a root register."); 769 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 770 OS << " { " << getQualifiedName(Roots.front()->TheDef); 771 for (unsigned r = 1; r != Roots.size(); ++r) 772 OS << ", " << getQualifiedName(Roots[r]->TheDef); 773 OS << " },\n"; 774 } 775 OS << "};\n\n"; 776 777 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 778 779 // Loop over all of the register classes... emitting each one. 780 OS << "namespace { // Register classes...\n"; 781 782 // Emit the register enum value arrays for each RegisterClass 783 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 784 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 785 ArrayRef<Record*> Order = RC.getOrder(); 786 787 // Give the register class a legal C name if it's anonymous. 788 std::string Name = RC.getName(); 789 790 // Emit the register list now. 791 OS << " // " << Name << " Register Class...\n" 792 << " const uint16_t " << Name 793 << "[] = {\n "; 794 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 795 Record *Reg = Order[i]; 796 OS << getQualifiedName(Reg) << ", "; 797 } 798 OS << "\n };\n\n"; 799 800 OS << " // " << Name << " Bit set.\n" 801 << " const uint8_t " << Name 802 << "Bits[] = {\n "; 803 BitVectorEmitter BVE; 804 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 805 Record *Reg = Order[i]; 806 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 807 } 808 BVE.print(OS); 809 OS << "\n };\n\n"; 810 811 } 812 OS << "}\n\n"; 813 814 OS << "extern const MCRegisterClass " << TargetName 815 << "MCRegisterClasses[] = {\n"; 816 817 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 818 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 819 820 // Asserts to make sure values will fit in table assuming types from 821 // MCRegisterInfo.h 822 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); 823 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large."); 824 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large."); 825 826 OS << " { " << '\"' << RC.getName() << "\", " 827 << RC.getName() << ", " << RC.getName() << "Bits, " 828 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 829 << RC.getQualifiedName() + "RegClassID" << ", " 830 << RC.SpillSize/8 << ", " 831 << RC.SpillAlignment/8 << ", " 832 << RC.CopyCost << ", " 833 << RC.Allocatable << " },\n"; 834 } 835 836 OS << "};\n\n"; 837 838 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 839 840 EmitRegMappingTables(OS, Regs, false); 841 842 // Emit Reg encoding table 843 OS << "extern const uint16_t " << TargetName; 844 OS << "RegEncodingTable[] = {\n"; 845 // Add entry for NoRegister 846 OS << " 0,\n"; 847 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 848 Record *Reg = Regs[i]->TheDef; 849 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 850 uint64_t Value = 0; 851 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 852 if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(b))) 853 Value |= (uint64_t)B->getValue() << b; 854 } 855 OS << " " << Value << ",\n"; 856 } 857 OS << "};\n"; // End of HW encoding table 858 859 // MCRegisterInfo initialization routine. 860 OS << "static inline void Init" << TargetName 861 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 862 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n" 863 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 864 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, " 865 << RegisterClasses.size() << ", " 866 << TargetName << "RegUnitRoots, " 867 << RegBank.getNumNativeRegUnits() << ", " 868 << TargetName << "RegDiffLists, " 869 << TargetName << "RegStrings, " 870 << TargetName << "SubRegIdxLists, " 871 << (SubRegIndices.size() + 1) << ",\n" 872 << " " << TargetName << "RegEncodingTable);\n\n"; 873 874 EmitRegMapping(OS, Regs, false); 875 876 OS << "}\n\n"; 877 878 OS << "} // End llvm namespace \n"; 879 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 880} 881 882void 883RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 884 CodeGenRegBank &RegBank) { 885 emitSourceFileHeader("Register Information Header Fragment", OS); 886 887 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 888 OS << "#undef GET_REGINFO_HEADER\n"; 889 890 const std::string &TargetName = Target.getName(); 891 std::string ClassName = TargetName + "GenRegisterInfo"; 892 893 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n"; 894 895 OS << "namespace llvm {\n\n"; 896 897 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 898 << " explicit " << ClassName 899 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n" 900 << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 901 << " { return false; }\n"; 902 if (!RegBank.getSubRegIndices().empty()) { 903 OS << " virtual unsigned composeSubRegIndicesImpl" 904 << "(unsigned, unsigned) const;\n" 905 << " virtual const TargetRegisterClass *" 906 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"; 907 } 908 OS << " virtual const RegClassWeight &getRegClassWeight(" 909 << "const TargetRegisterClass *RC) const;\n" 910 << " virtual unsigned getNumRegPressureSets() const;\n" 911 << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n" 912 << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n" 913 << " virtual const int *getRegClassPressureSets(" 914 << "const TargetRegisterClass *RC) const;\n" 915 << "};\n\n"; 916 917 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 918 919 if (!RegisterClasses.empty()) { 920 OS << "namespace " << RegisterClasses[0]->Namespace 921 << " { // Register classes\n"; 922 923 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 924 const CodeGenRegisterClass &RC = *RegisterClasses[i]; 925 const std::string &Name = RC.getName(); 926 927 // Output the extern for the instance. 928 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 929 } 930 OS << "} // end of namespace " << TargetName << "\n\n"; 931 } 932 OS << "} // End llvm namespace \n"; 933 OS << "#endif // GET_REGINFO_HEADER\n\n"; 934} 935 936// 937// runTargetDesc - Output the target register and register file descriptions. 938// 939void 940RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 941 CodeGenRegBank &RegBank){ 942 emitSourceFileHeader("Target Register and Register Classes Information", OS); 943 944 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 945 OS << "#undef GET_REGINFO_TARGET_DESC\n"; 946 947 OS << "namespace llvm {\n\n"; 948 949 // Get access to MCRegisterClass data. 950 OS << "extern const MCRegisterClass " << Target.getName() 951 << "MCRegisterClasses[];\n"; 952 953 // Start out by emitting each of the register classes. 954 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 955 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 956 957 // Collect all registers belonging to any allocatable class. 958 std::set<Record*> AllocatableRegs; 959 960 // Collect allocatable registers. 961 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 962 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 963 ArrayRef<Record*> Order = RC.getOrder(); 964 965 if (RC.Allocatable) 966 AllocatableRegs.insert(Order.begin(), Order.end()); 967 } 968 969 // Build a shared array of value types. 970 SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs; 971 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) 972 VTSeqs.add(RegisterClasses[rc]->VTs); 973 VTSeqs.layout(); 974 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 975 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 976 OS << "};\n"; 977 978 // Emit SubRegIndex names, skipping 0. 979 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 980 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 981 OS << SubRegIndices[i]->getName(); 982 if (i + 1 != e) 983 OS << "\", \""; 984 } 985 OS << "\" };\n\n"; 986 987 // Emit SubRegIndex lane masks, including 0. 988 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; 989 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 990 OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask) 991 << SubRegIndices[i]->getName() << '\n'; 992 } 993 OS << " };\n\n"; 994 995 OS << "\n"; 996 997 // Now that all of the structs have been emitted, emit the instances. 998 if (!RegisterClasses.empty()) { 999 OS << "\nstatic const TargetRegisterClass *const " 1000 << "NullRegClasses[] = { NULL };\n\n"; 1001 1002 // Emit register class bit mask tables. The first bit mask emitted for a 1003 // register class, RC, is the set of sub-classes, including RC itself. 1004 // 1005 // If RC has super-registers, also create a list of subreg indices and bit 1006 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1007 // SuperRC, that satisfies: 1008 // 1009 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1010 // 1011 // The 0-terminated list of subreg indices starts at: 1012 // 1013 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1014 // 1015 // The corresponding bitmasks follow the sub-class mask in memory. Each 1016 // mask has RCMaskWords uint32_t entries. 1017 // 1018 // Every bit mask present in the list has at least one bit set. 1019 1020 // Compress the sub-reg index lists. 1021 typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1022 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1023 SequenceToOffsetTable<IdxList> SuperRegIdxSeqs; 1024 BitVector MaskBV(RegisterClasses.size()); 1025 1026 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1027 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1028 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; 1029 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1030 1031 // Emit super-reg class masks for any relevant SubRegIndices that can 1032 // project into RC. 1033 IdxList &SRIList = SuperRegIdxLists[rc]; 1034 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1035 CodeGenSubRegIndex *Idx = SubRegIndices[sri]; 1036 MaskBV.reset(); 1037 RC.getSuperRegClasses(Idx, MaskBV); 1038 if (MaskBV.none()) 1039 continue; 1040 SRIList.push_back(Idx); 1041 OS << "\n "; 1042 printBitVectorAsHex(OS, MaskBV, 32); 1043 OS << "// " << Idx->getName(); 1044 } 1045 SuperRegIdxSeqs.add(SRIList); 1046 OS << "\n};\n\n"; 1047 } 1048 1049 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1050 SuperRegIdxSeqs.layout(); 1051 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1052 OS << "};\n\n"; 1053 1054 // Emit NULL terminated super-class lists. 1055 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1056 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1057 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1058 1059 // Skip classes without supers. We can reuse NullRegClasses. 1060 if (Supers.empty()) 1061 continue; 1062 1063 OS << "static const TargetRegisterClass *const " 1064 << RC.getName() << "Superclasses[] = {\n"; 1065 for (unsigned i = 0; i != Supers.size(); ++i) 1066 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; 1067 OS << " NULL\n};\n\n"; 1068 } 1069 1070 // Emit methods. 1071 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 1072 const CodeGenRegisterClass &RC = *RegisterClasses[i]; 1073 if (!RC.AltOrderSelect.empty()) { 1074 OS << "\nstatic inline unsigned " << RC.getName() 1075 << "AltOrderSelect(const MachineFunction &MF) {" 1076 << RC.AltOrderSelect << "}\n\n" 1077 << "static ArrayRef<uint16_t> " << RC.getName() 1078 << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1079 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1080 ArrayRef<Record*> Elems = RC.getOrder(oi); 1081 if (!Elems.empty()) { 1082 OS << " static const uint16_t AltOrder" << oi << "[] = {"; 1083 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1084 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1085 OS << " };\n"; 1086 } 1087 } 1088 OS << " const MCRegisterClass &MCR = " << Target.getName() 1089 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1090 << " const ArrayRef<uint16_t> Order[] = {\n" 1091 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1092 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1093 if (RC.getOrder(oi).empty()) 1094 OS << "),\n ArrayRef<uint16_t>("; 1095 else 1096 OS << "),\n makeArrayRef(AltOrder" << oi; 1097 OS << ")\n };\n const unsigned Select = " << RC.getName() 1098 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1099 << ");\n return Order[Select];\n}\n"; 1100 } 1101 } 1102 1103 // Now emit the actual value-initialized register class instances. 1104 OS << "namespace " << RegisterClasses[0]->Namespace 1105 << " { // Register class instances\n"; 1106 1107 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 1108 const CodeGenRegisterClass &RC = *RegisterClasses[i]; 1109 OS << " extern const TargetRegisterClass " 1110 << RegisterClasses[i]->getName() << "RegClass = {\n " 1111 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName() 1112 << "RegClassID],\n " 1113 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " 1114 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1115 << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n "; 1116 if (RC.getSuperClasses().empty()) 1117 OS << "NullRegClasses,\n "; 1118 else 1119 OS << RC.getName() << "Superclasses,\n "; 1120 if (RC.AltOrderSelect.empty()) 1121 OS << "0\n"; 1122 else 1123 OS << RC.getName() << "GetRawAllocationOrder\n"; 1124 OS << " };\n\n"; 1125 } 1126 1127 OS << "}\n"; 1128 } 1129 1130 OS << "\nnamespace {\n"; 1131 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1132 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 1133 OS << " &" << RegisterClasses[i]->getQualifiedName() 1134 << "RegClass,\n"; 1135 OS << " };\n"; 1136 OS << "}\n"; // End of anonymous namespace... 1137 1138 // Emit extra information about registers. 1139 const std::string &TargetName = Target.getName(); 1140 OS << "\nstatic const TargetRegisterInfoDesc " 1141 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1142 OS << " { 0, 0 },\n"; 1143 1144 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 1145 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 1146 const CodeGenRegister &Reg = *Regs[i]; 1147 OS << " { "; 1148 OS << Reg.CostPerUse << ", " 1149 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; 1150 } 1151 OS << "};\n"; // End of register descriptors... 1152 1153 1154 std::string ClassName = Target.getName() + "GenRegisterInfo"; 1155 1156 if (!SubRegIndices.empty()) 1157 emitComposeSubRegIndices(OS, RegBank, ClassName); 1158 1159 // Emit getSubClassWithSubReg. 1160 if (!SubRegIndices.empty()) { 1161 OS << "const TargetRegisterClass *" << ClassName 1162 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1163 << " const {\n"; 1164 // Use the smallest type that can hold a regclass ID with room for a 1165 // sentinel. 1166 if (RegisterClasses.size() < UINT8_MAX) 1167 OS << " static const uint8_t Table["; 1168 else if (RegisterClasses.size() < UINT16_MAX) 1169 OS << " static const uint16_t Table["; 1170 else 1171 throw "Too many register classes."; 1172 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n"; 1173 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) { 1174 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; 1175 OS << " {\t// " << RC.getName() << "\n"; 1176 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1177 CodeGenSubRegIndex *Idx = SubRegIndices[sri]; 1178 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx)) 1179 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName() 1180 << " -> " << SRC->getName() << "\n"; 1181 else 1182 OS << " 0,\t// " << Idx->getName() << "\n"; 1183 } 1184 OS << " },\n"; 1185 } 1186 OS << " };\n assert(RC && \"Missing regclass\");\n" 1187 << " if (!Idx) return RC;\n --Idx;\n" 1188 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n" 1189 << " unsigned TV = Table[RC->getID()][Idx];\n" 1190 << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n"; 1191 } 1192 1193 EmitRegUnitPressure(OS, RegBank, ClassName); 1194 1195 // Emit the constructor of the class... 1196 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1197 OS << "extern const uint16_t " << TargetName << "RegDiffLists[];\n"; 1198 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1199 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n"; 1200 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1201 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1202 1203 EmitRegMappingTables(OS, Regs, true); 1204 1205 OS << ClassName << "::\n" << ClassName 1206 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n" 1207 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1208 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" 1209 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable) {\n" 1210 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " 1211 << Regs.size()+1 << ", RA,\n " << TargetName 1212 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1213 << " " << TargetName << "RegUnitRoots,\n" 1214 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1215 << " " << TargetName << "RegDiffLists,\n" 1216 << " " << TargetName << "RegStrings,\n" 1217 << " " << TargetName << "SubRegIdxLists,\n" 1218 << " " << SubRegIndices.size() + 1 << ",\n" 1219 << " " << TargetName << "RegEncodingTable);\n\n"; 1220 1221 EmitRegMapping(OS, Regs, true); 1222 1223 OS << "}\n\n"; 1224 1225 1226 // Emit CalleeSavedRegs information. 1227 std::vector<Record*> CSRSets = 1228 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1229 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1230 Record *CSRSet = CSRSets[i]; 1231 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1232 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1233 1234 // Emit the *_SaveList list of callee-saved registers. 1235 OS << "static const uint16_t " << CSRSet->getName() 1236 << "_SaveList[] = { "; 1237 for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1238 OS << getQualifiedName((*Regs)[r]) << ", "; 1239 OS << "0 };\n"; 1240 1241 // Emit the *_RegMask bit mask of call-preserved registers. 1242 OS << "static const uint32_t " << CSRSet->getName() 1243 << "_RegMask[] = { "; 1244 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32); 1245 OS << "};\n"; 1246 } 1247 OS << "\n\n"; 1248 1249 OS << "} // End llvm namespace \n"; 1250 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1251} 1252 1253void RegisterInfoEmitter::run(raw_ostream &OS) { 1254 CodeGenTarget Target(Records); 1255 CodeGenRegBank &RegBank = Target.getRegBank(); 1256 RegBank.computeDerivedInfo(); 1257 1258 runEnums(OS, Target, RegBank); 1259 runMCDesc(OS, Target, RegBank); 1260 runTargetHeader(OS, Target, RegBank); 1261 runTargetDesc(OS, Target, RegBank); 1262} 1263 1264namespace llvm { 1265 1266void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1267 RegisterInfoEmitter(RK).run(OS); 1268} 1269 1270} // End llvm namespace 1271