1//===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines structures to encapsulate information gleaned from the 11// target register and register class definitions. 12// 13//===----------------------------------------------------------------------===// 14 15#include "CodeGenRegisters.h" 16#include "CodeGenTarget.h" 17#include "llvm/TableGen/Error.h" 18#include "llvm/ADT/IntEqClasses.h" 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/ADT/STLExtras.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/ADT/Twine.h" 23 24using namespace llvm; 25 26//===----------------------------------------------------------------------===// 27// CodeGenSubRegIndex 28//===----------------------------------------------------------------------===// 29 30CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum) 31 : TheDef(R), EnumValue(Enum), LaneMask(0) { 32 Name = R->getName(); 33 if (R->getValue("Namespace")) 34 Namespace = R->getValueAsString("Namespace"); 35} 36 37CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace, 38 unsigned Enum) 39 : TheDef(0), Name(N), Namespace(Nspace), EnumValue(Enum), LaneMask(0) { 40} 41 42std::string CodeGenSubRegIndex::getQualifiedName() const { 43 std::string N = getNamespace(); 44 if (!N.empty()) 45 N += "::"; 46 N += getName(); 47 return N; 48} 49 50void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { 51 if (!TheDef) 52 return; 53 54 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf"); 55 if (!Comps.empty()) { 56 if (Comps.size() != 2) 57 throw TGError(TheDef->getLoc(), "ComposedOf must have exactly two entries"); 58 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]); 59 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]); 60 CodeGenSubRegIndex *X = A->addComposite(B, this); 61 if (X) 62 throw TGError(TheDef->getLoc(), "Ambiguous ComposedOf entries"); 63 } 64 65 std::vector<Record*> Parts = 66 TheDef->getValueAsListOfDefs("CoveringSubRegIndices"); 67 if (!Parts.empty()) { 68 if (Parts.size() < 2) 69 throw TGError(TheDef->getLoc(), 70 "CoveredBySubRegs must have two or more entries"); 71 SmallVector<CodeGenSubRegIndex*, 8> IdxParts; 72 for (unsigned i = 0, e = Parts.size(); i != e; ++i) 73 IdxParts.push_back(RegBank.getSubRegIdx(Parts[i])); 74 RegBank.addConcatSubRegIndex(IdxParts, this); 75 } 76} 77 78unsigned CodeGenSubRegIndex::computeLaneMask() { 79 // Already computed? 80 if (LaneMask) 81 return LaneMask; 82 83 // Recursion guard, shouldn't be required. 84 LaneMask = ~0u; 85 86 // The lane mask is simply the union of all sub-indices. 87 unsigned M = 0; 88 for (CompMap::iterator I = Composed.begin(), E = Composed.end(); I != E; ++I) 89 M |= I->second->computeLaneMask(); 90 assert(M && "Missing lane mask, sub-register cycle?"); 91 LaneMask = M; 92 return LaneMask; 93} 94 95//===----------------------------------------------------------------------===// 96// CodeGenRegister 97//===----------------------------------------------------------------------===// 98 99CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum) 100 : TheDef(R), 101 EnumValue(Enum), 102 CostPerUse(R->getValueAsInt("CostPerUse")), 103 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")), 104 NumNativeRegUnits(0), 105 SubRegsComplete(false), 106 SuperRegsComplete(false), 107 TopoSig(~0u) 108{} 109 110void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { 111 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices"); 112 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs"); 113 114 if (SRIs.size() != SRs.size()) 115 throw TGError(TheDef->getLoc(), 116 "SubRegs and SubRegIndices must have the same size"); 117 118 for (unsigned i = 0, e = SRIs.size(); i != e; ++i) { 119 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i])); 120 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i])); 121 } 122 123 // Also compute leading super-registers. Each register has a list of 124 // covered-by-subregs super-registers where it appears as the first explicit 125 // sub-register. 126 // 127 // This is used by computeSecondarySubRegs() to find candidates. 128 if (CoveredBySubRegs && !ExplicitSubRegs.empty()) 129 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this); 130 131 // Add ad hoc alias links. This is a symmetric relationship between two 132 // registers, so build a symmetric graph by adding links in both ends. 133 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases"); 134 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { 135 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]); 136 ExplicitAliases.push_back(Reg); 137 Reg->ExplicitAliases.push_back(this); 138 } 139} 140 141const std::string &CodeGenRegister::getName() const { 142 return TheDef->getName(); 143} 144 145namespace { 146// Iterate over all register units in a set of registers. 147class RegUnitIterator { 148 CodeGenRegister::Set::const_iterator RegI, RegE; 149 CodeGenRegister::RegUnitList::const_iterator UnitI, UnitE; 150 151public: 152 RegUnitIterator(const CodeGenRegister::Set &Regs): 153 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { 154 155 if (RegI != RegE) { 156 UnitI = (*RegI)->getRegUnits().begin(); 157 UnitE = (*RegI)->getRegUnits().end(); 158 advance(); 159 } 160 } 161 162 bool isValid() const { return UnitI != UnitE; } 163 164 unsigned operator* () const { assert(isValid()); return *UnitI; } 165 166 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; } 167 168 /// Preincrement. Move to the next unit. 169 void operator++() { 170 assert(isValid() && "Cannot advance beyond the last operand"); 171 ++UnitI; 172 advance(); 173 } 174 175protected: 176 void advance() { 177 while (UnitI == UnitE) { 178 if (++RegI == RegE) 179 break; 180 UnitI = (*RegI)->getRegUnits().begin(); 181 UnitE = (*RegI)->getRegUnits().end(); 182 } 183 } 184}; 185} // namespace 186 187// Merge two RegUnitLists maintaining the order and removing duplicates. 188// Overwrites MergedRU in the process. 189static void mergeRegUnits(CodeGenRegister::RegUnitList &MergedRU, 190 const CodeGenRegister::RegUnitList &RRU) { 191 CodeGenRegister::RegUnitList LRU = MergedRU; 192 MergedRU.clear(); 193 std::set_union(LRU.begin(), LRU.end(), RRU.begin(), RRU.end(), 194 std::back_inserter(MergedRU)); 195} 196 197// Return true of this unit appears in RegUnits. 198static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) { 199 return std::count(RegUnits.begin(), RegUnits.end(), Unit); 200} 201 202// Inherit register units from subregisters. 203// Return true if the RegUnits changed. 204bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { 205 unsigned OldNumUnits = RegUnits.size(); 206 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); 207 I != E; ++I) { 208 CodeGenRegister *SR = I->second; 209 // Merge the subregister's units into this register's RegUnits. 210 mergeRegUnits(RegUnits, SR->RegUnits); 211 } 212 return OldNumUnits != RegUnits.size(); 213} 214 215const CodeGenRegister::SubRegMap & 216CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) { 217 // Only compute this map once. 218 if (SubRegsComplete) 219 return SubRegs; 220 SubRegsComplete = true; 221 222 // First insert the explicit subregs and make sure they are fully indexed. 223 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 224 CodeGenRegister *SR = ExplicitSubRegs[i]; 225 CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i]; 226 if (!SubRegs.insert(std::make_pair(Idx, SR)).second) 227 throw TGError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() + 228 " appears twice in Register " + getName()); 229 // Map explicit sub-registers first, so the names take precedence. 230 // The inherited sub-registers are mapped below. 231 SubReg2Idx.insert(std::make_pair(SR, Idx)); 232 } 233 234 // Keep track of inherited subregs and how they can be reached. 235 SmallPtrSet<CodeGenRegister*, 8> Orphans; 236 237 // Clone inherited subregs and place duplicate entries in Orphans. 238 // Here the order is important - earlier subregs take precedence. 239 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 240 CodeGenRegister *SR = ExplicitSubRegs[i]; 241 const SubRegMap &Map = SR->computeSubRegs(RegBank); 242 243 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE; 244 ++SI) { 245 if (!SubRegs.insert(*SI).second) 246 Orphans.insert(SI->second); 247 } 248 } 249 250 // Expand any composed subreg indices. 251 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a 252 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process 253 // expanded subreg indices recursively. 254 SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices; 255 for (unsigned i = 0; i != Indices.size(); ++i) { 256 CodeGenSubRegIndex *Idx = Indices[i]; 257 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites(); 258 CodeGenRegister *SR = SubRegs[Idx]; 259 const SubRegMap &Map = SR->computeSubRegs(RegBank); 260 261 // Look at the possible compositions of Idx. 262 // They may not all be supported by SR. 263 for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(), 264 E = Comps.end(); I != E; ++I) { 265 SubRegMap::const_iterator SRI = Map.find(I->first); 266 if (SRI == Map.end()) 267 continue; // Idx + I->first doesn't exist in SR. 268 // Add I->second as a name for the subreg SRI->second, assuming it is 269 // orphaned, and the name isn't already used for something else. 270 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) 271 continue; 272 // We found a new name for the orphaned sub-register. 273 SubRegs.insert(std::make_pair(I->second, SRI->second)); 274 Indices.push_back(I->second); 275 } 276 } 277 278 // Now Orphans contains the inherited subregisters without a direct index. 279 // Create inferred indexes for all missing entries. 280 // Work backwards in the Indices vector in order to compose subregs bottom-up. 281 // Consider this subreg sequence: 282 // 283 // qsub_1 -> dsub_0 -> ssub_0 284 // 285 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register 286 // can be reached in two different ways: 287 // 288 // qsub_1 -> ssub_0 289 // dsub_2 -> ssub_0 290 // 291 // We pick the latter composition because another register may have [dsub_0, 292 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The 293 // dsub_2 -> ssub_0 composition can be shared. 294 while (!Indices.empty() && !Orphans.empty()) { 295 CodeGenSubRegIndex *Idx = Indices.pop_back_val(); 296 CodeGenRegister *SR = SubRegs[Idx]; 297 const SubRegMap &Map = SR->computeSubRegs(RegBank); 298 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE; 299 ++SI) 300 if (Orphans.erase(SI->second)) 301 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second; 302 } 303 304 // Compute the inverse SubReg -> Idx map. 305 for (SubRegMap::const_iterator SI = SubRegs.begin(), SE = SubRegs.end(); 306 SI != SE; ++SI) { 307 if (SI->second == this) { 308 ArrayRef<SMLoc> Loc; 309 if (TheDef) 310 Loc = TheDef->getLoc(); 311 throw TGError(Loc, "Register " + getName() + 312 " has itself as a sub-register"); 313 } 314 // Ensure that every sub-register has a unique name. 315 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins = 316 SubReg2Idx.insert(std::make_pair(SI->second, SI->first)).first; 317 if (Ins->second == SI->first) 318 continue; 319 // Trouble: Two different names for SI->second. 320 ArrayRef<SMLoc> Loc; 321 if (TheDef) 322 Loc = TheDef->getLoc(); 323 throw TGError(Loc, "Sub-register can't have two names: " + 324 SI->second->getName() + " available as " + 325 SI->first->getName() + " and " + Ins->second->getName()); 326 } 327 328 // Derive possible names for sub-register concatenations from any explicit 329 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure 330 // that getConcatSubRegIndex() won't invent any concatenated indices that the 331 // user already specified. 332 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 333 CodeGenRegister *SR = ExplicitSubRegs[i]; 334 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1) 335 continue; 336 337 // SR is composed of multiple sub-regs. Find their names in this register. 338 SmallVector<CodeGenSubRegIndex*, 8> Parts; 339 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) 340 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j])); 341 342 // Offer this as an existing spelling for the concatenation of Parts. 343 RegBank.addConcatSubRegIndex(Parts, ExplicitSubRegIndices[i]); 344 } 345 346 // Initialize RegUnitList. Because getSubRegs is called recursively, this 347 // processes the register hierarchy in postorder. 348 // 349 // Inherit all sub-register units. It is good enough to look at the explicit 350 // sub-registers, the other registers won't contribute any more units. 351 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 352 CodeGenRegister *SR = ExplicitSubRegs[i]; 353 // Explicit sub-registers are usually disjoint, so this is a good way of 354 // computing the union. We may pick up a few duplicates that will be 355 // eliminated below. 356 unsigned N = RegUnits.size(); 357 RegUnits.append(SR->RegUnits.begin(), SR->RegUnits.end()); 358 std::inplace_merge(RegUnits.begin(), RegUnits.begin() + N, RegUnits.end()); 359 } 360 RegUnits.erase(std::unique(RegUnits.begin(), RegUnits.end()), RegUnits.end()); 361 362 // Absent any ad hoc aliasing, we create one register unit per leaf register. 363 // These units correspond to the maximal cliques in the register overlap 364 // graph which is optimal. 365 // 366 // When there is ad hoc aliasing, we simply create one unit per edge in the 367 // undirected ad hoc aliasing graph. Technically, we could do better by 368 // identifying maximal cliques in the ad hoc graph, but cliques larger than 2 369 // are extremely rare anyway (I've never seen one), so we don't bother with 370 // the added complexity. 371 for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) { 372 CodeGenRegister *AR = ExplicitAliases[i]; 373 // Only visit each edge once. 374 if (AR->SubRegsComplete) 375 continue; 376 // Create a RegUnit representing this alias edge, and add it to both 377 // registers. 378 unsigned Unit = RegBank.newRegUnit(this, AR); 379 RegUnits.push_back(Unit); 380 AR->RegUnits.push_back(Unit); 381 } 382 383 // Finally, create units for leaf registers without ad hoc aliases. Note that 384 // a leaf register with ad hoc aliases doesn't get its own unit - it isn't 385 // necessary. This means the aliasing leaf registers can share a single unit. 386 if (RegUnits.empty()) 387 RegUnits.push_back(RegBank.newRegUnit(this)); 388 389 // We have now computed the native register units. More may be adopted later 390 // for balancing purposes. 391 NumNativeRegUnits = RegUnits.size(); 392 393 return SubRegs; 394} 395 396// In a register that is covered by its sub-registers, try to find redundant 397// sub-registers. For example: 398// 399// QQ0 = {Q0, Q1} 400// Q0 = {D0, D1} 401// Q1 = {D2, D3} 402// 403// We can infer that D1_D2 is also a sub-register, even if it wasn't named in 404// the register definition. 405// 406// The explicitly specified registers form a tree. This function discovers 407// sub-register relationships that would force a DAG. 408// 409void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) { 410 // Collect new sub-registers first, add them later. 411 SmallVector<SubRegMap::value_type, 8> NewSubRegs; 412 413 // Look at the leading super-registers of each sub-register. Those are the 414 // candidates for new sub-registers, assuming they are fully contained in 415 // this register. 416 for (SubRegMap::iterator I = SubRegs.begin(), E = SubRegs.end(); I != E; ++I){ 417 const CodeGenRegister *SubReg = I->second; 418 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs; 419 for (unsigned i = 0, e = Leads.size(); i != e; ++i) { 420 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]); 421 // Already got this sub-register? 422 if (Cand == this || getSubRegIndex(Cand)) 423 continue; 424 // Check if each component of Cand is already a sub-register. 425 // We know that the first component is I->second, and is present with the 426 // name I->first. 427 SmallVector<CodeGenSubRegIndex*, 8> Parts(1, I->first); 428 assert(!Cand->ExplicitSubRegs.empty() && 429 "Super-register has no sub-registers"); 430 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) { 431 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j])) 432 Parts.push_back(Idx); 433 else { 434 // Sub-register doesn't exist. 435 Parts.clear(); 436 break; 437 } 438 } 439 // If some Cand sub-register is not part of this register, or if Cand only 440 // has one sub-register, there is nothing to do. 441 if (Parts.size() <= 1) 442 continue; 443 444 // Each part of Cand is a sub-register of this. Make the full Cand also 445 // a sub-register with a concatenated sub-register index. 446 CodeGenSubRegIndex *Concat= RegBank.getConcatSubRegIndex(Parts); 447 NewSubRegs.push_back(std::make_pair(Concat, Cand)); 448 } 449 } 450 451 // Now add all the new sub-registers. 452 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) { 453 // Don't add Cand if another sub-register is already using the index. 454 if (!SubRegs.insert(NewSubRegs[i]).second) 455 continue; 456 457 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first; 458 CodeGenRegister *NewSubReg = NewSubRegs[i].second; 459 SubReg2Idx.insert(std::make_pair(NewSubReg, NewIdx)); 460 } 461 462 // Create sub-register index composition maps for the synthesized indices. 463 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) { 464 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first; 465 CodeGenRegister *NewSubReg = NewSubRegs[i].second; 466 for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(), 467 SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) { 468 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); 469 if (!SubIdx) 470 throw TGError(TheDef->getLoc(), "No SubRegIndex for " + 471 SI->second->getName() + " in " + getName()); 472 NewIdx->addComposite(SI->first, SubIdx); 473 } 474 } 475} 476 477void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) { 478 // Only visit each register once. 479 if (SuperRegsComplete) 480 return; 481 SuperRegsComplete = true; 482 483 // Make sure all sub-registers have been visited first, so the super-reg 484 // lists will be topologically ordered. 485 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); 486 I != E; ++I) 487 I->second->computeSuperRegs(RegBank); 488 489 // Now add this as a super-register on all sub-registers. 490 // Also compute the TopoSigId in post-order. 491 TopoSigId Id; 492 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); 493 I != E; ++I) { 494 // Topological signature computed from SubIdx, TopoId(SubReg). 495 // Loops and idempotent indices have TopoSig = ~0u. 496 Id.push_back(I->first->EnumValue); 497 Id.push_back(I->second->TopoSig); 498 499 // Don't add duplicate entries. 500 if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this) 501 continue; 502 I->second->SuperRegs.push_back(this); 503 } 504 TopoSig = RegBank.getTopoSig(Id); 505} 506 507void 508CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet, 509 CodeGenRegBank &RegBank) const { 510 assert(SubRegsComplete && "Must precompute sub-registers"); 511 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 512 CodeGenRegister *SR = ExplicitSubRegs[i]; 513 if (OSet.insert(SR)) 514 SR->addSubRegsPreOrder(OSet, RegBank); 515 } 516 // Add any secondary sub-registers that weren't part of the explicit tree. 517 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); 518 I != E; ++I) 519 OSet.insert(I->second); 520} 521 522// Compute overlapping registers. 523// 524// The standard set is all super-registers and all sub-registers, but the 525// target description can add arbitrary overlapping registers via the 'Aliases' 526// field. This complicates things, but we can compute overlapping sets using 527// the following rules: 528// 529// 1. The relation overlap(A, B) is reflexive and symmetric but not transitive. 530// 531// 2. overlap(A, B) implies overlap(A, S) for all S in supers(B). 532// 533// Alternatively: 534// 535// overlap(A, B) iff there exists: 536// A' in { A, subregs(A) } and B' in { B, subregs(B) } such that: 537// A' = B' or A' in aliases(B') or B' in aliases(A'). 538// 539// Here subregs(A) is the full flattened sub-register set returned by 540// A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the 541// description of register A. 542// 543// This also implies that registers with a common sub-register are considered 544// overlapping. This can happen when forming register pairs: 545// 546// P0 = (R0, R1) 547// P1 = (R1, R2) 548// P2 = (R2, R3) 549// 550// In this case, we will infer an overlap between P0 and P1 because of the 551// shared sub-register R1. There is no overlap between P0 and P2. 552// 553void CodeGenRegister::computeOverlaps(CodeGenRegister::Set &Overlaps, 554 const CodeGenRegBank &RegBank) const { 555 assert(!RegUnits.empty() && "Compute register units before overlaps."); 556 557 // Register units are assigned such that the overlapping registers are the 558 // super-registers of the root registers of the register units. 559 for (unsigned rui = 0, rue = RegUnits.size(); rui != rue; ++rui) { 560 const RegUnit &RU = RegBank.getRegUnit(RegUnits[rui]); 561 ArrayRef<const CodeGenRegister*> Roots = RU.getRoots(); 562 for (unsigned ri = 0, re = Roots.size(); ri != re; ++ri) { 563 const CodeGenRegister *Root = Roots[ri]; 564 Overlaps.insert(Root); 565 ArrayRef<const CodeGenRegister*> Supers = Root->getSuperRegs(); 566 Overlaps.insert(Supers.begin(), Supers.end()); 567 } 568 } 569} 570 571// Get the sum of this register's unit weights. 572unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const { 573 unsigned Weight = 0; 574 for (RegUnitList::const_iterator I = RegUnits.begin(), E = RegUnits.end(); 575 I != E; ++I) { 576 Weight += RegBank.getRegUnit(*I).Weight; 577 } 578 return Weight; 579} 580 581//===----------------------------------------------------------------------===// 582// RegisterTuples 583//===----------------------------------------------------------------------===// 584 585// A RegisterTuples def is used to generate pseudo-registers from lists of 586// sub-registers. We provide a SetTheory expander class that returns the new 587// registers. 588namespace { 589struct TupleExpander : SetTheory::Expander { 590 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) { 591 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); 592 unsigned Dim = Indices.size(); 593 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); 594 if (Dim != SubRegs->getSize()) 595 throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch"); 596 if (Dim < 2) 597 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers"); 598 599 // Evaluate the sub-register lists to be zipped. 600 unsigned Length = ~0u; 601 SmallVector<SetTheory::RecSet, 4> Lists(Dim); 602 for (unsigned i = 0; i != Dim; ++i) { 603 ST.evaluate(SubRegs->getElement(i), Lists[i]); 604 Length = std::min(Length, unsigned(Lists[i].size())); 605 } 606 607 if (Length == 0) 608 return; 609 610 // Precompute some types. 611 Record *RegisterCl = Def->getRecords().getClass("Register"); 612 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl); 613 StringInit *BlankName = StringInit::get(""); 614 615 // Zip them up. 616 for (unsigned n = 0; n != Length; ++n) { 617 std::string Name; 618 Record *Proto = Lists[0][n]; 619 std::vector<Init*> Tuple; 620 unsigned CostPerUse = 0; 621 for (unsigned i = 0; i != Dim; ++i) { 622 Record *Reg = Lists[i][n]; 623 if (i) Name += '_'; 624 Name += Reg->getName(); 625 Tuple.push_back(DefInit::get(Reg)); 626 CostPerUse = std::max(CostPerUse, 627 unsigned(Reg->getValueAsInt("CostPerUse"))); 628 } 629 630 // Create a new Record representing the synthesized register. This record 631 // is only for consumption by CodeGenRegister, it is not added to the 632 // RecordKeeper. 633 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords()); 634 Elts.insert(NewReg); 635 636 // Copy Proto super-classes. 637 for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i) 638 NewReg->addSuperClass(Proto->getSuperClasses()[i]); 639 640 // Copy Proto fields. 641 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) { 642 RecordVal RV = Proto->getValues()[i]; 643 644 // Skip existing fields, like NAME. 645 if (NewReg->getValue(RV.getNameInit())) 646 continue; 647 648 StringRef Field = RV.getName(); 649 650 // Replace the sub-register list with Tuple. 651 if (Field == "SubRegs") 652 RV.setValue(ListInit::get(Tuple, RegisterRecTy)); 653 654 // Provide a blank AsmName. MC hacks are required anyway. 655 if (Field == "AsmName") 656 RV.setValue(BlankName); 657 658 // CostPerUse is aggregated from all Tuple members. 659 if (Field == "CostPerUse") 660 RV.setValue(IntInit::get(CostPerUse)); 661 662 // Composite registers are always covered by sub-registers. 663 if (Field == "CoveredBySubRegs") 664 RV.setValue(BitInit::get(true)); 665 666 // Copy fields from the RegisterTuples def. 667 if (Field == "SubRegIndices" || 668 Field == "CompositeIndices") { 669 NewReg->addValue(*Def->getValue(Field)); 670 continue; 671 } 672 673 // Some fields get their default uninitialized value. 674 if (Field == "DwarfNumbers" || 675 Field == "DwarfAlias" || 676 Field == "Aliases") { 677 if (const RecordVal *DefRV = RegisterCl->getValue(Field)) 678 NewReg->addValue(*DefRV); 679 continue; 680 } 681 682 // Everything else is copied from Proto. 683 NewReg->addValue(RV); 684 } 685 } 686 } 687}; 688} 689 690//===----------------------------------------------------------------------===// 691// CodeGenRegisterClass 692//===----------------------------------------------------------------------===// 693 694CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) 695 : TheDef(R), 696 Name(R->getName()), 697 TopoSigs(RegBank.getNumTopoSigs()), 698 EnumValue(-1) { 699 // Rename anonymous register classes. 700 if (R->getName().size() > 9 && R->getName()[9] == '.') { 701 static unsigned AnonCounter = 0; 702 R->setName("AnonRegClass_"+utostr(AnonCounter++)); 703 } 704 705 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); 706 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { 707 Record *Type = TypeList[i]; 708 if (!Type->isSubClassOf("ValueType")) 709 throw "RegTypes list member '" + Type->getName() + 710 "' does not derive from the ValueType class!"; 711 VTs.push_back(getValueType(Type)); 712 } 713 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); 714 715 // Allocation order 0 is the full set. AltOrders provides others. 716 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); 717 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); 718 Orders.resize(1 + AltOrders->size()); 719 720 // Default allocation order always contains all registers. 721 for (unsigned i = 0, e = Elements->size(); i != e; ++i) { 722 Orders[0].push_back((*Elements)[i]); 723 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]); 724 Members.insert(Reg); 725 TopoSigs.set(Reg->getTopoSig()); 726 } 727 728 // Alternative allocation orders may be subsets. 729 SetTheory::RecSet Order; 730 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { 731 RegBank.getSets().evaluate(AltOrders->getElement(i), Order); 732 Orders[1 + i].append(Order.begin(), Order.end()); 733 // Verify that all altorder members are regclass members. 734 while (!Order.empty()) { 735 CodeGenRegister *Reg = RegBank.getReg(Order.back()); 736 Order.pop_back(); 737 if (!contains(Reg)) 738 throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() + 739 " is not a class member"); 740 } 741 } 742 743 // Allow targets to override the size in bits of the RegisterClass. 744 unsigned Size = R->getValueAsInt("Size"); 745 746 Namespace = R->getValueAsString("Namespace"); 747 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits(); 748 SpillAlignment = R->getValueAsInt("Alignment"); 749 CopyCost = R->getValueAsInt("CopyCost"); 750 Allocatable = R->getValueAsBit("isAllocatable"); 751 AltOrderSelect = R->getValueAsString("AltOrderSelect"); 752} 753 754// Create an inferred register class that was missing from the .td files. 755// Most properties will be inherited from the closest super-class after the 756// class structure has been computed. 757CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, 758 StringRef Name, Key Props) 759 : Members(*Props.Members), 760 TheDef(0), 761 Name(Name), 762 TopoSigs(RegBank.getNumTopoSigs()), 763 EnumValue(-1), 764 SpillSize(Props.SpillSize), 765 SpillAlignment(Props.SpillAlignment), 766 CopyCost(0), 767 Allocatable(true) { 768 for (CodeGenRegister::Set::iterator I = Members.begin(), E = Members.end(); 769 I != E; ++I) 770 TopoSigs.set((*I)->getTopoSig()); 771} 772 773// Compute inherited propertied for a synthesized register class. 774void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) { 775 assert(!getDef() && "Only synthesized classes can inherit properties"); 776 assert(!SuperClasses.empty() && "Synthesized class without super class"); 777 778 // The last super-class is the smallest one. 779 CodeGenRegisterClass &Super = *SuperClasses.back(); 780 781 // Most properties are copied directly. 782 // Exceptions are members, size, and alignment 783 Namespace = Super.Namespace; 784 VTs = Super.VTs; 785 CopyCost = Super.CopyCost; 786 Allocatable = Super.Allocatable; 787 AltOrderSelect = Super.AltOrderSelect; 788 789 // Copy all allocation orders, filter out foreign registers from the larger 790 // super-class. 791 Orders.resize(Super.Orders.size()); 792 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) 793 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) 794 if (contains(RegBank.getReg(Super.Orders[i][j]))) 795 Orders[i].push_back(Super.Orders[i][j]); 796} 797 798bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const { 799 return Members.count(Reg); 800} 801 802namespace llvm { 803 raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) { 804 OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment; 805 for (CodeGenRegister::Set::const_iterator I = K.Members->begin(), 806 E = K.Members->end(); I != E; ++I) 807 OS << ", " << (*I)->getName(); 808 return OS << " }"; 809 } 810} 811 812// This is a simple lexicographical order that can be used to search for sets. 813// It is not the same as the topological order provided by TopoOrderRC. 814bool CodeGenRegisterClass::Key:: 815operator<(const CodeGenRegisterClass::Key &B) const { 816 assert(Members && B.Members); 817 if (*Members != *B.Members) 818 return *Members < *B.Members; 819 if (SpillSize != B.SpillSize) 820 return SpillSize < B.SpillSize; 821 return SpillAlignment < B.SpillAlignment; 822} 823 824// Returns true if RC is a strict subclass. 825// RC is a sub-class of this class if it is a valid replacement for any 826// instruction operand where a register of this classis required. It must 827// satisfy these conditions: 828// 829// 1. All RC registers are also in this. 830// 2. The RC spill size must not be smaller than our spill size. 831// 3. RC spill alignment must be compatible with ours. 832// 833static bool testSubClass(const CodeGenRegisterClass *A, 834 const CodeGenRegisterClass *B) { 835 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 && 836 A->SpillSize <= B->SpillSize && 837 std::includes(A->getMembers().begin(), A->getMembers().end(), 838 B->getMembers().begin(), B->getMembers().end(), 839 CodeGenRegister::Less()); 840} 841 842/// Sorting predicate for register classes. This provides a topological 843/// ordering that arranges all register classes before their sub-classes. 844/// 845/// Register classes with the same registers, spill size, and alignment form a 846/// clique. They will be ordered alphabetically. 847/// 848static int TopoOrderRC(const void *PA, const void *PB) { 849 const CodeGenRegisterClass *A = *(const CodeGenRegisterClass* const*)PA; 850 const CodeGenRegisterClass *B = *(const CodeGenRegisterClass* const*)PB; 851 if (A == B) 852 return 0; 853 854 // Order by ascending spill size. 855 if (A->SpillSize < B->SpillSize) 856 return -1; 857 if (A->SpillSize > B->SpillSize) 858 return 1; 859 860 // Order by ascending spill alignment. 861 if (A->SpillAlignment < B->SpillAlignment) 862 return -1; 863 if (A->SpillAlignment > B->SpillAlignment) 864 return 1; 865 866 // Order by descending set size. Note that the classes' allocation order may 867 // not have been computed yet. The Members set is always vaild. 868 if (A->getMembers().size() > B->getMembers().size()) 869 return -1; 870 if (A->getMembers().size() < B->getMembers().size()) 871 return 1; 872 873 // Finally order by name as a tie breaker. 874 return StringRef(A->getName()).compare(B->getName()); 875} 876 877std::string CodeGenRegisterClass::getQualifiedName() const { 878 if (Namespace.empty()) 879 return getName(); 880 else 881 return Namespace + "::" + getName(); 882} 883 884// Compute sub-classes of all register classes. 885// Assume the classes are ordered topologically. 886void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) { 887 ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses(); 888 889 // Visit backwards so sub-classes are seen first. 890 for (unsigned rci = RegClasses.size(); rci; --rci) { 891 CodeGenRegisterClass &RC = *RegClasses[rci - 1]; 892 RC.SubClasses.resize(RegClasses.size()); 893 RC.SubClasses.set(RC.EnumValue); 894 895 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique. 896 for (unsigned s = rci; s != RegClasses.size(); ++s) { 897 if (RC.SubClasses.test(s)) 898 continue; 899 CodeGenRegisterClass *SubRC = RegClasses[s]; 900 if (!testSubClass(&RC, SubRC)) 901 continue; 902 // SubRC is a sub-class. Grap all its sub-classes so we won't have to 903 // check them again. 904 RC.SubClasses |= SubRC->SubClasses; 905 } 906 907 // Sweep up missed clique members. They will be immediately preceding RC. 908 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s) 909 RC.SubClasses.set(s - 1); 910 } 911 912 // Compute the SuperClasses lists from the SubClasses vectors. 913 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) { 914 const BitVector &SC = RegClasses[rci]->getSubClasses(); 915 for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) { 916 if (unsigned(s) == rci) 917 continue; 918 RegClasses[s]->SuperClasses.push_back(RegClasses[rci]); 919 } 920 } 921 922 // With the class hierarchy in place, let synthesized register classes inherit 923 // properties from their closest super-class. The iteration order here can 924 // propagate properties down multiple levels. 925 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) 926 if (!RegClasses[rci]->getDef()) 927 RegClasses[rci]->inheritProperties(RegBank); 928} 929 930void 931CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, 932 BitVector &Out) const { 933 DenseMap<CodeGenSubRegIndex*, 934 SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator 935 FindI = SuperRegClasses.find(SubIdx); 936 if (FindI == SuperRegClasses.end()) 937 return; 938 for (SmallPtrSet<CodeGenRegisterClass*, 8>::const_iterator I = 939 FindI->second.begin(), E = FindI->second.end(); I != E; ++I) 940 Out.set((*I)->EnumValue); 941} 942 943// Populate a unique sorted list of units from a register set. 944void CodeGenRegisterClass::buildRegUnitSet( 945 std::vector<unsigned> &RegUnits) const { 946 std::vector<unsigned> TmpUnits; 947 for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI) 948 TmpUnits.push_back(*UnitI); 949 std::sort(TmpUnits.begin(), TmpUnits.end()); 950 std::unique_copy(TmpUnits.begin(), TmpUnits.end(), 951 std::back_inserter(RegUnits)); 952} 953 954//===----------------------------------------------------------------------===// 955// CodeGenRegBank 956//===----------------------------------------------------------------------===// 957 958CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) { 959 // Configure register Sets to understand register classes and tuples. 960 Sets.addFieldExpander("RegisterClass", "MemberList"); 961 Sets.addFieldExpander("CalleeSavedRegs", "SaveList"); 962 Sets.addExpander("RegisterTuples", new TupleExpander()); 963 964 // Read in the user-defined (named) sub-register indices. 965 // More indices will be synthesized later. 966 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex"); 967 std::sort(SRIs.begin(), SRIs.end(), LessRecord()); 968 for (unsigned i = 0, e = SRIs.size(); i != e; ++i) 969 getSubRegIdx(SRIs[i]); 970 // Build composite maps from ComposedOf fields. 971 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 972 SubRegIndices[i]->updateComponents(*this); 973 974 // Read in the register definitions. 975 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); 976 std::sort(Regs.begin(), Regs.end(), LessRecord()); 977 Registers.reserve(Regs.size()); 978 // Assign the enumeration values. 979 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 980 getReg(Regs[i]); 981 982 // Expand tuples and number the new registers. 983 std::vector<Record*> Tups = 984 Records.getAllDerivedDefinitions("RegisterTuples"); 985 for (unsigned i = 0, e = Tups.size(); i != e; ++i) { 986 const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]); 987 for (unsigned j = 0, je = TupRegs->size(); j != je; ++j) 988 getReg((*TupRegs)[j]); 989 } 990 991 // Now all the registers are known. Build the object graph of explicit 992 // register-register references. 993 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 994 Registers[i]->buildObjectGraph(*this); 995 996 // Compute register name map. 997 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 998 RegistersByName.GetOrCreateValue( 999 Registers[i]->TheDef->getValueAsString("AsmName"), 1000 Registers[i]); 1001 1002 // Precompute all sub-register maps. 1003 // This will create Composite entries for all inferred sub-register indices. 1004 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 1005 Registers[i]->computeSubRegs(*this); 1006 1007 // Infer even more sub-registers by combining leading super-registers. 1008 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 1009 if (Registers[i]->CoveredBySubRegs) 1010 Registers[i]->computeSecondarySubRegs(*this); 1011 1012 // After the sub-register graph is complete, compute the topologically 1013 // ordered SuperRegs list. 1014 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 1015 Registers[i]->computeSuperRegs(*this); 1016 1017 // Native register units are associated with a leaf register. They've all been 1018 // discovered now. 1019 NumNativeRegUnits = RegUnits.size(); 1020 1021 // Read in register class definitions. 1022 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass"); 1023 if (RCs.empty()) 1024 throw std::string("No 'RegisterClass' subclasses defined!"); 1025 1026 // Allocate user-defined register classes. 1027 RegClasses.reserve(RCs.size()); 1028 for (unsigned i = 0, e = RCs.size(); i != e; ++i) 1029 addToMaps(new CodeGenRegisterClass(*this, RCs[i])); 1030 1031 // Infer missing classes to create a full algebra. 1032 computeInferredRegisterClasses(); 1033 1034 // Order register classes topologically and assign enum values. 1035 array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC); 1036 for (unsigned i = 0, e = RegClasses.size(); i != e; ++i) 1037 RegClasses[i]->EnumValue = i; 1038 CodeGenRegisterClass::computeSubClasses(*this); 1039} 1040 1041// Create a synthetic CodeGenSubRegIndex without a corresponding Record. 1042CodeGenSubRegIndex* 1043CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) { 1044 CodeGenSubRegIndex *Idx = new CodeGenSubRegIndex(Name, Namespace, 1045 SubRegIndices.size() + 1); 1046 SubRegIndices.push_back(Idx); 1047 return Idx; 1048} 1049 1050CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) { 1051 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def]; 1052 if (Idx) 1053 return Idx; 1054 Idx = new CodeGenSubRegIndex(Def, SubRegIndices.size() + 1); 1055 SubRegIndices.push_back(Idx); 1056 return Idx; 1057} 1058 1059CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { 1060 CodeGenRegister *&Reg = Def2Reg[Def]; 1061 if (Reg) 1062 return Reg; 1063 Reg = new CodeGenRegister(Def, Registers.size() + 1); 1064 Registers.push_back(Reg); 1065 return Reg; 1066} 1067 1068void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { 1069 RegClasses.push_back(RC); 1070 1071 if (Record *Def = RC->getDef()) 1072 Def2RC.insert(std::make_pair(Def, RC)); 1073 1074 // Duplicate classes are rejected by insert(). 1075 // That's OK, we only care about the properties handled by CGRC::Key. 1076 CodeGenRegisterClass::Key K(*RC); 1077 Key2RC.insert(std::make_pair(K, RC)); 1078} 1079 1080// Create a synthetic sub-class if it is missing. 1081CodeGenRegisterClass* 1082CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, 1083 const CodeGenRegister::Set *Members, 1084 StringRef Name) { 1085 // Synthetic sub-class has the same size and alignment as RC. 1086 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment); 1087 RCKeyMap::const_iterator FoundI = Key2RC.find(K); 1088 if (FoundI != Key2RC.end()) 1089 return FoundI->second; 1090 1091 // Sub-class doesn't exist, create a new one. 1092 CodeGenRegisterClass *NewRC = new CodeGenRegisterClass(*this, Name, K); 1093 addToMaps(NewRC); 1094 return NewRC; 1095} 1096 1097CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { 1098 if (CodeGenRegisterClass *RC = Def2RC[Def]) 1099 return RC; 1100 1101 throw TGError(Def->getLoc(), "Not a known RegisterClass!"); 1102} 1103 1104CodeGenSubRegIndex* 1105CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A, 1106 CodeGenSubRegIndex *B) { 1107 // Look for an existing entry. 1108 CodeGenSubRegIndex *Comp = A->compose(B); 1109 if (Comp) 1110 return Comp; 1111 1112 // None exists, synthesize one. 1113 std::string Name = A->getName() + "_then_" + B->getName(); 1114 Comp = createSubRegIndex(Name, A->getNamespace()); 1115 A->addComposite(B, Comp); 1116 return Comp; 1117} 1118 1119CodeGenSubRegIndex *CodeGenRegBank:: 1120getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts) { 1121 assert(Parts.size() > 1 && "Need two parts to concatenate"); 1122 1123 // Look for an existing entry. 1124 CodeGenSubRegIndex *&Idx = ConcatIdx[Parts]; 1125 if (Idx) 1126 return Idx; 1127 1128 // None exists, synthesize one. 1129 std::string Name = Parts.front()->getName(); 1130 for (unsigned i = 1, e = Parts.size(); i != e; ++i) { 1131 Name += '_'; 1132 Name += Parts[i]->getName(); 1133 } 1134 return Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); 1135} 1136 1137void CodeGenRegBank::computeComposites() { 1138 // Keep track of TopoSigs visited. We only need to visit each TopoSig once, 1139 // and many registers will share TopoSigs on regular architectures. 1140 BitVector TopoSigs(getNumTopoSigs()); 1141 1142 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 1143 CodeGenRegister *Reg1 = Registers[i]; 1144 1145 // Skip identical subreg structures already processed. 1146 if (TopoSigs.test(Reg1->getTopoSig())) 1147 continue; 1148 TopoSigs.set(Reg1->getTopoSig()); 1149 1150 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs(); 1151 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(), 1152 e1 = SRM1.end(); i1 != e1; ++i1) { 1153 CodeGenSubRegIndex *Idx1 = i1->first; 1154 CodeGenRegister *Reg2 = i1->second; 1155 // Ignore identity compositions. 1156 if (Reg1 == Reg2) 1157 continue; 1158 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); 1159 // Try composing Idx1 with another SubRegIndex. 1160 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(), 1161 e2 = SRM2.end(); i2 != e2; ++i2) { 1162 CodeGenSubRegIndex *Idx2 = i2->first; 1163 CodeGenRegister *Reg3 = i2->second; 1164 // Ignore identity compositions. 1165 if (Reg2 == Reg3) 1166 continue; 1167 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3. 1168 CodeGenSubRegIndex *Idx3 = Reg1->getSubRegIndex(Reg3); 1169 assert(Idx3 && "Sub-register doesn't have an index"); 1170 1171 // Conflicting composition? Emit a warning but allow it. 1172 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3)) 1173 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() + 1174 " and " + Idx2->getQualifiedName() + 1175 " compose ambiguously as " + Prev->getQualifiedName() + 1176 " or " + Idx3->getQualifiedName()); 1177 } 1178 } 1179 } 1180} 1181 1182// Compute lane masks. This is similar to register units, but at the 1183// sub-register index level. Each bit in the lane mask is like a register unit 1184// class, and two lane masks will have a bit in common if two sub-register 1185// indices overlap in some register. 1186// 1187// Conservatively share a lane mask bit if two sub-register indices overlap in 1188// some registers, but not in others. That shouldn't happen a lot. 1189void CodeGenRegBank::computeSubRegIndexLaneMasks() { 1190 // First assign individual bits to all the leaf indices. 1191 unsigned Bit = 0; 1192 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 1193 CodeGenSubRegIndex *Idx = SubRegIndices[i]; 1194 if (Idx->getComposites().empty()) { 1195 Idx->LaneMask = 1u << Bit; 1196 // Share bit 31 in the unlikely case there are more than 32 leafs. 1197 if (Bit < 31) ++Bit; 1198 } else { 1199 Idx->LaneMask = 0; 1200 } 1201 } 1202 1203 // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented 1204 // by the sub-register graph? This doesn't occur in any known targets. 1205 1206 // Inherit lanes from composites. 1207 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 1208 SubRegIndices[i]->computeLaneMask(); 1209} 1210 1211namespace { 1212// UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is 1213// the transitive closure of the union of overlapping register 1214// classes. Together, the UberRegSets form a partition of the registers. If we 1215// consider overlapping register classes to be connected, then each UberRegSet 1216// is a set of connected components. 1217// 1218// An UberRegSet will likely be a horizontal slice of register names of 1219// the same width. Nontrivial subregisters should then be in a separate 1220// UberRegSet. But this property isn't required for valid computation of 1221// register unit weights. 1222// 1223// A Weight field caches the max per-register unit weight in each UberRegSet. 1224// 1225// A set of SingularDeterminants flags single units of some register in this set 1226// for which the unit weight equals the set weight. These units should not have 1227// their weight increased. 1228struct UberRegSet { 1229 CodeGenRegister::Set Regs; 1230 unsigned Weight; 1231 CodeGenRegister::RegUnitList SingularDeterminants; 1232 1233 UberRegSet(): Weight(0) {} 1234}; 1235} // namespace 1236 1237// Partition registers into UberRegSets, where each set is the transitive 1238// closure of the union of overlapping register classes. 1239// 1240// UberRegSets[0] is a special non-allocatable set. 1241static void computeUberSets(std::vector<UberRegSet> &UberSets, 1242 std::vector<UberRegSet*> &RegSets, 1243 CodeGenRegBank &RegBank) { 1244 1245 const std::vector<CodeGenRegister*> &Registers = RegBank.getRegisters(); 1246 1247 // The Register EnumValue is one greater than its index into Registers. 1248 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && 1249 "register enum value mismatch"); 1250 1251 // For simplicitly make the SetID the same as EnumValue. 1252 IntEqClasses UberSetIDs(Registers.size()+1); 1253 std::set<unsigned> AllocatableRegs; 1254 for (unsigned i = 0, e = RegBank.getRegClasses().size(); i != e; ++i) { 1255 1256 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i]; 1257 if (!RegClass->Allocatable) 1258 continue; 1259 1260 const CodeGenRegister::Set &Regs = RegClass->getMembers(); 1261 if (Regs.empty()) 1262 continue; 1263 1264 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue); 1265 assert(USetID && "register number 0 is invalid"); 1266 1267 AllocatableRegs.insert((*Regs.begin())->EnumValue); 1268 for (CodeGenRegister::Set::const_iterator I = llvm::next(Regs.begin()), 1269 E = Regs.end(); I != E; ++I) { 1270 AllocatableRegs.insert((*I)->EnumValue); 1271 UberSetIDs.join(USetID, (*I)->EnumValue); 1272 } 1273 } 1274 // Combine non-allocatable regs. 1275 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 1276 unsigned RegNum = Registers[i]->EnumValue; 1277 if (AllocatableRegs.count(RegNum)) 1278 continue; 1279 1280 UberSetIDs.join(0, RegNum); 1281 } 1282 UberSetIDs.compress(); 1283 1284 // Make the first UberSet a special unallocatable set. 1285 unsigned ZeroID = UberSetIDs[0]; 1286 1287 // Insert Registers into the UberSets formed by union-find. 1288 // Do not resize after this. 1289 UberSets.resize(UberSetIDs.getNumClasses()); 1290 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 1291 const CodeGenRegister *Reg = Registers[i]; 1292 unsigned USetID = UberSetIDs[Reg->EnumValue]; 1293 if (!USetID) 1294 USetID = ZeroID; 1295 else if (USetID == ZeroID) 1296 USetID = 0; 1297 1298 UberRegSet *USet = &UberSets[USetID]; 1299 USet->Regs.insert(Reg); 1300 RegSets[i] = USet; 1301 } 1302} 1303 1304// Recompute each UberSet weight after changing unit weights. 1305static void computeUberWeights(std::vector<UberRegSet> &UberSets, 1306 CodeGenRegBank &RegBank) { 1307 // Skip the first unallocatable set. 1308 for (std::vector<UberRegSet>::iterator I = llvm::next(UberSets.begin()), 1309 E = UberSets.end(); I != E; ++I) { 1310 1311 // Initialize all unit weights in this set, and remember the max units/reg. 1312 const CodeGenRegister *Reg = 0; 1313 unsigned MaxWeight = 0, Weight = 0; 1314 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) { 1315 if (Reg != UnitI.getReg()) { 1316 if (Weight > MaxWeight) 1317 MaxWeight = Weight; 1318 Reg = UnitI.getReg(); 1319 Weight = 0; 1320 } 1321 unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight; 1322 if (!UWeight) { 1323 UWeight = 1; 1324 RegBank.increaseRegUnitWeight(*UnitI, UWeight); 1325 } 1326 Weight += UWeight; 1327 } 1328 if (Weight > MaxWeight) 1329 MaxWeight = Weight; 1330 1331 // Update the set weight. 1332 I->Weight = MaxWeight; 1333 1334 // Find singular determinants. 1335 for (CodeGenRegister::Set::iterator RegI = I->Regs.begin(), 1336 RegE = I->Regs.end(); RegI != RegE; ++RegI) { 1337 if ((*RegI)->getRegUnits().size() == 1 1338 && (*RegI)->getWeight(RegBank) == I->Weight) 1339 mergeRegUnits(I->SingularDeterminants, (*RegI)->getRegUnits()); 1340 } 1341 } 1342} 1343 1344// normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of 1345// a register and its subregisters so that they have the same weight as their 1346// UberSet. Self-recursion processes the subregister tree in postorder so 1347// subregisters are normalized first. 1348// 1349// Side effects: 1350// - creates new adopted register units 1351// - causes superregisters to inherit adopted units 1352// - increases the weight of "singular" units 1353// - induces recomputation of UberWeights. 1354static bool normalizeWeight(CodeGenRegister *Reg, 1355 std::vector<UberRegSet> &UberSets, 1356 std::vector<UberRegSet*> &RegSets, 1357 std::set<unsigned> &NormalRegs, 1358 CodeGenRegister::RegUnitList &NormalUnits, 1359 CodeGenRegBank &RegBank) { 1360 bool Changed = false; 1361 if (!NormalRegs.insert(Reg->EnumValue).second) 1362 return Changed; 1363 1364 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); 1365 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(), 1366 SRE = SRM.end(); SRI != SRE; ++SRI) { 1367 if (SRI->second == Reg) 1368 continue; // self-cycles happen 1369 1370 Changed |= normalizeWeight(SRI->second, UberSets, RegSets, 1371 NormalRegs, NormalUnits, RegBank); 1372 } 1373 // Postorder register normalization. 1374 1375 // Inherit register units newly adopted by subregisters. 1376 if (Reg->inheritRegUnits(RegBank)) 1377 computeUberWeights(UberSets, RegBank); 1378 1379 // Check if this register is too skinny for its UberRegSet. 1380 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)]; 1381 1382 unsigned RegWeight = Reg->getWeight(RegBank); 1383 if (UberSet->Weight > RegWeight) { 1384 // A register unit's weight can be adjusted only if it is the singular unit 1385 // for this register, has not been used to normalize a subregister's set, 1386 // and has not already been used to singularly determine this UberRegSet. 1387 unsigned AdjustUnit = Reg->getRegUnits().front(); 1388 if (Reg->getRegUnits().size() != 1 1389 || hasRegUnit(NormalUnits, AdjustUnit) 1390 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) { 1391 // We don't have an adjustable unit, so adopt a new one. 1392 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight); 1393 Reg->adoptRegUnit(AdjustUnit); 1394 // Adopting a unit does not immediately require recomputing set weights. 1395 } 1396 else { 1397 // Adjust the existing single unit. 1398 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight); 1399 // The unit may be shared among sets and registers within this set. 1400 computeUberWeights(UberSets, RegBank); 1401 } 1402 Changed = true; 1403 } 1404 1405 // Mark these units normalized so superregisters can't change their weights. 1406 mergeRegUnits(NormalUnits, Reg->getRegUnits()); 1407 1408 return Changed; 1409} 1410 1411// Compute a weight for each register unit created during getSubRegs. 1412// 1413// The goal is that two registers in the same class will have the same weight, 1414// where each register's weight is defined as sum of its units' weights. 1415void CodeGenRegBank::computeRegUnitWeights() { 1416 std::vector<UberRegSet> UberSets; 1417 std::vector<UberRegSet*> RegSets(Registers.size()); 1418 computeUberSets(UberSets, RegSets, *this); 1419 // UberSets and RegSets are now immutable. 1420 1421 computeUberWeights(UberSets, *this); 1422 1423 // Iterate over each Register, normalizing the unit weights until reaching 1424 // a fix point. 1425 unsigned NumIters = 0; 1426 for (bool Changed = true; Changed; ++NumIters) { 1427 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights"); 1428 Changed = false; 1429 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 1430 CodeGenRegister::RegUnitList NormalUnits; 1431 std::set<unsigned> NormalRegs; 1432 Changed |= normalizeWeight(Registers[i], UberSets, RegSets, 1433 NormalRegs, NormalUnits, *this); 1434 } 1435 } 1436} 1437 1438// Find a set in UniqueSets with the same elements as Set. 1439// Return an iterator into UniqueSets. 1440static std::vector<RegUnitSet>::const_iterator 1441findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets, 1442 const RegUnitSet &Set) { 1443 std::vector<RegUnitSet>::const_iterator 1444 I = UniqueSets.begin(), E = UniqueSets.end(); 1445 for(;I != E; ++I) { 1446 if (I->Units == Set.Units) 1447 break; 1448 } 1449 return I; 1450} 1451 1452// Return true if the RUSubSet is a subset of RUSuperSet. 1453static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet, 1454 const std::vector<unsigned> &RUSuperSet) { 1455 return std::includes(RUSuperSet.begin(), RUSuperSet.end(), 1456 RUSubSet.begin(), RUSubSet.end()); 1457} 1458 1459// Iteratively prune unit sets. 1460void CodeGenRegBank::pruneUnitSets() { 1461 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets"); 1462 1463 // Form an equivalence class of UnitSets with no significant difference. 1464 std::vector<unsigned> SuperSetIDs; 1465 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); 1466 SubIdx != EndIdx; ++SubIdx) { 1467 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; 1468 unsigned SuperIdx = 0; 1469 for (; SuperIdx != EndIdx; ++SuperIdx) { 1470 if (SuperIdx == SubIdx) 1471 continue; 1472 1473 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx]; 1474 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units) 1475 && (SubSet.Units.size() + 3 > SuperSet.Units.size())) { 1476 break; 1477 } 1478 } 1479 if (SuperIdx == EndIdx) 1480 SuperSetIDs.push_back(SubIdx); 1481 } 1482 // Populate PrunedUnitSets with each equivalence class's superset. 1483 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size()); 1484 for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) { 1485 unsigned SuperIdx = SuperSetIDs[i]; 1486 PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name; 1487 PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units); 1488 } 1489 RegUnitSets.swap(PrunedUnitSets); 1490} 1491 1492// Create a RegUnitSet for each RegClass that contains all units in the class 1493// including adopted units that are necessary to model register pressure. Then 1494// iteratively compute RegUnitSets such that the union of any two overlapping 1495// RegUnitSets is repreresented. 1496// 1497// RegisterInfoEmitter will map each RegClass to its RegUnitClass and any 1498// RegUnitSet that is a superset of that RegUnitClass. 1499void CodeGenRegBank::computeRegUnitSets() { 1500 1501 // Compute a unique RegUnitSet for each RegClass. 1502 const ArrayRef<CodeGenRegisterClass*> &RegClasses = getRegClasses(); 1503 unsigned NumRegClasses = RegClasses.size(); 1504 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) { 1505 if (!RegClasses[RCIdx]->Allocatable) 1506 continue; 1507 1508 // Speculatively grow the RegUnitSets to hold the new set. 1509 RegUnitSets.resize(RegUnitSets.size() + 1); 1510 RegUnitSets.back().Name = RegClasses[RCIdx]->getName(); 1511 1512 // Compute a sorted list of units in this class. 1513 RegClasses[RCIdx]->buildRegUnitSet(RegUnitSets.back().Units); 1514 1515 // Find an existing RegUnitSet. 1516 std::vector<RegUnitSet>::const_iterator SetI = 1517 findRegUnitSet(RegUnitSets, RegUnitSets.back()); 1518 if (SetI != llvm::prior(RegUnitSets.end())) 1519 RegUnitSets.pop_back(); 1520 } 1521 1522 // Iteratively prune unit sets. 1523 pruneUnitSets(); 1524 1525 // Iterate over all unit sets, including new ones added by this loop. 1526 unsigned NumRegUnitSubSets = RegUnitSets.size(); 1527 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { 1528 // In theory, this is combinatorial. In practice, it needs to be bounded 1529 // by a small number of sets for regpressure to be efficient. 1530 // If the assert is hit, we need to implement pruning. 1531 assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference"); 1532 1533 // Compare new sets with all original classes. 1534 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1; 1535 SearchIdx != EndIdx; ++SearchIdx) { 1536 std::set<unsigned> Intersection; 1537 std::set_intersection(RegUnitSets[Idx].Units.begin(), 1538 RegUnitSets[Idx].Units.end(), 1539 RegUnitSets[SearchIdx].Units.begin(), 1540 RegUnitSets[SearchIdx].Units.end(), 1541 std::inserter(Intersection, Intersection.begin())); 1542 if (Intersection.empty()) 1543 continue; 1544 1545 // Speculatively grow the RegUnitSets to hold the new set. 1546 RegUnitSets.resize(RegUnitSets.size() + 1); 1547 RegUnitSets.back().Name = 1548 RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name; 1549 1550 std::set_union(RegUnitSets[Idx].Units.begin(), 1551 RegUnitSets[Idx].Units.end(), 1552 RegUnitSets[SearchIdx].Units.begin(), 1553 RegUnitSets[SearchIdx].Units.end(), 1554 std::inserter(RegUnitSets.back().Units, 1555 RegUnitSets.back().Units.begin())); 1556 1557 // Find an existing RegUnitSet, or add the union to the unique sets. 1558 std::vector<RegUnitSet>::const_iterator SetI = 1559 findRegUnitSet(RegUnitSets, RegUnitSets.back()); 1560 if (SetI != llvm::prior(RegUnitSets.end())) 1561 RegUnitSets.pop_back(); 1562 } 1563 } 1564 1565 // Iteratively prune unit sets after inferring supersets. 1566 pruneUnitSets(); 1567 1568 // For each register class, list the UnitSets that are supersets. 1569 RegClassUnitSets.resize(NumRegClasses); 1570 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) { 1571 if (!RegClasses[RCIdx]->Allocatable) 1572 continue; 1573 1574 // Recompute the sorted list of units in this class. 1575 std::vector<unsigned> RegUnits; 1576 RegClasses[RCIdx]->buildRegUnitSet(RegUnits); 1577 1578 // Don't increase pressure for unallocatable regclasses. 1579 if (RegUnits.empty()) 1580 continue; 1581 1582 // Find all supersets. 1583 for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); 1584 USIdx != USEnd; ++USIdx) { 1585 if (isRegUnitSubSet(RegUnits, RegUnitSets[USIdx].Units)) 1586 RegClassUnitSets[RCIdx].push_back(USIdx); 1587 } 1588 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass"); 1589 } 1590} 1591 1592void CodeGenRegBank::computeDerivedInfo() { 1593 computeComposites(); 1594 computeSubRegIndexLaneMasks(); 1595 1596 // Compute a weight for each register unit created during getSubRegs. 1597 // This may create adopted register units (with unit # >= NumNativeRegUnits). 1598 computeRegUnitWeights(); 1599 1600 // Compute a unique set of RegUnitSets. One for each RegClass and inferred 1601 // supersets for the union of overlapping sets. 1602 computeRegUnitSets(); 1603} 1604 1605// 1606// Synthesize missing register class intersections. 1607// 1608// Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X) 1609// returns a maximal register class for all X. 1610// 1611void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) { 1612 for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) { 1613 CodeGenRegisterClass *RC1 = RC; 1614 CodeGenRegisterClass *RC2 = RegClasses[rci]; 1615 if (RC1 == RC2) 1616 continue; 1617 1618 // Compute the set intersection of RC1 and RC2. 1619 const CodeGenRegister::Set &Memb1 = RC1->getMembers(); 1620 const CodeGenRegister::Set &Memb2 = RC2->getMembers(); 1621 CodeGenRegister::Set Intersection; 1622 std::set_intersection(Memb1.begin(), Memb1.end(), 1623 Memb2.begin(), Memb2.end(), 1624 std::inserter(Intersection, Intersection.begin()), 1625 CodeGenRegister::Less()); 1626 1627 // Skip disjoint class pairs. 1628 if (Intersection.empty()) 1629 continue; 1630 1631 // If RC1 and RC2 have different spill sizes or alignments, use the 1632 // larger size for sub-classing. If they are equal, prefer RC1. 1633 if (RC2->SpillSize > RC1->SpillSize || 1634 (RC2->SpillSize == RC1->SpillSize && 1635 RC2->SpillAlignment > RC1->SpillAlignment)) 1636 std::swap(RC1, RC2); 1637 1638 getOrCreateSubClass(RC1, &Intersection, 1639 RC1->getName() + "_and_" + RC2->getName()); 1640 } 1641} 1642 1643// 1644// Synthesize missing sub-classes for getSubClassWithSubReg(). 1645// 1646// Make sure that the set of registers in RC with a given SubIdx sub-register 1647// form a register class. Update RC->SubClassWithSubReg. 1648// 1649void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) { 1650 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex. 1651 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister::Set, 1652 CodeGenSubRegIndex::Less> SubReg2SetMap; 1653 1654 // Compute the set of registers supporting each SubRegIndex. 1655 SubReg2SetMap SRSets; 1656 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(), 1657 RE = RC->getMembers().end(); RI != RE; ++RI) { 1658 const CodeGenRegister::SubRegMap &SRM = (*RI)->getSubRegs(); 1659 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(), 1660 E = SRM.end(); I != E; ++I) 1661 SRSets[I->first].insert(*RI); 1662 } 1663 1664 // Find matching classes for all SRSets entries. Iterate in SubRegIndex 1665 // numerical order to visit synthetic indices last. 1666 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1667 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; 1668 SubReg2SetMap::const_iterator I = SRSets.find(SubIdx); 1669 // Unsupported SubRegIndex. Skip it. 1670 if (I == SRSets.end()) 1671 continue; 1672 // In most cases, all RC registers support the SubRegIndex. 1673 if (I->second.size() == RC->getMembers().size()) { 1674 RC->setSubClassWithSubReg(SubIdx, RC); 1675 continue; 1676 } 1677 // This is a real subset. See if we have a matching class. 1678 CodeGenRegisterClass *SubRC = 1679 getOrCreateSubClass(RC, &I->second, 1680 RC->getName() + "_with_" + I->first->getName()); 1681 RC->setSubClassWithSubReg(SubIdx, SubRC); 1682 } 1683} 1684 1685// 1686// Synthesize missing sub-classes of RC for getMatchingSuperRegClass(). 1687// 1688// Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X) 1689// has a maximal result for any SubIdx and any X >= FirstSubRegRC. 1690// 1691 1692void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC, 1693 unsigned FirstSubRegRC) { 1694 SmallVector<std::pair<const CodeGenRegister*, 1695 const CodeGenRegister*>, 16> SSPairs; 1696 BitVector TopoSigs(getNumTopoSigs()); 1697 1698 // Iterate in SubRegIndex numerical order to visit synthetic indices last. 1699 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1700 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; 1701 // Skip indexes that aren't fully supported by RC's registers. This was 1702 // computed by inferSubClassWithSubReg() above which should have been 1703 // called first. 1704 if (RC->getSubClassWithSubReg(SubIdx) != RC) 1705 continue; 1706 1707 // Build list of (Super, Sub) pairs for this SubIdx. 1708 SSPairs.clear(); 1709 TopoSigs.reset(); 1710 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(), 1711 RE = RC->getMembers().end(); RI != RE; ++RI) { 1712 const CodeGenRegister *Super = *RI; 1713 const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second; 1714 assert(Sub && "Missing sub-register"); 1715 SSPairs.push_back(std::make_pair(Super, Sub)); 1716 TopoSigs.set(Sub->getTopoSig()); 1717 } 1718 1719 // Iterate over sub-register class candidates. Ignore classes created by 1720 // this loop. They will never be useful. 1721 for (unsigned rci = FirstSubRegRC, rce = RegClasses.size(); rci != rce; 1722 ++rci) { 1723 CodeGenRegisterClass *SubRC = RegClasses[rci]; 1724 // Topological shortcut: SubRC members have the wrong shape. 1725 if (!TopoSigs.anyCommon(SubRC->getTopoSigs())) 1726 continue; 1727 // Compute the subset of RC that maps into SubRC. 1728 CodeGenRegister::Set SubSet; 1729 for (unsigned i = 0, e = SSPairs.size(); i != e; ++i) 1730 if (SubRC->contains(SSPairs[i].second)) 1731 SubSet.insert(SSPairs[i].first); 1732 if (SubSet.empty()) 1733 continue; 1734 // RC injects completely into SubRC. 1735 if (SubSet.size() == SSPairs.size()) { 1736 SubRC->addSuperRegClass(SubIdx, RC); 1737 continue; 1738 } 1739 // Only a subset of RC maps into SubRC. Make sure it is represented by a 1740 // class. 1741 getOrCreateSubClass(RC, &SubSet, RC->getName() + 1742 "_with_" + SubIdx->getName() + 1743 "_in_" + SubRC->getName()); 1744 } 1745 } 1746} 1747 1748 1749// 1750// Infer missing register classes. 1751// 1752void CodeGenRegBank::computeInferredRegisterClasses() { 1753 // When this function is called, the register classes have not been sorted 1754 // and assigned EnumValues yet. That means getSubClasses(), 1755 // getSuperClasses(), and hasSubClass() functions are defunct. 1756 unsigned FirstNewRC = RegClasses.size(); 1757 1758 // Visit all register classes, including the ones being added by the loop. 1759 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) { 1760 CodeGenRegisterClass *RC = RegClasses[rci]; 1761 1762 // Synthesize answers for getSubClassWithSubReg(). 1763 inferSubClassWithSubReg(RC); 1764 1765 // Synthesize answers for getCommonSubClass(). 1766 inferCommonSubClass(RC); 1767 1768 // Synthesize answers for getMatchingSuperRegClass(). 1769 inferMatchingSuperRegClass(RC); 1770 1771 // New register classes are created while this loop is running, and we need 1772 // to visit all of them. I particular, inferMatchingSuperRegClass needs 1773 // to match old super-register classes with sub-register classes created 1774 // after inferMatchingSuperRegClass was called. At this point, 1775 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC = 1776 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci]. 1777 if (rci + 1 == FirstNewRC) { 1778 unsigned NextNewRC = RegClasses.size(); 1779 for (unsigned rci2 = 0; rci2 != FirstNewRC; ++rci2) 1780 inferMatchingSuperRegClass(RegClasses[rci2], FirstNewRC); 1781 FirstNewRC = NextNewRC; 1782 } 1783 } 1784} 1785 1786/// getRegisterClassForRegister - Find the register class that contains the 1787/// specified physical register. If the register is not in a register class, 1788/// return null. If the register is in multiple classes, and the classes have a 1789/// superset-subset relationship and the same set of types, return the 1790/// superclass. Otherwise return null. 1791const CodeGenRegisterClass* 1792CodeGenRegBank::getRegClassForRegister(Record *R) { 1793 const CodeGenRegister *Reg = getReg(R); 1794 ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses(); 1795 const CodeGenRegisterClass *FoundRC = 0; 1796 for (unsigned i = 0, e = RCs.size(); i != e; ++i) { 1797 const CodeGenRegisterClass &RC = *RCs[i]; 1798 if (!RC.contains(Reg)) 1799 continue; 1800 1801 // If this is the first class that contains the register, 1802 // make a note of it and go on to the next class. 1803 if (!FoundRC) { 1804 FoundRC = &RC; 1805 continue; 1806 } 1807 1808 // If a register's classes have different types, return null. 1809 if (RC.getValueTypes() != FoundRC->getValueTypes()) 1810 return 0; 1811 1812 // Check to see if the previously found class that contains 1813 // the register is a subclass of the current class. If so, 1814 // prefer the superclass. 1815 if (RC.hasSubClass(FoundRC)) { 1816 FoundRC = &RC; 1817 continue; 1818 } 1819 1820 // Check to see if the previously found class that contains 1821 // the register is a superclass of the current class. If so, 1822 // prefer the superclass. 1823 if (FoundRC->hasSubClass(&RC)) 1824 continue; 1825 1826 // Multiple classes, and neither is a superclass of the other. 1827 // Return null. 1828 return 0; 1829 } 1830 return FoundRC; 1831} 1832 1833BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { 1834 SetVector<const CodeGenRegister*> Set; 1835 1836 // First add Regs with all sub-registers. 1837 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 1838 CodeGenRegister *Reg = getReg(Regs[i]); 1839 if (Set.insert(Reg)) 1840 // Reg is new, add all sub-registers. 1841 // The pre-ordering is not important here. 1842 Reg->addSubRegsPreOrder(Set, *this); 1843 } 1844 1845 // Second, find all super-registers that are completely covered by the set. 1846 for (unsigned i = 0; i != Set.size(); ++i) { 1847 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs(); 1848 for (unsigned j = 0, e = SR.size(); j != e; ++j) { 1849 const CodeGenRegister *Super = SR[j]; 1850 if (!Super->CoveredBySubRegs || Set.count(Super)) 1851 continue; 1852 // This new super-register is covered by its sub-registers. 1853 bool AllSubsInSet = true; 1854 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); 1855 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(), 1856 E = SRM.end(); I != E; ++I) 1857 if (!Set.count(I->second)) { 1858 AllSubsInSet = false; 1859 break; 1860 } 1861 // All sub-registers in Set, add Super as well. 1862 // We will visit Super later to recheck its super-registers. 1863 if (AllSubsInSet) 1864 Set.insert(Super); 1865 } 1866 } 1867 1868 // Convert to BitVector. 1869 BitVector BV(Registers.size() + 1); 1870 for (unsigned i = 0, e = Set.size(); i != e; ++i) 1871 BV.set(Set[i]->EnumValue); 1872 return BV; 1873} 1874