1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "MCTargetDesc/ARMAddressingModes.h" 13#include "MCTargetDesc/ARMMCExpr.h" 14#include "MCTargetDesc/ARMBaseInfo.h" 15#include "llvm/MC/EDInstInfo.h" 16#include "llvm/MC/MCInst.h" 17#include "llvm/MC/MCInstrDesc.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCContext.h" 20#include "llvm/MC/MCDisassembler.h" 21#include "llvm/MC/MCFixedLenDisassembler.h" 22#include "llvm/MC/MCSubtargetInfo.h" 23#include "llvm/Support/Debug.h" 24#include "llvm/Support/MemoryObject.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Support/LEB128.h" 27#include "llvm/Support/TargetRegistry.h" 28#include "llvm/Support/raw_ostream.h" 29#include <vector> 30 31using namespace llvm; 32 33typedef MCDisassembler::DecodeStatus DecodeStatus; 34 35namespace { 36 // Handles the condition code status of instructions in IT blocks 37 class ITStatus 38 { 39 public: 40 // Returns the condition code for instruction in IT block 41 unsigned getITCC() { 42 unsigned CC = ARMCC::AL; 43 if (instrInITBlock()) 44 CC = ITStates.back(); 45 return CC; 46 } 47 48 // Advances the IT block state to the next T or E 49 void advanceITState() { 50 ITStates.pop_back(); 51 } 52 53 // Returns true if the current instruction is in an IT block 54 bool instrInITBlock() { 55 return !ITStates.empty(); 56 } 57 58 // Returns true if current instruction is the last instruction in an IT block 59 bool instrLastInITBlock() { 60 return ITStates.size() == 1; 61 } 62 63 // Called when decoding an IT instruction. Sets the IT state for the following 64 // instructions that for the IT block. Firstcond and Mask correspond to the 65 // fields in the IT instruction encoding. 66 void setITState(char Firstcond, char Mask) { 67 // (3 - the number of trailing zeros) is the number of then / else. 68 unsigned CondBit0 = Firstcond & 1; 69 unsigned NumTZ = CountTrailingZeros_32(Mask); 70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 71 assert(NumTZ <= 3 && "Invalid IT mask!"); 72 // push condition codes onto the stack the correct order for the pops 73 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 74 bool T = ((Mask >> Pos) & 1) == CondBit0; 75 if (T) 76 ITStates.push_back(CCBits); 77 else 78 ITStates.push_back(CCBits ^ 1); 79 } 80 ITStates.push_back(CCBits); 81 } 82 83 private: 84 std::vector<unsigned char> ITStates; 85 }; 86} 87 88namespace { 89/// ARMDisassembler - ARM disassembler for all ARM platforms. 90class ARMDisassembler : public MCDisassembler { 91public: 92 /// Constructor - Initializes the disassembler. 93 /// 94 ARMDisassembler(const MCSubtargetInfo &STI) : 95 MCDisassembler(STI) { 96 } 97 98 ~ARMDisassembler() { 99 } 100 101 /// getInstruction - See MCDisassembler. 102 DecodeStatus getInstruction(MCInst &instr, 103 uint64_t &size, 104 const MemoryObject ®ion, 105 uint64_t address, 106 raw_ostream &vStream, 107 raw_ostream &cStream) const; 108 109 /// getEDInfo - See MCDisassembler. 110 const EDInstInfo *getEDInfo() const; 111private: 112}; 113 114/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 115class ThumbDisassembler : public MCDisassembler { 116public: 117 /// Constructor - Initializes the disassembler. 118 /// 119 ThumbDisassembler(const MCSubtargetInfo &STI) : 120 MCDisassembler(STI) { 121 } 122 123 ~ThumbDisassembler() { 124 } 125 126 /// getInstruction - See MCDisassembler. 127 DecodeStatus getInstruction(MCInst &instr, 128 uint64_t &size, 129 const MemoryObject ®ion, 130 uint64_t address, 131 raw_ostream &vStream, 132 raw_ostream &cStream) const; 133 134 /// getEDInfo - See MCDisassembler. 135 const EDInstInfo *getEDInfo() const; 136private: 137 mutable ITStatus ITBlock; 138 DecodeStatus AddThumbPredicate(MCInst&) const; 139 void UpdateThumbVFPPredicate(MCInst&) const; 140}; 141} 142 143static bool Check(DecodeStatus &Out, DecodeStatus In) { 144 switch (In) { 145 case MCDisassembler::Success: 146 // Out stays the same. 147 return true; 148 case MCDisassembler::SoftFail: 149 Out = In; 150 return true; 151 case MCDisassembler::Fail: 152 Out = In; 153 return false; 154 } 155 llvm_unreachable("Invalid DecodeStatus!"); 156} 157 158 159// Forward declare these because the autogenerated code will reference them. 160// Definitions are further down. 161static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 164 unsigned RegNo, uint64_t Address, 165 const void *Decoder); 166static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, const void *Decoder); 178static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 179 unsigned RegNo, 180 uint64_t Address, 181 const void *Decoder); 182static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 187 unsigned RegNo, uint64_t Address, 188 const void *Decoder); 189 190static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 203static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 208 unsigned Insn, 209 uint64_t Address, 210 const void *Decoder); 211static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 214 uint64_t Address, const void *Decoder); 215static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 220static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 221 unsigned Insn, 222 uint64_t Adddress, 223 const void *Decoder); 224static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 243 uint64_t Address, const void *Decoder); 244static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 259 uint64_t Address, const void *Decoder); 260static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 319 320static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 321 uint64_t Address, const void *Decoder); 322static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 345 uint64_t Address, const void *Decoder); 346static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 351 uint64_t Address, const void *Decoder); 352static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 353 uint64_t Address, const void *Decoder); 354static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 355 uint64_t Address, const void *Decoder); 356static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void *Decoder); 358static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 367 uint64_t Address, const void *Decoder); 368static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 371 uint64_t Address, const void *Decoder); 372static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 373 uint64_t Address, const void *Decoder); 374static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 375 uint64_t Address, const void *Decoder); 376static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 383static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 386 uint64_t Address, const void *Decoder); 387#include "ARMGenDisassemblerTables.inc" 388#include "ARMGenEDInfo.inc" 389 390static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 391 return new ARMDisassembler(STI); 392} 393 394static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 395 return new ThumbDisassembler(STI); 396} 397 398const EDInstInfo *ARMDisassembler::getEDInfo() const { 399 return instInfoARM; 400} 401 402const EDInstInfo *ThumbDisassembler::getEDInfo() const { 403 return instInfoARM; 404} 405 406DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 407 const MemoryObject &Region, 408 uint64_t Address, 409 raw_ostream &os, 410 raw_ostream &cs) const { 411 CommentStream = &cs; 412 413 uint8_t bytes[4]; 414 415 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 416 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 417 418 // We want to read exactly 4 bytes of data. 419 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 420 Size = 0; 421 return MCDisassembler::Fail; 422 } 423 424 // Encoded as a small-endian 32-bit word in the stream. 425 uint32_t insn = (bytes[3] << 24) | 426 (bytes[2] << 16) | 427 (bytes[1] << 8) | 428 (bytes[0] << 0); 429 430 // Calling the auto-generated decoder function. 431 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 432 Address, this, STI); 433 if (result != MCDisassembler::Fail) { 434 Size = 4; 435 return result; 436 } 437 438 // VFP and NEON instructions, similarly, are shared between ARM 439 // and Thumb modes. 440 MI.clear(); 441 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 442 if (result != MCDisassembler::Fail) { 443 Size = 4; 444 return result; 445 } 446 447 MI.clear(); 448 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 449 this, STI); 450 if (result != MCDisassembler::Fail) { 451 Size = 4; 452 // Add a fake predicate operand, because we share these instruction 453 // definitions with Thumb2 where these instructions are predicable. 454 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 455 return MCDisassembler::Fail; 456 return result; 457 } 458 459 MI.clear(); 460 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 461 this, STI); 462 if (result != MCDisassembler::Fail) { 463 Size = 4; 464 // Add a fake predicate operand, because we share these instruction 465 // definitions with Thumb2 where these instructions are predicable. 466 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 467 return MCDisassembler::Fail; 468 return result; 469 } 470 471 MI.clear(); 472 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 473 this, STI); 474 if (result != MCDisassembler::Fail) { 475 Size = 4; 476 // Add a fake predicate operand, because we share these instruction 477 // definitions with Thumb2 where these instructions are predicable. 478 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 479 return MCDisassembler::Fail; 480 return result; 481 } 482 483 MI.clear(); 484 485 Size = 0; 486 return MCDisassembler::Fail; 487} 488 489namespace llvm { 490extern const MCInstrDesc ARMInsts[]; 491} 492 493/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 494/// immediate Value in the MCInst. The immediate Value has had any PC 495/// adjustment made by the caller. If the instruction is a branch instruction 496/// then isBranch is true, else false. If the getOpInfo() function was set as 497/// part of the setupForSymbolicDisassembly() call then that function is called 498/// to get any symbolic information at the Address for this instruction. If 499/// that returns non-zero then the symbolic information it returns is used to 500/// create an MCExpr and that is added as an operand to the MCInst. If 501/// getOpInfo() returns zero and isBranch is true then a symbol look up for 502/// Value is done and if a symbol is found an MCExpr is created with that, else 503/// an MCExpr with Value is created. This function returns true if it adds an 504/// operand to the MCInst and false otherwise. 505static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 506 bool isBranch, uint64_t InstSize, 507 MCInst &MI, const void *Decoder) { 508 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 509 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 510 struct LLVMOpInfo1 SymbolicOp; 511 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 512 SymbolicOp.Value = Value; 513 void *DisInfo = Dis->getDisInfoBlock(); 514 515 if (!getOpInfo || 516 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 517 // Clear SymbolicOp.Value from above and also all other fields. 518 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 519 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 520 if (!SymbolLookUp) 521 return false; 522 uint64_t ReferenceType; 523 if (isBranch) 524 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 525 else 526 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 527 const char *ReferenceName; 528 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 529 &ReferenceName); 530 if (Name) { 531 SymbolicOp.AddSymbol.Name = Name; 532 SymbolicOp.AddSymbol.Present = true; 533 } 534 // For branches always create an MCExpr so it gets printed as hex address. 535 else if (isBranch) { 536 SymbolicOp.Value = Value; 537 } 538 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 539 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 540 if (!Name && !isBranch) 541 return false; 542 } 543 544 MCContext *Ctx = Dis->getMCContext(); 545 const MCExpr *Add = NULL; 546 if (SymbolicOp.AddSymbol.Present) { 547 if (SymbolicOp.AddSymbol.Name) { 548 StringRef Name(SymbolicOp.AddSymbol.Name); 549 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 550 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 551 } else { 552 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 553 } 554 } 555 556 const MCExpr *Sub = NULL; 557 if (SymbolicOp.SubtractSymbol.Present) { 558 if (SymbolicOp.SubtractSymbol.Name) { 559 StringRef Name(SymbolicOp.SubtractSymbol.Name); 560 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 561 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 562 } else { 563 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 564 } 565 } 566 567 const MCExpr *Off = NULL; 568 if (SymbolicOp.Value != 0) 569 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 570 571 const MCExpr *Expr; 572 if (Sub) { 573 const MCExpr *LHS; 574 if (Add) 575 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 576 else 577 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 578 if (Off != 0) 579 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 580 else 581 Expr = LHS; 582 } else if (Add) { 583 if (Off != 0) 584 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 585 else 586 Expr = Add; 587 } else { 588 if (Off != 0) 589 Expr = Off; 590 else 591 Expr = MCConstantExpr::Create(0, *Ctx); 592 } 593 594 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 595 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 596 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 597 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 598 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 599 MI.addOperand(MCOperand::CreateExpr(Expr)); 600 else 601 llvm_unreachable("bad SymbolicOp.VariantKind"); 602 603 return true; 604} 605 606/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 607/// referenced by a load instruction with the base register that is the Pc. 608/// These can often be values in a literal pool near the Address of the 609/// instruction. The Address of the instruction and its immediate Value are 610/// used as a possible literal pool entry. The SymbolLookUp call back will 611/// return the name of a symbol referenced by the literal pool's entry if 612/// the referenced address is that of a symbol. Or it will return a pointer to 613/// a literal 'C' string if the referenced address of the literal pool's entry 614/// is an address into a section with 'C' string literals. 615static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 616 const void *Decoder) { 617 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 618 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 619 if (SymbolLookUp) { 620 void *DisInfo = Dis->getDisInfoBlock(); 621 uint64_t ReferenceType; 622 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 623 const char *ReferenceName; 624 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 625 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 626 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 627 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 628 } 629} 630 631// Thumb1 instructions don't have explicit S bits. Rather, they 632// implicitly set CPSR. Since it's not represented in the encoding, the 633// auto-generated decoder won't inject the CPSR operand. We need to fix 634// that as a post-pass. 635static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 636 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 637 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 638 MCInst::iterator I = MI.begin(); 639 for (unsigned i = 0; i < NumOps; ++i, ++I) { 640 if (I == MI.end()) break; 641 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 642 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 644 return; 645 } 646 } 647 648 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 649} 650 651// Most Thumb instructions don't have explicit predicates in the 652// encoding, but rather get their predicates from IT context. We need 653// to fix up the predicate operands using this context information as a 654// post-pass. 655MCDisassembler::DecodeStatus 656ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 657 MCDisassembler::DecodeStatus S = Success; 658 659 // A few instructions actually have predicates encoded in them. Don't 660 // try to overwrite it if we're seeing one of those. 661 switch (MI.getOpcode()) { 662 case ARM::tBcc: 663 case ARM::t2Bcc: 664 case ARM::tCBZ: 665 case ARM::tCBNZ: 666 case ARM::tCPS: 667 case ARM::t2CPS3p: 668 case ARM::t2CPS2p: 669 case ARM::t2CPS1p: 670 case ARM::tMOVSr: 671 case ARM::tSETEND: 672 // Some instructions (mostly conditional branches) are not 673 // allowed in IT blocks. 674 if (ITBlock.instrInITBlock()) 675 S = SoftFail; 676 else 677 return Success; 678 break; 679 case ARM::tB: 680 case ARM::t2B: 681 case ARM::t2TBB: 682 case ARM::t2TBH: 683 // Some instructions (mostly unconditional branches) can 684 // only appears at the end of, or outside of, an IT. 685 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 686 S = SoftFail; 687 break; 688 default: 689 break; 690 } 691 692 // If we're in an IT block, base the predicate on that. Otherwise, 693 // assume a predicate of AL. 694 unsigned CC; 695 CC = ITBlock.getITCC(); 696 if (CC == 0xF) 697 CC = ARMCC::AL; 698 if (ITBlock.instrInITBlock()) 699 ITBlock.advanceITState(); 700 701 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 702 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 703 MCInst::iterator I = MI.begin(); 704 for (unsigned i = 0; i < NumOps; ++i, ++I) { 705 if (I == MI.end()) break; 706 if (OpInfo[i].isPredicate()) { 707 I = MI.insert(I, MCOperand::CreateImm(CC)); 708 ++I; 709 if (CC == ARMCC::AL) 710 MI.insert(I, MCOperand::CreateReg(0)); 711 else 712 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 713 return S; 714 } 715 } 716 717 I = MI.insert(I, MCOperand::CreateImm(CC)); 718 ++I; 719 if (CC == ARMCC::AL) 720 MI.insert(I, MCOperand::CreateReg(0)); 721 else 722 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 723 724 return S; 725} 726 727// Thumb VFP instructions are a special case. Because we share their 728// encodings between ARM and Thumb modes, and they are predicable in ARM 729// mode, the auto-generated decoder will give them an (incorrect) 730// predicate operand. We need to rewrite these operands based on the IT 731// context as a post-pass. 732void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 733 unsigned CC; 734 CC = ITBlock.getITCC(); 735 if (ITBlock.instrInITBlock()) 736 ITBlock.advanceITState(); 737 738 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 739 MCInst::iterator I = MI.begin(); 740 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 741 for (unsigned i = 0; i < NumOps; ++i, ++I) { 742 if (OpInfo[i].isPredicate() ) { 743 I->setImm(CC); 744 ++I; 745 if (CC == ARMCC::AL) 746 I->setReg(0); 747 else 748 I->setReg(ARM::CPSR); 749 return; 750 } 751 } 752} 753 754DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 755 const MemoryObject &Region, 756 uint64_t Address, 757 raw_ostream &os, 758 raw_ostream &cs) const { 759 CommentStream = &cs; 760 761 uint8_t bytes[4]; 762 763 assert((STI.getFeatureBits() & ARM::ModeThumb) && 764 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 765 766 // We want to read exactly 2 bytes of data. 767 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 768 Size = 0; 769 return MCDisassembler::Fail; 770 } 771 772 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 773 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 774 Address, this, STI); 775 if (result != MCDisassembler::Fail) { 776 Size = 2; 777 Check(result, AddThumbPredicate(MI)); 778 return result; 779 } 780 781 MI.clear(); 782 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 783 Address, this, STI); 784 if (result) { 785 Size = 2; 786 bool InITBlock = ITBlock.instrInITBlock(); 787 Check(result, AddThumbPredicate(MI)); 788 AddThumb1SBit(MI, InITBlock); 789 return result; 790 } 791 792 MI.clear(); 793 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 794 Address, this, STI); 795 if (result != MCDisassembler::Fail) { 796 Size = 2; 797 798 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 799 // the Thumb predicate. 800 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 801 result = MCDisassembler::SoftFail; 802 803 Check(result, AddThumbPredicate(MI)); 804 805 // If we find an IT instruction, we need to parse its condition 806 // code and mask operands so that we can apply them correctly 807 // to the subsequent instructions. 808 if (MI.getOpcode() == ARM::t2IT) { 809 810 unsigned Firstcond = MI.getOperand(0).getImm(); 811 unsigned Mask = MI.getOperand(1).getImm(); 812 ITBlock.setITState(Firstcond, Mask); 813 } 814 815 return result; 816 } 817 818 // We want to read exactly 4 bytes of data. 819 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 820 Size = 0; 821 return MCDisassembler::Fail; 822 } 823 824 uint32_t insn32 = (bytes[3] << 8) | 825 (bytes[2] << 0) | 826 (bytes[1] << 24) | 827 (bytes[0] << 16); 828 MI.clear(); 829 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 830 this, STI); 831 if (result != MCDisassembler::Fail) { 832 Size = 4; 833 bool InITBlock = ITBlock.instrInITBlock(); 834 Check(result, AddThumbPredicate(MI)); 835 AddThumb1SBit(MI, InITBlock); 836 return result; 837 } 838 839 MI.clear(); 840 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 841 this, STI); 842 if (result != MCDisassembler::Fail) { 843 Size = 4; 844 Check(result, AddThumbPredicate(MI)); 845 return result; 846 } 847 848 MI.clear(); 849 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 850 if (result != MCDisassembler::Fail) { 851 Size = 4; 852 UpdateThumbVFPPredicate(MI); 853 return result; 854 } 855 856 MI.clear(); 857 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 858 this, STI); 859 if (result != MCDisassembler::Fail) { 860 Size = 4; 861 Check(result, AddThumbPredicate(MI)); 862 return result; 863 } 864 865 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 866 MI.clear(); 867 uint32_t NEONLdStInsn = insn32; 868 NEONLdStInsn &= 0xF0FFFFFF; 869 NEONLdStInsn |= 0x04000000; 870 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 871 Address, this, STI); 872 if (result != MCDisassembler::Fail) { 873 Size = 4; 874 Check(result, AddThumbPredicate(MI)); 875 return result; 876 } 877 } 878 879 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 880 MI.clear(); 881 uint32_t NEONDataInsn = insn32; 882 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 883 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 884 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 885 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 886 Address, this, STI); 887 if (result != MCDisassembler::Fail) { 888 Size = 4; 889 Check(result, AddThumbPredicate(MI)); 890 return result; 891 } 892 } 893 894 Size = 0; 895 return MCDisassembler::Fail; 896} 897 898 899extern "C" void LLVMInitializeARMDisassembler() { 900 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 901 createARMDisassembler); 902 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 903 createThumbDisassembler); 904} 905 906static const uint16_t GPRDecoderTable[] = { 907 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 908 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 909 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 910 ARM::R12, ARM::SP, ARM::LR, ARM::PC 911}; 912 913static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 914 uint64_t Address, const void *Decoder) { 915 if (RegNo > 15) 916 return MCDisassembler::Fail; 917 918 unsigned Register = GPRDecoderTable[RegNo]; 919 Inst.addOperand(MCOperand::CreateReg(Register)); 920 return MCDisassembler::Success; 921} 922 923static DecodeStatus 924DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 925 uint64_t Address, const void *Decoder) { 926 DecodeStatus S = MCDisassembler::Success; 927 928 if (RegNo == 15) 929 S = MCDisassembler::SoftFail; 930 931 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 932 933 return S; 934} 935 936static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 937 uint64_t Address, const void *Decoder) { 938 if (RegNo > 7) 939 return MCDisassembler::Fail; 940 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 941} 942 943static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 944 uint64_t Address, const void *Decoder) { 945 unsigned Register = 0; 946 switch (RegNo) { 947 case 0: 948 Register = ARM::R0; 949 break; 950 case 1: 951 Register = ARM::R1; 952 break; 953 case 2: 954 Register = ARM::R2; 955 break; 956 case 3: 957 Register = ARM::R3; 958 break; 959 case 9: 960 Register = ARM::R9; 961 break; 962 case 12: 963 Register = ARM::R12; 964 break; 965 default: 966 return MCDisassembler::Fail; 967 } 968 969 Inst.addOperand(MCOperand::CreateReg(Register)); 970 return MCDisassembler::Success; 971} 972 973static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 974 uint64_t Address, const void *Decoder) { 975 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 976 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 977} 978 979static const uint16_t SPRDecoderTable[] = { 980 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 981 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 982 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 983 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 984 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 985 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 986 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 987 ARM::S28, ARM::S29, ARM::S30, ARM::S31 988}; 989 990static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 991 uint64_t Address, const void *Decoder) { 992 if (RegNo > 31) 993 return MCDisassembler::Fail; 994 995 unsigned Register = SPRDecoderTable[RegNo]; 996 Inst.addOperand(MCOperand::CreateReg(Register)); 997 return MCDisassembler::Success; 998} 999 1000static const uint16_t DPRDecoderTable[] = { 1001 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1002 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1003 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1004 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1005 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1006 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1007 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1008 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1009}; 1010 1011static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1012 uint64_t Address, const void *Decoder) { 1013 if (RegNo > 31) 1014 return MCDisassembler::Fail; 1015 1016 unsigned Register = DPRDecoderTable[RegNo]; 1017 Inst.addOperand(MCOperand::CreateReg(Register)); 1018 return MCDisassembler::Success; 1019} 1020 1021static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1022 uint64_t Address, const void *Decoder) { 1023 if (RegNo > 7) 1024 return MCDisassembler::Fail; 1025 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1026} 1027 1028static DecodeStatus 1029DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1030 uint64_t Address, const void *Decoder) { 1031 if (RegNo > 15) 1032 return MCDisassembler::Fail; 1033 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1034} 1035 1036static const uint16_t QPRDecoderTable[] = { 1037 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1038 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1039 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1040 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1041}; 1042 1043 1044static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1045 uint64_t Address, const void *Decoder) { 1046 if (RegNo > 31) 1047 return MCDisassembler::Fail; 1048 RegNo >>= 1; 1049 1050 unsigned Register = QPRDecoderTable[RegNo]; 1051 Inst.addOperand(MCOperand::CreateReg(Register)); 1052 return MCDisassembler::Success; 1053} 1054 1055static const uint16_t DPairDecoderTable[] = { 1056 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1057 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1058 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1059 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1060 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1061 ARM::Q15 1062}; 1063 1064static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1065 uint64_t Address, const void *Decoder) { 1066 if (RegNo > 30) 1067 return MCDisassembler::Fail; 1068 1069 unsigned Register = DPairDecoderTable[RegNo]; 1070 Inst.addOperand(MCOperand::CreateReg(Register)); 1071 return MCDisassembler::Success; 1072} 1073 1074static const uint16_t DPairSpacedDecoderTable[] = { 1075 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1076 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1077 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1078 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1079 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1080 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1081 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1082 ARM::D28_D30, ARM::D29_D31 1083}; 1084 1085static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1086 unsigned RegNo, 1087 uint64_t Address, 1088 const void *Decoder) { 1089 if (RegNo > 29) 1090 return MCDisassembler::Fail; 1091 1092 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1093 Inst.addOperand(MCOperand::CreateReg(Register)); 1094 return MCDisassembler::Success; 1095} 1096 1097static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1098 uint64_t Address, const void *Decoder) { 1099 if (Val == 0xF) return MCDisassembler::Fail; 1100 // AL predicate is not allowed on Thumb1 branches. 1101 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1102 return MCDisassembler::Fail; 1103 Inst.addOperand(MCOperand::CreateImm(Val)); 1104 if (Val == ARMCC::AL) { 1105 Inst.addOperand(MCOperand::CreateReg(0)); 1106 } else 1107 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1108 return MCDisassembler::Success; 1109} 1110 1111static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1112 uint64_t Address, const void *Decoder) { 1113 if (Val) 1114 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1115 else 1116 Inst.addOperand(MCOperand::CreateReg(0)); 1117 return MCDisassembler::Success; 1118} 1119 1120static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1121 uint64_t Address, const void *Decoder) { 1122 uint32_t imm = Val & 0xFF; 1123 uint32_t rot = (Val & 0xF00) >> 7; 1124 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1125 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1126 return MCDisassembler::Success; 1127} 1128 1129static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1130 uint64_t Address, const void *Decoder) { 1131 DecodeStatus S = MCDisassembler::Success; 1132 1133 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1134 unsigned type = fieldFromInstruction(Val, 5, 2); 1135 unsigned imm = fieldFromInstruction(Val, 7, 5); 1136 1137 // Register-immediate 1138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1139 return MCDisassembler::Fail; 1140 1141 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1142 switch (type) { 1143 case 0: 1144 Shift = ARM_AM::lsl; 1145 break; 1146 case 1: 1147 Shift = ARM_AM::lsr; 1148 break; 1149 case 2: 1150 Shift = ARM_AM::asr; 1151 break; 1152 case 3: 1153 Shift = ARM_AM::ror; 1154 break; 1155 } 1156 1157 if (Shift == ARM_AM::ror && imm == 0) 1158 Shift = ARM_AM::rrx; 1159 1160 unsigned Op = Shift | (imm << 3); 1161 Inst.addOperand(MCOperand::CreateImm(Op)); 1162 1163 return S; 1164} 1165 1166static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1167 uint64_t Address, const void *Decoder) { 1168 DecodeStatus S = MCDisassembler::Success; 1169 1170 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1171 unsigned type = fieldFromInstruction(Val, 5, 2); 1172 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1173 1174 // Register-register 1175 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1176 return MCDisassembler::Fail; 1177 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1178 return MCDisassembler::Fail; 1179 1180 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1181 switch (type) { 1182 case 0: 1183 Shift = ARM_AM::lsl; 1184 break; 1185 case 1: 1186 Shift = ARM_AM::lsr; 1187 break; 1188 case 2: 1189 Shift = ARM_AM::asr; 1190 break; 1191 case 3: 1192 Shift = ARM_AM::ror; 1193 break; 1194 } 1195 1196 Inst.addOperand(MCOperand::CreateImm(Shift)); 1197 1198 return S; 1199} 1200 1201static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1202 uint64_t Address, const void *Decoder) { 1203 DecodeStatus S = MCDisassembler::Success; 1204 1205 bool writebackLoad = false; 1206 unsigned writebackReg = 0; 1207 switch (Inst.getOpcode()) { 1208 default: 1209 break; 1210 case ARM::LDMIA_UPD: 1211 case ARM::LDMDB_UPD: 1212 case ARM::LDMIB_UPD: 1213 case ARM::LDMDA_UPD: 1214 case ARM::t2LDMIA_UPD: 1215 case ARM::t2LDMDB_UPD: 1216 writebackLoad = true; 1217 writebackReg = Inst.getOperand(0).getReg(); 1218 break; 1219 } 1220 1221 // Empty register lists are not allowed. 1222 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1223 for (unsigned i = 0; i < 16; ++i) { 1224 if (Val & (1 << i)) { 1225 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1226 return MCDisassembler::Fail; 1227 // Writeback not allowed if Rn is in the target list. 1228 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1229 Check(S, MCDisassembler::SoftFail); 1230 } 1231 } 1232 1233 return S; 1234} 1235 1236static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1237 uint64_t Address, const void *Decoder) { 1238 DecodeStatus S = MCDisassembler::Success; 1239 1240 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1241 unsigned regs = fieldFromInstruction(Val, 0, 8); 1242 1243 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1244 return MCDisassembler::Fail; 1245 for (unsigned i = 0; i < (regs - 1); ++i) { 1246 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1247 return MCDisassembler::Fail; 1248 } 1249 1250 return S; 1251} 1252 1253static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1254 uint64_t Address, const void *Decoder) { 1255 DecodeStatus S = MCDisassembler::Success; 1256 1257 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1258 unsigned regs = fieldFromInstruction(Val, 0, 8); 1259 1260 regs = regs >> 1; 1261 1262 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1263 return MCDisassembler::Fail; 1264 for (unsigned i = 0; i < (regs - 1); ++i) { 1265 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1266 return MCDisassembler::Fail; 1267 } 1268 1269 return S; 1270} 1271 1272static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1273 uint64_t Address, const void *Decoder) { 1274 // This operand encodes a mask of contiguous zeros between a specified MSB 1275 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1276 // the mask of all bits LSB-and-lower, and then xor them to create 1277 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1278 // create the final mask. 1279 unsigned msb = fieldFromInstruction(Val, 5, 5); 1280 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1281 1282 DecodeStatus S = MCDisassembler::Success; 1283 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1284 1285 uint32_t msb_mask = 0xFFFFFFFF; 1286 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1287 uint32_t lsb_mask = (1U << lsb) - 1; 1288 1289 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1290 return S; 1291} 1292 1293static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1294 uint64_t Address, const void *Decoder) { 1295 DecodeStatus S = MCDisassembler::Success; 1296 1297 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1298 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1299 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1300 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1301 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1302 unsigned U = fieldFromInstruction(Insn, 23, 1); 1303 1304 switch (Inst.getOpcode()) { 1305 case ARM::LDC_OFFSET: 1306 case ARM::LDC_PRE: 1307 case ARM::LDC_POST: 1308 case ARM::LDC_OPTION: 1309 case ARM::LDCL_OFFSET: 1310 case ARM::LDCL_PRE: 1311 case ARM::LDCL_POST: 1312 case ARM::LDCL_OPTION: 1313 case ARM::STC_OFFSET: 1314 case ARM::STC_PRE: 1315 case ARM::STC_POST: 1316 case ARM::STC_OPTION: 1317 case ARM::STCL_OFFSET: 1318 case ARM::STCL_PRE: 1319 case ARM::STCL_POST: 1320 case ARM::STCL_OPTION: 1321 case ARM::t2LDC_OFFSET: 1322 case ARM::t2LDC_PRE: 1323 case ARM::t2LDC_POST: 1324 case ARM::t2LDC_OPTION: 1325 case ARM::t2LDCL_OFFSET: 1326 case ARM::t2LDCL_PRE: 1327 case ARM::t2LDCL_POST: 1328 case ARM::t2LDCL_OPTION: 1329 case ARM::t2STC_OFFSET: 1330 case ARM::t2STC_PRE: 1331 case ARM::t2STC_POST: 1332 case ARM::t2STC_OPTION: 1333 case ARM::t2STCL_OFFSET: 1334 case ARM::t2STCL_PRE: 1335 case ARM::t2STCL_POST: 1336 case ARM::t2STCL_OPTION: 1337 if (coproc == 0xA || coproc == 0xB) 1338 return MCDisassembler::Fail; 1339 break; 1340 default: 1341 break; 1342 } 1343 1344 Inst.addOperand(MCOperand::CreateImm(coproc)); 1345 Inst.addOperand(MCOperand::CreateImm(CRd)); 1346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1347 return MCDisassembler::Fail; 1348 1349 switch (Inst.getOpcode()) { 1350 case ARM::t2LDC2_OFFSET: 1351 case ARM::t2LDC2L_OFFSET: 1352 case ARM::t2LDC2_PRE: 1353 case ARM::t2LDC2L_PRE: 1354 case ARM::t2STC2_OFFSET: 1355 case ARM::t2STC2L_OFFSET: 1356 case ARM::t2STC2_PRE: 1357 case ARM::t2STC2L_PRE: 1358 case ARM::LDC2_OFFSET: 1359 case ARM::LDC2L_OFFSET: 1360 case ARM::LDC2_PRE: 1361 case ARM::LDC2L_PRE: 1362 case ARM::STC2_OFFSET: 1363 case ARM::STC2L_OFFSET: 1364 case ARM::STC2_PRE: 1365 case ARM::STC2L_PRE: 1366 case ARM::t2LDC_OFFSET: 1367 case ARM::t2LDCL_OFFSET: 1368 case ARM::t2LDC_PRE: 1369 case ARM::t2LDCL_PRE: 1370 case ARM::t2STC_OFFSET: 1371 case ARM::t2STCL_OFFSET: 1372 case ARM::t2STC_PRE: 1373 case ARM::t2STCL_PRE: 1374 case ARM::LDC_OFFSET: 1375 case ARM::LDCL_OFFSET: 1376 case ARM::LDC_PRE: 1377 case ARM::LDCL_PRE: 1378 case ARM::STC_OFFSET: 1379 case ARM::STCL_OFFSET: 1380 case ARM::STC_PRE: 1381 case ARM::STCL_PRE: 1382 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1383 Inst.addOperand(MCOperand::CreateImm(imm)); 1384 break; 1385 case ARM::t2LDC2_POST: 1386 case ARM::t2LDC2L_POST: 1387 case ARM::t2STC2_POST: 1388 case ARM::t2STC2L_POST: 1389 case ARM::LDC2_POST: 1390 case ARM::LDC2L_POST: 1391 case ARM::STC2_POST: 1392 case ARM::STC2L_POST: 1393 case ARM::t2LDC_POST: 1394 case ARM::t2LDCL_POST: 1395 case ARM::t2STC_POST: 1396 case ARM::t2STCL_POST: 1397 case ARM::LDC_POST: 1398 case ARM::LDCL_POST: 1399 case ARM::STC_POST: 1400 case ARM::STCL_POST: 1401 imm |= U << 8; 1402 // fall through. 1403 default: 1404 // The 'option' variant doesn't encode 'U' in the immediate since 1405 // the immediate is unsigned [0,255]. 1406 Inst.addOperand(MCOperand::CreateImm(imm)); 1407 break; 1408 } 1409 1410 switch (Inst.getOpcode()) { 1411 case ARM::LDC_OFFSET: 1412 case ARM::LDC_PRE: 1413 case ARM::LDC_POST: 1414 case ARM::LDC_OPTION: 1415 case ARM::LDCL_OFFSET: 1416 case ARM::LDCL_PRE: 1417 case ARM::LDCL_POST: 1418 case ARM::LDCL_OPTION: 1419 case ARM::STC_OFFSET: 1420 case ARM::STC_PRE: 1421 case ARM::STC_POST: 1422 case ARM::STC_OPTION: 1423 case ARM::STCL_OFFSET: 1424 case ARM::STCL_PRE: 1425 case ARM::STCL_POST: 1426 case ARM::STCL_OPTION: 1427 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1428 return MCDisassembler::Fail; 1429 break; 1430 default: 1431 break; 1432 } 1433 1434 return S; 1435} 1436 1437static DecodeStatus 1438DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1439 uint64_t Address, const void *Decoder) { 1440 DecodeStatus S = MCDisassembler::Success; 1441 1442 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1443 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1444 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1445 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1446 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1447 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1448 unsigned P = fieldFromInstruction(Insn, 24, 1); 1449 unsigned W = fieldFromInstruction(Insn, 21, 1); 1450 1451 // On stores, the writeback operand precedes Rt. 1452 switch (Inst.getOpcode()) { 1453 case ARM::STR_POST_IMM: 1454 case ARM::STR_POST_REG: 1455 case ARM::STRB_POST_IMM: 1456 case ARM::STRB_POST_REG: 1457 case ARM::STRT_POST_REG: 1458 case ARM::STRT_POST_IMM: 1459 case ARM::STRBT_POST_REG: 1460 case ARM::STRBT_POST_IMM: 1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1462 return MCDisassembler::Fail; 1463 break; 1464 default: 1465 break; 1466 } 1467 1468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1469 return MCDisassembler::Fail; 1470 1471 // On loads, the writeback operand comes after Rt. 1472 switch (Inst.getOpcode()) { 1473 case ARM::LDR_POST_IMM: 1474 case ARM::LDR_POST_REG: 1475 case ARM::LDRB_POST_IMM: 1476 case ARM::LDRB_POST_REG: 1477 case ARM::LDRBT_POST_REG: 1478 case ARM::LDRBT_POST_IMM: 1479 case ARM::LDRT_POST_REG: 1480 case ARM::LDRT_POST_IMM: 1481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1482 return MCDisassembler::Fail; 1483 break; 1484 default: 1485 break; 1486 } 1487 1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1489 return MCDisassembler::Fail; 1490 1491 ARM_AM::AddrOpc Op = ARM_AM::add; 1492 if (!fieldFromInstruction(Insn, 23, 1)) 1493 Op = ARM_AM::sub; 1494 1495 bool writeback = (P == 0) || (W == 1); 1496 unsigned idx_mode = 0; 1497 if (P && writeback) 1498 idx_mode = ARMII::IndexModePre; 1499 else if (!P && writeback) 1500 idx_mode = ARMII::IndexModePost; 1501 1502 if (writeback && (Rn == 15 || Rn == Rt)) 1503 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1504 1505 if (reg) { 1506 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1507 return MCDisassembler::Fail; 1508 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1509 switch( fieldFromInstruction(Insn, 5, 2)) { 1510 case 0: 1511 Opc = ARM_AM::lsl; 1512 break; 1513 case 1: 1514 Opc = ARM_AM::lsr; 1515 break; 1516 case 2: 1517 Opc = ARM_AM::asr; 1518 break; 1519 case 3: 1520 Opc = ARM_AM::ror; 1521 break; 1522 default: 1523 return MCDisassembler::Fail; 1524 } 1525 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1526 if (Opc == ARM_AM::ror && amt == 0) 1527 Opc = ARM_AM::rrx; 1528 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1529 1530 Inst.addOperand(MCOperand::CreateImm(imm)); 1531 } else { 1532 Inst.addOperand(MCOperand::CreateReg(0)); 1533 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1534 Inst.addOperand(MCOperand::CreateImm(tmp)); 1535 } 1536 1537 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1538 return MCDisassembler::Fail; 1539 1540 return S; 1541} 1542 1543static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1544 uint64_t Address, const void *Decoder) { 1545 DecodeStatus S = MCDisassembler::Success; 1546 1547 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1548 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1549 unsigned type = fieldFromInstruction(Val, 5, 2); 1550 unsigned imm = fieldFromInstruction(Val, 7, 5); 1551 unsigned U = fieldFromInstruction(Val, 12, 1); 1552 1553 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1554 switch (type) { 1555 case 0: 1556 ShOp = ARM_AM::lsl; 1557 break; 1558 case 1: 1559 ShOp = ARM_AM::lsr; 1560 break; 1561 case 2: 1562 ShOp = ARM_AM::asr; 1563 break; 1564 case 3: 1565 ShOp = ARM_AM::ror; 1566 break; 1567 } 1568 1569 if (ShOp == ARM_AM::ror && imm == 0) 1570 ShOp = ARM_AM::rrx; 1571 1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1573 return MCDisassembler::Fail; 1574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1575 return MCDisassembler::Fail; 1576 unsigned shift; 1577 if (U) 1578 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1579 else 1580 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1581 Inst.addOperand(MCOperand::CreateImm(shift)); 1582 1583 return S; 1584} 1585 1586static DecodeStatus 1587DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1588 uint64_t Address, const void *Decoder) { 1589 DecodeStatus S = MCDisassembler::Success; 1590 1591 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1592 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1593 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1594 unsigned type = fieldFromInstruction(Insn, 22, 1); 1595 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1596 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1597 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1598 unsigned W = fieldFromInstruction(Insn, 21, 1); 1599 unsigned P = fieldFromInstruction(Insn, 24, 1); 1600 unsigned Rt2 = Rt + 1; 1601 1602 bool writeback = (W == 1) | (P == 0); 1603 1604 // For {LD,ST}RD, Rt must be even, else undefined. 1605 switch (Inst.getOpcode()) { 1606 case ARM::STRD: 1607 case ARM::STRD_PRE: 1608 case ARM::STRD_POST: 1609 case ARM::LDRD: 1610 case ARM::LDRD_PRE: 1611 case ARM::LDRD_POST: 1612 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1613 break; 1614 default: 1615 break; 1616 } 1617 switch (Inst.getOpcode()) { 1618 case ARM::STRD: 1619 case ARM::STRD_PRE: 1620 case ARM::STRD_POST: 1621 if (P == 0 && W == 1) 1622 S = MCDisassembler::SoftFail; 1623 1624 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1625 S = MCDisassembler::SoftFail; 1626 if (type && Rm == 15) 1627 S = MCDisassembler::SoftFail; 1628 if (Rt2 == 15) 1629 S = MCDisassembler::SoftFail; 1630 if (!type && fieldFromInstruction(Insn, 8, 4)) 1631 S = MCDisassembler::SoftFail; 1632 break; 1633 case ARM::STRH: 1634 case ARM::STRH_PRE: 1635 case ARM::STRH_POST: 1636 if (Rt == 15) 1637 S = MCDisassembler::SoftFail; 1638 if (writeback && (Rn == 15 || Rn == Rt)) 1639 S = MCDisassembler::SoftFail; 1640 if (!type && Rm == 15) 1641 S = MCDisassembler::SoftFail; 1642 break; 1643 case ARM::LDRD: 1644 case ARM::LDRD_PRE: 1645 case ARM::LDRD_POST: 1646 if (type && Rn == 15){ 1647 if (Rt2 == 15) 1648 S = MCDisassembler::SoftFail; 1649 break; 1650 } 1651 if (P == 0 && W == 1) 1652 S = MCDisassembler::SoftFail; 1653 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1654 S = MCDisassembler::SoftFail; 1655 if (!type && writeback && Rn == 15) 1656 S = MCDisassembler::SoftFail; 1657 if (writeback && (Rn == Rt || Rn == Rt2)) 1658 S = MCDisassembler::SoftFail; 1659 break; 1660 case ARM::LDRH: 1661 case ARM::LDRH_PRE: 1662 case ARM::LDRH_POST: 1663 if (type && Rn == 15){ 1664 if (Rt == 15) 1665 S = MCDisassembler::SoftFail; 1666 break; 1667 } 1668 if (Rt == 15) 1669 S = MCDisassembler::SoftFail; 1670 if (!type && Rm == 15) 1671 S = MCDisassembler::SoftFail; 1672 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1673 S = MCDisassembler::SoftFail; 1674 break; 1675 case ARM::LDRSH: 1676 case ARM::LDRSH_PRE: 1677 case ARM::LDRSH_POST: 1678 case ARM::LDRSB: 1679 case ARM::LDRSB_PRE: 1680 case ARM::LDRSB_POST: 1681 if (type && Rn == 15){ 1682 if (Rt == 15) 1683 S = MCDisassembler::SoftFail; 1684 break; 1685 } 1686 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1687 S = MCDisassembler::SoftFail; 1688 if (!type && (Rt == 15 || Rm == 15)) 1689 S = MCDisassembler::SoftFail; 1690 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1691 S = MCDisassembler::SoftFail; 1692 break; 1693 default: 1694 break; 1695 } 1696 1697 if (writeback) { // Writeback 1698 if (P) 1699 U |= ARMII::IndexModePre << 9; 1700 else 1701 U |= ARMII::IndexModePost << 9; 1702 1703 // On stores, the writeback operand precedes Rt. 1704 switch (Inst.getOpcode()) { 1705 case ARM::STRD: 1706 case ARM::STRD_PRE: 1707 case ARM::STRD_POST: 1708 case ARM::STRH: 1709 case ARM::STRH_PRE: 1710 case ARM::STRH_POST: 1711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1712 return MCDisassembler::Fail; 1713 break; 1714 default: 1715 break; 1716 } 1717 } 1718 1719 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1720 return MCDisassembler::Fail; 1721 switch (Inst.getOpcode()) { 1722 case ARM::STRD: 1723 case ARM::STRD_PRE: 1724 case ARM::STRD_POST: 1725 case ARM::LDRD: 1726 case ARM::LDRD_PRE: 1727 case ARM::LDRD_POST: 1728 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1729 return MCDisassembler::Fail; 1730 break; 1731 default: 1732 break; 1733 } 1734 1735 if (writeback) { 1736 // On loads, the writeback operand comes after Rt. 1737 switch (Inst.getOpcode()) { 1738 case ARM::LDRD: 1739 case ARM::LDRD_PRE: 1740 case ARM::LDRD_POST: 1741 case ARM::LDRH: 1742 case ARM::LDRH_PRE: 1743 case ARM::LDRH_POST: 1744 case ARM::LDRSH: 1745 case ARM::LDRSH_PRE: 1746 case ARM::LDRSH_POST: 1747 case ARM::LDRSB: 1748 case ARM::LDRSB_PRE: 1749 case ARM::LDRSB_POST: 1750 case ARM::LDRHTr: 1751 case ARM::LDRSBTr: 1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1753 return MCDisassembler::Fail; 1754 break; 1755 default: 1756 break; 1757 } 1758 } 1759 1760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1761 return MCDisassembler::Fail; 1762 1763 if (type) { 1764 Inst.addOperand(MCOperand::CreateReg(0)); 1765 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1766 } else { 1767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1768 return MCDisassembler::Fail; 1769 Inst.addOperand(MCOperand::CreateImm(U)); 1770 } 1771 1772 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1773 return MCDisassembler::Fail; 1774 1775 return S; 1776} 1777 1778static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1779 uint64_t Address, const void *Decoder) { 1780 DecodeStatus S = MCDisassembler::Success; 1781 1782 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1783 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1784 1785 switch (mode) { 1786 case 0: 1787 mode = ARM_AM::da; 1788 break; 1789 case 1: 1790 mode = ARM_AM::ia; 1791 break; 1792 case 2: 1793 mode = ARM_AM::db; 1794 break; 1795 case 3: 1796 mode = ARM_AM::ib; 1797 break; 1798 } 1799 1800 Inst.addOperand(MCOperand::CreateImm(mode)); 1801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1802 return MCDisassembler::Fail; 1803 1804 return S; 1805} 1806 1807static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1808 unsigned Insn, 1809 uint64_t Address, const void *Decoder) { 1810 DecodeStatus S = MCDisassembler::Success; 1811 1812 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1813 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1814 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1815 1816 if (pred == 0xF) { 1817 switch (Inst.getOpcode()) { 1818 case ARM::LDMDA: 1819 Inst.setOpcode(ARM::RFEDA); 1820 break; 1821 case ARM::LDMDA_UPD: 1822 Inst.setOpcode(ARM::RFEDA_UPD); 1823 break; 1824 case ARM::LDMDB: 1825 Inst.setOpcode(ARM::RFEDB); 1826 break; 1827 case ARM::LDMDB_UPD: 1828 Inst.setOpcode(ARM::RFEDB_UPD); 1829 break; 1830 case ARM::LDMIA: 1831 Inst.setOpcode(ARM::RFEIA); 1832 break; 1833 case ARM::LDMIA_UPD: 1834 Inst.setOpcode(ARM::RFEIA_UPD); 1835 break; 1836 case ARM::LDMIB: 1837 Inst.setOpcode(ARM::RFEIB); 1838 break; 1839 case ARM::LDMIB_UPD: 1840 Inst.setOpcode(ARM::RFEIB_UPD); 1841 break; 1842 case ARM::STMDA: 1843 Inst.setOpcode(ARM::SRSDA); 1844 break; 1845 case ARM::STMDA_UPD: 1846 Inst.setOpcode(ARM::SRSDA_UPD); 1847 break; 1848 case ARM::STMDB: 1849 Inst.setOpcode(ARM::SRSDB); 1850 break; 1851 case ARM::STMDB_UPD: 1852 Inst.setOpcode(ARM::SRSDB_UPD); 1853 break; 1854 case ARM::STMIA: 1855 Inst.setOpcode(ARM::SRSIA); 1856 break; 1857 case ARM::STMIA_UPD: 1858 Inst.setOpcode(ARM::SRSIA_UPD); 1859 break; 1860 case ARM::STMIB: 1861 Inst.setOpcode(ARM::SRSIB); 1862 break; 1863 case ARM::STMIB_UPD: 1864 Inst.setOpcode(ARM::SRSIB_UPD); 1865 break; 1866 default: 1867 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1868 } 1869 1870 // For stores (which become SRS's, the only operand is the mode. 1871 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1872 Inst.addOperand( 1873 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1874 return S; 1875 } 1876 1877 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1878 } 1879 1880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1881 return MCDisassembler::Fail; 1882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1883 return MCDisassembler::Fail; // Tied 1884 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1885 return MCDisassembler::Fail; 1886 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1887 return MCDisassembler::Fail; 1888 1889 return S; 1890} 1891 1892static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1893 uint64_t Address, const void *Decoder) { 1894 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1895 unsigned M = fieldFromInstruction(Insn, 17, 1); 1896 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1897 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1898 1899 DecodeStatus S = MCDisassembler::Success; 1900 1901 // imod == '01' --> UNPREDICTABLE 1902 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1903 // return failure here. The '01' imod value is unprintable, so there's 1904 // nothing useful we could do even if we returned UNPREDICTABLE. 1905 1906 if (imod == 1) return MCDisassembler::Fail; 1907 1908 if (imod && M) { 1909 Inst.setOpcode(ARM::CPS3p); 1910 Inst.addOperand(MCOperand::CreateImm(imod)); 1911 Inst.addOperand(MCOperand::CreateImm(iflags)); 1912 Inst.addOperand(MCOperand::CreateImm(mode)); 1913 } else if (imod && !M) { 1914 Inst.setOpcode(ARM::CPS2p); 1915 Inst.addOperand(MCOperand::CreateImm(imod)); 1916 Inst.addOperand(MCOperand::CreateImm(iflags)); 1917 if (mode) S = MCDisassembler::SoftFail; 1918 } else if (!imod && M) { 1919 Inst.setOpcode(ARM::CPS1p); 1920 Inst.addOperand(MCOperand::CreateImm(mode)); 1921 if (iflags) S = MCDisassembler::SoftFail; 1922 } else { 1923 // imod == '00' && M == '0' --> UNPREDICTABLE 1924 Inst.setOpcode(ARM::CPS1p); 1925 Inst.addOperand(MCOperand::CreateImm(mode)); 1926 S = MCDisassembler::SoftFail; 1927 } 1928 1929 return S; 1930} 1931 1932static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1933 uint64_t Address, const void *Decoder) { 1934 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1935 unsigned M = fieldFromInstruction(Insn, 8, 1); 1936 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1937 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1938 1939 DecodeStatus S = MCDisassembler::Success; 1940 1941 // imod == '01' --> UNPREDICTABLE 1942 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1943 // return failure here. The '01' imod value is unprintable, so there's 1944 // nothing useful we could do even if we returned UNPREDICTABLE. 1945 1946 if (imod == 1) return MCDisassembler::Fail; 1947 1948 if (imod && M) { 1949 Inst.setOpcode(ARM::t2CPS3p); 1950 Inst.addOperand(MCOperand::CreateImm(imod)); 1951 Inst.addOperand(MCOperand::CreateImm(iflags)); 1952 Inst.addOperand(MCOperand::CreateImm(mode)); 1953 } else if (imod && !M) { 1954 Inst.setOpcode(ARM::t2CPS2p); 1955 Inst.addOperand(MCOperand::CreateImm(imod)); 1956 Inst.addOperand(MCOperand::CreateImm(iflags)); 1957 if (mode) S = MCDisassembler::SoftFail; 1958 } else if (!imod && M) { 1959 Inst.setOpcode(ARM::t2CPS1p); 1960 Inst.addOperand(MCOperand::CreateImm(mode)); 1961 if (iflags) S = MCDisassembler::SoftFail; 1962 } else { 1963 // imod == '00' && M == '0' --> UNPREDICTABLE 1964 Inst.setOpcode(ARM::t2CPS1p); 1965 Inst.addOperand(MCOperand::CreateImm(mode)); 1966 S = MCDisassembler::SoftFail; 1967 } 1968 1969 return S; 1970} 1971 1972static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1973 uint64_t Address, const void *Decoder) { 1974 DecodeStatus S = MCDisassembler::Success; 1975 1976 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1977 unsigned imm = 0; 1978 1979 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1980 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1981 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1982 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1983 1984 if (Inst.getOpcode() == ARM::t2MOVTi16) 1985 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1986 return MCDisassembler::Fail; 1987 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1988 return MCDisassembler::Fail; 1989 1990 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1991 Inst.addOperand(MCOperand::CreateImm(imm)); 1992 1993 return S; 1994} 1995 1996static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1997 uint64_t Address, const void *Decoder) { 1998 DecodeStatus S = MCDisassembler::Success; 1999 2000 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2001 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2002 unsigned imm = 0; 2003 2004 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2005 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2006 2007 if (Inst.getOpcode() == ARM::MOVTi16) 2008 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2009 return MCDisassembler::Fail; 2010 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2011 return MCDisassembler::Fail; 2012 2013 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2014 Inst.addOperand(MCOperand::CreateImm(imm)); 2015 2016 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2017 return MCDisassembler::Fail; 2018 2019 return S; 2020} 2021 2022static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2023 uint64_t Address, const void *Decoder) { 2024 DecodeStatus S = MCDisassembler::Success; 2025 2026 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2027 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2028 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2029 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2030 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2031 2032 if (pred == 0xF) 2033 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2034 2035 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2036 return MCDisassembler::Fail; 2037 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2038 return MCDisassembler::Fail; 2039 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2040 return MCDisassembler::Fail; 2041 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2042 return MCDisassembler::Fail; 2043 2044 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2045 return MCDisassembler::Fail; 2046 2047 return S; 2048} 2049 2050static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2051 uint64_t Address, const void *Decoder) { 2052 DecodeStatus S = MCDisassembler::Success; 2053 2054 unsigned add = fieldFromInstruction(Val, 12, 1); 2055 unsigned imm = fieldFromInstruction(Val, 0, 12); 2056 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2057 2058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2059 return MCDisassembler::Fail; 2060 2061 if (!add) imm *= -1; 2062 if (imm == 0 && !add) imm = INT32_MIN; 2063 Inst.addOperand(MCOperand::CreateImm(imm)); 2064 if (Rn == 15) 2065 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2066 2067 return S; 2068} 2069 2070static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2071 uint64_t Address, const void *Decoder) { 2072 DecodeStatus S = MCDisassembler::Success; 2073 2074 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2075 unsigned U = fieldFromInstruction(Val, 8, 1); 2076 unsigned imm = fieldFromInstruction(Val, 0, 8); 2077 2078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2079 return MCDisassembler::Fail; 2080 2081 if (U) 2082 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2083 else 2084 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2085 2086 return S; 2087} 2088 2089static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2090 uint64_t Address, const void *Decoder) { 2091 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2092} 2093 2094static DecodeStatus 2095DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2096 uint64_t Address, const void *Decoder) { 2097 DecodeStatus Status = MCDisassembler::Success; 2098 2099 // Note the J1 and J2 values are from the encoded instruction. So here 2100 // change them to I1 and I2 values via as documented: 2101 // I1 = NOT(J1 EOR S); 2102 // I2 = NOT(J2 EOR S); 2103 // and build the imm32 with one trailing zero as documented: 2104 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2105 unsigned S = fieldFromInstruction(Insn, 26, 1); 2106 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2107 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2108 unsigned I1 = !(J1 ^ S); 2109 unsigned I2 = !(J2 ^ S); 2110 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2111 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2112 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2113 int imm32 = SignExtend32<24>(tmp << 1); 2114 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2115 true, 4, Inst, Decoder)) 2116 Inst.addOperand(MCOperand::CreateImm(imm32)); 2117 2118 return Status; 2119} 2120 2121static DecodeStatus 2122DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2123 uint64_t Address, const void *Decoder) { 2124 DecodeStatus S = MCDisassembler::Success; 2125 2126 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2127 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2128 2129 if (pred == 0xF) { 2130 Inst.setOpcode(ARM::BLXi); 2131 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2132 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2133 true, 4, Inst, Decoder)) 2134 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2135 return S; 2136 } 2137 2138 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2139 true, 4, Inst, Decoder)) 2140 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2141 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2142 return MCDisassembler::Fail; 2143 2144 return S; 2145} 2146 2147 2148static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2149 uint64_t Address, const void *Decoder) { 2150 DecodeStatus S = MCDisassembler::Success; 2151 2152 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2153 unsigned align = fieldFromInstruction(Val, 4, 2); 2154 2155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2156 return MCDisassembler::Fail; 2157 if (!align) 2158 Inst.addOperand(MCOperand::CreateImm(0)); 2159 else 2160 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2161 2162 return S; 2163} 2164 2165static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2166 uint64_t Address, const void *Decoder) { 2167 DecodeStatus S = MCDisassembler::Success; 2168 2169 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2170 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2171 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2172 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2173 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2174 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2175 2176 // First output register 2177 switch (Inst.getOpcode()) { 2178 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2179 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2180 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2181 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2182 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2183 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2184 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2185 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2186 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2187 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2188 return MCDisassembler::Fail; 2189 break; 2190 case ARM::VLD2b16: 2191 case ARM::VLD2b32: 2192 case ARM::VLD2b8: 2193 case ARM::VLD2b16wb_fixed: 2194 case ARM::VLD2b16wb_register: 2195 case ARM::VLD2b32wb_fixed: 2196 case ARM::VLD2b32wb_register: 2197 case ARM::VLD2b8wb_fixed: 2198 case ARM::VLD2b8wb_register: 2199 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2200 return MCDisassembler::Fail; 2201 break; 2202 default: 2203 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2204 return MCDisassembler::Fail; 2205 } 2206 2207 // Second output register 2208 switch (Inst.getOpcode()) { 2209 case ARM::VLD3d8: 2210 case ARM::VLD3d16: 2211 case ARM::VLD3d32: 2212 case ARM::VLD3d8_UPD: 2213 case ARM::VLD3d16_UPD: 2214 case ARM::VLD3d32_UPD: 2215 case ARM::VLD4d8: 2216 case ARM::VLD4d16: 2217 case ARM::VLD4d32: 2218 case ARM::VLD4d8_UPD: 2219 case ARM::VLD4d16_UPD: 2220 case ARM::VLD4d32_UPD: 2221 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2222 return MCDisassembler::Fail; 2223 break; 2224 case ARM::VLD3q8: 2225 case ARM::VLD3q16: 2226 case ARM::VLD3q32: 2227 case ARM::VLD3q8_UPD: 2228 case ARM::VLD3q16_UPD: 2229 case ARM::VLD3q32_UPD: 2230 case ARM::VLD4q8: 2231 case ARM::VLD4q16: 2232 case ARM::VLD4q32: 2233 case ARM::VLD4q8_UPD: 2234 case ARM::VLD4q16_UPD: 2235 case ARM::VLD4q32_UPD: 2236 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2237 return MCDisassembler::Fail; 2238 default: 2239 break; 2240 } 2241 2242 // Third output register 2243 switch(Inst.getOpcode()) { 2244 case ARM::VLD3d8: 2245 case ARM::VLD3d16: 2246 case ARM::VLD3d32: 2247 case ARM::VLD3d8_UPD: 2248 case ARM::VLD3d16_UPD: 2249 case ARM::VLD3d32_UPD: 2250 case ARM::VLD4d8: 2251 case ARM::VLD4d16: 2252 case ARM::VLD4d32: 2253 case ARM::VLD4d8_UPD: 2254 case ARM::VLD4d16_UPD: 2255 case ARM::VLD4d32_UPD: 2256 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2257 return MCDisassembler::Fail; 2258 break; 2259 case ARM::VLD3q8: 2260 case ARM::VLD3q16: 2261 case ARM::VLD3q32: 2262 case ARM::VLD3q8_UPD: 2263 case ARM::VLD3q16_UPD: 2264 case ARM::VLD3q32_UPD: 2265 case ARM::VLD4q8: 2266 case ARM::VLD4q16: 2267 case ARM::VLD4q32: 2268 case ARM::VLD4q8_UPD: 2269 case ARM::VLD4q16_UPD: 2270 case ARM::VLD4q32_UPD: 2271 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2272 return MCDisassembler::Fail; 2273 break; 2274 default: 2275 break; 2276 } 2277 2278 // Fourth output register 2279 switch (Inst.getOpcode()) { 2280 case ARM::VLD4d8: 2281 case ARM::VLD4d16: 2282 case ARM::VLD4d32: 2283 case ARM::VLD4d8_UPD: 2284 case ARM::VLD4d16_UPD: 2285 case ARM::VLD4d32_UPD: 2286 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2287 return MCDisassembler::Fail; 2288 break; 2289 case ARM::VLD4q8: 2290 case ARM::VLD4q16: 2291 case ARM::VLD4q32: 2292 case ARM::VLD4q8_UPD: 2293 case ARM::VLD4q16_UPD: 2294 case ARM::VLD4q32_UPD: 2295 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2296 return MCDisassembler::Fail; 2297 break; 2298 default: 2299 break; 2300 } 2301 2302 // Writeback operand 2303 switch (Inst.getOpcode()) { 2304 case ARM::VLD1d8wb_fixed: 2305 case ARM::VLD1d16wb_fixed: 2306 case ARM::VLD1d32wb_fixed: 2307 case ARM::VLD1d64wb_fixed: 2308 case ARM::VLD1d8wb_register: 2309 case ARM::VLD1d16wb_register: 2310 case ARM::VLD1d32wb_register: 2311 case ARM::VLD1d64wb_register: 2312 case ARM::VLD1q8wb_fixed: 2313 case ARM::VLD1q16wb_fixed: 2314 case ARM::VLD1q32wb_fixed: 2315 case ARM::VLD1q64wb_fixed: 2316 case ARM::VLD1q8wb_register: 2317 case ARM::VLD1q16wb_register: 2318 case ARM::VLD1q32wb_register: 2319 case ARM::VLD1q64wb_register: 2320 case ARM::VLD1d8Twb_fixed: 2321 case ARM::VLD1d8Twb_register: 2322 case ARM::VLD1d16Twb_fixed: 2323 case ARM::VLD1d16Twb_register: 2324 case ARM::VLD1d32Twb_fixed: 2325 case ARM::VLD1d32Twb_register: 2326 case ARM::VLD1d64Twb_fixed: 2327 case ARM::VLD1d64Twb_register: 2328 case ARM::VLD1d8Qwb_fixed: 2329 case ARM::VLD1d8Qwb_register: 2330 case ARM::VLD1d16Qwb_fixed: 2331 case ARM::VLD1d16Qwb_register: 2332 case ARM::VLD1d32Qwb_fixed: 2333 case ARM::VLD1d32Qwb_register: 2334 case ARM::VLD1d64Qwb_fixed: 2335 case ARM::VLD1d64Qwb_register: 2336 case ARM::VLD2d8wb_fixed: 2337 case ARM::VLD2d16wb_fixed: 2338 case ARM::VLD2d32wb_fixed: 2339 case ARM::VLD2q8wb_fixed: 2340 case ARM::VLD2q16wb_fixed: 2341 case ARM::VLD2q32wb_fixed: 2342 case ARM::VLD2d8wb_register: 2343 case ARM::VLD2d16wb_register: 2344 case ARM::VLD2d32wb_register: 2345 case ARM::VLD2q8wb_register: 2346 case ARM::VLD2q16wb_register: 2347 case ARM::VLD2q32wb_register: 2348 case ARM::VLD2b8wb_fixed: 2349 case ARM::VLD2b16wb_fixed: 2350 case ARM::VLD2b32wb_fixed: 2351 case ARM::VLD2b8wb_register: 2352 case ARM::VLD2b16wb_register: 2353 case ARM::VLD2b32wb_register: 2354 Inst.addOperand(MCOperand::CreateImm(0)); 2355 break; 2356 case ARM::VLD3d8_UPD: 2357 case ARM::VLD3d16_UPD: 2358 case ARM::VLD3d32_UPD: 2359 case ARM::VLD3q8_UPD: 2360 case ARM::VLD3q16_UPD: 2361 case ARM::VLD3q32_UPD: 2362 case ARM::VLD4d8_UPD: 2363 case ARM::VLD4d16_UPD: 2364 case ARM::VLD4d32_UPD: 2365 case ARM::VLD4q8_UPD: 2366 case ARM::VLD4q16_UPD: 2367 case ARM::VLD4q32_UPD: 2368 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2369 return MCDisassembler::Fail; 2370 break; 2371 default: 2372 break; 2373 } 2374 2375 // AddrMode6 Base (register+alignment) 2376 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2377 return MCDisassembler::Fail; 2378 2379 // AddrMode6 Offset (register) 2380 switch (Inst.getOpcode()) { 2381 default: 2382 // The below have been updated to have explicit am6offset split 2383 // between fixed and register offset. For those instructions not 2384 // yet updated, we need to add an additional reg0 operand for the 2385 // fixed variant. 2386 // 2387 // The fixed offset encodes as Rm == 0xd, so we check for that. 2388 if (Rm == 0xd) { 2389 Inst.addOperand(MCOperand::CreateReg(0)); 2390 break; 2391 } 2392 // Fall through to handle the register offset variant. 2393 case ARM::VLD1d8wb_fixed: 2394 case ARM::VLD1d16wb_fixed: 2395 case ARM::VLD1d32wb_fixed: 2396 case ARM::VLD1d64wb_fixed: 2397 case ARM::VLD1d8Twb_fixed: 2398 case ARM::VLD1d16Twb_fixed: 2399 case ARM::VLD1d32Twb_fixed: 2400 case ARM::VLD1d64Twb_fixed: 2401 case ARM::VLD1d8Qwb_fixed: 2402 case ARM::VLD1d16Qwb_fixed: 2403 case ARM::VLD1d32Qwb_fixed: 2404 case ARM::VLD1d64Qwb_fixed: 2405 case ARM::VLD1d8wb_register: 2406 case ARM::VLD1d16wb_register: 2407 case ARM::VLD1d32wb_register: 2408 case ARM::VLD1d64wb_register: 2409 case ARM::VLD1q8wb_fixed: 2410 case ARM::VLD1q16wb_fixed: 2411 case ARM::VLD1q32wb_fixed: 2412 case ARM::VLD1q64wb_fixed: 2413 case ARM::VLD1q8wb_register: 2414 case ARM::VLD1q16wb_register: 2415 case ARM::VLD1q32wb_register: 2416 case ARM::VLD1q64wb_register: 2417 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2418 // variant encodes Rm == 0xf. Anything else is a register offset post- 2419 // increment and we need to add the register operand to the instruction. 2420 if (Rm != 0xD && Rm != 0xF && 2421 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2422 return MCDisassembler::Fail; 2423 break; 2424 case ARM::VLD2d8wb_fixed: 2425 case ARM::VLD2d16wb_fixed: 2426 case ARM::VLD2d32wb_fixed: 2427 case ARM::VLD2b8wb_fixed: 2428 case ARM::VLD2b16wb_fixed: 2429 case ARM::VLD2b32wb_fixed: 2430 case ARM::VLD2q8wb_fixed: 2431 case ARM::VLD2q16wb_fixed: 2432 case ARM::VLD2q32wb_fixed: 2433 break; 2434 } 2435 2436 return S; 2437} 2438 2439static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2440 uint64_t Address, const void *Decoder) { 2441 DecodeStatus S = MCDisassembler::Success; 2442 2443 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2444 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2445 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2446 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2447 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2448 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2449 2450 // Writeback Operand 2451 switch (Inst.getOpcode()) { 2452 case ARM::VST1d8wb_fixed: 2453 case ARM::VST1d16wb_fixed: 2454 case ARM::VST1d32wb_fixed: 2455 case ARM::VST1d64wb_fixed: 2456 case ARM::VST1d8wb_register: 2457 case ARM::VST1d16wb_register: 2458 case ARM::VST1d32wb_register: 2459 case ARM::VST1d64wb_register: 2460 case ARM::VST1q8wb_fixed: 2461 case ARM::VST1q16wb_fixed: 2462 case ARM::VST1q32wb_fixed: 2463 case ARM::VST1q64wb_fixed: 2464 case ARM::VST1q8wb_register: 2465 case ARM::VST1q16wb_register: 2466 case ARM::VST1q32wb_register: 2467 case ARM::VST1q64wb_register: 2468 case ARM::VST1d8Twb_fixed: 2469 case ARM::VST1d16Twb_fixed: 2470 case ARM::VST1d32Twb_fixed: 2471 case ARM::VST1d64Twb_fixed: 2472 case ARM::VST1d8Twb_register: 2473 case ARM::VST1d16Twb_register: 2474 case ARM::VST1d32Twb_register: 2475 case ARM::VST1d64Twb_register: 2476 case ARM::VST1d8Qwb_fixed: 2477 case ARM::VST1d16Qwb_fixed: 2478 case ARM::VST1d32Qwb_fixed: 2479 case ARM::VST1d64Qwb_fixed: 2480 case ARM::VST1d8Qwb_register: 2481 case ARM::VST1d16Qwb_register: 2482 case ARM::VST1d32Qwb_register: 2483 case ARM::VST1d64Qwb_register: 2484 case ARM::VST2d8wb_fixed: 2485 case ARM::VST2d16wb_fixed: 2486 case ARM::VST2d32wb_fixed: 2487 case ARM::VST2d8wb_register: 2488 case ARM::VST2d16wb_register: 2489 case ARM::VST2d32wb_register: 2490 case ARM::VST2q8wb_fixed: 2491 case ARM::VST2q16wb_fixed: 2492 case ARM::VST2q32wb_fixed: 2493 case ARM::VST2q8wb_register: 2494 case ARM::VST2q16wb_register: 2495 case ARM::VST2q32wb_register: 2496 case ARM::VST2b8wb_fixed: 2497 case ARM::VST2b16wb_fixed: 2498 case ARM::VST2b32wb_fixed: 2499 case ARM::VST2b8wb_register: 2500 case ARM::VST2b16wb_register: 2501 case ARM::VST2b32wb_register: 2502 if (Rm == 0xF) 2503 return MCDisassembler::Fail; 2504 Inst.addOperand(MCOperand::CreateImm(0)); 2505 break; 2506 case ARM::VST3d8_UPD: 2507 case ARM::VST3d16_UPD: 2508 case ARM::VST3d32_UPD: 2509 case ARM::VST3q8_UPD: 2510 case ARM::VST3q16_UPD: 2511 case ARM::VST3q32_UPD: 2512 case ARM::VST4d8_UPD: 2513 case ARM::VST4d16_UPD: 2514 case ARM::VST4d32_UPD: 2515 case ARM::VST4q8_UPD: 2516 case ARM::VST4q16_UPD: 2517 case ARM::VST4q32_UPD: 2518 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2519 return MCDisassembler::Fail; 2520 break; 2521 default: 2522 break; 2523 } 2524 2525 // AddrMode6 Base (register+alignment) 2526 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2527 return MCDisassembler::Fail; 2528 2529 // AddrMode6 Offset (register) 2530 switch (Inst.getOpcode()) { 2531 default: 2532 if (Rm == 0xD) 2533 Inst.addOperand(MCOperand::CreateReg(0)); 2534 else if (Rm != 0xF) { 2535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2536 return MCDisassembler::Fail; 2537 } 2538 break; 2539 case ARM::VST1d8wb_fixed: 2540 case ARM::VST1d16wb_fixed: 2541 case ARM::VST1d32wb_fixed: 2542 case ARM::VST1d64wb_fixed: 2543 case ARM::VST1q8wb_fixed: 2544 case ARM::VST1q16wb_fixed: 2545 case ARM::VST1q32wb_fixed: 2546 case ARM::VST1q64wb_fixed: 2547 case ARM::VST1d8Twb_fixed: 2548 case ARM::VST1d16Twb_fixed: 2549 case ARM::VST1d32Twb_fixed: 2550 case ARM::VST1d64Twb_fixed: 2551 case ARM::VST1d8Qwb_fixed: 2552 case ARM::VST1d16Qwb_fixed: 2553 case ARM::VST1d32Qwb_fixed: 2554 case ARM::VST1d64Qwb_fixed: 2555 case ARM::VST2d8wb_fixed: 2556 case ARM::VST2d16wb_fixed: 2557 case ARM::VST2d32wb_fixed: 2558 case ARM::VST2q8wb_fixed: 2559 case ARM::VST2q16wb_fixed: 2560 case ARM::VST2q32wb_fixed: 2561 case ARM::VST2b8wb_fixed: 2562 case ARM::VST2b16wb_fixed: 2563 case ARM::VST2b32wb_fixed: 2564 break; 2565 } 2566 2567 2568 // First input register 2569 switch (Inst.getOpcode()) { 2570 case ARM::VST1q16: 2571 case ARM::VST1q32: 2572 case ARM::VST1q64: 2573 case ARM::VST1q8: 2574 case ARM::VST1q16wb_fixed: 2575 case ARM::VST1q16wb_register: 2576 case ARM::VST1q32wb_fixed: 2577 case ARM::VST1q32wb_register: 2578 case ARM::VST1q64wb_fixed: 2579 case ARM::VST1q64wb_register: 2580 case ARM::VST1q8wb_fixed: 2581 case ARM::VST1q8wb_register: 2582 case ARM::VST2d16: 2583 case ARM::VST2d32: 2584 case ARM::VST2d8: 2585 case ARM::VST2d16wb_fixed: 2586 case ARM::VST2d16wb_register: 2587 case ARM::VST2d32wb_fixed: 2588 case ARM::VST2d32wb_register: 2589 case ARM::VST2d8wb_fixed: 2590 case ARM::VST2d8wb_register: 2591 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2592 return MCDisassembler::Fail; 2593 break; 2594 case ARM::VST2b16: 2595 case ARM::VST2b32: 2596 case ARM::VST2b8: 2597 case ARM::VST2b16wb_fixed: 2598 case ARM::VST2b16wb_register: 2599 case ARM::VST2b32wb_fixed: 2600 case ARM::VST2b32wb_register: 2601 case ARM::VST2b8wb_fixed: 2602 case ARM::VST2b8wb_register: 2603 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2604 return MCDisassembler::Fail; 2605 break; 2606 default: 2607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2608 return MCDisassembler::Fail; 2609 } 2610 2611 // Second input register 2612 switch (Inst.getOpcode()) { 2613 case ARM::VST3d8: 2614 case ARM::VST3d16: 2615 case ARM::VST3d32: 2616 case ARM::VST3d8_UPD: 2617 case ARM::VST3d16_UPD: 2618 case ARM::VST3d32_UPD: 2619 case ARM::VST4d8: 2620 case ARM::VST4d16: 2621 case ARM::VST4d32: 2622 case ARM::VST4d8_UPD: 2623 case ARM::VST4d16_UPD: 2624 case ARM::VST4d32_UPD: 2625 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2626 return MCDisassembler::Fail; 2627 break; 2628 case ARM::VST3q8: 2629 case ARM::VST3q16: 2630 case ARM::VST3q32: 2631 case ARM::VST3q8_UPD: 2632 case ARM::VST3q16_UPD: 2633 case ARM::VST3q32_UPD: 2634 case ARM::VST4q8: 2635 case ARM::VST4q16: 2636 case ARM::VST4q32: 2637 case ARM::VST4q8_UPD: 2638 case ARM::VST4q16_UPD: 2639 case ARM::VST4q32_UPD: 2640 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2641 return MCDisassembler::Fail; 2642 break; 2643 default: 2644 break; 2645 } 2646 2647 // Third input register 2648 switch (Inst.getOpcode()) { 2649 case ARM::VST3d8: 2650 case ARM::VST3d16: 2651 case ARM::VST3d32: 2652 case ARM::VST3d8_UPD: 2653 case ARM::VST3d16_UPD: 2654 case ARM::VST3d32_UPD: 2655 case ARM::VST4d8: 2656 case ARM::VST4d16: 2657 case ARM::VST4d32: 2658 case ARM::VST4d8_UPD: 2659 case ARM::VST4d16_UPD: 2660 case ARM::VST4d32_UPD: 2661 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2662 return MCDisassembler::Fail; 2663 break; 2664 case ARM::VST3q8: 2665 case ARM::VST3q16: 2666 case ARM::VST3q32: 2667 case ARM::VST3q8_UPD: 2668 case ARM::VST3q16_UPD: 2669 case ARM::VST3q32_UPD: 2670 case ARM::VST4q8: 2671 case ARM::VST4q16: 2672 case ARM::VST4q32: 2673 case ARM::VST4q8_UPD: 2674 case ARM::VST4q16_UPD: 2675 case ARM::VST4q32_UPD: 2676 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2677 return MCDisassembler::Fail; 2678 break; 2679 default: 2680 break; 2681 } 2682 2683 // Fourth input register 2684 switch (Inst.getOpcode()) { 2685 case ARM::VST4d8: 2686 case ARM::VST4d16: 2687 case ARM::VST4d32: 2688 case ARM::VST4d8_UPD: 2689 case ARM::VST4d16_UPD: 2690 case ARM::VST4d32_UPD: 2691 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2692 return MCDisassembler::Fail; 2693 break; 2694 case ARM::VST4q8: 2695 case ARM::VST4q16: 2696 case ARM::VST4q32: 2697 case ARM::VST4q8_UPD: 2698 case ARM::VST4q16_UPD: 2699 case ARM::VST4q32_UPD: 2700 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2701 return MCDisassembler::Fail; 2702 break; 2703 default: 2704 break; 2705 } 2706 2707 return S; 2708} 2709 2710static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2711 uint64_t Address, const void *Decoder) { 2712 DecodeStatus S = MCDisassembler::Success; 2713 2714 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2715 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2716 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2717 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2718 unsigned align = fieldFromInstruction(Insn, 4, 1); 2719 unsigned size = fieldFromInstruction(Insn, 6, 2); 2720 2721 if (size == 0 && align == 1) 2722 return MCDisassembler::Fail; 2723 align *= (1 << size); 2724 2725 switch (Inst.getOpcode()) { 2726 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2727 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2728 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2729 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2730 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 break; 2733 default: 2734 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2735 return MCDisassembler::Fail; 2736 break; 2737 } 2738 if (Rm != 0xF) { 2739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2740 return MCDisassembler::Fail; 2741 } 2742 2743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2744 return MCDisassembler::Fail; 2745 Inst.addOperand(MCOperand::CreateImm(align)); 2746 2747 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2748 // variant encodes Rm == 0xf. Anything else is a register offset post- 2749 // increment and we need to add the register operand to the instruction. 2750 if (Rm != 0xD && Rm != 0xF && 2751 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2752 return MCDisassembler::Fail; 2753 2754 return S; 2755} 2756 2757static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2758 uint64_t Address, const void *Decoder) { 2759 DecodeStatus S = MCDisassembler::Success; 2760 2761 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2762 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2763 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2764 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2765 unsigned align = fieldFromInstruction(Insn, 4, 1); 2766 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2767 align *= 2*size; 2768 2769 switch (Inst.getOpcode()) { 2770 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2771 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2772 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2773 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2774 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2775 return MCDisassembler::Fail; 2776 break; 2777 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2778 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2779 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2780 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2781 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2782 return MCDisassembler::Fail; 2783 break; 2784 default: 2785 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2786 return MCDisassembler::Fail; 2787 break; 2788 } 2789 2790 if (Rm != 0xF) 2791 Inst.addOperand(MCOperand::CreateImm(0)); 2792 2793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2794 return MCDisassembler::Fail; 2795 Inst.addOperand(MCOperand::CreateImm(align)); 2796 2797 if (Rm != 0xD && Rm != 0xF) { 2798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2799 return MCDisassembler::Fail; 2800 } 2801 2802 return S; 2803} 2804 2805static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2806 uint64_t Address, const void *Decoder) { 2807 DecodeStatus S = MCDisassembler::Success; 2808 2809 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2810 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2811 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2812 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2813 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2814 2815 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2816 return MCDisassembler::Fail; 2817 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2818 return MCDisassembler::Fail; 2819 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2820 return MCDisassembler::Fail; 2821 if (Rm != 0xF) { 2822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 } 2825 2826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2827 return MCDisassembler::Fail; 2828 Inst.addOperand(MCOperand::CreateImm(0)); 2829 2830 if (Rm == 0xD) 2831 Inst.addOperand(MCOperand::CreateReg(0)); 2832 else if (Rm != 0xF) { 2833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 } 2836 2837 return S; 2838} 2839 2840static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2841 uint64_t Address, const void *Decoder) { 2842 DecodeStatus S = MCDisassembler::Success; 2843 2844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2845 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2846 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2847 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2848 unsigned size = fieldFromInstruction(Insn, 6, 2); 2849 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2850 unsigned align = fieldFromInstruction(Insn, 4, 1); 2851 2852 if (size == 0x3) { 2853 if (align == 0) 2854 return MCDisassembler::Fail; 2855 size = 4; 2856 align = 16; 2857 } else { 2858 if (size == 2) { 2859 size = 1 << size; 2860 align *= 8; 2861 } else { 2862 size = 1 << size; 2863 align *= 4*size; 2864 } 2865 } 2866 2867 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2868 return MCDisassembler::Fail; 2869 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2870 return MCDisassembler::Fail; 2871 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2872 return MCDisassembler::Fail; 2873 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2874 return MCDisassembler::Fail; 2875 if (Rm != 0xF) { 2876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 } 2879 2880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2881 return MCDisassembler::Fail; 2882 Inst.addOperand(MCOperand::CreateImm(align)); 2883 2884 if (Rm == 0xD) 2885 Inst.addOperand(MCOperand::CreateReg(0)); 2886 else if (Rm != 0xF) { 2887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 } 2890 2891 return S; 2892} 2893 2894static DecodeStatus 2895DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2896 uint64_t Address, const void *Decoder) { 2897 DecodeStatus S = MCDisassembler::Success; 2898 2899 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2900 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2901 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2902 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2903 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2904 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2905 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2906 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2907 2908 if (Q) { 2909 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2910 return MCDisassembler::Fail; 2911 } else { 2912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2913 return MCDisassembler::Fail; 2914 } 2915 2916 Inst.addOperand(MCOperand::CreateImm(imm)); 2917 2918 switch (Inst.getOpcode()) { 2919 case ARM::VORRiv4i16: 2920 case ARM::VORRiv2i32: 2921 case ARM::VBICiv4i16: 2922 case ARM::VBICiv2i32: 2923 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2924 return MCDisassembler::Fail; 2925 break; 2926 case ARM::VORRiv8i16: 2927 case ARM::VORRiv4i32: 2928 case ARM::VBICiv8i16: 2929 case ARM::VBICiv4i32: 2930 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2931 return MCDisassembler::Fail; 2932 break; 2933 default: 2934 break; 2935 } 2936 2937 return S; 2938} 2939 2940static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2941 uint64_t Address, const void *Decoder) { 2942 DecodeStatus S = MCDisassembler::Success; 2943 2944 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2945 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2946 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2947 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2948 unsigned size = fieldFromInstruction(Insn, 18, 2); 2949 2950 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2951 return MCDisassembler::Fail; 2952 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2953 return MCDisassembler::Fail; 2954 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2955 2956 return S; 2957} 2958 2959static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2960 uint64_t Address, const void *Decoder) { 2961 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2962 return MCDisassembler::Success; 2963} 2964 2965static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2966 uint64_t Address, const void *Decoder) { 2967 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2968 return MCDisassembler::Success; 2969} 2970 2971static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2972 uint64_t Address, const void *Decoder) { 2973 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2974 return MCDisassembler::Success; 2975} 2976 2977static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2978 uint64_t Address, const void *Decoder) { 2979 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2980 return MCDisassembler::Success; 2981} 2982 2983static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2984 uint64_t Address, const void *Decoder) { 2985 DecodeStatus S = MCDisassembler::Success; 2986 2987 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2988 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2989 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2990 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 2991 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2992 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2993 unsigned op = fieldFromInstruction(Insn, 6, 1); 2994 2995 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2996 return MCDisassembler::Fail; 2997 if (op) { 2998 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2999 return MCDisassembler::Fail; // Writeback 3000 } 3001 3002 switch (Inst.getOpcode()) { 3003 case ARM::VTBL2: 3004 case ARM::VTBX2: 3005 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 break; 3008 default: 3009 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3010 return MCDisassembler::Fail; 3011 } 3012 3013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3014 return MCDisassembler::Fail; 3015 3016 return S; 3017} 3018 3019static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3020 uint64_t Address, const void *Decoder) { 3021 DecodeStatus S = MCDisassembler::Success; 3022 3023 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3024 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3025 3026 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3027 return MCDisassembler::Fail; 3028 3029 switch(Inst.getOpcode()) { 3030 default: 3031 return MCDisassembler::Fail; 3032 case ARM::tADR: 3033 break; // tADR does not explicitly represent the PC as an operand. 3034 case ARM::tADDrSPi: 3035 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3036 break; 3037 } 3038 3039 Inst.addOperand(MCOperand::CreateImm(imm)); 3040 return S; 3041} 3042 3043static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3044 uint64_t Address, const void *Decoder) { 3045 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3046 true, 2, Inst, Decoder)) 3047 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3048 return MCDisassembler::Success; 3049} 3050 3051static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3052 uint64_t Address, const void *Decoder) { 3053 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3054 true, 4, Inst, Decoder)) 3055 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3056 return MCDisassembler::Success; 3057} 3058 3059static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3060 uint64_t Address, const void *Decoder) { 3061 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4, 3062 true, 2, Inst, Decoder)) 3063 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 3064 return MCDisassembler::Success; 3065} 3066 3067static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3068 uint64_t Address, const void *Decoder) { 3069 DecodeStatus S = MCDisassembler::Success; 3070 3071 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3072 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3073 3074 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3075 return MCDisassembler::Fail; 3076 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3077 return MCDisassembler::Fail; 3078 3079 return S; 3080} 3081 3082static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3083 uint64_t Address, const void *Decoder) { 3084 DecodeStatus S = MCDisassembler::Success; 3085 3086 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3087 unsigned imm = fieldFromInstruction(Val, 3, 5); 3088 3089 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3090 return MCDisassembler::Fail; 3091 Inst.addOperand(MCOperand::CreateImm(imm)); 3092 3093 return S; 3094} 3095 3096static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3097 uint64_t Address, const void *Decoder) { 3098 unsigned imm = Val << 2; 3099 3100 Inst.addOperand(MCOperand::CreateImm(imm)); 3101 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3102 3103 return MCDisassembler::Success; 3104} 3105 3106static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3107 uint64_t Address, const void *Decoder) { 3108 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3109 Inst.addOperand(MCOperand::CreateImm(Val)); 3110 3111 return MCDisassembler::Success; 3112} 3113 3114static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3115 uint64_t Address, const void *Decoder) { 3116 DecodeStatus S = MCDisassembler::Success; 3117 3118 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3119 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3120 unsigned imm = fieldFromInstruction(Val, 0, 2); 3121 3122 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3123 return MCDisassembler::Fail; 3124 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3125 return MCDisassembler::Fail; 3126 Inst.addOperand(MCOperand::CreateImm(imm)); 3127 3128 return S; 3129} 3130 3131static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3132 uint64_t Address, const void *Decoder) { 3133 DecodeStatus S = MCDisassembler::Success; 3134 3135 switch (Inst.getOpcode()) { 3136 case ARM::t2PLDs: 3137 case ARM::t2PLDWs: 3138 case ARM::t2PLIs: 3139 break; 3140 default: { 3141 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3142 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3143 return MCDisassembler::Fail; 3144 } 3145 } 3146 3147 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3148 if (Rn == 0xF) { 3149 switch (Inst.getOpcode()) { 3150 case ARM::t2LDRBs: 3151 Inst.setOpcode(ARM::t2LDRBpci); 3152 break; 3153 case ARM::t2LDRHs: 3154 Inst.setOpcode(ARM::t2LDRHpci); 3155 break; 3156 case ARM::t2LDRSHs: 3157 Inst.setOpcode(ARM::t2LDRSHpci); 3158 break; 3159 case ARM::t2LDRSBs: 3160 Inst.setOpcode(ARM::t2LDRSBpci); 3161 break; 3162 case ARM::t2PLDs: 3163 Inst.setOpcode(ARM::t2PLDi12); 3164 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3165 break; 3166 default: 3167 return MCDisassembler::Fail; 3168 } 3169 3170 int imm = fieldFromInstruction(Insn, 0, 12); 3171 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3172 Inst.addOperand(MCOperand::CreateImm(imm)); 3173 3174 return S; 3175 } 3176 3177 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3178 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3179 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3180 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3181 return MCDisassembler::Fail; 3182 3183 return S; 3184} 3185 3186static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3187 uint64_t Address, const void *Decoder) { 3188 if (Val == 0) 3189 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3190 else { 3191 int imm = Val & 0xFF; 3192 3193 if (!(Val & 0x100)) imm *= -1; 3194 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3195 } 3196 3197 return MCDisassembler::Success; 3198} 3199 3200static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3201 uint64_t Address, const void *Decoder) { 3202 DecodeStatus S = MCDisassembler::Success; 3203 3204 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3205 unsigned imm = fieldFromInstruction(Val, 0, 9); 3206 3207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3208 return MCDisassembler::Fail; 3209 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3210 return MCDisassembler::Fail; 3211 3212 return S; 3213} 3214 3215static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3216 uint64_t Address, const void *Decoder) { 3217 DecodeStatus S = MCDisassembler::Success; 3218 3219 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3220 unsigned imm = fieldFromInstruction(Val, 0, 8); 3221 3222 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3223 return MCDisassembler::Fail; 3224 3225 Inst.addOperand(MCOperand::CreateImm(imm)); 3226 3227 return S; 3228} 3229 3230static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3231 uint64_t Address, const void *Decoder) { 3232 int imm = Val & 0xFF; 3233 if (Val == 0) 3234 imm = INT32_MIN; 3235 else if (!(Val & 0x100)) 3236 imm *= -1; 3237 Inst.addOperand(MCOperand::CreateImm(imm)); 3238 3239 return MCDisassembler::Success; 3240} 3241 3242 3243static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3244 uint64_t Address, const void *Decoder) { 3245 DecodeStatus S = MCDisassembler::Success; 3246 3247 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3248 unsigned imm = fieldFromInstruction(Val, 0, 9); 3249 3250 // Some instructions always use an additive offset. 3251 switch (Inst.getOpcode()) { 3252 case ARM::t2LDRT: 3253 case ARM::t2LDRBT: 3254 case ARM::t2LDRHT: 3255 case ARM::t2LDRSBT: 3256 case ARM::t2LDRSHT: 3257 case ARM::t2STRT: 3258 case ARM::t2STRBT: 3259 case ARM::t2STRHT: 3260 imm |= 0x100; 3261 break; 3262 default: 3263 break; 3264 } 3265 3266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3267 return MCDisassembler::Fail; 3268 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3269 return MCDisassembler::Fail; 3270 3271 return S; 3272} 3273 3274static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3275 uint64_t Address, const void *Decoder) { 3276 DecodeStatus S = MCDisassembler::Success; 3277 3278 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3279 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3280 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3281 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3282 addr |= Rn << 9; 3283 unsigned load = fieldFromInstruction(Insn, 20, 1); 3284 3285 if (!load) { 3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3287 return MCDisassembler::Fail; 3288 } 3289 3290 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3291 return MCDisassembler::Fail; 3292 3293 if (load) { 3294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 } 3297 3298 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3299 return MCDisassembler::Fail; 3300 3301 return S; 3302} 3303 3304static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3305 uint64_t Address, const void *Decoder) { 3306 DecodeStatus S = MCDisassembler::Success; 3307 3308 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3309 unsigned imm = fieldFromInstruction(Val, 0, 12); 3310 3311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3312 return MCDisassembler::Fail; 3313 Inst.addOperand(MCOperand::CreateImm(imm)); 3314 3315 return S; 3316} 3317 3318 3319static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3320 uint64_t Address, const void *Decoder) { 3321 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3322 3323 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3324 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3325 Inst.addOperand(MCOperand::CreateImm(imm)); 3326 3327 return MCDisassembler::Success; 3328} 3329 3330static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3331 uint64_t Address, const void *Decoder) { 3332 DecodeStatus S = MCDisassembler::Success; 3333 3334 if (Inst.getOpcode() == ARM::tADDrSP) { 3335 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3336 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3337 3338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3339 return MCDisassembler::Fail; 3340 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3342 return MCDisassembler::Fail; 3343 } else if (Inst.getOpcode() == ARM::tADDspr) { 3344 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3345 3346 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3347 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3349 return MCDisassembler::Fail; 3350 } 3351 3352 return S; 3353} 3354 3355static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3356 uint64_t Address, const void *Decoder) { 3357 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3358 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3359 3360 Inst.addOperand(MCOperand::CreateImm(imod)); 3361 Inst.addOperand(MCOperand::CreateImm(flags)); 3362 3363 return MCDisassembler::Success; 3364} 3365 3366static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3367 uint64_t Address, const void *Decoder) { 3368 DecodeStatus S = MCDisassembler::Success; 3369 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3370 unsigned add = fieldFromInstruction(Insn, 4, 1); 3371 3372 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 Inst.addOperand(MCOperand::CreateImm(add)); 3375 3376 return S; 3377} 3378 3379static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3380 uint64_t Address, const void *Decoder) { 3381 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3382 // Note only one trailing zero not two. Also the J1 and J2 values are from 3383 // the encoded instruction. So here change to I1 and I2 values via: 3384 // I1 = NOT(J1 EOR S); 3385 // I2 = NOT(J2 EOR S); 3386 // and build the imm32 with two trailing zeros as documented: 3387 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3388 unsigned S = (Val >> 23) & 1; 3389 unsigned J1 = (Val >> 22) & 1; 3390 unsigned J2 = (Val >> 21) & 1; 3391 unsigned I1 = !(J1 ^ S); 3392 unsigned I2 = !(J2 ^ S); 3393 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3394 int imm32 = SignExtend32<25>(tmp << 1); 3395 3396 if (!tryAddingSymbolicOperand(Address, 3397 (Address & ~2u) + imm32 + 4, 3398 true, 4, Inst, Decoder)) 3399 Inst.addOperand(MCOperand::CreateImm(imm32)); 3400 return MCDisassembler::Success; 3401} 3402 3403static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3404 uint64_t Address, const void *Decoder) { 3405 if (Val == 0xA || Val == 0xB) 3406 return MCDisassembler::Fail; 3407 3408 Inst.addOperand(MCOperand::CreateImm(Val)); 3409 return MCDisassembler::Success; 3410} 3411 3412static DecodeStatus 3413DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3414 uint64_t Address, const void *Decoder) { 3415 DecodeStatus S = MCDisassembler::Success; 3416 3417 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3418 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3419 3420 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3422 return MCDisassembler::Fail; 3423 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3424 return MCDisassembler::Fail; 3425 return S; 3426} 3427 3428static DecodeStatus 3429DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3430 uint64_t Address, const void *Decoder) { 3431 DecodeStatus S = MCDisassembler::Success; 3432 3433 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3434 if (pred == 0xE || pred == 0xF) { 3435 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3436 switch (opc) { 3437 default: 3438 return MCDisassembler::Fail; 3439 case 0xf3bf8f4: 3440 Inst.setOpcode(ARM::t2DSB); 3441 break; 3442 case 0xf3bf8f5: 3443 Inst.setOpcode(ARM::t2DMB); 3444 break; 3445 case 0xf3bf8f6: 3446 Inst.setOpcode(ARM::t2ISB); 3447 break; 3448 } 3449 3450 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3451 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3452 } 3453 3454 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3455 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3456 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3457 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3458 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3459 3460 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3463 return MCDisassembler::Fail; 3464 3465 return S; 3466} 3467 3468// Decode a shifted immediate operand. These basically consist 3469// of an 8-bit value, and a 4-bit directive that specifies either 3470// a splat operation or a rotation. 3471static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3472 uint64_t Address, const void *Decoder) { 3473 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3474 if (ctrl == 0) { 3475 unsigned byte = fieldFromInstruction(Val, 8, 2); 3476 unsigned imm = fieldFromInstruction(Val, 0, 8); 3477 switch (byte) { 3478 case 0: 3479 Inst.addOperand(MCOperand::CreateImm(imm)); 3480 break; 3481 case 1: 3482 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3483 break; 3484 case 2: 3485 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3486 break; 3487 case 3: 3488 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3489 (imm << 8) | imm)); 3490 break; 3491 } 3492 } else { 3493 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3494 unsigned rot = fieldFromInstruction(Val, 7, 5); 3495 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3496 Inst.addOperand(MCOperand::CreateImm(imm)); 3497 } 3498 3499 return MCDisassembler::Success; 3500} 3501 3502static DecodeStatus 3503DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3504 uint64_t Address, const void *Decoder){ 3505 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3506 true, 2, Inst, Decoder)) 3507 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3508 return MCDisassembler::Success; 3509} 3510 3511static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3512 uint64_t Address, const void *Decoder){ 3513 // Val is passed in as S:J1:J2:imm10:imm11 3514 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3515 // the encoded instruction. So here change to I1 and I2 values via: 3516 // I1 = NOT(J1 EOR S); 3517 // I2 = NOT(J2 EOR S); 3518 // and build the imm32 with one trailing zero as documented: 3519 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3520 unsigned S = (Val >> 23) & 1; 3521 unsigned J1 = (Val >> 22) & 1; 3522 unsigned J2 = (Val >> 21) & 1; 3523 unsigned I1 = !(J1 ^ S); 3524 unsigned I2 = !(J2 ^ S); 3525 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3526 int imm32 = SignExtend32<25>(tmp << 1); 3527 3528 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3529 true, 4, Inst, Decoder)) 3530 Inst.addOperand(MCOperand::CreateImm(imm32)); 3531 return MCDisassembler::Success; 3532} 3533 3534static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3535 uint64_t Address, const void *Decoder) { 3536 if (Val & ~0xf) 3537 return MCDisassembler::Fail; 3538 3539 Inst.addOperand(MCOperand::CreateImm(Val)); 3540 return MCDisassembler::Success; 3541} 3542 3543static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3544 uint64_t Address, const void *Decoder) { 3545 if (!Val) return MCDisassembler::Fail; 3546 Inst.addOperand(MCOperand::CreateImm(Val)); 3547 return MCDisassembler::Success; 3548} 3549 3550static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3551 uint64_t Address, const void *Decoder) { 3552 DecodeStatus S = MCDisassembler::Success; 3553 3554 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3555 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3556 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3557 3558 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3559 3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3565 return MCDisassembler::Fail; 3566 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3567 return MCDisassembler::Fail; 3568 3569 return S; 3570} 3571 3572 3573static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3574 uint64_t Address, const void *Decoder){ 3575 DecodeStatus S = MCDisassembler::Success; 3576 3577 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3578 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3579 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3580 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3581 3582 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3583 return MCDisassembler::Fail; 3584 3585 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3586 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3587 3588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3589 return MCDisassembler::Fail; 3590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3591 return MCDisassembler::Fail; 3592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3593 return MCDisassembler::Fail; 3594 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3595 return MCDisassembler::Fail; 3596 3597 return S; 3598} 3599 3600static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3601 uint64_t Address, const void *Decoder) { 3602 DecodeStatus S = MCDisassembler::Success; 3603 3604 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3605 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3606 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3607 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3608 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3609 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3610 3611 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3612 3613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3614 return MCDisassembler::Fail; 3615 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3616 return MCDisassembler::Fail; 3617 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3618 return MCDisassembler::Fail; 3619 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3620 return MCDisassembler::Fail; 3621 3622 return S; 3623} 3624 3625static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3626 uint64_t Address, const void *Decoder) { 3627 DecodeStatus S = MCDisassembler::Success; 3628 3629 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3630 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3631 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3632 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3633 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3634 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3635 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3636 3637 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3638 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3639 3640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3645 return MCDisassembler::Fail; 3646 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3647 return MCDisassembler::Fail; 3648 3649 return S; 3650} 3651 3652 3653static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3654 uint64_t Address, const void *Decoder) { 3655 DecodeStatus S = MCDisassembler::Success; 3656 3657 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3658 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3659 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3660 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3661 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3662 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3663 3664 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3665 3666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3667 return MCDisassembler::Fail; 3668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3669 return MCDisassembler::Fail; 3670 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3671 return MCDisassembler::Fail; 3672 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3673 return MCDisassembler::Fail; 3674 3675 return S; 3676} 3677 3678static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3679 uint64_t Address, const void *Decoder) { 3680 DecodeStatus S = MCDisassembler::Success; 3681 3682 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3683 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3684 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3685 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3686 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3687 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3688 3689 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3690 3691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3692 return MCDisassembler::Fail; 3693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3694 return MCDisassembler::Fail; 3695 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3696 return MCDisassembler::Fail; 3697 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3698 return MCDisassembler::Fail; 3699 3700 return S; 3701} 3702 3703static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3704 uint64_t Address, const void *Decoder) { 3705 DecodeStatus S = MCDisassembler::Success; 3706 3707 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3708 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3709 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3710 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3711 unsigned size = fieldFromInstruction(Insn, 10, 2); 3712 3713 unsigned align = 0; 3714 unsigned index = 0; 3715 switch (size) { 3716 default: 3717 return MCDisassembler::Fail; 3718 case 0: 3719 if (fieldFromInstruction(Insn, 4, 1)) 3720 return MCDisassembler::Fail; // UNDEFINED 3721 index = fieldFromInstruction(Insn, 5, 3); 3722 break; 3723 case 1: 3724 if (fieldFromInstruction(Insn, 5, 1)) 3725 return MCDisassembler::Fail; // UNDEFINED 3726 index = fieldFromInstruction(Insn, 6, 2); 3727 if (fieldFromInstruction(Insn, 4, 1)) 3728 align = 2; 3729 break; 3730 case 2: 3731 if (fieldFromInstruction(Insn, 6, 1)) 3732 return MCDisassembler::Fail; // UNDEFINED 3733 index = fieldFromInstruction(Insn, 7, 1); 3734 3735 switch (fieldFromInstruction(Insn, 4, 2)) { 3736 case 0 : 3737 align = 0; break; 3738 case 3: 3739 align = 4; break; 3740 default: 3741 return MCDisassembler::Fail; 3742 } 3743 break; 3744 } 3745 3746 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3747 return MCDisassembler::Fail; 3748 if (Rm != 0xF) { // Writeback 3749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3750 return MCDisassembler::Fail; 3751 } 3752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3753 return MCDisassembler::Fail; 3754 Inst.addOperand(MCOperand::CreateImm(align)); 3755 if (Rm != 0xF) { 3756 if (Rm != 0xD) { 3757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3758 return MCDisassembler::Fail; 3759 } else 3760 Inst.addOperand(MCOperand::CreateReg(0)); 3761 } 3762 3763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3764 return MCDisassembler::Fail; 3765 Inst.addOperand(MCOperand::CreateImm(index)); 3766 3767 return S; 3768} 3769 3770static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3771 uint64_t Address, const void *Decoder) { 3772 DecodeStatus S = MCDisassembler::Success; 3773 3774 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3775 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3776 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3777 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3778 unsigned size = fieldFromInstruction(Insn, 10, 2); 3779 3780 unsigned align = 0; 3781 unsigned index = 0; 3782 switch (size) { 3783 default: 3784 return MCDisassembler::Fail; 3785 case 0: 3786 if (fieldFromInstruction(Insn, 4, 1)) 3787 return MCDisassembler::Fail; // UNDEFINED 3788 index = fieldFromInstruction(Insn, 5, 3); 3789 break; 3790 case 1: 3791 if (fieldFromInstruction(Insn, 5, 1)) 3792 return MCDisassembler::Fail; // UNDEFINED 3793 index = fieldFromInstruction(Insn, 6, 2); 3794 if (fieldFromInstruction(Insn, 4, 1)) 3795 align = 2; 3796 break; 3797 case 2: 3798 if (fieldFromInstruction(Insn, 6, 1)) 3799 return MCDisassembler::Fail; // UNDEFINED 3800 index = fieldFromInstruction(Insn, 7, 1); 3801 3802 switch (fieldFromInstruction(Insn, 4, 2)) { 3803 case 0: 3804 align = 0; break; 3805 case 3: 3806 align = 4; break; 3807 default: 3808 return MCDisassembler::Fail; 3809 } 3810 break; 3811 } 3812 3813 if (Rm != 0xF) { // Writeback 3814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3815 return MCDisassembler::Fail; 3816 } 3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 Inst.addOperand(MCOperand::CreateImm(align)); 3820 if (Rm != 0xF) { 3821 if (Rm != 0xD) { 3822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3823 return MCDisassembler::Fail; 3824 } else 3825 Inst.addOperand(MCOperand::CreateReg(0)); 3826 } 3827 3828 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3829 return MCDisassembler::Fail; 3830 Inst.addOperand(MCOperand::CreateImm(index)); 3831 3832 return S; 3833} 3834 3835 3836static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3837 uint64_t Address, const void *Decoder) { 3838 DecodeStatus S = MCDisassembler::Success; 3839 3840 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3841 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3842 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3843 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3844 unsigned size = fieldFromInstruction(Insn, 10, 2); 3845 3846 unsigned align = 0; 3847 unsigned index = 0; 3848 unsigned inc = 1; 3849 switch (size) { 3850 default: 3851 return MCDisassembler::Fail; 3852 case 0: 3853 index = fieldFromInstruction(Insn, 5, 3); 3854 if (fieldFromInstruction(Insn, 4, 1)) 3855 align = 2; 3856 break; 3857 case 1: 3858 index = fieldFromInstruction(Insn, 6, 2); 3859 if (fieldFromInstruction(Insn, 4, 1)) 3860 align = 4; 3861 if (fieldFromInstruction(Insn, 5, 1)) 3862 inc = 2; 3863 break; 3864 case 2: 3865 if (fieldFromInstruction(Insn, 5, 1)) 3866 return MCDisassembler::Fail; // UNDEFINED 3867 index = fieldFromInstruction(Insn, 7, 1); 3868 if (fieldFromInstruction(Insn, 4, 1) != 0) 3869 align = 8; 3870 if (fieldFromInstruction(Insn, 6, 1)) 3871 inc = 2; 3872 break; 3873 } 3874 3875 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3876 return MCDisassembler::Fail; 3877 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 if (Rm != 0xF) { // Writeback 3880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3881 return MCDisassembler::Fail; 3882 } 3883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3884 return MCDisassembler::Fail; 3885 Inst.addOperand(MCOperand::CreateImm(align)); 3886 if (Rm != 0xF) { 3887 if (Rm != 0xD) { 3888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3889 return MCDisassembler::Fail; 3890 } else 3891 Inst.addOperand(MCOperand::CreateReg(0)); 3892 } 3893 3894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3895 return MCDisassembler::Fail; 3896 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3897 return MCDisassembler::Fail; 3898 Inst.addOperand(MCOperand::CreateImm(index)); 3899 3900 return S; 3901} 3902 3903static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3904 uint64_t Address, const void *Decoder) { 3905 DecodeStatus S = MCDisassembler::Success; 3906 3907 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3908 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3909 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3910 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3911 unsigned size = fieldFromInstruction(Insn, 10, 2); 3912 3913 unsigned align = 0; 3914 unsigned index = 0; 3915 unsigned inc = 1; 3916 switch (size) { 3917 default: 3918 return MCDisassembler::Fail; 3919 case 0: 3920 index = fieldFromInstruction(Insn, 5, 3); 3921 if (fieldFromInstruction(Insn, 4, 1)) 3922 align = 2; 3923 break; 3924 case 1: 3925 index = fieldFromInstruction(Insn, 6, 2); 3926 if (fieldFromInstruction(Insn, 4, 1)) 3927 align = 4; 3928 if (fieldFromInstruction(Insn, 5, 1)) 3929 inc = 2; 3930 break; 3931 case 2: 3932 if (fieldFromInstruction(Insn, 5, 1)) 3933 return MCDisassembler::Fail; // UNDEFINED 3934 index = fieldFromInstruction(Insn, 7, 1); 3935 if (fieldFromInstruction(Insn, 4, 1) != 0) 3936 align = 8; 3937 if (fieldFromInstruction(Insn, 6, 1)) 3938 inc = 2; 3939 break; 3940 } 3941 3942 if (Rm != 0xF) { // Writeback 3943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3944 return MCDisassembler::Fail; 3945 } 3946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3947 return MCDisassembler::Fail; 3948 Inst.addOperand(MCOperand::CreateImm(align)); 3949 if (Rm != 0xF) { 3950 if (Rm != 0xD) { 3951 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3952 return MCDisassembler::Fail; 3953 } else 3954 Inst.addOperand(MCOperand::CreateReg(0)); 3955 } 3956 3957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3958 return MCDisassembler::Fail; 3959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3960 return MCDisassembler::Fail; 3961 Inst.addOperand(MCOperand::CreateImm(index)); 3962 3963 return S; 3964} 3965 3966 3967static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3968 uint64_t Address, const void *Decoder) { 3969 DecodeStatus S = MCDisassembler::Success; 3970 3971 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3972 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3973 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3974 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3975 unsigned size = fieldFromInstruction(Insn, 10, 2); 3976 3977 unsigned align = 0; 3978 unsigned index = 0; 3979 unsigned inc = 1; 3980 switch (size) { 3981 default: 3982 return MCDisassembler::Fail; 3983 case 0: 3984 if (fieldFromInstruction(Insn, 4, 1)) 3985 return MCDisassembler::Fail; // UNDEFINED 3986 index = fieldFromInstruction(Insn, 5, 3); 3987 break; 3988 case 1: 3989 if (fieldFromInstruction(Insn, 4, 1)) 3990 return MCDisassembler::Fail; // UNDEFINED 3991 index = fieldFromInstruction(Insn, 6, 2); 3992 if (fieldFromInstruction(Insn, 5, 1)) 3993 inc = 2; 3994 break; 3995 case 2: 3996 if (fieldFromInstruction(Insn, 4, 2)) 3997 return MCDisassembler::Fail; // UNDEFINED 3998 index = fieldFromInstruction(Insn, 7, 1); 3999 if (fieldFromInstruction(Insn, 6, 1)) 4000 inc = 2; 4001 break; 4002 } 4003 4004 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4005 return MCDisassembler::Fail; 4006 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4007 return MCDisassembler::Fail; 4008 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4009 return MCDisassembler::Fail; 4010 4011 if (Rm != 0xF) { // Writeback 4012 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4013 return MCDisassembler::Fail; 4014 } 4015 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4016 return MCDisassembler::Fail; 4017 Inst.addOperand(MCOperand::CreateImm(align)); 4018 if (Rm != 0xF) { 4019 if (Rm != 0xD) { 4020 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4021 return MCDisassembler::Fail; 4022 } else 4023 Inst.addOperand(MCOperand::CreateReg(0)); 4024 } 4025 4026 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4031 return MCDisassembler::Fail; 4032 Inst.addOperand(MCOperand::CreateImm(index)); 4033 4034 return S; 4035} 4036 4037static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4038 uint64_t Address, const void *Decoder) { 4039 DecodeStatus S = MCDisassembler::Success; 4040 4041 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4042 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4043 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4044 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4045 unsigned size = fieldFromInstruction(Insn, 10, 2); 4046 4047 unsigned align = 0; 4048 unsigned index = 0; 4049 unsigned inc = 1; 4050 switch (size) { 4051 default: 4052 return MCDisassembler::Fail; 4053 case 0: 4054 if (fieldFromInstruction(Insn, 4, 1)) 4055 return MCDisassembler::Fail; // UNDEFINED 4056 index = fieldFromInstruction(Insn, 5, 3); 4057 break; 4058 case 1: 4059 if (fieldFromInstruction(Insn, 4, 1)) 4060 return MCDisassembler::Fail; // UNDEFINED 4061 index = fieldFromInstruction(Insn, 6, 2); 4062 if (fieldFromInstruction(Insn, 5, 1)) 4063 inc = 2; 4064 break; 4065 case 2: 4066 if (fieldFromInstruction(Insn, 4, 2)) 4067 return MCDisassembler::Fail; // UNDEFINED 4068 index = fieldFromInstruction(Insn, 7, 1); 4069 if (fieldFromInstruction(Insn, 6, 1)) 4070 inc = 2; 4071 break; 4072 } 4073 4074 if (Rm != 0xF) { // Writeback 4075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4076 return MCDisassembler::Fail; 4077 } 4078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4079 return MCDisassembler::Fail; 4080 Inst.addOperand(MCOperand::CreateImm(align)); 4081 if (Rm != 0xF) { 4082 if (Rm != 0xD) { 4083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4084 return MCDisassembler::Fail; 4085 } else 4086 Inst.addOperand(MCOperand::CreateReg(0)); 4087 } 4088 4089 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4090 return MCDisassembler::Fail; 4091 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4092 return MCDisassembler::Fail; 4093 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4094 return MCDisassembler::Fail; 4095 Inst.addOperand(MCOperand::CreateImm(index)); 4096 4097 return S; 4098} 4099 4100 4101static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4102 uint64_t Address, const void *Decoder) { 4103 DecodeStatus S = MCDisassembler::Success; 4104 4105 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4106 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4107 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4108 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4109 unsigned size = fieldFromInstruction(Insn, 10, 2); 4110 4111 unsigned align = 0; 4112 unsigned index = 0; 4113 unsigned inc = 1; 4114 switch (size) { 4115 default: 4116 return MCDisassembler::Fail; 4117 case 0: 4118 if (fieldFromInstruction(Insn, 4, 1)) 4119 align = 4; 4120 index = fieldFromInstruction(Insn, 5, 3); 4121 break; 4122 case 1: 4123 if (fieldFromInstruction(Insn, 4, 1)) 4124 align = 8; 4125 index = fieldFromInstruction(Insn, 6, 2); 4126 if (fieldFromInstruction(Insn, 5, 1)) 4127 inc = 2; 4128 break; 4129 case 2: 4130 switch (fieldFromInstruction(Insn, 4, 2)) { 4131 case 0: 4132 align = 0; break; 4133 case 3: 4134 return MCDisassembler::Fail; 4135 default: 4136 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4137 } 4138 4139 index = fieldFromInstruction(Insn, 7, 1); 4140 if (fieldFromInstruction(Insn, 6, 1)) 4141 inc = 2; 4142 break; 4143 } 4144 4145 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4146 return MCDisassembler::Fail; 4147 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4148 return MCDisassembler::Fail; 4149 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4150 return MCDisassembler::Fail; 4151 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4152 return MCDisassembler::Fail; 4153 4154 if (Rm != 0xF) { // Writeback 4155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4156 return MCDisassembler::Fail; 4157 } 4158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4159 return MCDisassembler::Fail; 4160 Inst.addOperand(MCOperand::CreateImm(align)); 4161 if (Rm != 0xF) { 4162 if (Rm != 0xD) { 4163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4164 return MCDisassembler::Fail; 4165 } else 4166 Inst.addOperand(MCOperand::CreateReg(0)); 4167 } 4168 4169 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4170 return MCDisassembler::Fail; 4171 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4172 return MCDisassembler::Fail; 4173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4174 return MCDisassembler::Fail; 4175 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 Inst.addOperand(MCOperand::CreateImm(index)); 4178 4179 return S; 4180} 4181 4182static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4183 uint64_t Address, const void *Decoder) { 4184 DecodeStatus S = MCDisassembler::Success; 4185 4186 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4187 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4188 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4189 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4190 unsigned size = fieldFromInstruction(Insn, 10, 2); 4191 4192 unsigned align = 0; 4193 unsigned index = 0; 4194 unsigned inc = 1; 4195 switch (size) { 4196 default: 4197 return MCDisassembler::Fail; 4198 case 0: 4199 if (fieldFromInstruction(Insn, 4, 1)) 4200 align = 4; 4201 index = fieldFromInstruction(Insn, 5, 3); 4202 break; 4203 case 1: 4204 if (fieldFromInstruction(Insn, 4, 1)) 4205 align = 8; 4206 index = fieldFromInstruction(Insn, 6, 2); 4207 if (fieldFromInstruction(Insn, 5, 1)) 4208 inc = 2; 4209 break; 4210 case 2: 4211 switch (fieldFromInstruction(Insn, 4, 2)) { 4212 case 0: 4213 align = 0; break; 4214 case 3: 4215 return MCDisassembler::Fail; 4216 default: 4217 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4218 } 4219 4220 index = fieldFromInstruction(Insn, 7, 1); 4221 if (fieldFromInstruction(Insn, 6, 1)) 4222 inc = 2; 4223 break; 4224 } 4225 4226 if (Rm != 0xF) { // Writeback 4227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4228 return MCDisassembler::Fail; 4229 } 4230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4231 return MCDisassembler::Fail; 4232 Inst.addOperand(MCOperand::CreateImm(align)); 4233 if (Rm != 0xF) { 4234 if (Rm != 0xD) { 4235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4236 return MCDisassembler::Fail; 4237 } else 4238 Inst.addOperand(MCOperand::CreateReg(0)); 4239 } 4240 4241 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4246 return MCDisassembler::Fail; 4247 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4248 return MCDisassembler::Fail; 4249 Inst.addOperand(MCOperand::CreateImm(index)); 4250 4251 return S; 4252} 4253 4254static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4255 uint64_t Address, const void *Decoder) { 4256 DecodeStatus S = MCDisassembler::Success; 4257 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4258 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4259 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4260 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4261 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4262 4263 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4264 S = MCDisassembler::SoftFail; 4265 4266 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4267 return MCDisassembler::Fail; 4268 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4271 return MCDisassembler::Fail; 4272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4273 return MCDisassembler::Fail; 4274 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4275 return MCDisassembler::Fail; 4276 4277 return S; 4278} 4279 4280static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4281 uint64_t Address, const void *Decoder) { 4282 DecodeStatus S = MCDisassembler::Success; 4283 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4284 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4285 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4286 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4287 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4288 4289 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4290 S = MCDisassembler::SoftFail; 4291 4292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4293 return MCDisassembler::Fail; 4294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4297 return MCDisassembler::Fail; 4298 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4299 return MCDisassembler::Fail; 4300 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4301 return MCDisassembler::Fail; 4302 4303 return S; 4304} 4305 4306static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4307 uint64_t Address, const void *Decoder) { 4308 DecodeStatus S = MCDisassembler::Success; 4309 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4310 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4311 4312 if (pred == 0xF) { 4313 pred = 0xE; 4314 S = MCDisassembler::SoftFail; 4315 } 4316 4317 if (mask == 0x0) { 4318 mask |= 0x8; 4319 S = MCDisassembler::SoftFail; 4320 } 4321 4322 Inst.addOperand(MCOperand::CreateImm(pred)); 4323 Inst.addOperand(MCOperand::CreateImm(mask)); 4324 return S; 4325} 4326 4327static DecodeStatus 4328DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4329 uint64_t Address, const void *Decoder) { 4330 DecodeStatus S = MCDisassembler::Success; 4331 4332 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4333 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4334 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4335 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4336 unsigned W = fieldFromInstruction(Insn, 21, 1); 4337 unsigned U = fieldFromInstruction(Insn, 23, 1); 4338 unsigned P = fieldFromInstruction(Insn, 24, 1); 4339 bool writeback = (W == 1) | (P == 0); 4340 4341 addr |= (U << 8) | (Rn << 9); 4342 4343 if (writeback && (Rn == Rt || Rn == Rt2)) 4344 Check(S, MCDisassembler::SoftFail); 4345 if (Rt == Rt2) 4346 Check(S, MCDisassembler::SoftFail); 4347 4348 // Rt 4349 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4350 return MCDisassembler::Fail; 4351 // Rt2 4352 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4353 return MCDisassembler::Fail; 4354 // Writeback operand 4355 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4356 return MCDisassembler::Fail; 4357 // addr 4358 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4359 return MCDisassembler::Fail; 4360 4361 return S; 4362} 4363 4364static DecodeStatus 4365DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4366 uint64_t Address, const void *Decoder) { 4367 DecodeStatus S = MCDisassembler::Success; 4368 4369 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4370 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4371 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4372 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4373 unsigned W = fieldFromInstruction(Insn, 21, 1); 4374 unsigned U = fieldFromInstruction(Insn, 23, 1); 4375 unsigned P = fieldFromInstruction(Insn, 24, 1); 4376 bool writeback = (W == 1) | (P == 0); 4377 4378 addr |= (U << 8) | (Rn << 9); 4379 4380 if (writeback && (Rn == Rt || Rn == Rt2)) 4381 Check(S, MCDisassembler::SoftFail); 4382 4383 // Writeback operand 4384 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4385 return MCDisassembler::Fail; 4386 // Rt 4387 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4388 return MCDisassembler::Fail; 4389 // Rt2 4390 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4391 return MCDisassembler::Fail; 4392 // addr 4393 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4394 return MCDisassembler::Fail; 4395 4396 return S; 4397} 4398 4399static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4400 uint64_t Address, const void *Decoder) { 4401 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4402 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4403 if (sign1 != sign2) return MCDisassembler::Fail; 4404 4405 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4406 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4407 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4408 Val |= sign1 << 12; 4409 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4410 4411 return MCDisassembler::Success; 4412} 4413 4414static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4415 uint64_t Address, 4416 const void *Decoder) { 4417 DecodeStatus S = MCDisassembler::Success; 4418 4419 // Shift of "asr #32" is not allowed in Thumb2 mode. 4420 if (Val == 0x20) S = MCDisassembler::SoftFail; 4421 Inst.addOperand(MCOperand::CreateImm(Val)); 4422 return S; 4423} 4424 4425static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4426 uint64_t Address, const void *Decoder) { 4427 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4428 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4429 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4430 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4431 4432 if (pred == 0xF) 4433 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4434 4435 DecodeStatus S = MCDisassembler::Success; 4436 4437 if (Rt == Rn || Rn == Rt2) 4438 S = MCDisassembler::SoftFail; 4439 4440 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4441 return MCDisassembler::Fail; 4442 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4443 return MCDisassembler::Fail; 4444 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4445 return MCDisassembler::Fail; 4446 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4447 return MCDisassembler::Fail; 4448 4449 return S; 4450} 4451 4452static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4453 uint64_t Address, const void *Decoder) { 4454 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4455 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4456 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4457 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4458 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4459 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4460 4461 DecodeStatus S = MCDisassembler::Success; 4462 4463 // VMOVv2f32 is ambiguous with these decodings. 4464 if (!(imm & 0x38) && cmode == 0xF) { 4465 Inst.setOpcode(ARM::VMOVv2f32); 4466 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4467 } 4468 4469 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4470 4471 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4472 return MCDisassembler::Fail; 4473 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4474 return MCDisassembler::Fail; 4475 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4476 4477 return S; 4478} 4479 4480static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4481 uint64_t Address, const void *Decoder) { 4482 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4483 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4484 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4485 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4486 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4487 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4488 4489 DecodeStatus S = MCDisassembler::Success; 4490 4491 // VMOVv4f32 is ambiguous with these decodings. 4492 if (!(imm & 0x38) && cmode == 0xF) { 4493 Inst.setOpcode(ARM::VMOVv4f32); 4494 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4495 } 4496 4497 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4498 4499 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4500 return MCDisassembler::Fail; 4501 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4502 return MCDisassembler::Fail; 4503 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4504 4505 return S; 4506} 4507 4508static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4509 uint64_t Address, const void *Decoder) { 4510 DecodeStatus S = MCDisassembler::Success; 4511 4512 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4513 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4514 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4515 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4516 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4517 4518 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4519 S = MCDisassembler::SoftFail; 4520 4521 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4522 return MCDisassembler::Fail; 4523 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4524 return MCDisassembler::Fail; 4525 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4526 return MCDisassembler::Fail; 4527 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4528 return MCDisassembler::Fail; 4529 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4530 return MCDisassembler::Fail; 4531 4532 return S; 4533} 4534 4535static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4536 uint64_t Address, const void *Decoder) { 4537 4538 DecodeStatus S = MCDisassembler::Success; 4539 4540 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4541 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4542 unsigned cop = fieldFromInstruction(Val, 8, 4); 4543 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4544 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4545 4546 if ((cop & ~0x1) == 0xa) 4547 return MCDisassembler::Fail; 4548 4549 if (Rt == Rt2) 4550 S = MCDisassembler::SoftFail; 4551 4552 Inst.addOperand(MCOperand::CreateImm(cop)); 4553 Inst.addOperand(MCOperand::CreateImm(opc1)); 4554 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4555 return MCDisassembler::Fail; 4556 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4557 return MCDisassembler::Fail; 4558 Inst.addOperand(MCOperand::CreateImm(CRm)); 4559 4560 return S; 4561} 4562 4563