1/* 2 * Copyright (c) 2000-2012 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28/* 29 * @OSF_COPYRIGHT@ 30 */ 31/* CMU_ENDHIST */ 32/* 33 * Mach Operating System 34 * Copyright (c) 1991,1990 Carnegie Mellon University 35 * All Rights Reserved. 36 * 37 * Permission to use, copy, modify and distribute this software and its 38 * documentation is hereby granted, provided that both the copyright 39 * notice and this permission notice appear in all copies of the 40 * software, derivative works or modified versions, and any portions 41 * thereof, and that both notices appear in supporting documentation. 42 * 43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * Carnegie Mellon requests users of this software to return to 48 * 49 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 50 * School of Computer Science 51 * Carnegie Mellon University 52 * Pittsburgh PA 15213-3890 53 * 54 * any improvements or extensions that they make and grant Carnegie Mellon 55 * the rights to redistribute these changes. 56 */ 57 58/* 59 */ 60 61/* 62 * Processor registers for i386 and i486. 63 */ 64#ifndef _I386_PROC_REG_H_ 65#define _I386_PROC_REG_H_ 66 67/* 68 * Model Specific Registers 69 */ 70#define MSR_P5_TSC 0x10 /* Time Stamp Register */ 71#define MSR_P5_CESR 0x11 /* Control and Event Select Register */ 72#define MSR_P5_CTR0 0x12 /* Counter #0 */ 73#define MSR_P5_CTR1 0x13 /* Counter #1 */ 74 75#define MSR_P5_CESR_PC 0x0200 /* Pin Control */ 76#define MSR_P5_CESR_CC 0x01C0 /* Counter Control mask */ 77#define MSR_P5_CESR_ES 0x003F /* Event Control mask */ 78 79#define MSR_P5_CESR_SHIFT 16 /* Shift to get Counter 1 */ 80#define MSR_P5_CESR_MASK (MSR_P5_CESR_PC|\ 81 MSR_P5_CESR_CC|\ 82 MSR_P5_CESR_ES) /* Mask Counter */ 83 84#define MSR_P5_CESR_CC_CLOCK 0x0100 /* Clock Counting (otherwise Event) */ 85#define MSR_P5_CESR_CC_DISABLE 0x0000 /* Disable counter */ 86#define MSR_P5_CESR_CC_CPL012 0x0040 /* Count if the CPL == 0, 1, 2 */ 87#define MSR_P5_CESR_CC_CPL3 0x0080 /* Count if the CPL == 3 */ 88#define MSR_P5_CESR_CC_CPL 0x00C0 /* Count regardless of the CPL */ 89 90#define MSR_P5_CESR_ES_DATA_READ 0x000000 /* Data Read */ 91#define MSR_P5_CESR_ES_DATA_WRITE 0x000001 /* Data Write */ 92#define MSR_P5_CESR_ES_DATA_RW 0x101000 /* Data Read or Write */ 93#define MSR_P5_CESR_ES_DATA_TLB_MISS 0x000010 /* Data TLB Miss */ 94#define MSR_P5_CESR_ES_DATA_READ_MISS 0x000011 /* Data Read Miss */ 95#define MSR_P5_CESR_ES_DATA_WRITE_MISS 0x000100 /* Data Write Miss */ 96#define MSR_P5_CESR_ES_DATA_RW_MISS 0x101001 /* Data Read or Write Miss */ 97#define MSR_P5_CESR_ES_HIT_EM 0x000101 /* Write (hit) to M|E state */ 98#define MSR_P5_CESR_ES_DATA_CACHE_WB 0x000110 /* Cache lines written back */ 99#define MSR_P5_CESR_ES_EXTERNAL_SNOOP 0x000111 /* External Snoop */ 100#define MSR_P5_CESR_ES_CACHE_SNOOP_HIT 0x001000 /* Data cache snoop hits */ 101#define MSR_P5_CESR_ES_MEM_ACCESS_PIPE 0x001001 /* Mem. access in both pipes */ 102#define MSR_P5_CESR_ES_BANK_CONFLICTS 0x001010 /* Bank conflicts */ 103#define MSR_P5_CESR_ES_MISALIGNED 0x001011 /* Misaligned Memory or I/O */ 104#define MSR_P5_CESR_ES_CODE_READ 0x001100 /* Code Read */ 105#define MSR_P5_CESR_ES_CODE_TLB_MISS 0x001101 /* Code TLB miss */ 106#define MSR_P5_CESR_ES_CODE_CACHE_MISS 0x001110 /* Code Cache miss */ 107#define MSR_P5_CESR_ES_SEGMENT_LOADED 0x001111 /* Any segment reg. loaded */ 108#define MSR_P5_CESR_ES_BRANCHE 0x010010 /* Branches */ 109#define MSR_P5_CESR_ES_BTB_HIT 0x010011 /* BTB Hits */ 110#define MSR_P5_CESR_ES_BRANCHE_BTB 0x010100 /* Taken branch or BTB Hit */ 111#define MSR_P5_CESR_ES_PIPELINE_FLUSH 0x010101 /* Pipeline Flushes */ 112#define MSR_P5_CESR_ES_INSTRUCTION 0x010110 /* Instruction executed */ 113#define MSR_P5_CESR_ES_INSTRUCTION_V 0x010111 /* Inst. executed (v-pipe) */ 114#define MSR_P5_CESR_ES_BUS_CYCLE 0x011000 /* Clocks while bus cycle */ 115#define MSR_P5_CESR_ES_FULL_WRITE_BUF 0x011001 /* Clocks while full wrt buf. */ 116#define MSR_P5_CESR_ES_DATA_MEM_READ 0x011010 /* Pipeline waiting for read */ 117#define MSR_P5_CESR_ES_WRITE_EM 0x011011 /* Stall on write E|M state */ 118#define MSR_P5_CESR_ES_LOCKED_CYCLE 0x011100 /* Locked bus cycles */ 119#define MSR_P5_CESR_ES_IO_CYCLE 0x011101 /* I/O Read or Write cycles */ 120#define MSR_P5_CESR_ES_NON_CACHEABLE 0x011110 /* Non-cacheable Mem. read */ 121#define MSR_P5_CESR_ES_AGI 0x011111 /* Stall because of AGI */ 122#define MSR_P5_CESR_ES_FLOP 0x100010 /* Floating Point operations */ 123#define MSR_P5_CESR_ES_BREAK_DR0 0x100011 /* Breakpoint matches on DR0 */ 124#define MSR_P5_CESR_ES_BREAK_DR1 0x100100 /* Breakpoint matches on DR1 */ 125#define MSR_P5_CESR_ES_BREAK_DR2 0x100101 /* Breakpoint matches on DR2 */ 126#define MSR_P5_CESR_ES_BREAK_DR3 0x100110 /* Breakpoint matches on DR3 */ 127#define MSR_P5_CESR_ES_HARDWARE_IT 0x100111 /* Hardware interrupts */ 128 129/* 130 * CR0 131 */ 132#define CR0_PG 0x80000000 /* Enable paging */ 133#define CR0_CD 0x40000000 /* i486: Cache disable */ 134#define CR0_NW 0x20000000 /* i486: No write-through */ 135#define CR0_AM 0x00040000 /* i486: Alignment check mask */ 136#define CR0_WP 0x00010000 /* i486: Write-protect kernel access */ 137#define CR0_NE 0x00000020 /* i486: Handle numeric exceptions */ 138#define CR0_ET 0x00000010 /* Extension type is 80387 */ 139 /* (not official) */ 140#define CR0_TS 0x00000008 /* Task switch */ 141#define CR0_EM 0x00000004 /* Emulate coprocessor */ 142#define CR0_MP 0x00000002 /* Monitor coprocessor */ 143#define CR0_PE 0x00000001 /* Enable protected mode */ 144 145/* 146 * CR4 147 */ 148#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execute Protect */ 149#define CR4_OSXSAVE 0x00040000 /* OS supports XSAVE */ 150#define CR4_PCIDE 0x00020000 /* PCID Enable */ 151#define CR4_RDWRFSGS 0x00010000 /* RDWRFSGS Enable */ 152#define CR4_SMXE 0x00004000 /* Enable SMX operation */ 153#define CR4_VMXE 0x00002000 /* Enable VMX operation */ 154#define CR4_OSXMM 0x00000400 /* SSE/SSE2 exception support in OS */ 155#define CR4_OSFXS 0x00000200 /* SSE/SSE2 OS supports FXSave */ 156#define CR4_PCE 0x00000100 /* Performance-Monitor Count Enable */ 157#define CR4_PGE 0x00000080 /* Page Global Enable */ 158#define CR4_MCE 0x00000040 /* Machine Check Exceptions */ 159#define CR4_PAE 0x00000020 /* Physical Address Extensions */ 160#define CR4_PSE 0x00000010 /* Page Size Extensions */ 161#define CR4_DE 0x00000008 /* Debugging Extensions */ 162#define CR4_TSD 0x00000004 /* Time Stamp Disable */ 163#define CR4_PVI 0x00000002 /* Protected-mode Virtual Interrupts */ 164#define CR4_VME 0x00000001 /* Virtual-8086 Mode Extensions */ 165 166/* 167 * XCR0 - XFEATURE_ENABLED_MASK (a.k.a. XFEM) register 168 */ 169#define XCR0_YMM 0x0000000000000004ULL /* YMM state available */ 170#define XFEM_YMM XCR0_YMM 171#define XCR0_SSE 0x0000000000000002ULL /* SSE supported by XSAVE/XRESTORE */ 172#define XCR0_X87 0x0000000000000001ULL /* x87, FPU/MMX (always set) */ 173#define XFEM_SSE XCR0_SSE 174#define XFEM_X87 XCR0_X87 175#define XCR0 (0) 176 177#define PMAP_PCID_PRESERVE (1ULL << 63) 178#define PMAP_PCID_MASK (0xFFF) 179 180#ifndef ASSEMBLER 181 182#include <sys/cdefs.h> 183#include <stdint.h> 184 185__BEGIN_DECLS 186 187#define set_ts() set_cr0(get_cr0() | CR0_TS) 188 189static inline uint16_t get_es(void) 190{ 191 uint16_t es; 192 __asm__ volatile("mov %%es, %0" : "=r" (es)); 193 return es; 194} 195 196static inline void set_es(uint16_t es) 197{ 198 __asm__ volatile("mov %0, %%es" : : "r" (es)); 199} 200 201static inline uint16_t get_ds(void) 202{ 203 uint16_t ds; 204 __asm__ volatile("mov %%ds, %0" : "=r" (ds)); 205 return ds; 206} 207 208static inline void set_ds(uint16_t ds) 209{ 210 __asm__ volatile("mov %0, %%ds" : : "r" (ds)); 211} 212 213static inline uint16_t get_fs(void) 214{ 215 uint16_t fs; 216 __asm__ volatile("mov %%fs, %0" : "=r" (fs)); 217 return fs; 218} 219 220static inline void set_fs(uint16_t fs) 221{ 222 __asm__ volatile("mov %0, %%fs" : : "r" (fs)); 223} 224 225static inline uint16_t get_gs(void) 226{ 227 uint16_t gs; 228 __asm__ volatile("mov %%gs, %0" : "=r" (gs)); 229 return gs; 230} 231 232static inline void set_gs(uint16_t gs) 233{ 234 __asm__ volatile("mov %0, %%gs" : : "r" (gs)); 235} 236 237static inline uint16_t get_ss(void) 238{ 239 uint16_t ss; 240 __asm__ volatile("mov %%ss, %0" : "=r" (ss)); 241 return ss; 242} 243 244static inline void set_ss(uint16_t ss) 245{ 246 __asm__ volatile("mov %0, %%ss" : : "r" (ss)); 247} 248 249static inline uintptr_t get_cr0(void) 250{ 251 uintptr_t cr0; 252 __asm__ volatile("mov %%cr0, %0" : "=r" (cr0)); 253 return(cr0); 254} 255 256static inline void set_cr0(uintptr_t value) 257{ 258 __asm__ volatile("mov %0, %%cr0" : : "r" (value)); 259} 260 261static inline uintptr_t get_cr2(void) 262{ 263 uintptr_t cr2; 264 __asm__ volatile("mov %%cr2, %0" : "=r" (cr2)); 265 return(cr2); 266} 267 268static inline uintptr_t get_cr3_raw(void) 269{ 270 register uintptr_t cr3; 271 __asm__ volatile("mov %%cr3, %0" : "=r" (cr3)); 272 return(cr3); 273} 274 275static inline void set_cr3_raw(uintptr_t value) 276{ 277 __asm__ volatile("mov %0, %%cr3" : : "r" (value)); 278} 279 280static inline uintptr_t get_cr3_base(void) 281{ 282 register uintptr_t cr3; 283 __asm__ volatile("mov %%cr3, %0" : "=r" (cr3)); 284 return(cr3 & ~(0xFFFULL)); 285} 286 287static inline void set_cr3_composed(uintptr_t base, uint16_t pcid, uint32_t preserve) 288{ 289 __asm__ volatile("mov %0, %%cr3" : : "r" (base | pcid | ( ( (uint64_t)preserve) << 63) ) ); 290} 291 292static inline uintptr_t get_cr4(void) 293{ 294 uintptr_t cr4; 295 __asm__ volatile("mov %%cr4, %0" : "=r" (cr4)); 296 return(cr4); 297} 298 299static inline void set_cr4(uintptr_t value) 300{ 301 __asm__ volatile("mov %0, %%cr4" : : "r" (value)); 302} 303 304static inline uintptr_t x86_get_flags(void) 305{ 306 uintptr_t erflags; 307 __asm__ volatile("pushf; pop %0" : "=r" (erflags)); 308 return erflags; 309} 310 311static inline void clear_ts(void) 312{ 313 __asm__ volatile("clts"); 314} 315 316static inline unsigned short get_tr(void) 317{ 318 unsigned short seg; 319 __asm__ volatile("str %0" : "=rm" (seg)); 320 return(seg); 321} 322 323static inline void set_tr(unsigned int seg) 324{ 325 __asm__ volatile("ltr %0" : : "rm" ((unsigned short)(seg))); 326} 327 328static inline unsigned short sldt(void) 329{ 330 unsigned short seg; 331 __asm__ volatile("sldt %0" : "=rm" (seg)); 332 return(seg); 333} 334 335static inline void lldt(unsigned int seg) 336{ 337 __asm__ volatile("lldt %0" : : "rm" ((unsigned short)(seg))); 338} 339 340static inline void lgdt(uintptr_t *desc) 341{ 342 __asm__ volatile("lgdt %0" : : "m" (*desc)); 343} 344 345static inline void lidt(uintptr_t *desc) 346{ 347 __asm__ volatile("lidt %0" : : "m" (*desc)); 348} 349 350static inline void swapgs(void) 351{ 352 __asm__ volatile("swapgs"); 353} 354 355#ifdef MACH_KERNEL_PRIVATE 356 357static inline void flush_tlb_raw(void) 358{ 359 set_cr3_raw(get_cr3_raw()); 360} 361extern int rdmsr64_carefully(uint32_t msr, uint64_t *val); 362extern int wrmsr64_carefully(uint32_t msr, uint64_t val); 363#endif /* MACH_KERNEL_PRIVATE */ 364 365static inline void wbinvd(void) 366{ 367 __asm__ volatile("wbinvd"); 368} 369 370static inline void invlpg(uintptr_t addr) 371{ 372 __asm__ volatile("invlpg (%0)" :: "r" (addr) : "memory"); 373} 374 375/* 376 * Access to machine-specific registers (available on 586 and better only) 377 * Note: the rd* operations modify the parameters directly (without using 378 * pointer indirection), this allows gcc to optimize better 379 */ 380 381#define rdmsr(msr,lo,hi) \ 382 __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr)) 383 384#define wrmsr(msr,lo,hi) \ 385 __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi)) 386 387#define rdtsc(lo,hi) \ 388 __asm__ volatile("lfence; rdtsc; lfence" : "=a" (lo), "=d" (hi)) 389 390#define rdtsc_nofence(lo,hi) \ 391 __asm__ volatile("rdtsc" : "=a" (lo), "=d" (hi)) 392 393#define write_tsc(lo,hi) wrmsr(0x10, lo, hi) 394 395#define rdpmc(counter,lo,hi) \ 396 __asm__ volatile("rdpmc" : "=a" (lo), "=d" (hi) : "c" (counter)) 397 398#ifdef XNU_KERNEL_PRIVATE 399extern void do_mfence(void); 400#define mfence() do_mfence() 401#endif 402 403static inline uint64_t rdpmc64(uint32_t pmc) 404{ 405 uint32_t lo=0, hi=0; 406 rdpmc(pmc, lo, hi); 407 return (((uint64_t)hi) << 32) | ((uint64_t)lo); 408} 409 410static inline uint64_t rdmsr64(uint32_t msr) 411{ 412 uint32_t lo=0, hi=0; 413 rdmsr(msr, lo, hi); 414 return (((uint64_t)hi) << 32) | ((uint64_t)lo); 415} 416 417static inline void wrmsr64(uint32_t msr, uint64_t val) 418{ 419 wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL)); 420} 421 422static inline uint64_t rdtsc64(void) 423{ 424 uint64_t lo, hi; 425 rdtsc(lo, hi); 426 return ((hi) << 32) | (lo); 427} 428 429static inline uint64_t rdtscp64(uint32_t *aux) 430{ 431 uint64_t lo, hi; 432 __asm__ volatile("rdtscp; mov %%ecx, %1" 433 : "=a" (lo), "=d" (hi), "=m" (*aux) 434 : 435 : "ecx"); 436 return ((hi) << 32) | (lo); 437} 438 439 440/* 441 * rdmsr_carefully() returns 0 when the MSR has been read successfully, 442 * or non-zero (1) if the MSR does not exist. 443 * The implementation is in locore.s. 444 */ 445extern int rdmsr_carefully(uint32_t msr, uint32_t *lo, uint32_t *hi); 446__END_DECLS 447 448#endif /* ASSEMBLER */ 449 450#define MSR_IA32_P5_MC_ADDR 0 451#define MSR_IA32_P5_MC_TYPE 1 452#define MSR_IA32_PLATFORM_ID 0x17 453#define MSR_IA32_EBL_CR_POWERON 0x2a 454 455#define MSR_IA32_APIC_BASE 0x1b 456#define MSR_IA32_APIC_BASE_BSP (1<<8) 457#define MSR_IA32_APIC_BASE_EXTENDED (1<<10) 458#define MSR_IA32_APIC_BASE_ENABLE (1<<11) 459#define MSR_IA32_APIC_BASE_BASE (0xfffff<<12) 460 461#define MSR_CORE_THREAD_COUNT 0x35 462 463#define MSR_IA32_FEATURE_CONTROL 0x3a 464#define MSR_IA32_FEATCTL_LOCK (1<<0) 465#define MSR_IA32_FEATCTL_VMXON_SMX (1<<1) 466#define MSR_IA32_FEATCTL_VMXON (1<<2) 467#define MSR_IA32_FEATCTL_CSTATE_SMI (1<<16) 468 469#define MSR_IA32_UPDT_TRIG 0x79 470#define MSR_IA32_BIOS_SIGN_ID 0x8b 471#define MSR_IA32_UCODE_WRITE MSR_IA32_UPDT_TRIG 472#define MSR_IA32_UCODE_REV MSR_IA32_BIOS_SIGN_ID 473 474#define MSR_IA32_PERFCTR0 0xc1 475#define MSR_IA32_PERFCTR1 0xc2 476 477#define MSR_PLATFORM_INFO 0xce 478 479#define MSR_IA32_MPERF 0xE7 480#define MSR_IA32_APERF 0xE8 481 482#define MSR_IA32_BBL_CR_CTL 0x119 483 484#define MSR_IA32_SYSENTER_CS 0x174 485#define MSR_IA32_SYSENTER_ESP 0x175 486#define MSR_IA32_SYSENTER_EIP 0x176 487 488#define MSR_IA32_MCG_CAP 0x179 489#define MSR_IA32_MCG_STATUS 0x17a 490#define MSR_IA32_MCG_CTL 0x17b 491 492#define MSR_IA32_EVNTSEL0 0x186 493#define MSR_IA32_EVNTSEL1 0x187 494 495#define MSR_FLEX_RATIO 0x194 496#define MSR_IA32_PERF_STS 0x198 497#define MSR_IA32_PERF_CTL 0x199 498#define MSR_IA32_CLOCK_MODULATION 0x19a 499 500#define MSR_IA32_MISC_ENABLE 0x1a0 501 502 503#define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 504#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 505 506#define MSR_IA32_DEBUGCTLMSR 0x1d9 507#define MSR_IA32_LASTBRANCHFROMIP 0x1db 508#define MSR_IA32_LASTBRANCHTOIP 0x1dc 509#define MSR_IA32_LASTINTFROMIP 0x1dd 510#define MSR_IA32_LASTINTTOIP 0x1de 511 512#define MSR_IA32_CR_PAT 0x277 513 514#define MSR_IA32_MTRRCAP 0xfe 515#define MSR_IA32_MTRR_DEF_TYPE 0x2ff 516#define MSR_IA32_MTRR_PHYSBASE(n) (0x200 + 2*(n)) 517#define MSR_IA32_MTRR_PHYSMASK(n) (0x200 + 2*(n) + 1) 518#define MSR_IA32_MTRR_FIX64K_00000 0x250 519#define MSR_IA32_MTRR_FIX16K_80000 0x258 520#define MSR_IA32_MTRR_FIX16K_A0000 0x259 521#define MSR_IA32_MTRR_FIX4K_C0000 0x268 522#define MSR_IA32_MTRR_FIX4K_C8000 0x269 523#define MSR_IA32_MTRR_FIX4K_D0000 0x26a 524#define MSR_IA32_MTRR_FIX4K_D8000 0x26b 525#define MSR_IA32_MTRR_FIX4K_E0000 0x26c 526#define MSR_IA32_MTRR_FIX4K_E8000 0x26d 527#define MSR_IA32_MTRR_FIX4K_F0000 0x26e 528#define MSR_IA32_MTRR_FIX4K_F8000 0x26f 529 530#define MSR_IA32_PERF_FIXED_CTR0 0x309 531 532#define MSR_IA32_PERF_FIXED_CTR_CTRL 0x38D 533#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E 534#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F 535#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390 536 537#define MSR_IA32_PKG_C3_RESIDENCY 0x3F8 538#define MSR_IA32_PKG_C6_RESIDENCY 0x3F9 539#define MSR_IA32_PKG_C7_RESIDENCY 0x3FA 540 541#define MSR_IA32_CORE_C3_RESIDENCY 0x3FC 542#define MSR_IA32_CORE_C6_RESIDENCY 0x3FD 543#define MSR_IA32_CORE_C7_RESIDENCY 0x3FE 544 545#define MSR_IA32_MC0_CTL 0x400 546#define MSR_IA32_MC0_STATUS 0x401 547#define MSR_IA32_MC0_ADDR 0x402 548#define MSR_IA32_MC0_MISC 0x403 549 550#define MSR_IA32_VMX_BASE 0x480 551#define MSR_IA32_VMX_BASIC MSR_IA32_VMX_BASE 552#define MSR_IA32_VMX_PINBASED_CTLS MSR_IA32_VMX_BASE+1 553#define MSR_IA32_VMX_PROCBASED_CTLS MSR_IA32_VMX_BASE+2 554#define MSR_IA32_VMX_EXIT_CTLS MSR_IA32_VMX_BASE+3 555#define MSR_IA32_VMX_ENTRY_CTLS MSR_IA32_VMX_BASE+4 556#define MSR_IA32_VMX_MISC MSR_IA32_VMX_BASE+5 557#define MSR_IA32_VMX_CR0_FIXED0 MSR_IA32_VMX_BASE+6 558#define MSR_IA32_VMX_CR0_FIXED1 MSR_IA32_VMX_BASE+7 559#define MSR_IA32_VMX_CR4_FIXED0 MSR_IA32_VMX_BASE+8 560#define MSR_IA32_VMX_CR4_FIXED1 MSR_IA32_VMX_BASE+9 561#define MSR_IA32_VMX_VMCS_ENUM MSR_IA32_VMX_BASE+10 562#define MSR_IA32_VMX_PROCBASED_CTLS2 MSR_IA32_VMX_BASE+11 563#define MSR_IA32_VMX_EPT_VPID_CAP MSR_IA32_VMX_BASE+12 564#define MSR_IA32_VMX_TRUE_PINBASED_CTLS MSR_IA32_VMX_BASE+13 565#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS MSR_IA32_VMX_BASE+14 566#define MSR_IA32_VMX_TRUE_VMEXIT_CTLS MSR_IA32_VMX_BASE+15 567#define MSR_IA32_VMX_TRUE_VMENTRY_CTLS MSR_IA32_VMX_BASE+16 568#define MSR_IA32_VMX_VMFUNC MSR_IA32_VMX_BASE+17 569 570#define MSR_IA32_DS_AREA 0x600 571 572#define MSR_IA32_PKG_POWER_SKU_UNIT 0x606 573#define MSR_IA32_PKG_C2_RESIDENCY 0x60D 574#define MSR_IA32_PKG_ENERGY_STATUS 0x611 575#define MSR_IA32_DDR_ENERGY_STATUS 0x619 576#define MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER 0x61D 577#define MSR_IA32_RING_PERF_STATUS 0x621 578 579#define MSR_IA32_PKG_C8_RESIDENCY 0x630 580#define MSR_IA32_PKG_C9_RESIDENCY 0x631 581#define MSR_IA32_PKG_C10_RESIDENCY 0x632 582 583#define MSR_IA32_PP0_ENERGY_STATUS 0x639 584#define MSR_IA32_PP1_ENERGY_STATUS 0x641 585#define MSR_IA32_IA_PERF_LIMIT_REASONS 0x690 586#define MSR_IA32_GT_PERF_LIMIT_REASONS 0x6B0 587 588#define MSR_IA32_TSC_DEADLINE 0x6e0 589 590#define MSR_IA32_EFER 0xC0000080 591#define MSR_IA32_EFER_SCE 0x00000001 592#define MSR_IA32_EFER_LME 0x00000100 593#define MSR_IA32_EFER_LMA 0x00000400 594#define MSR_IA32_EFER_NXE 0x00000800 595 596#define MSR_IA32_STAR 0xC0000081 597#define MSR_IA32_LSTAR 0xC0000082 598#define MSR_IA32_CSTAR 0xC0000083 599#define MSR_IA32_FMASK 0xC0000084 600 601#define MSR_IA32_FS_BASE 0xC0000100 602#define MSR_IA32_GS_BASE 0xC0000101 603#define MSR_IA32_KERNEL_GS_BASE 0xC0000102 604#define MSR_IA32_TSC_AUX 0xC0000103 605 606#endif /* _I386_PROC_REG_H_ */ 607