1//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86SUBTARGET_H
15#define X86SUBTARGET_H
16
17#include "llvm/CallingConv.h"
18#include "llvm/ADT/Triple.h"
19#include "llvm/Target/TargetSubtargetInfo.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "X86GenSubtargetInfo.inc"
24
25namespace llvm {
26class GlobalValue;
27class StringRef;
28class TargetMachine;
29
30/// PICStyles - The X86 backend supports a number of different styles of PIC.
31///
32namespace PICStyles {
33enum Style {
34  StubPIC,          // Used on i386-darwin in -fPIC mode.
35  StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36  GOT,              // Used on many 32-bit unices in -fPIC mode.
37  RIPRel,           // Used on X86-64 when not in -static mode.
38  None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
39};
40}
41
42class X86Subtarget : public X86GenSubtargetInfo {
43protected:
44  enum X86SSEEnum {
45    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
46  };
47
48  enum X863DNowEnum {
49    NoThreeDNow, ThreeDNow, ThreeDNowA
50  };
51
52  enum X86ProcFamilyEnum {
53    Others, IntelAtom
54  };
55
56  /// X86ProcFamily - X86 processor family: Intel Atom, and others
57  X86ProcFamilyEnum X86ProcFamily;
58
59  /// PICStyle - Which PIC style to use
60  ///
61  PICStyles::Style PICStyle;
62
63  /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
64  /// none supported.
65  X86SSEEnum X86SSELevel;
66
67  /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
68  ///
69  X863DNowEnum X863DNowLevel;
70
71  /// HasCMov - True if this processor has conditional move instructions
72  /// (generally pentium pro+).
73  bool HasCMov;
74
75  /// HasX86_64 - True if the processor supports X86-64 instructions.
76  ///
77  bool HasX86_64;
78
79  /// HasPOPCNT - True if the processor supports POPCNT.
80  bool HasPOPCNT;
81
82  /// HasSSE4A - True if the processor supports SSE4A instructions.
83  bool HasSSE4A;
84
85  /// HasAES - Target has AES instructions
86  bool HasAES;
87
88  /// HasPCLMUL - Target has carry-less multiplication
89  bool HasPCLMUL;
90
91  /// HasFMA - Target has 3-operand fused multiply-add
92  bool HasFMA;
93
94  /// HasFMA4 - Target has 4-operand fused multiply-add
95  bool HasFMA4;
96
97  /// HasXOP - Target has XOP instructions
98  bool HasXOP;
99
100  /// HasMOVBE - True if the processor has the MOVBE instruction.
101  bool HasMOVBE;
102
103  /// HasRDRAND - True if the processor has the RDRAND instruction.
104  bool HasRDRAND;
105
106  /// HasF16C - Processor has 16-bit floating point conversion instructions.
107  bool HasF16C;
108
109  /// HasFSGSBase - Processor has FS/GS base insturctions.
110  bool HasFSGSBase;
111
112  /// HasLZCNT - Processor has LZCNT instruction.
113  bool HasLZCNT;
114
115  /// HasBMI - Processor has BMI1 instructions.
116  bool HasBMI;
117
118  /// HasBMI2 - Processor has BMI2 instructions.
119  bool HasBMI2;
120
121  /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
122  bool IsBTMemSlow;
123
124  /// IsUAMemFast - True if unaligned memory access is fast.
125  bool IsUAMemFast;
126
127  /// HasVectorUAMem - True if SIMD operations can have unaligned memory
128  /// operands. This may require setting a feature bit in the processor.
129  bool HasVectorUAMem;
130
131  /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
132  /// this is true for most x86-64 chips, but not the first AMD chips.
133  bool HasCmpxchg16b;
134
135  /// UseLeaForSP - True if the LEA instruction should be used for adjusting
136  /// the stack pointer. This is an optimization for Intel Atom processors.
137  bool UseLeaForSP;
138
139  /// HasSlowDivide - True if smaller divides are significantly faster than
140  /// full divides and should be used when possible.
141  bool HasSlowDivide;
142
143  /// PostRAScheduler - True if using post-register-allocation scheduler.
144  bool PostRAScheduler;
145
146  /// stackAlignment - The minimum alignment known to hold of the stack frame on
147  /// entry to the function and which must be maintained by every function.
148  unsigned stackAlignment;
149
150  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
151  ///
152  unsigned MaxInlineSizeThreshold;
153
154  /// TargetTriple - What processor and OS we're targeting.
155  Triple TargetTriple;
156
157  /// Instruction itineraries for scheduling
158  InstrItineraryData InstrItins;
159
160private:
161  /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
162  bool In64BitMode;
163
164public:
165
166  /// This constructor initializes the data members to match that
167  /// of the specified triple.
168  ///
169  X86Subtarget(const std::string &TT, const std::string &CPU,
170               const std::string &FS,
171               unsigned StackAlignOverride, bool is64Bit);
172
173  /// getStackAlignment - Returns the minimum alignment known to hold of the
174  /// stack frame on entry to the function and which must be maintained by every
175  /// function for this subtarget.
176  unsigned getStackAlignment() const { return stackAlignment; }
177
178  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
179  /// that still makes it profitable to inline the call.
180  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
181
182  /// ParseSubtargetFeatures - Parses features string setting specified
183  /// subtarget options.  Definition of function is auto generated by tblgen.
184  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
185
186  /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
187  /// instruction.
188  void AutoDetectSubtargetFeatures();
189
190  bool is64Bit() const { return In64BitMode; }
191
192  PICStyles::Style getPICStyle() const { return PICStyle; }
193  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
194
195  bool hasCMov() const { return HasCMov; }
196  bool hasMMX() const { return X86SSELevel >= MMX; }
197  bool hasSSE1() const { return X86SSELevel >= SSE1; }
198  bool hasSSE2() const { return X86SSELevel >= SSE2; }
199  bool hasSSE3() const { return X86SSELevel >= SSE3; }
200  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
201  bool hasSSE41() const { return X86SSELevel >= SSE41; }
202  bool hasSSE42() const { return X86SSELevel >= SSE42; }
203  bool hasAVX() const { return X86SSELevel >= AVX; }
204  bool hasAVX2() const { return X86SSELevel >= AVX2; }
205  bool hasSSE4A() const { return HasSSE4A; }
206  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
207  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
208  bool hasPOPCNT() const { return HasPOPCNT; }
209  bool hasAES() const { return HasAES; }
210  bool hasPCLMUL() const { return HasPCLMUL; }
211  bool hasFMA() const { return HasFMA; }
212  // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
213  bool hasFMA4() const { return HasFMA4 && !HasFMA; }
214  bool hasXOP() const { return HasXOP; }
215  bool hasMOVBE() const { return HasMOVBE; }
216  bool hasRDRAND() const { return HasRDRAND; }
217  bool hasF16C() const { return HasF16C; }
218  bool hasFSGSBase() const { return HasFSGSBase; }
219  bool hasLZCNT() const { return HasLZCNT; }
220  bool hasBMI() const { return HasBMI; }
221  bool hasBMI2() const { return HasBMI2; }
222  bool isBTMemSlow() const { return IsBTMemSlow; }
223  bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
224  bool hasVectorUAMem() const { return HasVectorUAMem; }
225  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
226  bool useLeaForSP() const { return UseLeaForSP; }
227  bool hasSlowDivide() const { return HasSlowDivide; }
228
229  bool isAtom() const { return X86ProcFamily == IntelAtom; }
230
231  const Triple &getTargetTriple() const { return TargetTriple; }
232
233  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
234  bool isTargetFreeBSD() const {
235    return TargetTriple.getOS() == Triple::FreeBSD;
236  }
237  bool isTargetSolaris() const {
238    return TargetTriple.getOS() == Triple::Solaris;
239  }
240
241  // ELF is a reasonably sane default and the only other X86 targets we
242  // support are Darwin and Windows. Just use "not those".
243  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
244  bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
245  bool isTargetNaCl() const {
246    return TargetTriple.getOS() == Triple::NativeClient;
247  }
248  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
249  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
250  bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
251  bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
252  bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
253  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
254  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
255  bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
256
257  bool isTargetWin64() const {
258    // FIXME: x86_64-cygwin has not been released yet.
259    return In64BitMode && TargetTriple.isOSWindows();
260  }
261
262  bool isTargetWin32() const {
263    // FIXME: Cygwin is included for isTargetWin64 -- should it be included
264    // here too?
265    return !In64BitMode && (isTargetMingw() || isTargetWindows());
266  }
267
268  bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
269  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
270  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
271
272  bool isPICStyleStubPIC() const {
273    return PICStyle == PICStyles::StubPIC;
274  }
275
276  bool isPICStyleStubNoDynamic() const {
277    return PICStyle == PICStyles::StubDynamicNoPIC;
278  }
279  bool isPICStyleStubAny() const {
280    return PICStyle == PICStyles::StubDynamicNoPIC ||
281           PICStyle == PICStyles::StubPIC; }
282
283  /// ClassifyGlobalReference - Classify a global variable reference for the
284  /// current subtarget according to how we should reference it in a non-pcrel
285  /// context.
286  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
287                                        const TargetMachine &TM)const;
288
289  /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
290  /// current subtarget according to how we should reference it in a non-pcrel
291  /// context.
292  unsigned char ClassifyBlockAddressReference() const;
293
294  /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
295  /// to immediate address.
296  bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
297
298  /// This function returns the name of a function which has an interface
299  /// like the non-standard bzero function, if such a function exists on
300  /// the current subtarget and it is considered prefereable over
301  /// memset with zero passed as the second argument. Otherwise it
302  /// returns null.
303  const char *getBZeroEntry() const;
304
305  /// enablePostRAScheduler - run for Atom optimization.
306  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
307                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
308                             RegClassVector& CriticalPathRCs) const;
309
310  bool postRAScheduler() const { return PostRAScheduler; }
311
312  /// getInstrItins = Return the instruction itineraries based on the
313  /// subtarget selection.
314  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
315};
316
317} // End llvm namespace
318
319#endif
320