1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef X86ISELLOWERING_H 16#define X86ISELLOWERING_H 17 18#include "X86Subtarget.h" 19#include "X86RegisterInfo.h" 20#include "X86MachineFunctionInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/CallingConvLower.h" 26 27namespace llvm { 28 namespace X86ISD { 29 // X86 Specific DAG Nodes 30 enum NodeType { 31 // Start the numbering where the builtin ops leave off. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 /// BSF - Bit scan forward. 35 /// BSR - Bit scan reverse. 36 BSF, 37 BSR, 38 39 /// SHLD, SHRD - Double shift instructions. These correspond to 40 /// X86::SHLDxx and X86::SHRDxx instructions. 41 SHLD, 42 SHRD, 43 44 /// FAND - Bitwise logical AND of floating point values. This corresponds 45 /// to X86::ANDPS or X86::ANDPD. 46 FAND, 47 48 /// FOR - Bitwise logical OR of floating point values. This corresponds 49 /// to X86::ORPS or X86::ORPD. 50 FOR, 51 52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53 /// to X86::XORPS or X86::XORPD. 54 FXOR, 55 56 /// FSRL - Bitwise logical right shift of floating point values. These 57 /// corresponds to X86::PSRLDQ. 58 FSRL, 59 60 /// CALL - These operations represent an abstract X86 call 61 /// instruction, which includes a bunch of information. In particular the 62 /// operands of these node are: 63 /// 64 /// #0 - The incoming token chain 65 /// #1 - The callee 66 /// #2 - The number of arg bytes the caller pushes on the stack. 67 /// #3 - The number of arg bytes the callee pops off the stack. 68 /// #4 - The value to pass in AL/AX/EAX (optional) 69 /// #5 - The value to pass in DL/DX/EDX (optional) 70 /// 71 /// The result values of these nodes are: 72 /// 73 /// #0 - The outgoing token chain 74 /// #1 - The first register result value (optional) 75 /// #2 - The second register result value (optional) 76 /// 77 CALL, 78 79 /// RDTSC_DAG - This operation implements the lowering for 80 /// readcyclecounter 81 RDTSC_DAG, 82 83 /// X86 compare and logical compare instructions. 84 CMP, COMI, UCOMI, 85 86 /// X86 bit-test instructions. 87 BT, 88 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 90 /// operand, usually produced by a CMP instruction. 91 SETCC, 92 93 // Same as SETCC except it's materialized with a sbb and the value is all 94 // one's or all zero's. 95 SETCC_CARRY, // R = carry_bit ? ~0 : 0 96 97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 98 /// Operands are two FP values to compare; result is a mask of 99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs. 100 FSETCCss, FSETCCsd, 101 102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, 103 /// result in an integer GPR. Needs masking for scalar result. 104 FGETSIGNx86, 105 106 /// X86 conditional moves. Operand 0 and operand 1 are the two values 107 /// to select from. Operand 2 is the condition code, and operand 3 is the 108 /// flag operand produced by a CMP or TEST instruction. It also writes a 109 /// flag result. 110 CMOV, 111 112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 113 /// is the block to branch if condition is true, operand 2 is the 114 /// condition code, and operand 3 is the flag operand produced by a CMP 115 /// or TEST instruction. 116 BRCOND, 117 118 /// Return with a flag operand. Operand 0 is the chain operand, operand 119 /// 1 is the number of bytes of stack to pop. 120 RET_FLAG, 121 122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 123 REP_STOS, 124 125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 126 REP_MOVS, 127 128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl 129 /// at function entry, used for PIC code. 130 GlobalBaseReg, 131 132 /// Wrapper - A wrapper node for TargetConstantPool, 133 /// TargetExternalSymbol, and TargetGlobalAddress. 134 Wrapper, 135 136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 137 /// relative displacements. 138 WrapperRIP, 139 140 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector 141 /// to an MMX vector. If you think this is too close to the previous 142 /// mnemonic, so do I; blame Intel. 143 MOVDQ2Q, 144 145 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 146 /// i32, corresponds to X86::PEXTRB. 147 PEXTRB, 148 149 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 150 /// i32, corresponds to X86::PEXTRW. 151 PEXTRW, 152 153 /// INSERTPS - Insert any element of a 4 x float vector into any element 154 /// of a destination 4 x floatvector. 155 INSERTPS, 156 157 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 158 /// corresponds to X86::PINSRB. 159 PINSRB, 160 161 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 162 /// corresponds to X86::PINSRW. 163 PINSRW, MMX_PINSRW, 164 165 /// PSHUFB - Shuffle 16 8-bit values within a vector. 166 PSHUFB, 167 168 /// ANDNP - Bitwise Logical AND NOT of Packed FP values. 169 ANDNP, 170 171 /// PSIGN - Copy integer sign. 172 PSIGN, 173 174 /// BLENDV - Blend where the selector is an XMM. 175 BLENDV, 176 177 /// BLENDxx - Blend where the selector is an immediate. 178 BLENDPW, 179 BLENDPS, 180 BLENDPD, 181 182 /// HADD - Integer horizontal add. 183 HADD, 184 185 /// HSUB - Integer horizontal sub. 186 HSUB, 187 188 /// FHADD - Floating point horizontal add. 189 FHADD, 190 191 /// FHSUB - Floating point horizontal sub. 192 FHSUB, 193 194 /// FMAX, FMIN - Floating point max and min. 195 /// 196 FMAX, FMIN, 197 198 /// FMAXC, FMINC - Commutative FMIN and FMAX. 199 FMAXC, FMINC, 200 201 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 202 /// approximation. Note that these typically require refinement 203 /// in order to obtain suitable precision. 204 FRSQRT, FRCP, 205 206 // TLSADDR - Thread Local Storage. 207 TLSADDR, 208 209 // TLSBASEADDR - Thread Local Storage. A call to get the start address 210 // of the TLS block for the current module. 211 TLSBASEADDR, 212 213 // TLSCALL - Thread Local Storage. When calling to an OS provided 214 // thunk at the address from an earlier relocation. 215 TLSCALL, 216 217 // EH_RETURN - Exception Handling helpers. 218 EH_RETURN, 219 220 /// TC_RETURN - Tail call return. 221 /// operand #0 chain 222 /// operand #1 callee (register or absolute) 223 /// operand #2 stack adjustment 224 /// operand #3 optional in flag 225 TC_RETURN, 226 227 // VZEXT_MOVL - Vector move low and zero extend. 228 VZEXT_MOVL, 229 230 // VSEXT_MOVL - Vector move low and sign extend. 231 VSEXT_MOVL, 232 233 // VFPEXT - Vector FP extend. 234 VFPEXT, 235 236 // VSHL, VSRL - 128-bit vector logical left / right shift 237 VSHLDQ, VSRLDQ, 238 239 // VSHL, VSRL, VSRA - Vector shift elements 240 VSHL, VSRL, VSRA, 241 242 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate 243 VSHLI, VSRLI, VSRAI, 244 245 // CMPP - Vector packed double/float comparison. 246 CMPP, 247 248 // PCMP* - Vector integer comparisons. 249 PCMPEQ, PCMPGT, 250 251 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results. 252 ADD, SUB, ADC, SBB, SMUL, 253 INC, DEC, OR, XOR, AND, 254 255 ANDN, // ANDN - Bitwise AND NOT with FLAGS results. 256 257 BLSI, // BLSI - Extract lowest set isolated bit 258 BLSMSK, // BLSMSK - Get mask up to lowest set bit 259 BLSR, // BLSR - Reset lowest set bit 260 261 UMUL, // LOW, HI, FLAGS = umul LHS, RHS 262 263 // MUL_IMM - X86 specific multiply by immediate. 264 MUL_IMM, 265 266 // PTEST - Vector bitwise comparisons 267 PTEST, 268 269 // TESTP - Vector packed fp sign bitwise comparisons 270 TESTP, 271 272 // Several flavors of instructions with vector shuffle behaviors. 273 PALIGN, 274 PSHUFD, 275 PSHUFHW, 276 PSHUFLW, 277 SHUFP, 278 MOVDDUP, 279 MOVSHDUP, 280 MOVSLDUP, 281 MOVLHPS, 282 MOVLHPD, 283 MOVHLPS, 284 MOVLPS, 285 MOVLPD, 286 MOVSD, 287 MOVSS, 288 UNPCKL, 289 UNPCKH, 290 VPERMILP, 291 VPERMV, 292 VPERMI, 293 VPERM2X128, 294 VBROADCAST, 295 296 // PMULUDQ - Vector multiply packed unsigned doubleword integers 297 PMULUDQ, 298 299 // FMA nodes 300 FMADD, 301 FNMADD, 302 FMSUB, 303 FNMSUB, 304 FMADDSUB, 305 FMSUBADD, 306 307 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 308 // according to %al. An operator is needed so that this can be expanded 309 // with control flow. 310 VASTART_SAVE_XMM_REGS, 311 312 // WIN_ALLOCA - Windows's _chkstk call to do stack probing. 313 WIN_ALLOCA, 314 315 // SEG_ALLOCA - For allocating variable amounts of stack space when using 316 // segmented stacks. Check if the current stacklet has enough space, and 317 // falls back to heap allocation if not. 318 SEG_ALLOCA, 319 320 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui. 321 WIN_FTOL, 322 323 // Memory barrier 324 MEMBARRIER, 325 MFENCE, 326 SFENCE, 327 LFENCE, 328 329 // FNSTSW16r - Store FP status word into i16 register. 330 FNSTSW16r, 331 332 // SAHF - Store contents of %ah into %eflags. 333 SAHF, 334 335 // RDRAND - Get a random integer and indicate whether it is valid in CF. 336 RDRAND, 337 338 // PCMP*STRI 339 PCMPISTRI, 340 PCMPESTRI, 341 342 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 343 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 344 // Atomic 64-bit binary operations. 345 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 346 ATOMSUB64_DAG, 347 ATOMOR64_DAG, 348 ATOMXOR64_DAG, 349 ATOMAND64_DAG, 350 ATOMNAND64_DAG, 351 ATOMMAX64_DAG, 352 ATOMMIN64_DAG, 353 ATOMUMAX64_DAG, 354 ATOMUMIN64_DAG, 355 ATOMSWAP64_DAG, 356 357 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap. 358 LCMPXCHG_DAG, 359 LCMPXCHG8_DAG, 360 LCMPXCHG16_DAG, 361 362 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 363 VZEXT_LOAD, 364 365 // FNSTCW16m - Store FP control world into i16 memory. 366 FNSTCW16m, 367 368 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 369 /// integer destination in memory and a FP reg source. This corresponds 370 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 371 /// has two inputs (token chain and address) and two outputs (int value 372 /// and token chain). 373 FP_TO_INT16_IN_MEM, 374 FP_TO_INT32_IN_MEM, 375 FP_TO_INT64_IN_MEM, 376 377 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 378 /// integer source in memory and FP reg result. This corresponds to the 379 /// X86::FILD*m instructions. It has three inputs (token chain, address, 380 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 381 /// also produces a flag). 382 FILD, 383 FILD_FLAG, 384 385 /// FLD - This instruction implements an extending load to FP stack slots. 386 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 387 /// operand, ptr to load from, and a ValueType node indicating the type 388 /// to load to. 389 FLD, 390 391 /// FST - This instruction implements a truncating store to FP stack 392 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 393 /// chain operand, value to store, address, and a ValueType to store it 394 /// as. 395 FST, 396 397 /// VAARG_64 - This instruction grabs the address of the next argument 398 /// from a va_list. (reads and modifies the va_list in memory) 399 VAARG_64 400 401 // WARNING: Do not add anything in the end unless you want the node to 402 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 403 // thought as target memory ops! 404 }; 405 } 406 407 /// Define some predicates that are used for node matching. 408 namespace X86 { 409 /// isVEXTRACTF128Index - Return true if the specified 410 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 411 /// suitable for input to VEXTRACTF128. 412 bool isVEXTRACTF128Index(SDNode *N); 413 414 /// isVINSERTF128Index - Return true if the specified 415 /// INSERT_SUBVECTOR operand specifies a subvector insert that is 416 /// suitable for input to VINSERTF128. 417 bool isVINSERTF128Index(SDNode *N); 418 419 /// getExtractVEXTRACTF128Immediate - Return the appropriate 420 /// immediate to extract the specified EXTRACT_SUBVECTOR index 421 /// with VEXTRACTF128 instructions. 422 unsigned getExtractVEXTRACTF128Immediate(SDNode *N); 423 424 /// getInsertVINSERTF128Immediate - Return the appropriate 425 /// immediate to insert at the specified INSERT_SUBVECTOR index 426 /// with VINSERTF128 instructions. 427 unsigned getInsertVINSERTF128Immediate(SDNode *N); 428 429 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 430 /// constant +0.0. 431 bool isZeroNode(SDValue Elt); 432 433 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 434 /// fit into displacement field of the instruction. 435 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 436 bool hasSymbolicDisplacement = true); 437 438 439 /// isCalleePop - Determines whether the callee is required to pop its 440 /// own arguments. Callee pop is necessary to support tail calls. 441 bool isCalleePop(CallingConv::ID CallingConv, 442 bool is64Bit, bool IsVarArg, bool TailCallOpt); 443 } 444 445 //===--------------------------------------------------------------------===// 446 // X86TargetLowering - X86 Implementation of the TargetLowering interface 447 class X86TargetLowering : public TargetLowering { 448 public: 449 explicit X86TargetLowering(X86TargetMachine &TM); 450 451 virtual unsigned getJumpTableEncoding() const; 452 453 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; } 454 455 virtual const MCExpr * 456 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 457 const MachineBasicBlock *MBB, unsigned uid, 458 MCContext &Ctx) const; 459 460 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 461 /// jumptable. 462 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 463 SelectionDAG &DAG) const; 464 virtual const MCExpr * 465 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 466 unsigned JTI, MCContext &Ctx) const; 467 468 /// getStackPtrReg - Return the stack pointer register we are using: either 469 /// ESP or RSP. 470 unsigned getStackPtrReg() const { return X86StackPtr; } 471 472 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 473 /// function arguments in the caller parameter area. For X86, aggregates 474 /// that contains are placed at 16-byte boundaries while the rest are at 475 /// 4-byte boundaries. 476 virtual unsigned getByValTypeAlignment(Type *Ty) const; 477 478 /// getOptimalMemOpType - Returns the target specific optimal type for load 479 /// and store operations as a result of memset, memcpy, and memmove 480 /// lowering. If DstAlign is zero that means it's safe to destination 481 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 482 /// means there isn't a need to check it against alignment requirement, 483 /// probably because the source does not need to be loaded. If 484 /// 'IsZeroVal' is true, that means it's safe to return a 485 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 486 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 487 /// constant so it does not need to be loaded. 488 /// It returns EVT::Other if the type should be determined using generic 489 /// target-independent logic. 490 virtual EVT 491 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 492 bool IsZeroVal, bool MemcpyStrSrc, 493 MachineFunction &MF) const; 494 495 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 496 /// unaligned memory accesses. of the specified type. 497 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 498 return true; 499 } 500 501 /// LowerOperation - Provide custom lowering hooks for some operations. 502 /// 503 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 504 505 /// ReplaceNodeResults - Replace the results of node with an illegal result 506 /// type with new values built out of custom code. 507 /// 508 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 509 SelectionDAG &DAG) const; 510 511 512 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 513 514 /// isTypeDesirableForOp - Return true if the target has native support for 515 /// the specified value type and it is 'desirable' to use the type for the 516 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 517 /// instruction encodings are longer and some i16 instructions are slow. 518 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const; 519 520 /// isTypeDesirable - Return true if the target has native support for the 521 /// specified value type and it is 'desirable' to use the type. e.g. On x86 522 /// i16 is legal, but undesirable since i16 instruction encodings are longer 523 /// and some i16 instructions are slow. 524 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 525 526 virtual MachineBasicBlock * 527 EmitInstrWithCustomInserter(MachineInstr *MI, 528 MachineBasicBlock *MBB) const; 529 530 531 /// getTargetNodeName - This method returns the name of a target specific 532 /// DAG node. 533 virtual const char *getTargetNodeName(unsigned Opcode) const; 534 535 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 536 virtual EVT getSetCCResultType(EVT VT) const; 537 538 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 539 /// in Mask are known to be either zero or one and return them in the 540 /// KnownZero/KnownOne bitsets. 541 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 542 APInt &KnownZero, 543 APInt &KnownOne, 544 const SelectionDAG &DAG, 545 unsigned Depth = 0) const; 546 547 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the 548 // operation that are sign bits. 549 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 550 unsigned Depth) const; 551 552 virtual bool 553 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 554 555 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 556 557 virtual bool ExpandInlineAsm(CallInst *CI) const; 558 559 ConstraintType getConstraintType(const std::string &Constraint) const; 560 561 /// Examine constraint string and operand type and determine a weight value. 562 /// The operand object must already have been set up with the operand type. 563 virtual ConstraintWeight getSingleConstraintMatchWeight( 564 AsmOperandInfo &info, const char *constraint) const; 565 566 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 567 568 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 569 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 570 /// true it means one of the asm constraint of the inline asm instruction 571 /// being processed is 'm'. 572 virtual void LowerAsmOperandForConstraint(SDValue Op, 573 std::string &Constraint, 574 std::vector<SDValue> &Ops, 575 SelectionDAG &DAG) const; 576 577 /// getRegForInlineAsmConstraint - Given a physical register constraint 578 /// (e.g. {edx}), return the register number and the register class for the 579 /// register. This should only be used for C_Register constraints. On 580 /// error, this returns a register number of 0. 581 std::pair<unsigned, const TargetRegisterClass*> 582 getRegForInlineAsmConstraint(const std::string &Constraint, 583 EVT VT) const; 584 585 /// isLegalAddressingMode - Return true if the addressing mode represented 586 /// by AM is legal for this target, for a load/store of the specified type. 587 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 588 589 /// isLegalICmpImmediate - Return true if the specified immediate is legal 590 /// icmp immediate, that is the target has icmp instructions which can 591 /// compare a register against the immediate without having to materialize 592 /// the immediate into a register. 593 virtual bool isLegalICmpImmediate(int64_t Imm) const; 594 595 /// isLegalAddImmediate - Return true if the specified immediate is legal 596 /// add immediate, that is the target has add instructions which can 597 /// add a register and the immediate without having to materialize 598 /// the immediate into a register. 599 virtual bool isLegalAddImmediate(int64_t Imm) const; 600 601 /// isTruncateFree - Return true if it's free to truncate a value of 602 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 603 /// register EAX to i16 by referencing its sub-register AX. 604 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 605 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 606 607 /// isZExtFree - Return true if any actual instruction that defines a 608 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 609 /// register. This does not necessarily include registers defined in 610 /// unknown ways, such as incoming arguments, or copies from unknown 611 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 612 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 613 /// all instructions that define 32-bit values implicit zero-extend the 614 /// result out to 64 bits. 615 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const; 616 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 617 618 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 619 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 620 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 621 /// is expanded to mul + add. 622 virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; } 623 624 /// isNarrowingProfitable - Return true if it's profitable to narrow 625 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 626 /// from i32 to i8 but not from i32 to i16. 627 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 628 629 /// isFPImmLegal - Returns true if the target can instruction select the 630 /// specified FP immediate natively. If false, the legalizer will 631 /// materialize the FP immediate as a load from a constant pool. 632 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 633 634 /// isShuffleMaskLegal - Targets can use this to indicate that they only 635 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 636 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 637 /// values are assumed to be legal. 638 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 639 EVT VT) const; 640 641 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 642 /// used by Targets can use this to indicate if there is a suitable 643 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 644 /// pool entry. 645 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 646 EVT VT) const; 647 648 /// ShouldShrinkFPConstant - If true, then instruction selection should 649 /// seek to shrink the FP constant of the specified type to a smaller type 650 /// in order to save space and / or reduce runtime. 651 virtual bool ShouldShrinkFPConstant(EVT VT) const { 652 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 653 // expensive than a straight movsd. On the other hand, it's important to 654 // shrink long double fp constant since fldt is very slow. 655 return !X86ScalarSSEf64 || VT == MVT::f80; 656 } 657 658 const X86Subtarget* getSubtarget() const { 659 return Subtarget; 660 } 661 662 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 663 /// computed in an SSE register, not on the X87 floating point stack. 664 bool isScalarFPTypeInSSEReg(EVT VT) const { 665 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 666 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 667 } 668 669 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine 670 /// for fptoui. 671 bool isTargetFTOL() const { 672 return Subtarget->isTargetWindows() && !Subtarget->is64Bit(); 673 } 674 675 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be 676 /// used for fptoui to the given type. 677 bool isIntegerTypeFTOL(EVT VT) const { 678 return isTargetFTOL() && VT == MVT::i64; 679 } 680 681 /// createFastISel - This method returns a target specific FastISel object, 682 /// or null if the target does not support "fast" ISel. 683 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 684 const TargetLibraryInfo *libInfo) const; 685 686 /// getStackCookieLocation - Return true if the target stores stack 687 /// protector cookies at a fixed offset in some non-standard address 688 /// space, and populates the address space and offset as 689 /// appropriate. 690 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const; 691 692 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 693 SelectionDAG &DAG) const; 694 695 protected: 696 std::pair<const TargetRegisterClass*, uint8_t> 697 findRepresentativeClass(EVT VT) const; 698 699 private: 700 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 701 /// make the right decision when generating code for different targets. 702 const X86Subtarget *Subtarget; 703 const X86RegisterInfo *RegInfo; 704 const TargetData *TD; 705 706 /// X86StackPtr - X86 physical register used as stack ptr. 707 unsigned X86StackPtr; 708 709 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 710 /// floating point ops. 711 /// When SSE is available, use it for f32 operations. 712 /// When SSE2 is available, use it for f64 operations. 713 bool X86ScalarSSEf32; 714 bool X86ScalarSSEf64; 715 716 /// LegalFPImmediates - A list of legal fp immediates. 717 std::vector<APFloat> LegalFPImmediates; 718 719 /// addLegalFPImmediate - Indicate that this x86 target can instruction 720 /// select the specified FP immediate natively. 721 void addLegalFPImmediate(const APFloat& Imm) { 722 LegalFPImmediates.push_back(Imm); 723 } 724 725 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 726 CallingConv::ID CallConv, bool isVarArg, 727 const SmallVectorImpl<ISD::InputArg> &Ins, 728 DebugLoc dl, SelectionDAG &DAG, 729 SmallVectorImpl<SDValue> &InVals) const; 730 SDValue LowerMemArgument(SDValue Chain, 731 CallingConv::ID CallConv, 732 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 733 DebugLoc dl, SelectionDAG &DAG, 734 const CCValAssign &VA, MachineFrameInfo *MFI, 735 unsigned i) const; 736 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 737 DebugLoc dl, SelectionDAG &DAG, 738 const CCValAssign &VA, 739 ISD::ArgFlagsTy Flags) const; 740 741 // Call lowering helpers. 742 743 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 744 /// for tail call optimization. Targets which want to do tail call 745 /// optimization should implement this function. 746 bool IsEligibleForTailCallOptimization(SDValue Callee, 747 CallingConv::ID CalleeCC, 748 bool isVarArg, 749 bool isCalleeStructRet, 750 bool isCallerStructRet, 751 Type *RetTy, 752 const SmallVectorImpl<ISD::OutputArg> &Outs, 753 const SmallVectorImpl<SDValue> &OutVals, 754 const SmallVectorImpl<ISD::InputArg> &Ins, 755 SelectionDAG& DAG) const; 756 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const; 757 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 758 SDValue Chain, bool IsTailCall, bool Is64Bit, 759 int FPDiff, DebugLoc dl) const; 760 761 unsigned GetAlignedArgumentStackSize(unsigned StackSize, 762 SelectionDAG &DAG) const; 763 764 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 765 bool isSigned, 766 bool isReplace) const; 767 768 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 769 SelectionDAG &DAG) const; 770 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 771 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 772 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 773 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 774 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 775 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 776 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 777 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 778 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 779 int64_t Offset, SelectionDAG &DAG) const; 780 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 781 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 782 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 783 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 784 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const; 785 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 786 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 787 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 788 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 789 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 790 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 791 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 792 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const; 793 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 794 SDValue LowerToBT(SDValue And, ISD::CondCode CC, 795 DebugLoc dl, SelectionDAG &DAG) const; 796 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 797 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 798 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 799 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 800 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const; 801 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 802 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 803 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 804 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 805 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 806 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 807 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 808 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 809 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 810 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 811 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; 812 813 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 814 815 // Utility functions to help LowerVECTOR_SHUFFLE 816 SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const; 817 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const; 818 819 SDValue LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const; 820 821 SDValue LowerVectorFpExtend(SDValue &Op, SelectionDAG &DAG) const; 822 823 virtual SDValue 824 LowerFormalArguments(SDValue Chain, 825 CallingConv::ID CallConv, bool isVarArg, 826 const SmallVectorImpl<ISD::InputArg> &Ins, 827 DebugLoc dl, SelectionDAG &DAG, 828 SmallVectorImpl<SDValue> &InVals) const; 829 virtual SDValue 830 LowerCall(CallLoweringInfo &CLI, 831 SmallVectorImpl<SDValue> &InVals) const; 832 833 virtual SDValue 834 LowerReturn(SDValue Chain, 835 CallingConv::ID CallConv, bool isVarArg, 836 const SmallVectorImpl<ISD::OutputArg> &Outs, 837 const SmallVectorImpl<SDValue> &OutVals, 838 DebugLoc dl, SelectionDAG &DAG) const; 839 840 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 841 842 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 843 844 virtual EVT 845 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 846 ISD::NodeType ExtendKind) const; 847 848 virtual bool 849 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 850 bool isVarArg, 851 const SmallVectorImpl<ISD::OutputArg> &Outs, 852 LLVMContext &Context) const; 853 854 /// Utility function to emit string processing sse4.2 instructions 855 /// that return in xmm0. 856 /// This takes the instruction to expand, the associated machine basic 857 /// block, the number of args, and whether or not the second arg is 858 /// in memory or not. 859 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 860 unsigned argNum, bool inMem) const; 861 862 /// Utility functions to emit monitor and mwait instructions. These 863 /// need to make sure that the arguments to the intrinsic are in the 864 /// correct registers. 865 MachineBasicBlock *EmitMonitor(MachineInstr *MI, 866 MachineBasicBlock *BB) const; 867 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const; 868 869 /// Utility function to emit atomic-load-arith operations (and, or, xor, 870 /// nand, max, min, umax, umin). It takes the corresponding instruction to 871 /// expand, the associated machine basic block, and the associated X86 872 /// opcodes for reg/reg. 873 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI, 874 MachineBasicBlock *MBB) const; 875 876 /// Utility function to emit atomic-load-arith operations (and, or, xor, 877 /// nand, add, sub, swap) for 64-bit operands on 32-bit target. 878 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI, 879 MachineBasicBlock *MBB) const; 880 881 // Utility function to emit the low-level va_arg code for X86-64. 882 MachineBasicBlock *EmitVAARG64WithCustomInserter( 883 MachineInstr *MI, 884 MachineBasicBlock *MBB) const; 885 886 /// Utility function to emit the xmm reg save portion of va_start. 887 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 888 MachineInstr *BInstr, 889 MachineBasicBlock *BB) const; 890 891 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 892 MachineBasicBlock *BB) const; 893 894 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, 895 MachineBasicBlock *BB) const; 896 897 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, 898 MachineBasicBlock *BB, 899 bool Is64Bit) const; 900 901 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, 902 MachineBasicBlock *BB) const; 903 904 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI, 905 MachineBasicBlock *BB) const; 906 907 /// Emit nodes that will be selected as "test Op0,Op0", or something 908 /// equivalent, for use with the given x86 condition code. 909 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const; 910 911 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 912 /// equivalent, for use with the given x86 condition code. 913 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 914 SelectionDAG &DAG) const; 915 916 /// Convert a comparison if required by the subtarget. 917 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const; 918 }; 919 920 namespace X86 { 921 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 922 const TargetLibraryInfo *libInfo); 923 } 924} 925 926#endif // X86ISELLOWERING_H 927