1//===-- PPCScheduleG3.td - PPC G3 Scheduling Definitions ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the G3 (750) processor.
11//
12//===----------------------------------------------------------------------===//
13
14
15def G3Itineraries : ProcessorItineraries<
16  [IU1, IU2, FPU1, BPU, SRU, SLU], [], [
17  InstrItinData<IntSimple   , [InstrStage<1, [IU1, IU2]>]>,
18  InstrItinData<IntGeneral  , [InstrStage<1, [IU1, IU2]>]>,
19  InstrItinData<IntCompare  , [InstrStage<1, [IU1, IU2]>]>,
20  InstrItinData<IntDivW     , [InstrStage<19, [IU1]>]>,
21  InstrItinData<IntMFFS     , [InstrStage<1, [FPU1]>]>,
22  InstrItinData<IntMTFSB0   , [InstrStage<3, [FPU1]>]>,
23  InstrItinData<IntMulHW    , [InstrStage<5, [IU1]>]>,
24  InstrItinData<IntMulHWU   , [InstrStage<6, [IU1]>]>,
25  InstrItinData<IntMulLI    , [InstrStage<3, [IU1]>]>,
26  InstrItinData<IntRotate   , [InstrStage<1, [IU1, IU2]>]>,
27  InstrItinData<IntShift    , [InstrStage<1, [IU1, IU2]>]>,
28  InstrItinData<IntTrapW    , [InstrStage<2, [IU1, IU2]>]>,
29  InstrItinData<BrB         , [InstrStage<1, [BPU]>]>,
30  InstrItinData<BrCR        , [InstrStage<1, [SRU]>]>,
31  InstrItinData<BrMCR       , [InstrStage<1, [SRU]>]>,
32  InstrItinData<BrMCRX      , [InstrStage<1, [SRU]>]>,
33  InstrItinData<LdStDCBA    , [InstrStage<2, [SLU]>]>,
34  InstrItinData<LdStDCBF    , [InstrStage<3, [SLU]>]>,
35  InstrItinData<LdStDCBI    , [InstrStage<3, [SLU]>]>,
36  InstrItinData<LdStLoad    , [InstrStage<2, [SLU]>]>,
37  InstrItinData<LdStLoadUpd , [InstrStage<2, [SLU]>]>,  
38  InstrItinData<LdStStore   , [InstrStage<2, [SLU]>]>,
39  InstrItinData<LdStStoreUpd, [InstrStage<2, [SLU]>]>,  
40  InstrItinData<LdStICBI    , [InstrStage<3, [SLU]>]>,
41  InstrItinData<LdStSTFD    , [InstrStage<2, [SLU]>]>,
42  InstrItinData<LdStSTFDU   , [InstrStage<2, [SLU]>]>,
43  InstrItinData<LdStLFD     , [InstrStage<2, [SLU]>]>,
44  InstrItinData<LdStLFDU    , [InstrStage<2, [SLU]>]>,
45  InstrItinData<LdStLHA     , [InstrStage<2, [SLU]>]>,
46  InstrItinData<LdStLHAU    , [InstrStage<2, [SLU]>]>,  
47  InstrItinData<LdStLMW     , [InstrStage<34, [SLU]>]>,
48  InstrItinData<LdStLWARX   , [InstrStage<3, [SLU]>]>,
49  InstrItinData<LdStSTWCX   , [InstrStage<8, [SLU]>]>,
50  InstrItinData<LdStSync    , [InstrStage<3, [SLU]>]>,
51  InstrItinData<SprISYNC    , [InstrStage<2, [SRU]>]>,
52  InstrItinData<SprMFSR     , [InstrStage<3, [SRU]>]>,
53  InstrItinData<SprMTMSR    , [InstrStage<1, [SRU]>]>,
54  InstrItinData<SprMTSR     , [InstrStage<2, [SRU]>]>,
55  InstrItinData<SprTLBSYNC  , [InstrStage<3, [SRU]>]>,
56  InstrItinData<SprMFCR     , [InstrStage<1, [SRU]>]>,
57  InstrItinData<SprMFMSR    , [InstrStage<1, [SRU]>]>,
58  InstrItinData<SprMFSPR    , [InstrStage<3, [SRU]>]>,
59  InstrItinData<SprMFTB     , [InstrStage<3, [SRU]>]>,
60  InstrItinData<SprMTSPR    , [InstrStage<2, [SRU]>]>,
61  InstrItinData<SprMTSRIN   , [InstrStage<2, [SRU]>]>,
62  InstrItinData<SprRFI      , [InstrStage<2, [SRU]>]>,
63  InstrItinData<SprSC       , [InstrStage<2, [SRU]>]>,
64  InstrItinData<FPGeneral   , [InstrStage<1, [FPU1]>]>,
65  InstrItinData<FPAddSub    , [InstrStage<1, [FPU1]>]>,
66  InstrItinData<FPCompare   , [InstrStage<1, [FPU1]>]>,
67  InstrItinData<FPDivD      , [InstrStage<31, [FPU1]>]>,
68  InstrItinData<FPDivS      , [InstrStage<17, [FPU1]>]>,
69  InstrItinData<FPFused     , [InstrStage<2, [FPU1]>]>,
70  InstrItinData<FPRes       , [InstrStage<10, [FPU1]>]>
71]>;
72