1//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ARM specific subclass of TargetSubtargetInfo. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMSubtarget.h" 15#include "ARMBaseRegisterInfo.h" 16#include "ARMBaseInstrInfo.h" 17#include "llvm/GlobalValue.h" 18#include "llvm/Target/TargetInstrInfo.h" 19#include "llvm/Support/CommandLine.h" 20 21#define GET_SUBTARGETINFO_TARGET_DESC 22#define GET_SUBTARGETINFO_CTOR 23#include "ARMGenSubtargetInfo.inc" 24 25using namespace llvm; 26 27static cl::opt<bool> 28ReserveR9("arm-reserve-r9", cl::Hidden, 29 cl::desc("Reserve R9, making it unavailable as GPR")); 30 31static cl::opt<bool> 32DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden); 33 34static cl::opt<bool> 35UseFusedMulOps("arm-use-mulops", 36 cl::init(true), cl::Hidden); 37 38static cl::opt<bool> 39StrictAlign("arm-strict-align", cl::Hidden, 40 cl::desc("Disallow all unaligned memory accesses")); 41 42 43ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, 44 const std::string &FS) 45 : ARMGenSubtargetInfo(TT, CPU, FS) 46 , ARMProcFamily(Others) 47 , HasV4TOps(false) 48 , HasV5TOps(false) 49 , HasV5TEOps(false) 50 , HasV6Ops(false) 51 , HasV6T2Ops(false) 52 , HasV7Ops(false) 53 , HasVFPv2(false) 54 , HasVFPv3(false) 55 , HasVFPv4(false) 56 , HasNEON(false) 57 , UseNEONForSinglePrecisionFP(false) 58 , UseMulOps(UseFusedMulOps) 59 , SlowFPVMLx(false) 60 , HasVMLxForwarding(false) 61 , SlowFPBrcc(false) 62 , InThumbMode(false) 63 , HasThumb2(false) 64 , IsMClass(false) 65 , NoARM(false) 66 , PostRAScheduler(false) 67 , IsR9Reserved(ReserveR9) 68 , UseMovt(false) 69 , SupportsTailCall(false) 70 , HasFP16(false) 71 , HasD16(false) 72 , HasHardwareDivide(false) 73 , HasHardwareDivideInARM(false) 74 , HasT2ExtractPack(false) 75 , HasDataBarrier(false) 76 , Pref32BitThumb(false) 77 , AvoidCPSRPartialUpdate(false) 78 , HasRAS(false) 79 , HasMPExtension(false) 80 , FPOnlySP(false) 81 , AllowsUnalignedMem(false) 82 , Thumb2DSP(false) 83 , stackAlignment(4) 84 , CPUString(CPU) 85 , TargetTriple(TT) 86 , TargetABI(ARM_ABI_APCS) { 87 // Determine default and user specified characteristics 88 if (CPUString.empty()) 89 CPUString = "generic"; 90 91 // Insert the architecture feature derived from the target triple into the 92 // feature string. This is important for setting features that are implied 93 // based on the architecture version. 94 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString); 95 if (!FS.empty()) { 96 if (!ArchFS.empty()) 97 ArchFS = ArchFS + "," + FS; 98 else 99 ArchFS = FS; 100 } 101 ParseSubtargetFeatures(CPUString, ArchFS); 102 103 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a 104 // ARM version or CPU and then remove this. 105 if (!HasV6T2Ops && hasThumb2()) 106 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; 107 108 // Keep a pointer to static instruction cost data for the specified CPU. 109 SchedModel = getSchedModelForCPU(CPUString); 110 111 // Initialize scheduling itinerary for the specified CPU. 112 InstrItins = getInstrItineraryForCPU(CPUString); 113 114 if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass())) 115 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g. 116 // Darwin-EABI conforms to AACPS but not the rest of EABI. 117 TargetABI = ARM_ABI_AAPCS; 118 119 if (isAAPCS_ABI()) 120 stackAlignment = 8; 121 122 if (!isTargetIOS()) 123 UseMovt = hasV6T2Ops(); 124 else { 125 IsR9Reserved = ReserveR9 | !HasV6Ops; 126 UseMovt = DarwinUseMOVT && hasV6T2Ops(); 127 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0); 128 } 129 130 if (!isThumb() || hasThumb2()) 131 PostRAScheduler = true; 132 133 // v6+ may or may not support unaligned mem access depending on the system 134 // configuration. 135 if (!StrictAlign && hasV6Ops() && isTargetDarwin()) 136 AllowsUnalignedMem = true; 137} 138 139 140/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol. 141bool 142ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV, 143 Reloc::Model RelocM) const { 144 if (RelocM == Reloc::Static) 145 return false; 146 147 // Materializable GVs (in JIT lazy compilation mode) do not require an extra 148 // load from stub. 149 bool isDecl = GV->hasAvailableExternallyLinkage(); 150 if (GV->isDeclaration() && !GV->isMaterializable()) 151 isDecl = true; 152 153 if (!isTargetDarwin()) { 154 // Extra load is needed for all externally visible. 155 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility()) 156 return false; 157 return true; 158 } else { 159 if (RelocM == Reloc::PIC_) { 160 // If this is a strong reference to a definition, it is definitely not 161 // through a stub. 162 if (!isDecl && !GV->isWeakForLinker()) 163 return false; 164 165 // Unless we have a symbol with hidden visibility, we have to go through a 166 // normal $non_lazy_ptr stub because this symbol might be resolved late. 167 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 168 return true; 169 170 // If symbol visibility is hidden, we have a stub for common symbol 171 // references and external declarations. 172 if (isDecl || GV->hasCommonLinkage()) 173 // Hidden $non_lazy_ptr reference. 174 return true; 175 176 return false; 177 } else { 178 // If this is a strong reference to a definition, it is definitely not 179 // through a stub. 180 if (!isDecl && !GV->isWeakForLinker()) 181 return false; 182 183 // Unless we have a symbol with hidden visibility, we have to go through a 184 // normal $non_lazy_ptr stub because this symbol might be resolved late. 185 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 186 return true; 187 } 188 } 189 190 return false; 191} 192 193unsigned ARMSubtarget::getMispredictionPenalty() const { 194 return SchedModel->MispredictPenalty; 195} 196 197bool ARMSubtarget::enablePostRAScheduler( 198 CodeGenOpt::Level OptLevel, 199 TargetSubtargetInfo::AntiDepBreakMode& Mode, 200 RegClassVector& CriticalPathRCs) const { 201 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; 202 CriticalPathRCs.clear(); 203 CriticalPathRCs.push_back(&ARM::GPRRegClass); 204 return PostRAScheduler && OptLevel >= CodeGenOpt::Default; 205} 206