1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Subtarget state. 21// 22 23def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 24 "Thumb mode">; 25 26//===----------------------------------------------------------------------===// 27// ARM Subtarget features. 28// 29 30def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 31 "Enable VFP2 instructions">; 32def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 33 "Enable VFP3 instructions", 34 [FeatureVFP2]>; 35def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 36 "Enable NEON instructions", 37 [FeatureVFP3]>; 38def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 39 "Enable Thumb2 instructions">; 40def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 41 "Does not support ARM mode execution">; 42def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 43 "Enable half-precision floating point">; 44def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 45 "Enable VFP4 instructions", 46 [FeatureVFP3, FeatureFP16]>; 47def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 48 "Restrict VFP3 to 16 double registers">; 49def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 50 "Enable divide instructions">; 51def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 52 "HasHardwareDivideInARM", "true", 53 "Enable divide instructions in ARM mode">; 54def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 55 "Enable Thumb2 extract and pack instructions">; 56def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 57 "Has data barrier (dmb / dsb) instructions">; 58def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 59 "FP compare + branch is slow">; 60def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 61 "Floating point unit supports single precision only">; 62 63// Some processors have FP multiply-accumulate instructions that don't 64// play nicely with other VFP / NEON instructions, and it's generally better 65// to just not use them. 66def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 67 "Disable VFP / NEON MAC instructions">; 68 69// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 70def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 71 "HasVMLxForwarding", "true", 72 "Has multiplier accumulator forwarding">; 73 74// Some processors benefit from using NEON instructions for scalar 75// single-precision FP operations. 76def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 77 "true", 78 "Use NEON for single precision FP">; 79 80 81// Disable 32-bit to 16-bit narrowing for experimentation. 82def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 83 "Prefer 32-bit Thumb instrs">; 84 85/// Some instructions update CPSR partially, which can add false dependency for 86/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 87/// mapped to a separate physical register. Avoid partial CPSR update for these 88/// processors. 89def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 90 "AvoidCPSRPartialUpdate", "true", 91 "Avoid CPSR partial update for OOO execution">; 92 93// Some processors perform return stack prediction. CodeGen should avoid issue 94// "normal" call instructions to callees which do not return. 95def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", 96 "Has return address stack">; 97 98/// Some M architectures don't have the DSP extension (v7E-M vs. v7M) 99def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true", 100 "Supports v7 DSP instructions in Thumb2">; 101 102// Multiprocessing extension. 103def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 104 "Supports Multiprocessing extension">; 105 106// M-series ISA? 107def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true", 108 "Is microcontroller profile ('M' series)">; 109 110// ARM ISAs. 111def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 112 "Support ARM v4T instructions">; 113def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 114 "Support ARM v5T instructions", 115 [HasV4TOps]>; 116def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 117 "Support ARM v5TE, v5TEj, and v5TExp instructions", 118 [HasV5TOps]>; 119def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 120 "Support ARM v6 instructions", 121 [HasV5TEOps]>; 122def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 123 "Support ARM v6t2 instructions", 124 [HasV6Ops, FeatureThumb2]>; 125def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 126 "Support ARM v7 instructions", 127 [HasV6T2Ops]>; 128 129//===----------------------------------------------------------------------===// 130// ARM Processors supported. 131// 132 133include "ARMSchedule.td" 134 135// ARM processor families. 136def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 137 "Cortex-A8 ARM processors", 138 [FeatureSlowFPBrcc, FeatureNEONForFP, 139 FeatureHasSlowFPVMLx, FeatureVMLxForwarding, 140 FeatureT2XtPk]>; 141def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 142 "Cortex-A9 ARM processors", 143 [FeatureVMLxForwarding, 144 FeatureT2XtPk, FeatureFP16, 145 FeatureAvoidPartialCPSR 146 ]>; 147def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 148 "Swift ARM processors", 149 [FeatureNEONForFP, FeatureT2XtPk, 150 FeatureVFP4, FeatureMP, FeatureHWDiv, 151 FeatureHWDivARM, FeatureAvoidPartialCPSR, 152 FeatureHasSlowFPVMLx]>; 153 154// FIXME: It has not been determined if A15 has these features. 155def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 156 "Cortex-A15 ARM processors", 157 [FeatureT2XtPk, FeatureFP16, 158 FeatureAvoidPartialCPSR]>; 159 160class ProcNoItin<string Name, list<SubtargetFeature> Features> 161 : Processor<Name, NoItineraries, Features>; 162 163// V4 Processors. 164def : ProcNoItin<"generic", []>; 165def : ProcNoItin<"arm8", []>; 166def : ProcNoItin<"arm810", []>; 167def : ProcNoItin<"strongarm", []>; 168def : ProcNoItin<"strongarm110", []>; 169def : ProcNoItin<"strongarm1100", []>; 170def : ProcNoItin<"strongarm1110", []>; 171 172// V4T Processors. 173def : ProcNoItin<"arm7tdmi", [HasV4TOps]>; 174def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>; 175def : ProcNoItin<"arm710t", [HasV4TOps]>; 176def : ProcNoItin<"arm720t", [HasV4TOps]>; 177def : ProcNoItin<"arm9", [HasV4TOps]>; 178def : ProcNoItin<"arm9tdmi", [HasV4TOps]>; 179def : ProcNoItin<"arm920", [HasV4TOps]>; 180def : ProcNoItin<"arm920t", [HasV4TOps]>; 181def : ProcNoItin<"arm922t", [HasV4TOps]>; 182def : ProcNoItin<"arm940t", [HasV4TOps]>; 183def : ProcNoItin<"ep9312", [HasV4TOps]>; 184 185// V5T Processors. 186def : ProcNoItin<"arm10tdmi", [HasV5TOps]>; 187def : ProcNoItin<"arm1020t", [HasV5TOps]>; 188 189// V5TE Processors. 190def : ProcNoItin<"arm9e", [HasV5TEOps]>; 191def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>; 192def : ProcNoItin<"arm946e-s", [HasV5TEOps]>; 193def : ProcNoItin<"arm966e-s", [HasV5TEOps]>; 194def : ProcNoItin<"arm968e-s", [HasV5TEOps]>; 195def : ProcNoItin<"arm10e", [HasV5TEOps]>; 196def : ProcNoItin<"arm1020e", [HasV5TEOps]>; 197def : ProcNoItin<"arm1022e", [HasV5TEOps]>; 198def : ProcNoItin<"xscale", [HasV5TEOps]>; 199def : ProcNoItin<"iwmmxt", [HasV5TEOps]>; 200 201// V6 Processors. 202def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>; 203def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 204 FeatureHasSlowFPVMLx]>; 205def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>; 206def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 207 FeatureHasSlowFPVMLx]>; 208def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>; 209def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 210 FeatureHasSlowFPVMLx]>; 211 212// V6M Processors. 213def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM, 214 FeatureDB, FeatureMClass]>; 215 216// V6T2 Processors. 217def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, 218 FeatureDSPThumb2]>; 219def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2, 220 FeatureHasSlowFPVMLx, 221 FeatureDSPThumb2]>; 222 223// V7a Processors. 224// FIXME: Cortex-A7 definition is similar to A8, but it has VFP4 and div 225// instructions. 226def : ProcessorModel<"cortex-a7", CortexA8Model, 227 [HasV7Ops, FeatureNEON, FeatureDB, 228 FeatureDSPThumb2, FeatureHasRAS, 229 FeatureNEONForFP, 230 FeatureHasSlowFPVMLx,FeatureVMLxForwarding, 231 FeatureT2XtPk, 232 FeatureVFP4, 233 FeatureHWDiv, FeatureHWDivARM]>; 234def : ProcessorModel<"cortex-a8", CortexA8Model, 235 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB, 236 FeatureDSPThumb2, FeatureHasRAS]>; 237def : ProcessorModel<"cortex-a9", CortexA9Model, 238 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 239 FeatureDSPThumb2, FeatureHasRAS]>; 240def : ProcessorModel<"cortex-a9-mp", CortexA9Model, 241 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 242 FeatureDSPThumb2, FeatureMP, 243 FeatureHasRAS]>; 244 245// FIXME: A15 has currently the same ProcessorModel as A9. 246def : ProcessorModel<"cortex-a15", CortexA9Model, 247 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB, 248 FeatureDSPThumb2, FeatureHasRAS]>; 249 250// V7M Processors. 251def : ProcNoItin<"cortex-m3", [HasV7Ops, 252 FeatureThumb2, FeatureNoARM, FeatureDB, 253 FeatureHWDiv, FeatureMClass]>; 254 255// V7EM Processors. 256def : ProcNoItin<"cortex-m4", [HasV7Ops, 257 FeatureThumb2, FeatureNoARM, FeatureDB, 258 FeatureHWDiv, FeatureDSPThumb2, 259 FeatureT2XtPk, FeatureVFP4, 260 FeatureVFPOnlySP, FeatureMClass]>; 261 262// Swift uArch Processors. 263def : ProcessorModel<"swift", SwiftModel, 264 [ProcSwift, HasV7Ops, FeatureNEON, 265 FeatureDB, FeatureDSPThumb2, 266 FeatureHasRAS]>; 267 268//===----------------------------------------------------------------------===// 269// Register File Description 270//===----------------------------------------------------------------------===// 271 272include "ARMRegisterInfo.td" 273 274include "ARMCallingConv.td" 275 276//===----------------------------------------------------------------------===// 277// Instruction Descriptions 278//===----------------------------------------------------------------------===// 279 280include "ARMInstrInfo.td" 281 282def ARMInstrInfo : InstrInfo; 283 284 285//===----------------------------------------------------------------------===// 286// Assembly printer 287//===----------------------------------------------------------------------===// 288// ARM Uses the MC printer for asm output, so make sure the TableGen 289// AsmWriter bits get associated with the correct class. 290def ARMAsmWriter : AsmWriter { 291 string AsmWriterClassName = "InstPrinter"; 292 bit isMCAsmWriter = 1; 293} 294 295//===----------------------------------------------------------------------===// 296// Declare the target which we are implementing 297//===----------------------------------------------------------------------===// 298 299def ARM : Target { 300 // Pull in Instruction Info: 301 let InstructionSet = ARMInstrInfo; 302 303 let AssemblyWriters = [ARMAsmWriter]; 304} 305