1/*
2 * Copyright (c) 2000-2008 Apple Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License").  You may not use this file except in compliance with the
9 * License.  Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22/*
23 *
24 *	IOPCIATA.cpp
25 *
26 *	class defining the portions of PCI-ATA class controllers which
27 *	are generally common to most PCI ATA bus controllers, such as DMA
28 *  programming.
29 *
30 */
31
32#include <IOKit/IOTypes.h>
33#include "IOATATypes.h"
34#include "IOATAController.h"
35#include "IOATADevice.h"
36#include "IOATABusInfo.h"
37#include "IOATADevConfig.h"
38
39#include <IOKit/IOMemoryCursor.h>
40
41#include <libkern/OSByteOrder.h>
42#include <libkern/OSAtomic.h>
43
44#include "IOPCIATA.h"
45#include "IOATABusCommand.h"
46
47#ifdef DLOG
48#undef DLOG
49#endif
50
51//#define ATA_DEBUG 1
52
53#ifdef  ATA_DEBUG
54#define DLOG(fmt, args...)  IOLog(fmt, ## args)
55#else
56#define DLOG(fmt, args...)
57#endif
58
59// some day, we'll have an ATA recorder for IOKit
60
61#define ATARecordEventMACRO(type,param,bus,data) 		(void) (type); (void) (param); (void) (bus); (void) (data)
62
63
64#pragma mark -IOService Overrides -
65
66// 33 prd  descriptors are normally required to satisfy a
67// maximum ATA transaction of 256 * 512 byte sectors.
68// however due to restrictions on PCI style DMA engines,
69// the number of descriptors must increase to something more
70// than that.
71#define kATAXferDMADesc 64
72#define kATAMaxDMADesc kATAXferDMADesc
73
74// up to 256 ATA sectors per transfer
75#define kMaxATAXfer	512 * 256
76
77#define _prdBuffer	reserved->_prdBuffer
78
79
80//---------------------------------------------------------------------------
81
82#define super IOATAController
83
84OSDefineMetaClass( IOPCIATA, IOATAController )
85OSDefineAbstractStructors( IOPCIATA, IOATAController )
86    OSMetaClassDefineReservedUnused(IOPCIATA, 0);
87    OSMetaClassDefineReservedUnused(IOPCIATA, 1);
88    OSMetaClassDefineReservedUnused(IOPCIATA, 2);
89    OSMetaClassDefineReservedUnused(IOPCIATA, 3);
90    OSMetaClassDefineReservedUnused(IOPCIATA, 4);
91    OSMetaClassDefineReservedUnused(IOPCIATA, 5);
92    OSMetaClassDefineReservedUnused(IOPCIATA, 6);
93    OSMetaClassDefineReservedUnused(IOPCIATA, 7);
94    OSMetaClassDefineReservedUnused(IOPCIATA, 8);
95    OSMetaClassDefineReservedUnused(IOPCIATA, 9);
96    OSMetaClassDefineReservedUnused(IOPCIATA, 10);
97    OSMetaClassDefineReservedUnused(IOPCIATA, 11);
98    OSMetaClassDefineReservedUnused(IOPCIATA, 12);
99    OSMetaClassDefineReservedUnused(IOPCIATA, 13);
100    OSMetaClassDefineReservedUnused(IOPCIATA, 14);
101    OSMetaClassDefineReservedUnused(IOPCIATA, 15);
102    OSMetaClassDefineReservedUnused(IOPCIATA, 16);
103    OSMetaClassDefineReservedUnused(IOPCIATA, 17);
104    OSMetaClassDefineReservedUnused(IOPCIATA, 18);
105    OSMetaClassDefineReservedUnused(IOPCIATA, 19);
106    OSMetaClassDefineReservedUnused(IOPCIATA, 20);
107
108//---------------------------------------------------------------------------
109
110bool
111IOPCIATA::init(OSDictionary * properties)
112{
113
114    DLOG("IOPCIATA::init() starting\n");
115
116    // Initialize instance variables.
117	_bmCommandReg = 0;
118	_bmStatusReg = 0;
119	_bmPRDAddresReg = 0;
120
121	_prdTable = 0;
122	_prdTablePhysical = 0;
123	_DMACursor = 0;
124
125	_dmaState = IOPCIATA::kATADMAInactive;
126
127
128
129    if (super::init(properties) == false)
130    {
131        DLOG("IOPCIATA: super::init() failed\n");
132        return false;
133    }
134
135
136    DLOG("IOPCIATA::init() done\n");
137
138
139    return true;
140}
141
142
143
144/*---------------------------------------------------------------------------
145 *
146 *	Override IOService start.
147 *
148 *	Subclasses should override the start method, call the super::start
149 *	first then add interrupt sources and probe their busses for devices
150 *	and create device nubs as needed.
151 ---------------------------------------------------------------------------*/
152
153bool
154IOPCIATA::start(IOService *provider)
155{
156     DLOG("IOPCIATA::start() begin\n");
157
158 	// call start on the superclass
159    if (!super::start( provider))
160 	{
161        DLOG("IOPCIATA: super::start() failed\n");
162        return false;
163	}
164
165	reserved = ( ExpansionData * ) IOMalloc ( sizeof ( ExpansionData ) );
166	if ( !reserved )
167		return false;
168
169	bzero ( reserved, sizeof ( ExpansionData ) );
170
171	// Allocate the DMA descriptor area
172	if( ! allocDMAChannel() )
173	{
174        DLOG("IOPCIATA:  allocDMAChannel failed\n");
175		return false;
176
177	}
178
179    DLOG("IOPCIATA::start() done\n");
180    return true;
181}
182
183/*---------------------------------------------------------------------------
184 *	free() - the pseudo destructor. Let go of what we don't need anymore.
185 *
186 *
187 ---------------------------------------------------------------------------*/
188void
189IOPCIATA::free()
190{
191
192	freeDMAChannel();
193
194	if ( reserved )
195	{
196		IOFree ( reserved, sizeof ( ExpansionData ) );
197		reserved = NULL;
198	}
199
200	super::free();
201
202
203}
204
205
206#pragma mark -initialization-
207
208
209
210/*---------------------------------------------------------------------------
211 *
212 *	allocate memory and resources for the DMA descriptors.
213 *
214 *
215 ---------------------------------------------------------------------------*/
216bool
217IOPCIATA::allocDMAChannel(void)
218{
219
220	if(  _bmCommandReg == 0
221		||	_bmStatusReg == 0
222		|| _bmPRDAddresReg == 0 )
223	{
224
225		DLOG("IOPCIATA bm regs not initialised.\n");
226		return false;
227
228	}
229
230	_prdBuffer = IOBufferMemoryDescriptor::inTaskWithPhysicalMask(
231		kernel_task,
232		kIODirectionInOut | kIOMemoryPhysicallyContiguous,
233		sizeof(PRD) * kATAMaxDMADesc,
234		0xFFFFFFF0UL );
235
236    if ( !_prdBuffer )
237    {
238        IOLog("%s: PRD buffer allocation failed\n", getName());
239        return false;
240    }
241
242	_prdBuffer->prepare ( );
243
244	_prdTable			= (PRD *) _prdBuffer->getBytesNoCopy();
245	_prdTablePhysical	= _prdBuffer->getPhysicalAddress();
246
247	_DMACursor = IONaturalMemoryCursor::withSpecification(0x10000, /*64K*/
248                                       					kMaxATAXfer  /* 256 * 512 */
249                                     					/*inAlignment - Memory descriptors and cursors don't support alignment
250                                     					flags yet. */);
251
252
253	if( ! _DMACursor )
254	{
255		freeDMAChannel();
256		DLOG("IOPCIATA alloc DMACursor failed\n");
257		return false;
258	}
259
260
261	// fill the chain with stop commands to initialize it.
262	initATADMAChains(_prdTable);
263
264	return true;
265}
266
267
268/*---------------------------------------------------------------------------
269 *
270 *	deallocate memory and resources for the DMA descriptors.
271 *
272 *
273 ---------------------------------------------------------------------------*/
274bool
275IOPCIATA::freeDMAChannel(void)
276{
277
278	if( _prdBuffer )
279	{
280		// make sure the engine is stopped
281		stopDMA();
282
283		// free the descriptor table.
284        _prdBuffer->complete();
285        _prdBuffer->release();
286        _prdBuffer = NULL;
287        _prdTable = NULL;
288        _prdTablePhysical = 0;
289	}
290
291	if( _DMACursor )
292	{
293
294		_DMACursor->release();
295		_DMACursor = NULL;
296
297	}
298
299	return true;
300}
301
302
303
304
305#pragma mark -DMA Interface-
306
307/*---------------------------------------------------------------------------
308 *
309 * Subclasses should take necessary action to create DMA channel programs,
310 * for the current memory descriptor in _currentCommand and activate the
311 * the DMA hardware
312 ---------------------------------------------------------------------------*/
313IOReturn
314IOPCIATA::startDMA( void )
315{
316
317	IOReturn err = kATANoErr;
318
319	// first make sure the engine is stopped.
320	stopDMA();
321
322
323	// reality check the memory descriptor in the current command
324
325	// state flag
326	_dmaState = kATADMAStarting;
327
328	// create the channel commands
329	err = createChannelCommands();
330
331	if(	err )
332	{
333
334		DLOG("IOPCIATA error createChannelCmds err = %ld\n", (long int)err);
335		stopDMA();
336		return err;
337
338	}
339
340	// fire the engine
341	activateDMAEngine();
342
343	return err;
344
345
346}
347
348
349
350
351/*---------------------------------------------------------------------------
352 * Subclasses should take all actions necesary to safely shutdown DMA engines
353 * in any state of activity, whether finished, pending or stopped. Calling
354 * this function must be harmless reguardless of the state of the engine.
355 *
356 ---------------------------------------------------------------------------*/
357IOReturn
358IOPCIATA::stopDMA( void )
359{
360
361	if(_dmaState != kATADMAInactive)
362		shutDownATADMA();
363
364
365	_dmaState = kATADMAInactive;
366	return kATANoErr;
367
368}
369
370#pragma mark -DMA Implementation-
371
372
373//----------------------------------------------------------------------------------------
374//	Function:		InitATADMAChains
375//	Description:	Initializes the chains with STOP commands.
376//
377//	Input:			Pointer to the DBDMA descriptor area: descPtr
378//
379//	Output:			None
380//----------------------------------------------------------------------------------------
381void
382IOPCIATA::initATADMAChains (PRD* descPtr)
383{
384	UInt32 i;
385
386	/* Initialize the data-transfer PRD channel command descriptors. */
387
388
389	for (i = 0; i < kATAMaxDMADesc; i++)
390	{
391		descPtr->bufferPtr = 0;
392		descPtr->byteCount = 1;
393		// set the stop DMA bit on the last transaction.
394		descPtr->flags = OSSwapHostToLittleInt16( (UInt16) kLast_PRD);
395		descPtr++;
396	}
397}
398
399
400/*----------------------------------------------------------------------------------------
401//	Function:		stopDMAEngine
402//	Description:	Stops the DMA engine itself.  on the ATA bus
403//	Input:			none
404//	Output:			None
405----------------------------------------------------------------------------------------*/
406void
407IOPCIATA::stopDMAEngine(void)
408{
409	OSSynchronizeIO();
410	*_bmCommandReg = mBMCmdStop;
411
412}
413
414
415
416/*----------------------------------------------------------------------------------------
417//	Function:		activateDMAEngine
418//	Description:	Activate the dma engine on the ATA bus associated with current device.
419					engine will begin executing the command chain already programmed.
420//	Input:			None
421//	Output:			None
422//----------------------------------------------------------------------------------------*/
423void
424IOPCIATA::activateDMAEngine(void)
425{
426
427	DLOG("IOPCIATA prd table is at: %lx\n", _prdTablePhysical);
428
429	// clear error bit prior to starting.
430	*_bmStatusReg = (UInt8) mBMStatusError | mBMStatusInt | (_currentCommand->getUnit() == 0 ? mBMStatusDrv0 : mBMStatusDrv1) ;
431	OSSynchronizeIO();
432
433	// set the address pointer.
434	*_bmPRDAddresReg = OSSwapHostToLittleInt32((UInt32) _prdTablePhysical);
435	OSSynchronizeIO();
436
437	// active the DMA engine.
438	UInt8 theCommand = (_currentCommand->getFlags() & mATAFlagIORead) ?  mBMCmdStartInput : mBMCmdStartOutput;
439
440	DLOG("IOPCIATA: bmCommand is %X\n", theCommand);
441
442
443	*_bmCommandReg = theCommand;
444	OSSynchronizeIO();
445
446
447	DLOG("IOPCIATA: bmStaus is %X\n", *_bmStatusReg);
448
449
450}
451
452
453//----------------------------------------------------------------------------------------
454//	Function:		ShutDownATADMA
455//	Description:	Stops the dma engine on the current ATA bus.
456//					This routine is used to stop the DMA
457//					such as may be desired during error recovery.
458//	Input:			None
459//	Output:			None
460//----------------------------------------------------------------------------------------
461void
462IOPCIATA::shutDownATADMA (void)
463{
464
465	// set the state semaphore
466	_dmaState = kATADMAInactive;
467
468	stopDMAEngine();
469
470}
471
472
473/********************************************************************************
474*                                                                               *
475*	s e t P R D                                                                 *
476*                                                                               *
477*********************************************************************************
478*
479*	Purpose:	Fills in the "Physical Region Descriptor" with the correct
480*				endian-ness
481*
482*	Input:		bffr - pointer to data
483*				count - of bytes in this data buffer
484*				tableElement - points to PRD to use
485*
486*	Output:		PRD - filled in
487*
488********************************************************************************/
489
490void
491IOPCIATA::setPRD(UInt8 *bffr, UInt16 count, PRD *tableElement, UInt16 end)
492{
493	DLOG("IOPCIATA set PRD ptr = %lx count = %x flags = %x\n", (long) bffr, count, end);
494
495	tableElement->bufferPtr = OSSwapHostToLittleInt32((UInt32)(uintptr_t)bffr);
496	tableElement->byteCount = OSSwapHostToLittleInt16(count);
497	tableElement->flags = OSSwapHostToLittleInt16(end);
498}
499
500
501/*---------------------------------------------------------------------------
502 *
503 *	create the DMA channel commands.
504 *
505 *
506 ---------------------------------------------------------------------------*/
507IOReturn
508IOPCIATA::createChannelCommands(void)
509{
510	IOMemoryDescriptor* descriptor = _currentCommand->getBuffer();
511	IOMemoryCursor::PhysicalSegment physSegment;
512	UInt32 index = 0;
513	UInt8		*xferDataPtr, *ptr2EndData, *next64KBlock, *starting64KBlock;
514	UInt32		xferCount, count2Next64KBlock;
515
516	if( ! descriptor )
517	{
518
519		DLOG("IOPCIATA nil buffer!\n");
520		return -1;
521	}
522
523	// This form of DMA engine can only do 1 pass. It cannot execute multiple chains.
524
525	// calculate remaining bytes in this transfer
526	IOByteCount bytesRemaining = _currentCommand->getByteCount() ;
527
528	// calculate position pointer
529	IOByteCount xfrPosition = _currentCommand->getPosition() ;
530
531	IOByteCount  transferSize = 0;
532
533	// There's a unique problem with pci-style controllers, in that each dma transaction is not allowed to
534	// cross a 64K boundary. This leaves us with the yucky task of picking apart any descriptor segments that
535	// cross such a boundary ourselves.
536
537		while( _DMACursor->getPhysicalSegments(
538											descriptor,
539					       					xfrPosition,
540					       					&physSegment,
541					     					1,
542					     					bytesRemaining,  // limit to the requested number of bytes in the event the descriptors is larger
543					       					&transferSize) )
544		{
545
546			xferDataPtr = (UInt8*) physSegment.location;
547			xferCount = physSegment.length;
548
549			// update the bytes remaining after this pass
550			bytesRemaining -= xferCount;
551			xfrPosition += xferCount;
552
553			// now we have to examine the segment to see whether it crosses (a) 64k boundary(s)
554			starting64KBlock = (UInt8*) ( (uintptr_t) xferDataPtr & 0xffff0000);
555			ptr2EndData = xferDataPtr + xferCount;
556			next64KBlock  = (starting64KBlock + 0x10000);
557
558
559			// loop until this physical segment is fully accounted for.
560			// it is possible to have a memory descriptor which crosses more than one 64K boundary in a
561			// single span.
562			while( xferCount > 0 )
563			{
564				if (ptr2EndData > next64KBlock)
565				{
566					count2Next64KBlock = next64KBlock - xferDataPtr;
567					if (index < kATAMaxDMADesc)
568					{
569						setPRD(xferDataPtr, (UInt16)count2Next64KBlock, &_prdTable[index], kContinue_PRD);
570						xferDataPtr = next64KBlock;
571						next64KBlock += 0x10000;
572						xferCount -= count2Next64KBlock;
573						index++;
574
575					} else {
576
577						DLOG("IOPCIATA dma too big, PRD table exhausted A.\n");
578						_dmaState = kATADMAError;
579						return -1;
580					}
581
582				} else {
583
584					if (index < kATAMaxDMADesc)
585					{
586						setPRD(xferDataPtr, (UInt16) xferCount, &_prdTable[index], (bytesRemaining == 0) ? kLast_PRD : kContinue_PRD);
587						xferCount = 0;
588						index++;
589
590					} else {
591
592						DLOG("IOPCIATA dma too big, PRD table exhausted B.\n");
593						_dmaState = kATADMAError;
594						return -1;
595					}
596				}
597			}
598
599	} // end of segment counting loop.
600
601
602
603	// transfer is satisfied and only need to check status on interrupt.
604	_dmaState = kATADMAStatus;
605
606	DLOG("IOPCIATA PRD chain end %ld \n", index);
607
608
609	// chain is now ready for execution.
610
611	return kATANoErr;
612
613}
614
615
616
617/*---------------------------------------------------------------------------
618 *
619 *	handleDeviceInterrupt - overriden here so we can make sure that the DMA has
620 * processed in the event first.
621 *
622 ---------------------------------------------------------------------------*/
623IOReturn
624IOPCIATA::handleDeviceInterrupt(void)
625{
626
627
628	if( _dmaState == kATADMAStatus )
629	{
630		OSSynchronizeIO();
631		UInt8 bmStatus = *_bmStatusReg;
632
633		if( bmStatus & mBMStatusError )
634		{
635
636			_dmaState = kATADMAError;
637
638		} else {
639
640			_currentCommand->setActualTransfer(_currentCommand->getByteCount());
641			_dmaState = kATADMAComplete;
642		}
643		stopDMA();
644
645	}
646	return super::handleDeviceInterrupt();
647
648}
649
650
651
652