1/* 2 * Copyright (c) 2000-2008 Apple, Inc. All rights reserved. 3 * 4 * @APPLE_LICENSE_HEADER_START@ 5 * 6 * The contents of this file constitute Original Code as defined in and 7 * are subject to the Apple Public Source License Version 1.1 (the 8 * "License"). You may not use this file except in compliance with the 9 * License. Please obtain a copy of the License at 10 * http://www.apple.com/publicsource and read it before using this file. 11 * 12 * This Original Code and all software distributed under the License are 13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER 14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the 17 * License for the specific language governing rights and limitations 18 * under the License. 19 * 20 * @APPLE_LICENSE_HEADER_END@ 21 */ 22 23/* 24 * 25 * IOATAController.cpp 26 * 27 */ 28 29 30#include <IOKit/assert.h> 31#include <IOKit/IOCommandGate.h> 32#include <IOKit/IOTypes.h> 33#include <IOKit/IOTimerEventSource.h> 34#include <IOKit/storage/IOStorageProtocolCharacteristics.h> 35#include "IOATATypes.h" 36#include "IOATAController.h" 37#include "IOATACommand.h" 38#include "IOATADevice.h" 39#include "IOATABusInfo.h" 40#include "IOATADevConfig.h" 41#include "IOATABusCommand.h" 42#include "ATATimerEventSource.h" 43 44 45#include <libkern/OSByteOrder.h> 46#include <libkern/OSAtomic.h> 47 48 49// for wait U8Status, loop time in uS 50#define kStatusDelayTime 5 51// how many times through the loop for a MS. 52#define kStatusDelayLoopMS 1000 / kStatusDelayTime 53 54 55#define _doubleBufferDesc reserved->_doubleBufferDesc 56 57 58#ifdef DLOG 59#undef DLOG 60#endif 61 62//#define ATA_DEBUG 1 63 64#ifdef ATA_DEBUG 65#define DLOG(fmt, args...) IOLog(fmt, ## args) 66#else 67#define DLOG(fmt, args...) 68#endif 69 70 71#pragma mark -IOService Overrides - 72 73 74 75//--------------------------------------------------------------------------- 76 77#define super IOService 78 79OSDefineMetaClass( IOATAController, IOService ) 80OSDefineAbstractStructors( IOATAController, IOService ) 81 OSMetaClassDefineReservedUnused(IOATAController, 0); 82 OSMetaClassDefineReservedUnused(IOATAController, 1); 83 OSMetaClassDefineReservedUnused(IOATAController, 2); 84 OSMetaClassDefineReservedUnused(IOATAController, 3); 85 OSMetaClassDefineReservedUnused(IOATAController, 4); 86 OSMetaClassDefineReservedUnused(IOATAController, 5); 87 OSMetaClassDefineReservedUnused(IOATAController, 6); 88 OSMetaClassDefineReservedUnused(IOATAController, 7); 89 OSMetaClassDefineReservedUnused(IOATAController, 8); 90 OSMetaClassDefineReservedUnused(IOATAController, 9); 91 OSMetaClassDefineReservedUnused(IOATAController, 10); 92 OSMetaClassDefineReservedUnused(IOATAController, 11); 93 OSMetaClassDefineReservedUnused(IOATAController, 12); 94 OSMetaClassDefineReservedUnused(IOATAController, 13); 95 OSMetaClassDefineReservedUnused(IOATAController, 14); 96 OSMetaClassDefineReservedUnused(IOATAController, 15); 97 OSMetaClassDefineReservedUnused(IOATAController, 16); 98 OSMetaClassDefineReservedUnused(IOATAController, 17); 99 OSMetaClassDefineReservedUnused(IOATAController, 18); 100 OSMetaClassDefineReservedUnused(IOATAController, 19); 101 OSMetaClassDefineReservedUnused(IOATAController, 20); 102 103//--------------------------------------------------------------------------- 104 105 106 107bool 108IOATAController::init(OSDictionary * properties) 109{ 110 DLOG("IOATAController::init() starting\n"); 111 112 113 // Initialize instance variables. 114 // 115 _workLoop = 0; 116 _cmdGate = 0; 117 _provider = 0; 118 _timer = 0; 119 120 queue_init( &_commandQueue ); 121 122 if (super::init(properties) == false) 123 { 124 DLOG("IOATAController: super::init() failed\n"); 125 return false; 126 } 127 128 DLOG("IOATAController::init() done\n"); 129 130 return true; 131} 132 133 134/*--------------------------------------------------------------------------- 135 * 136 * Check and see if we really match this device. 137 * override to accept or reject close matches based on further information 138 ---------------------------------------------------------------------------*/ 139 140IOService* 141IOATAController::probe(IOService* provider, SInt32* score) 142{ 143 144 return this; 145 146} 147 148/*--------------------------------------------------------------------------- 149 * 150 * Override IOService start. 151 * 152 * Subclasses should override the start method, call the super::start 153 * first then add interrupt sources and probe their busses for devices 154 * and create device nubs as needed. 155 ---------------------------------------------------------------------------*/ 156 157bool 158IOATAController::start(IOService *provider) 159{ 160 161 OSObject * prop; 162 163 DLOG("IOATAController::start() begin\n"); 164 165 _provider = provider; 166 _busState = IOATAController::kBusFree; 167 _currentCommand = 0L; 168 _selectedUnit = kATAInvalidDeviceID; 169 _queueState = IOATAController::kQueueOpen; 170 171 // call start on the superclass 172 if (!super::start(_provider)) 173 { 174 DLOG("IOATAController: super::start() failed\n"); 175 return false; 176 } 177 178 prop = getProperty ( kIOPropertyPhysicalInterconnectTypeKey, gIOServicePlane ); 179 if ( prop == NULL ) 180 { 181 setProperty ( kIOPropertyPhysicalInterconnectTypeKey, kIOPropertyPhysicalInterconnectTypeATA); 182 } 183 184 prop = getProperty ( kIOPropertyPhysicalInterconnectLocationKey, gIOServicePlane ); 185 if ( prop == NULL ) 186 { 187 setProperty ( kIOPropertyPhysicalInterconnectLocationKey, kIOPropertyInternalKey); 188 } 189 190 reserved = ( ExpansionData * ) IOMalloc ( sizeof ( ExpansionData ) ); 191 if ( !reserved ) 192 return false; 193 194 bzero ( reserved, sizeof ( ExpansionData ) ); 195 196 if( !configureTFPointers() ) 197 { 198 DLOG("IOATA TF Pointers failed\n"); 199 return false; 200 } 201 202 if( !scanForDrives() ) 203 { 204 DLOG("IOATA scan for drives failed\n"); 205 return false; 206 } 207 208 // Allocate the double buffer for PIO (and non-aligned DMA if needed) transfers. 209 if(! allocateDoubleBuffer() ) 210 { 211 DLOG("IOATA doubleBuffer alloc failed\n"); 212 return false; 213 } 214 215 // a device specific subclass will create the work loop and attach 216 _workLoop = getWorkLoop(); 217 if (!_workLoop) 218 { 219 DLOG("IOATA: IOWorkLoop allocation failed\n"); 220 return false; 221 } 222 223 _workLoop->retain(); 224 225 // create a timer event source and attach it to the work loop 226 _timer = ATATimerEventSource::ataTimerEventSource(this, 227 (ATATimerEventSource::Action) timeoutOccured); 228 229 if (!_timer || _workLoop->addEventSource(_timer)) 230 { 231 DLOG("IOATA: ATATImerEventSource allocation failed\n"); 232 return false; 233 } 234 235 236 // create a commandGate and attach it to the work loop. 237 _cmdGate = IOCommandGate::commandGate(this); 238 239 if (!_cmdGate || _workLoop->addEventSource(_cmdGate)) 240 { 241 DLOG("IOATAController: IOCommandGate failed\n"); 242 return false; 243 } 244 245 //3643376 make it easier for ASP to find disk drives in the system. 246 247 registerService(); 248 249 DLOG("IOATAController::start() done\n"); 250 return true; 251} 252 253/*--------------------------------------------------------------------------- 254 * free() - the pseudo destructor. Let go of what we don't need anymore. 255 * 256 * 257 ---------------------------------------------------------------------------*/ 258void 259IOATAController::free() 260{ 261 262 if ( _workLoop ) 263 { 264 265 if ( _cmdGate ) 266 { 267 268 _workLoop->removeEventSource(_cmdGate); 269 _cmdGate = NULL; 270 271 } 272 273 if ( _timer ) 274 { 275 276 _workLoop->removeEventSource(_timer); 277 _timer = NULL; 278 279 } 280 281 _workLoop->release(); 282 283 } 284 285 if ( reserved ) 286 { 287 288 if ( _doubleBufferDesc ) 289 { 290 291 _doubleBufferDesc->complete(); 292 _doubleBufferDesc->release(); 293 _doubleBuffer.bufferSize = 0; 294 _doubleBuffer.logicalBuffer = 0; 295 _doubleBuffer.physicalBuffer = 0; 296 _doubleBufferDesc = NULL; 297 298 } 299 300 } 301 302 if ( reserved ) 303 { 304 IOFree ( reserved, sizeof ( ExpansionData ) ); 305 reserved = NULL; 306 } 307 308 super::free(); 309 310 311} 312 313 314#pragma mark -initialization- 315 316/*--------------------------------------------------------------------------- 317 * 318 // false if couldn't allocate the per-bus double buffer. 319 // controllers should provide implementation where needed 320 // for DMA hardware compatibility. The default method provides 321 // a 4K buffer for PIO since MemoryDescriptors do not by default have 322 // logical addresses in the kernel space. 323 ---------------------------------------------------------------------------*/ 324bool 325IOATAController::allocateDoubleBuffer( void ) 326{ 327 328 DLOG("IOATAController::allocateDoubleBuffer() started\n"); 329 330 _doubleBufferDesc = IOBufferMemoryDescriptor::inTaskWithPhysicalMask( 331 kernel_task, 332 kIODirectionInOut | kIOMemoryPhysicallyContiguous, 333 (kATADefaultSectorSize * 8), 334 0xFFFFF000UL ); 335 336 if ( !_doubleBufferDesc ) 337 { 338 IOLog("%s: double buffer allocation failed\n", getName()); 339 return false; 340 } 341 342 _doubleBufferDesc->prepare(); 343 _doubleBuffer.logicalBuffer = (IOLogicalAddress)_doubleBufferDesc->getBytesNoCopy(); 344 _doubleBuffer.physicalBuffer = _doubleBufferDesc->getPhysicalAddress(); 345 _doubleBuffer.bufferSize = kATADefaultSectorSize * 8; 346 347 DLOG("IOATAController::allocateDoubleBuffer() done\n"); 348 349 return true; 350 351} 352 353/*--------------------------------------------------------------------------- 354 * 355 * Initialize the taskfile pointers to the addresses of the ATA registers 356 * in your hardware. Subclasses must provide implementation. 357 * 358 ---------------------------------------------------------------------------*/ 359bool 360IOATAController::configureTFPointers(void) 361{ 362 363 DLOG("IOATA: configureTFPointers. must provide implementation.\n"); 364 return false; 365 366} 367 368 369#pragma mark -client interface- 370 371/*--------------------------------------------------------------------------- 372 * 373 * select the bus timing configuration for a particular device 374 * should be called by device driver after doing an identify device command and working out 375 * the desired timing configuration. 376 * should be followed by a Set Features comand to the device to set it in a 377 * matching transfer mode. 378 ---------------------------------------------------------------------------*/ 379IOReturn 380IOATAController::selectConfig( IOATADevConfig* configRequest, UInt32 unitNumber) 381{ 382 383 384 DLOG("IOATA: sublcass must implement selectConfig.\n"); 385 386 return kATAModeNotSupported; 387 388} 389 390/*--------------------------------------------------------------------------- 391 * 392 * Find out what the current bus timing configuration is for a particular 393 * device. 394 * Subclasses must implement 395 * 396 ---------------------------------------------------------------------------*/ 397IOReturn 398IOATAController::getConfig( IOATADevConfig* configOut, UInt32 unitNumber) 399{ 400 401 402 DLOG("IOATA: sublcass must implement getConfig.\n"); 403 404 return kATAModeNotSupported; 405 406 407} 408 409/*--------------------------------------------------------------------------- 410 * 411 * All ata controller subclasses must provide an implementation. 412 * 413 * 414 ---------------------------------------------------------------------------*/ 415 416IOReturn 417IOATAController::provideBusInfo( IOATABusInfo* infoOut) 418{ 419 420 DLOG(" IOATA: sublcass must implement provideBusInfo\n"); 421 422 return -1; 423} 424 425 426 427/*--------------------------------------------------------------------------- 428 * 429 * The main call which puts something on the work loop 430 * 431 ---------------------------------------------------------------------------*/ 432 433IOReturn 434IOATAController::executeCommand(IOATADevice* nub, IOATABusCommand* command) 435{ 436 if( !command || !nub ) 437 return -1; 438 439 IOReturn resultCode = kATANoErr; 440 441 // flag the command as in use. 442 command->setCommandInUse(); 443 444 _cmdGate->runAction( (IOCommandGate::Action) 445 &IOATAController::executeCommandAction, 446 (void *) command, // arg 0 447 (void *) &resultCode, // arg 1 448 0, 0); // arg2 arg 3 449 450 451 452 return resultCode; 453} 454 455 456#pragma mark -workloop entry- 457 458 459 460 461/*--------------------------------------------------------------------------- 462 * 463 * Static function called by the internal IOCommandGate object to 464 * handle a runAction() request invoked by executeCommand(). 465 * 466 ---------------------------------------------------------------------------*/ 467void 468IOATAController::executeCommandAction(OSObject * owner, 469 void * arg0, 470 void * arg1, 471 void * /* arg2 */, 472 void * /* arg3 */) 473{ 474 475 476 IOATAController* self = (IOATAController*) owner; 477 IOATABusCommand* command = (IOATABusCommand*) arg0; 478 IOReturn* result = (IOReturn*) arg1; 479 480 // do a little reality check. 481 assert(command && result); 482 483 *result = self->handleCommand( (void*)command ); 484 485} 486 487 488/*--------------------------------------------------------------------------- 489 * 490 * Do something with the command 491 * 492 ---------------------------------------------------------------------------*/ 493IOReturn 494IOATAController::handleCommand( void* param0, /* the command */ 495 void* param1, /* not used = 0 */ 496 void* param2, /* not used = 0 */ 497 void* param3 ) /* not used = 0 */ 498{ 499 500 501 IOATABusCommand* command = (IOATABusCommand*) param0; 502 503 if( command == 0L ) 504 { 505 DLOG("IOATAController::handleCmd nill ptr\n"); 506 return -1; 507 } 508 509 // set the state flag on the transaction. 510 command->state = kATAInitial; 511 512 // Put the command on the queue. 513 enqueueCommand( command ); 514 515 // wake up it is time to go to work 516 dispatchNext(); 517 518 // No error on async commands 519 return kATANoErr; 520 521 522} 523 524 525/*--------------------------------------------------------------------------- 526 * 527 * enqueueCommand looks at the command flags and queues it at the tail if 528 * unless it is immediate, then it puts it at the head of the queue. 529 * 530 ---------------------------------------------------------------------------*/ 531IOReturn 532IOATAController::enqueueCommand( IOATABusCommand* command) 533{ 534 535 // immediate means go to the head of the queue. 536 // This could get sticky - if there's already an 537 // immediate command at the head of the queue. 538 539 // whether a new immediate should go to the head, or behind the 540 // most recent already queued immediate is unsettled at this time. 541 542 if( command->getFlags() & mATAFlagImmediate ) 543 { 544 545 queue_enter_first( &_commandQueue, 546 command, 547 IOATABusCommand*, 548 queueChain ); 549 550 551 } else { 552 553 // put at the tail. 554 555 queue_enter( &_commandQueue, 556 command, 557 IOATABusCommand*, 558 queueChain ); 559 560 } 561 562 563 return kATANoErr; 564 565} 566 567 568 569/*--------------------------------------------------------------------------- 570 * 571 * dequeueFirstCommand take the first command off the head of the queue 572 * returns a IOATABusCommand*, or nil if empty. 573 * 574 ---------------------------------------------------------------------------*/ 575IOATABusCommand* 576IOATAController::dequeueFirstCommand( void ) 577{ 578 579 IOATABusCommand* cmdPtr = 0L; 580 581 if( !queue_empty( &_commandQueue ) ) 582 { 583 queue_remove_first( &_commandQueue, 584 cmdPtr, 585 IOATABusCommand*, 586 queueChain ); 587 588 } 589 return cmdPtr; 590 591} 592 593/*--------------------------------------------------------------------------- 594 * true - bus is ready to dispatch commands 595 * false - bus is busy with a current command. 596 * 597 ---------------------------------------------------------------------------*/ 598bool 599IOATAController::busCanDispatch( void ) 600{ 601 602 // normal case 603 if( _busState == IOATAController::kBusFree 604 && _queueState == IOATAController::kQueueOpen ) 605 { 606 return true; 607 } 608 609 610 // special case if we are dispatching immediate commands only 611 if( _busState == IOATAController::kBusFree 612 && _queueState == IOATAController::kQueueLocked 613 && _immediateGate == kImmediateOK 614 && !queue_empty( &_commandQueue ) ) 615 { 616 617 DLOG("IOATA Qfrozen check for immediate\n"); 618 619 // make sure the head of the queue is immediate 620 IOATABusCommand* cmdPtr = (IOATABusCommand*) queue_first( & _commandQueue ) ; 621 622 if( cmdPtr != 0 623 && (cmdPtr->getFlags() & mATAFlagImmediate) ) 624 { 625 DLOG("IOTA q-head is immediate\n"); 626 return true; 627 } 628 } 629 630 631 // otherwise no dispatch. 632 return false; 633 634} 635 636 637/*--------------------------------------------------------------------------- 638 * 639 * this should only be called on the single-threaded side of the command gate. 640 * 641 * 642 ---------------------------------------------------------------------------*/ 643IOReturn 644IOATAController::dispatchNext( void ) 645{ 646 647 IOReturn result = kATANoErr; 648 649 DLOG("IOATAController::dispatchNext start\n"); 650 651 // check that the hardware is free and ready to accept commands 652 if( !busCanDispatch() ) 653 return result; 654 655 // set the bus state flag 656 _busState = IOATAController::kBusBusy; 657 658 // take the command at the head of the queue and make current. 659 _currentCommand = dequeueFirstCommand(); 660 661 if( _currentCommand == 0L ) 662 { 663 // if there's nothing in the queue, free the bus and 664 // return. 665 666 DLOG("IOATAController::dispatchNext queue empty\n"); 667 _busState = IOATAController::kBusFree; 668 return kATAQueueEmpty; 669 670 } 671 672 // set the state flag on the transaction. 673 _currentCommand->state = IOATAController::kATAStarted; 674 675 // IF we are in the special case circumstance of running commands 676 // that re-enter the command gate because they were dispatched during 677 // an executeEventCallout(), we MUST poll the device for command completion 678 // This is an ugly artifact of the workloop design. 679 680 if( _queueState == IOATAController::kQueueLocked 681 && _immediateGate == kImmediateOK 682 && _currentCommand->getFlags() & mATAFlagImmediate) 683 { 684 685 _currentCommand->setFlags(_currentCommand->getFlags() | mATAFlagUseNoIRQ ); 686 687 } 688 689 // in case someone tries to slip a reset command through as an exec IO. 690 691 if( _currentCommand->getTaskFilePtr()->ataTFCommand == 0x08 ) 692 { 693 694 _currentCommand->setOpcode(kATAFnBusReset); 695 } 696 697 698 switch( _currentCommand->getOpcode() ) 699 { 700 701 702 case kATAFnExecIO: /* Execute ATA I/O */ 703 case kATAPIFnExecIO: /* ATAPI I/O */ 704 result = handleExecIO(); 705 break; 706 707 case kATAFnRegAccess: /* Register Access */ 708 result = handleRegAccess(); 709 break; 710 711 case kATAFnBusReset: /* Reset ATA bus */ 712 result = handleBusReset(); 713 break; 714 715 case kATAFnQFlush: /* I/O Queue Release */ 716 result = handleQueueFlush(); 717 break; 718 719 720 default: 721 _currentCommand->setResult( kATAUnknownOpcode ); 722 result = kATAUnknownOpcode; 723 _currentCommand->state = IOATAController::kATAComplete; 724 completeIO(kATAUnknownOpcode); 725 break; 726 727 } 728 729 DLOG("IOATAController::dispatchNext done return = %ld\n", (long int)result); 730 731 return result; 732 733} 734 735 736 737/*--------------------------------------------------------------------------- 738 * Calls the device driver(s) which are connected to this bus in order to 739 * inform them that an event occurred that may require their attention. 740 * Resets would be such an event, as the drivers may need to immediately 741 * reconfigure their devices BEFORE any other commands may be issued. 742 * 743 ---------------------------------------------------------------------------*/ 744void 745IOATAController::executeEventCallouts( ataEventCode event, ataUnitID unit ) 746{ 747 748 // make the current command local, in preparation for allowing 749 // immediate commands through. 750 IOATABusCommand* currCommand = _currentCommand; 751 UInt32 currQueueState = _queueState; 752 UInt32 currBusState = _busState; 753 UInt32 currImmed = _immediateGate; 754 755 // unbusy the bus, but freeze the queue 756 // this allows immediate commands to run 757 _queueState = kQueueLocked; 758 _busState = kBusFree; 759 _immediateGate = kImmediateOK; 760 _currentCommand = 0; 761 762 763 for( int i = 0; i < 2; i++) 764 { 765 // call the device as requested, or both devices if the unit id 766 // isn't 0 or 1. 767 if( (_nub[i] != 0L ) 768 && ( (unit == kATAInvalidDeviceID) || (unit == i) ) ) 769 { 770 // during notify event, device drivers will have an opportunity 771 // to execute commands to their devices in immediate mode on this thread. 772 773 _nub[i]->notifyEvent( event ); 774 775 } 776 777 } 778 779 // retore the state of the bus, queue, immediate gate and current commands 780 781 _queueState = currQueueState; 782 _busState = currBusState; 783 _immediateGate = currImmed; 784 _currentCommand = currCommand; 785 786 787} 788 789 790/*--------------------------------------------------------------------------- 791 * 792 * 793 * 794 * 795 ---------------------------------------------------------------------------*/ 796void 797IOATAController::completeIO( IOReturn commandResult ) 798{ 799 DLOG("IOATAController::completeIO start = %ld\n",(long int)commandResult); 800 801 802 // make the current command local and nil the command in execution. 803 IOATABusCommand* finishedCmd = _currentCommand; 804 // someone called completeIO with no command executing. 805 if( finishedCmd == 0L ) 806 return; 807 808 // nil the current command 809 _currentCommand = 0L; 810 811 finishedCmd->state = IOATAController::kATADone; 812 813 // clear the timer if it is running. 814 stopTimer(); 815 stopDMA(); 816 817 // set the bus state to free to allow next dispatch. 818 _busState = IOATAController::kBusFree; 819 820 // set the result code in case someone didn't update it already. 821 finishedCmd->setResult(commandResult); 822 823 // complete the IO and execute the callback if any prior to 824 // dispatching next command. Gives device drivers a chance to 825 // recover from error. 826 finishedCmd->executeCallback(); 827 828 dispatchNext(); 829 830 DLOG("IOATAController::completeIO done\n"); 831 832 833} 834 835#pragma mark -timers- 836/*--------------------------------------------------------------------------- 837 * start the transaction timer for a transaction. 838 * 839 * 840 * 841 ---------------------------------------------------------------------------*/ 842IOReturn 843IOATAController::startTimer( UInt32 inMS) 844{ 845 IOReturn err = kATANoErr; 846 847 // make sure it is not armed first. 848 _timer->disable(); 849 _timer->cancelTimeout(); 850 851 // arm the timer 852 _timer->enable(); 853 err = _timer->setTimeoutMS( inMS ); 854 855 if( err ) 856 { 857 DLOG("IOATAController::startTimer failed\n"); 858 859 } 860 861 return err; 862 863} 864 865/*--------------------------------------------------------------------------- 866 * 867 * Kill a running timer. 868 * 869 * 870 ---------------------------------------------------------------------------*/ 871void 872IOATAController::stopTimer(void) 873{ 874 _timer->disable(); 875 _timer->cancelTimeout(); 876 877} 878 879 880/*--------------------------------------------------------------------------- 881 * 882 * simple static function that is called by the timerEventSource via the 883 * command gate. 884 * 885 ---------------------------------------------------------------------------*/ 886void 887IOATAController::timeoutOccured(OSObject *owner, IOTimerEventSource *sender) 888{ 889 IOATAController* self = (IOATAController*) owner; 890 self->handleTimeout(); 891} 892 893 894/*--------------------------------------------------------------------------- 895 * Timer event sources can't fire while we're on the safe side of a command gate 896 * so we need a way to check for a timeout happening while we are inside 897 * the thread-safe part of the code. Unfortunately, TimerEventSource provides 898 * no means to check if it has expired, so this function always returns false 899 * for now. Eventually, either Timer will get an subclass that allows this. 900 ---------------------------------------------------------------------------*/ 901bool 902IOATAController::checkTimeout( void ) 903{ 904 // check to see if the timer has expired while on the 905 // safe side of the command-gate. 906 907 return _timer->hasTimedOut(); 908 909} 910 911 912/*--------------------------------------------------------------------------- 913 * 914 * Do what is necessary to fail the current IO command because the HW did not 915 * respond within the alloted time. 916 * 917 ---------------------------------------------------------------------------*/ 918void 919IOATAController::handleTimeout( void ) 920{ 921 // if there's a current command, kill it with timeout error 922 923 if( _currentCommand != 0L ) 924 { 925 926 if( (_currentCommand->getFlags() & mATAFlagUseDMA ) == mATAFlagUseDMA ) 927 { 928 stopDMA(); 929 930 } 931 932 _currentCommand->setResult( kATATimeoutErr ); 933 _currentCommand->state = IOATAController::kATAComplete; 934 asyncStatus(); 935 completeIO(kATATimeoutErr); 936 937 } else { 938 939 // otherwise, check and see if there's anything to dispatch 940 // that has been overlooked somehow. 941 dispatchNext(); 942 943 } 944 945} 946 947#pragma mark -Workloop handlers- 948/*--------------------------------------------------------------------------- 949 * 950 * handleDeviceInterrupt - once the primary part of the device interrupt 951 * service routine determines that a device interrupt has occured and is 952 * valid, this routine should be called to handle the post interrupt service 953 * 954 ---------------------------------------------------------------------------*/ 955IOReturn 956IOATAController::handleDeviceInterrupt(void) 957{ 958 // mark volatile to enforce reading the register. 959 volatile UInt8 status = 0x00; 960 961 // make sure there's a command active 962 if( !_currentCommand ) 963 { 964 DLOG("IOATA Device Int no command active\n"); 965 return kATADevIntNoCmd; 966 } 967 // read the actual status register to clear the interrupt. 968 status = *_tfStatusCmdReg; 969 OSSynchronizeIO(); 970 971 return asyncIO(); 972 973} 974 975/*--------------------------------------------------------------------------- 976 * 977 * 978 * 979 * 980 ---------------------------------------------------------------------------*/ 981 982IOReturn 983IOATAController::handleExecIO( void ) 984{ 985 IOReturn err = kATANoErr; 986 987 // select the desired device 988 // don't start the IOTimer until after selection as there are no 989 // generation counts in the IOTimerEventSource. Device Selection will honor 990 // the timeout value in ms on its own. 991 err = selectDevice( _currentCommand->getUnit() ); 992 if( err ) 993 { 994 IOLog("IOATAController device blocking bus.\n"); 995 _currentCommand->state = IOATAController::kATAComplete; 996 997 if( _currentCommand->getFlags() & mATAFlagUseNoIRQ ) 998 { 999 completeIO( kIOReturnOffline ); 1000 return kIOReturnOffline; 1001 } 1002 1003 startTimer( 1000 ); // start a 1 second timeout so that we can unwind the stack if the bus is stuck. 1004 return kATANoErr; // defer error handling to the timer thread. 1005 } 1006 1007 // start the IO Timer 1008 startTimer( _currentCommand->getTimeoutMS() ); 1009 1010 1011 // go to asyncIO and start the state machine. 1012 // indicate the command has been issued 1013 _currentCommand->state = IOATAController::kATAStarted; 1014 if( _currentCommand->getFlags() & mATAFlagUseNoIRQ ) 1015 { 1016 err = synchronousIO(); 1017 } else { 1018 err = asyncIO(); 1019 } 1020 1021 // return success and pend IRQ for further operation or completion. 1022 1023 return err; 1024 1025} 1026 1027/*--------------------------------------------------------------------------- 1028 * 1029 * 1030 * 1031 * 1032 ---------------------------------------------------------------------------*/ 1033IOReturn 1034IOATAController::handleRegAccess( void ) 1035{ 1036 IOReturn err = kATANoErr; 1037 1038 // select the desired device 1039 err = selectDevice( _currentCommand->getUnit() ); 1040 if( err ) 1041 { 1042 _currentCommand->state = IOATAController::kATAComplete; 1043 completeIO( err ); 1044 return err; 1045 } 1046 1047 bool isWrite = (_currentCommand->getFlags() & mATAFlagIOWrite) ? true : false; 1048 1049 err = registerAccess( isWrite ); 1050 _currentCommand->state = IOATAController::kATAComplete; 1051 completeIO( err ); 1052 return err; 1053 1054} 1055 1056 1057/*--------------------------------------------------------------------------- 1058 * 1059 * 1060 * 1061 * 1062 ---------------------------------------------------------------------------*/ 1063IOReturn 1064IOATAController::handleBusReset(void) 1065{ 1066 1067 bool isATAPIReset = ((_currentCommand->getFlags() & mATAFlagProtocolATAPI) != 0); 1068 bool doATAPI[2]; 1069 IOReturn err = kATANoErr; 1070 UInt8 index; 1071 UInt8 statCheck; 1072 1073 DLOG("IOATA bus reset start.\n"); 1074 1075 doATAPI[0] = doATAPI[1] = false; 1076 1077 // If this is an ATAPI reset select just the corresponding atapi device (instead of both) 1078 if(isATAPIReset) 1079 { 1080 doATAPI[_currentCommand->getUnit()] = true; // Mark only selected ATAPI as reset victim. 1081 1082 }else{ 1083 1084 doATAPI[0] = doATAPI[1] = true; // In ATA case, mark both as candidates for reset commands prior to a bus reset. 1085 1086 } 1087 1088 1089 // Issue the needed ATAPI reset commands 1090 for(index=0;index<2;index++) 1091 { 1092 if( doATAPI[index] && _devInfo[index].type == kATAPIDeviceType) 1093 { 1094 OSSynchronizeIO(); 1095 *_tfSDHReg = mATASectorSize + (index << 4); 1096 1097 // read the alt status and disreguard to provide 400ns delay 1098 OSSynchronizeIO(); 1099 statCheck = *_tfAltSDevCReg; 1100 1101 err = softResetBus(true); 1102 } 1103 1104 } 1105 1106 1107 // once the ATAPI device has been reset, contact the device driver 1108 if(isATAPIReset) 1109 { 1110 executeEventCallouts( kATAPIResetEvent, _currentCommand->getUnit() ); 1111 } 1112 1113 1114 // Handle the ATA reset case 1115 if(!isATAPIReset) 1116 { 1117 err = softResetBus(); 1118 executeEventCallouts( kATAResetEvent, kATAInvalidDeviceID ); 1119 } 1120 1121 _currentCommand->state = IOATAController::kATAComplete; 1122 1123 DLOG("IOATA bus reset done.\n"); 1124 1125 1126 completeIO( err ); 1127 1128 1129 return err; 1130 1131} 1132 1133 1134/*--------------------------------------------------------------------------- 1135 * 1136 * 1137 * 1138 * 1139 ---------------------------------------------------------------------------*/ 1140IOReturn 1141IOATAController::handleQueueFlush( void ) 1142{ 1143 1144 //BUG do something here. 1145 1146 1147 return kATANoErr; 1148} 1149 1150 1151/*--------------------------------------------------------------------------- 1152 * 1153 * Use the state-indicator of the current command to figure out what to do 1154 * after an interrupt, etc. This is the heart of the ATA state-machine. 1155 * 1156 ---------------------------------------------------------------------------*/ 1157IOReturn 1158IOATAController::asyncIO(void) 1159{ 1160 IOReturn err = kATANoErr; 1161 1162 if( (_currentCommand->getFlags() & mATAFlagProtocolATAPI) == mATAFlagProtocolATAPI 1163 && _currentCommand->getPacketSize() > 0) 1164 { 1165 1166 _currentCommand->state = determineATAPIState(); 1167 } 1168 1169 switch( _currentCommand->state ) 1170 { 1171 1172 1173 case kATAStarted : // taskfile issue 1174 err = asyncCommand(); 1175 DLOG("ATAController:: command sent: err = %ld state= %lx\n", (long int) err, (int) _currentCommand->state); 1176 if( err ) 1177 { 1178 _currentCommand->state = IOATAController::kATAComplete; 1179 asyncStatus(); 1180 break; 1181 } 1182 1183 // if next state isn't write packet, or if the packet device asserts IRQ, 1184 // return pending the next interrupt. 1185 if( _currentCommand->state != IOATAController::kATAPICmd 1186 || _devInfo[ _currentCommand->getUnit() ].packetSend == kATAPIIRQPacket ) 1187 { 1188 // pending IRQ 1189 DLOG("ATAController:: pending IRQ for packet\n"); 1190 break; 1191 } 1192 1193 // otherwise fall through and send the packet for DRQ devices. 1194 case kATAPICmd: // packet issue 1195 DLOG("ATAController:: issue packet\n"); 1196 err = writePacket(); 1197 if( err ) 1198 { 1199 _currentCommand->state = IOATAController::kATAComplete; 1200 asyncStatus(); 1201 break; 1202 } 1203 1204 // if there's data IO, next phase is dataTx, otherwise check status. 1205 if( (_currentCommand->getFlags() & (mATAFlagIORead | mATAFlagIOWrite ) ) 1206 && ((_currentCommand->getFlags() & mATAFlagUseDMA ) != mATAFlagUseDMA ) ) 1207 { 1208 _currentCommand->state = IOATAController::kATADataTx; 1209 } else { 1210 // this is a non-data command, the next step is to check status. 1211 _currentCommand->state = IOATAController::kATAStatus; 1212 } 1213 1214 break; 1215 1216 case kATADataTx: // PIO data transfer phase 1217 err = asyncData(); 1218 if( err ) 1219 { 1220 _currentCommand->state = IOATAController::kATAComplete; 1221 asyncStatus(); 1222 break; 1223 } 1224 1225 // if there's more data to transfer, then 1226 // break. If ATA protocol PIO write, then break for IRQ 1227 if(_currentCommand->state == kATADataTx 1228 || ( (_currentCommand->getFlags() & (mATAFlagProtocolATAPI | mATAFlagIOWrite | mATAFlagUseDMA) ) == mATAFlagIOWrite ) ) 1229 { 1230 break; 1231 } 1232 1233 if( (_currentCommand->getFlags() & mATAFlagProtocolATAPI) == mATAFlagProtocolATAPI 1234 && _currentCommand->getPacketSize() > 0) 1235 { 1236 // atapi devices will go to status after an interrupt. 1237 break; 1238 } 1239 1240 // else fall through to status state. 1241 case kATAStatus: // data tx complete 1242 err = asyncStatus(); 1243 _currentCommand->state = IOATAController::kATAComplete; 1244 break; 1245 1246 // state machine is somehow inconsistent 1247 default: 1248 DLOG("IOATA AsyncIO state broken\n"); 1249 err = kATAErrUnknownType; 1250 _currentCommand->state = IOATAController::kATAComplete; 1251 break; 1252 1253 }// end of switch ->state 1254 1255 1256 // call completeIO if the command is marked for completion. 1257 1258 // BUG consider allowing the timeout to run rather than completing 1259 // at this point. It might be safer to simply allow it to execute 1260 // rather than move on the state machine at this point, since there's 1261 // a possible race-condition if the timer expires while still inside the 1262 // command gate. 1263 1264 if( _currentCommand->state == IOATAController::kATAComplete ) 1265 { 1266 completeIO(err); 1267 } 1268 1269 return err; 1270 1271 1272} 1273 1274/*--------------------------------------------------------------------------- 1275 * This is a special-case state machine which synchronously polls the 1276 * status of the hardware while completing the command. This is used only in 1277 * special case of IO's which cannot be completed for some reason using the 1278 * normal interrupt system. This may involve vendor-specific commands, or 1279 * certain instances where the interrupts may not be available, such as when 1280 * handling commands issued as a result of messaging the drivers after a reset 1281 * event. DMA commands are NOT accepted, only non-data and PIO commands. 1282 ---------------------------------------------------------------------------*/ 1283IOReturn 1284IOATAController::synchronousIO(void) 1285{ 1286 IOReturn err = kATANoErr; 1287 1288 OSSynchronizeIO(); 1289 *_tfAltSDevCReg = 0x02; // disable interrupts 1290 1291 1292 // start by issuing the command 1293 err = asyncCommand(); 1294 DLOG("ATAController::synchronous command sent: err = %ld state= %lx\n", (long int) err, (int) _currentCommand->state); 1295 if( err ) 1296 { 1297 _currentCommand->state = IOATAController::kATAComplete; 1298 1299 } else { 1300 1301 // spin on status until the next phase 1302 1303 for( UInt32 i = 0; i< 3000; i++) 1304 { 1305 if( waitForU8Status( mATABusy, 0x00 ) ) 1306 break; 1307 IOSleep(10); //allow other threads to run. 1308 } 1309 1310 } 1311 1312 1313 // if packet, send packet next 1314 if( _currentCommand->state == IOATAController::kATAPICmd ) 1315 { 1316 DLOG("ATAController::synchronous issue packet\n"); 1317 err = writePacket(); 1318 1319 if( err == kATANoErr ) 1320 { 1321 // if there's data IO, next phase is dataTx, otherwise check status. 1322 if( (_currentCommand->getFlags() & (mATAFlagIORead | mATAFlagIOWrite ) ) 1323 && ((_currentCommand->getFlags() & mATAFlagUseDMA ) != mATAFlagUseDMA ) ) 1324 1325 { 1326 _currentCommand->state = IOATAController::kATADataTx; 1327 1328 } else { 1329 1330 // this is a non-data command, the next step is to check status. 1331 _currentCommand->state = IOATAController::kATAStatus; 1332 } 1333 1334 } else { 1335 1336 // an error occured writing the packet. 1337 _currentCommand->state = IOATAController::kATAComplete; 1338 } 1339 } 1340 1341 1342 // PIO data transfer phase 1343 1344 if( _currentCommand->state == IOATAController::kATADataTx ) 1345 { 1346 while( _currentCommand->state == IOATAController::kATADataTx ) 1347 { 1348 err = asyncData(); 1349 if( err ) 1350 { 1351 _currentCommand->state = IOATAController::kATAComplete; 1352 break; 1353 } 1354 } 1355 1356 if( (_currentCommand->getFlags() & mATAFlagProtocolATAPI) == mATAFlagProtocolATAPI 1357 && _currentCommand->getPacketSize() > 0) 1358 { 1359 // atapi devices will go to status after an interrupt. 1360 waitForU8Status( mATABusy, 0x00 ); 1361 } 1362 1363 } 1364 1365 // else fall through to status state. 1366 if( _currentCommand->state == IOATAController::kATAStatus ) 1367 { 1368 err = asyncStatus(); 1369 _currentCommand->state = IOATAController::kATAComplete; 1370 } 1371 1372 1373 1374 // read the status register to make sure the hardware is in a consistent state. 1375 volatile UInt8 finalStatus = *_tfStatusCmdReg; 1376 OSSynchronizeIO(); 1377 finalStatus++; 1378 // call completeIO if the command is marked for completion. 1379 1380 if( _currentCommand->state == IOATAController::kATAComplete ) 1381 { 1382 completeIO(err); 1383 } 1384 1385 OSSynchronizeIO(); 1386 *_tfAltSDevCReg = 0x00; // enable interrupts 1387 1388 return err; 1389 1390 1391} 1392 1393 1394//---------------------------------------------------------------------------------------- 1395// FUNCTION: asyncStatus 1396// Description: Get the end result of the IO from the device. 1397// Input: none 1398// Output: ATAError code 1399//---------------------------------------------------------------------------------------- 1400 1401IOReturn 1402IOATAController::asyncStatus(void) 1403{ 1404 IOReturn err = kATANoErr; 1405 1406 UInt8 status = *_tfAltSDevCReg; 1407 OSSynchronizeIO(); 1408 1409 UInt8 error = 0x00; 1410 1411 // if err bit is set, read the error register 1412 if( status & mATAError ) 1413 { 1414 error = *_tfFeatureReg; 1415 OSSynchronizeIO(); 1416 err = kATADeviceError; 1417 // look for error results in the TF 1418 if( _currentCommand->getFlags() & (mATAFlagTFAccess | mATAFlagTFAccessResult) ) 1419 { 1420 registerAccess( false ); 1421 } 1422 1423 1424 // if this command returns results in registers on successful completion 1425 // read them now. 1426 } else if( _currentCommand->getFlags() & mATAFlagTFAccessResult ) { 1427 1428 registerAccess( false ); 1429 } 1430 1431 _currentCommand->setEndResult( status, error); 1432 1433 return err; 1434} 1435 1436 1437 1438 1439 1440/*--------------------------------------------------------------------------- 1441 * 1442 * Command phase 1443 * 1444 * 1445 ---------------------------------------------------------------------------*/ 1446IOReturn 1447IOATAController::asyncCommand(void) 1448{ 1449 IOReturn err = kATANoErr; 1450 1451 // if DMA, program and activate the DMA channel 1452 if( (_currentCommand->getFlags() & mATAFlagUseDMA ) == mATAFlagUseDMA ) 1453 { 1454 err = startDMA(); 1455 } 1456 1457 if( err ) 1458 { 1459 stopDMA(); 1460 return err; 1461 } 1462 1463 DLOG("ATAController: command flags = %lx , packet size = %d\n",_currentCommand->getFlags(), _currentCommand->getPacketSize() ); 1464 1465 err = issueCommand(); 1466 if( err ) 1467 return err; 1468 1469 // if the command is an atapi command, set state to issue packet and return 1470 1471 if( (_currentCommand->getFlags() & mATAFlagProtocolATAPI) == mATAFlagProtocolATAPI 1472 && _currentCommand->getPacketSize() > 0) 1473 1474 { 1475 // set to packet state 1476 _currentCommand->state = IOATAController::kATAPICmd; 1477 return err; 1478 } 1479 1480 // if DMA operation, return with status pending. 1481 1482 if( (_currentCommand->getFlags() & mATAFlagUseDMA ) == mATAFlagUseDMA ) 1483 { 1484 _currentCommand->state = IOATAController::kATAStatus; 1485 return err; 1486 } 1487 1488 // if PIO write operation, wait for DRQ and send the first sector 1489 // or sectors if multiple 1490 if( (_currentCommand->getFlags() 1491 & (mATAFlagIOWrite | mATAFlagUseDMA | mATAFlagProtocolATAPI) ) 1492 == mATAFlagIOWrite ) 1493 { 1494 1495 // mark the command as data tx state. 1496 _currentCommand->state = IOATAController::kATADataTx; 1497 // send first data segment. 1498 return asyncData(); 1499 } 1500 1501 if( (_currentCommand->getFlags() & mATAFlagIORead ) == mATAFlagIORead ) 1502 { 1503 // read data on next phase. 1504 _currentCommand->state = IOATAController::kATADataTx; 1505 1506 } else { 1507 1508 // this is a PIO non-data command or a DMA command the next step is to check status. 1509 _currentCommand->state = IOATAController::kATAStatus; 1510 } 1511 1512 return err; 1513 1514} 1515 1516 1517/*--------------------------------------------------------------------------- 1518 * 1519 * PIO data transfer phase 1520 * 1521 * 1522 ---------------------------------------------------------------------------*/ 1523IOReturn 1524IOATAController::asyncData(void) 1525{ 1526 1527 // first check and see if data is remaining for transfer 1528 1529 IOByteCount bytesRemaining = _currentCommand->getByteCount() 1530 - _currentCommand->getActualTransfer(); 1531 1532 // nothing to do 1533 if(bytesRemaining < 1) 1534 { 1535 _currentCommand->state = kATAStatus; 1536 return kATANoErr; 1537 } 1538 1539 1540 UInt8 status= 0x00; 1541 1542 // check for DRQ 1543 while ( !checkTimeout() ) 1544 { 1545 // read the alt status reg 1546 OSSynchronizeIO(); 1547 status = *_tfAltSDevCReg; 1548 // mask the BSY and DRQ bits 1549 status &= (mATABusy | mATADataRequest | mATAError); 1550 1551 // look for BSY=0 and ERR=1 1552 if( mATAError == status ) 1553 { 1554 // hardware has indicated an error condition 1555 _currentCommand->state = kATAStatus; 1556 return kATADeviceError; 1557 break; 1558 } 1559 1560 1561 // look for BSY=0 and DRQ=1 1562 if( mATADataRequest == status ) 1563 { 1564 break; 1565 } 1566 1567 // No need to loop quickly. This makes it easier to 1568 // figure things out on a bus analyzer rather than fill its 1569 // buffer with thousands of status reads. 1570 1571 IODelay( 10 ); 1572 } 1573 1574 // let the timeout through 1575 if ( checkTimeout() ) 1576 { 1577 _currentCommand->state = kATAStatus; 1578 return kATATimeoutErr; 1579 } 1580 1581 IOMemoryDescriptor* descriptor = _currentCommand->getBuffer(); 1582 1583 // The IOMemoryDescriptor may not have a logical address mapping (aka, 1584 // virtual address) within the kernel address space. This poses a problem 1585 // when doing PIO data transfers, which means the CPU is reading/writing 1586 // the device data register and moving data to/from a memory address in the 1587 // host. This requires some kind of logical address. However, in protected 1588 // memory systems it is costly to map the client's buffer and give it a 1589 // virtual address. 1590 1591 // so all PIO data is double buffered to a chunk of mapped and wired memory 1592 // in the kernel space. IOMemoryDescriptor provides methods to read/write 1593 // the physical address it contains. 1594 1595 1596 IOByteCount xfrPosition = _currentCommand->getPosition() + 1597 _currentCommand->getActualTransfer(); 1598 1599 IOByteCount thisPass = bytesRemaining; 1600 IOByteCount overrun = 0; 1601 1602 // pare down to the number of bytes between interrupts 1603 // to be transferred. Do this chunk, then pend the 1604 // next IRQ if bytes remain. 1605 if( thisPass > _currentCommand->getTransferChunkSize() ) 1606 { 1607 thisPass = _currentCommand->getTransferChunkSize(); 1608 } 1609 1610 // for atapi, see how many bytes the device is willing to transfer 1611 // by reading the device registers. 1612 if( _currentCommand->getFlags() & mATAFlagProtocolATAPI) 1613 { 1614 thisPass = readATAPIByteCount(); 1615 1616 // check for device overrun 1617 if( thisPass > bytesRemaining ) 1618 { 1619 overrun = thisPass - bytesRemaining; 1620 thisPass = bytesRemaining; 1621 1622 } 1623 1624 } 1625 1626 1627 while( thisPass > 0 ) 1628 { 1629 IOByteCount bufferBytes = (thisPass > _doubleBuffer.bufferSize )? _doubleBuffer.bufferSize : thisPass; 1630 1631 // read 1632 if( _currentCommand->getFlags() & mATAFlagIORead ) 1633 { 1634 // device to buffer 1635 txDataIn(_doubleBuffer.logicalBuffer, bufferBytes ); 1636 // buffer to descriptor 1637 descriptor->writeBytes( xfrPosition, (void*) _doubleBuffer.logicalBuffer, bufferBytes); 1638 1639 } else { //write 1640 1641 // descriptor to buffer 1642 descriptor->readBytes( xfrPosition, (void*) _doubleBuffer.logicalBuffer, bufferBytes ); 1643 // buffer to device 1644 txDataOut(_doubleBuffer.logicalBuffer, bufferBytes); 1645 1646 } 1647 // update indicators 1648 xfrPosition += bufferBytes; 1649 thisPass -= bufferBytes; 1650 _currentCommand->setActualTransfer(_currentCommand->getActualTransfer() + bufferBytes); 1651 bytesRemaining -= bufferBytes; 1652 } 1653 1654 // sometimes ATAPI devices indicate more bytes than the host 1655 // expects to transfer. We have to read/write the data register to satisfy the 1656 // device so it is ready to accept commands afterwards. 1657 if(overrun) 1658 { 1659 handleOverrun( overrun ); 1660 } 1661 1662 if(bytesRemaining > 1) 1663 { 1664 // next IRQ means more data 1665 _currentCommand->state = kATADataTx; 1666 1667 } else { 1668 1669 // next IRQ is a status check for completion 1670 _currentCommand->state = kATAStatus; 1671 1672 } 1673 1674 return kATANoErr; 1675 1676} 1677 1678 1679 1680 1681 1682#pragma mark - Hardware Access - 1683 1684/*--------------------------------------------------------------------------- 1685 * Notify the controller to update the timing configuration for a 1686 * newly-selected device. Controller drivers may need to supply implementation 1687 * for this command if their hardware doesn't maintain seperate timing registers 1688 * per device. 1689 ---------------------------------------------------------------------------*/ 1690 1691void 1692IOATAController::selectIOTiming( ataUnitID unit ) 1693{ 1694 1695 1696} 1697 1698 1699/*--------------------------------------------------------------------------- 1700 * 1701 * Perform device selection according to ATA standards document 1702 * 1703 * 1704 ---------------------------------------------------------------------------*/ 1705IOReturn 1706IOATAController::selectDevice( ataUnitID unit ) 1707{ 1708 UInt32 msLoops = _currentCommand->getTimeoutMS()/10; 1709 1710 // do a reality check 1711 if( ! ( (kATADevice0DeviceID == unit) 1712 || (kATADevice1DeviceID == unit ) ) ) 1713 { 1714 1715 DLOG( "IOATA: invalid device ID selected\n"); 1716 return kATAInvalidDevID; 1717 1718 } 1719 1720 // give a chance for software to select the correct IO Timing 1721 // in case the hardware doesn't maintain seperate timing regs 1722 // for each device on the bus. 1723 selectIOTiming( unit ); 1724 1725 UInt8 preReqMask = (mATABusy | mATADataRequest ); 1726 UInt8 preReqCondition = 0x00; 1727 1728 // if the device is already selected, no need to reselect it. 1729 // However, we do need to test for the correct status 1730 // before allowing a command to continue. So we check for BSY=0 and DRQ=0 1731 // before selecting a device that isn't already selected first. 1732 1733 // if the unit needs to be selected, test for a good bus and write the bit. 1734 if( unit != _selectedUnit) 1735 { 1736 1737 // check that BSY and DRQ are clear before selection 1738 while( !waitForU8Status( preReqMask, preReqCondition ) ) 1739 { 1740 1741 OSSynchronizeIO(); 1742 if( msLoops == 0 1743 || (*_tfStatusCmdReg & mATADataRequest) == mATADataRequest 1744 || checkTimeout() ) 1745 { 1746 DLOG( "IOATA: BUSY or DRQ can't select device. \n"); 1747 return kATAErrDevBusy; 1748 1749 } 1750 msLoops--; 1751 IOSleep(10); // allow other threads to run. 1752 } 1753 1754 // invalide the currently selected device in case there's an error 1755 _selectedUnit = kATAInvalidDeviceID; 1756 1757 // write the selection bit 1758 *_tfSDHReg = ( unit << 4 ); 1759 OSSynchronizeIO(); 1760 } 1761 1762 // unit was either selected above or was already the active device. Test for 1763 // pre-requisite condition for commands. 1764 1765 // for ATA devices, DRDY=1 is required with the exception of 1766 // Init Drive Params and Execute Device diagnostics, 90h and 91h 1767 // as of ATA6, draft d1410r1a 1768 // for Packet devices, DRDY is ignored for all commands. 1769 1770 if( _devInfo[ unit ].type == kATADeviceType 1771 && _currentCommand->getOpcode() == kATAFnExecIO 1772 && _currentCommand->getTaskFilePtr()->ataTFCommand != 0x90 1773 && _currentCommand->getTaskFilePtr()->ataTFCommand != 0x91 ) 1774 { 1775 1776 preReqMask |= mATADriveReady; 1777 preReqCondition |= mATADriveReady; 1778 1779 } 1780 1781 // wait for BSY to clear 1782 msLoops = 10; 1783 1784 while( !waitForU8Status( (mATABusy ), 0x00 )) 1785 { 1786 1787 OSSynchronizeIO(); 1788 if( msLoops == 0 1789 || (*_tfStatusCmdReg & mATADataRequest) == mATADataRequest 1790 || checkTimeout() ) 1791 { 1792 DLOG( "IOATA: BUSY can't select device. \n"); 1793 return kATAErrDevBusy; 1794 1795 } 1796 msLoops--; 1797 IOSleep(10); // allow other threads to run. 1798 } 1799 1800 // enable device interrupt 1801 *_tfAltSDevCReg = 0x00; 1802 OSSynchronizeIO(); 1803 1804 // successful device selection. 1805 _selectedUnit = unit; 1806 return kATANoErr; 1807 1808 1809} 1810 1811 1812/*--------------------------------------------------------------------------- 1813 * This function issues the task file to the device, including the command. 1814 * The device should be selected prior to calling this function. We write 1815 * Dev/head register in this function since it contains parameters, but 1816 * do not check for successful device selection. 1817 * 1818 ---------------------------------------------------------------------------*/ 1819IOReturn 1820IOATAController::issueCommand( void ) 1821{ 1822 if( _currentCommand == 0 ) 1823 { 1824 DLOG("IOATA can't issue nil command\n"); 1825 return kATAErrUnknownType; 1826 } 1827 1828 1829 1830 if( _currentCommand->getFlags() & mATAFlag48BitLBA ) 1831 { 1832 IOExtendedLBA* extLBA = _currentCommand->getExtendedLBA(); 1833 *_tfSDHReg = extLBA->getDevice(); 1834 OSSynchronizeIO(); 1835 1836 *_tfFeatureReg = (extLBA->getFeatures16() & 0xFF00) >> 8 ; 1837 *_tfSCountReg = (extLBA->getSectorCount16() & 0xFF00) >> 8 ; 1838 *_tfSectorNReg = (extLBA->getLBALow16() & 0xFF00) >> 8 ; 1839 *_tfCylLoReg = (extLBA->getLBAMid16() & 0xFF00) >> 8 ; 1840 *_tfCylHiReg = (extLBA->getLBAHigh16() & 0xFF00) >> 8 ; 1841 OSSynchronizeIO(); 1842 1843 *_tfFeatureReg = extLBA->getFeatures16() & 0x00FF; 1844 *_tfSCountReg = extLBA->getSectorCount16() & 0x00FF; 1845 *_tfSectorNReg = extLBA->getLBALow16() & 0x00FF; 1846 *_tfCylLoReg = extLBA->getLBAMid16() & 0x00FF; 1847 *_tfCylHiReg = extLBA->getLBAHigh16() & 0x00FF; 1848 OSSynchronizeIO(); 1849 1850 *_tfStatusCmdReg = extLBA->getCommand(); 1851 OSSynchronizeIO(); 1852 1853 1854 } else { 1855 1856 ataTaskFile* tfRegs = _currentCommand->getTaskFilePtr(); 1857 1858 OSSynchronizeIO(); 1859 1860 *_tfSDHReg = tfRegs->ataTFSDH; 1861 1862 OSSynchronizeIO(); 1863 1864 *_tfFeatureReg = tfRegs->ataTFFeatures; 1865 *_tfSCountReg = tfRegs->ataTFCount; 1866 *_tfSectorNReg = tfRegs->ataTFSector; 1867 *_tfCylLoReg = tfRegs->ataTFCylLo; 1868 *_tfCylHiReg = tfRegs->ataTFCylHigh; 1869 1870 OSSynchronizeIO(); 1871 1872 *_tfStatusCmdReg = tfRegs->ataTFCommand; 1873 } 1874 1875 return kATANoErr; 1876} 1877 1878 1879 1880 1881/*--------------------------------------------------------------------------- 1882 * 1883 * 1884 * 1885 * 1886 ---------------------------------------------------------------------------*/ 1887IOReturn 1888IOATAController::writePacket( void ) 1889{ 1890 1891 UInt32 packetSize = _currentCommand->getPacketSize(); 1892 UInt16* packetData = _currentCommand->getPacketData(); 1893 1894 // First check if this ATAPI command requires a command packet. 1895 if ( packetSize == 0) 1896 { 1897 return kATANoErr; 1898 } 1899 1900 UInt8 status = 0x00; 1901 1902 // While the drive is busy, wait for it to set DRQ. 1903 // limit the amount of time we will wait for a drive to set DRQ 1904 // ATA specs imply that all devices should set DRQ within 3ms. 1905 // we will allow up to 30ms. 1906 1907 UInt32 breakDRQ = 3; 1908 1909 1910 while ( !waitForU8Status( (mATABusy | mATADataRequest), mATADataRequest) 1911 && !checkTimeout() 1912 && (breakDRQ != 0) ) 1913 { 1914 // check for a device abort - not legal under ATA standards, 1915 // but it could happen 1916 status = *_tfAltSDevCReg; 1917 //mask the BSY and ERR bits 1918 status &= (mATABusy | mATAError); 1919 1920 // look for BSY=0 and ERR = 1 1921 if( mATAError == status ) 1922 { 1923 return kATADeviceError; 1924 } 1925 1926 breakDRQ--; 1927 IOSleep( 10 ); // allow other threads to run 1928 } 1929 1930 // let the timeout through 1931 if ( checkTimeout() 1932 || breakDRQ == 0) 1933 { 1934 return kATATimeoutErr; 1935 } 1936 // write the packet 1937 UInt32 packetLength = 6; 1938 1939 if( packetSize > 12 ) 1940 { 1941 packetLength = 8; 1942 1943 } 1944 1945 for( UInt32 i = 0; i < packetLength; i++) 1946 { 1947 OSSynchronizeIO(); 1948 * _tfDataReg = *packetData; 1949 packetData++; 1950 } 1951 1952 return kATANoErr ; 1953 1954} 1955 1956 1957 1958 1959 1960/*--------------------------------------------------------------------------- 1961 * 1962 * 1963 * 1964 * 1965 ---------------------------------------------------------------------------*/ 1966IOReturn 1967IOATAController::softResetBus( bool doATAPI ) 1968{ 1969 1970 IOReturn result = kATANoErr; 1971 1972 if (doATAPI) 1973 { 1974 // ATAPI resets are directed to a device (0/1) which must be preselected 1975 // before entering this function. 1976 1977 DLOG("IOATA reset command.\n"); 1978 *_tfStatusCmdReg = kSOFTRESET; 1979 OSSynchronizeIO(); 1980 1981 } else { 1982 1983 // begin the ATA soft reset sequence, which affects both devices on the 1984 // bus 1985 1986 1987 // We will set nIEN bit to 0 to force the IRQ line to be driven by the selected 1988 // device. We were seeing a small number of cases where the tristated line 1989 // caused false interrupts to the host. 1990 1991 *_tfAltSDevCReg = mATADCRReset; 1992 OSSynchronizeIO(); 1993 1994 // ATA standards only dictate >5us of hold time for the soft reset operation 1995 // 100 us should be sufficient for any device to notice the soft reset. 1996 1997 IODelay( 100 ); 1998 1999 2000 *_tfAltSDevCReg = 0x00; 2001 OSSynchronizeIO(); 2002 2003 DLOG("IOATA soft reset sequenced\n"); 2004 2005 // a reset operation has the effect of selecting device 0 as a result. 2006 // in this case, we will force our host controller to actually execute the 2007 // device selection protocol before the next command. 2008 2009 _selectedUnit = kATAInvalidDeviceID; 2010 2011 } 2012 2013 // ATA-4 and ATA-5 require the host to wait for >2ms 2014 // after a sRST before sampling the drive status register. 2015 IOSleep(50); 2016 2017 // ATA and ATAPI devices indicate reset completion somewhat differently 2018 // for ATA, wait for BSY=0 and RDY=1. For ATAPI, wait for BSY=0 only. 2019 UInt8 readyMask = mATABusy; 2020 UInt8 readyOn = 0x00; 2021 2022 if( (_devInfo[0].type == kATADeviceType) 2023 && (!doATAPI) ) 2024 { 2025 readyMask |= mATADriveReady; //mask-in the busy + ready bit 2026 readyOn = mATADriveReady; // look for a RDY=1 as well as BSY=0 2027 } 2028 2029 2030 bool resetFailed = true; 2031 2032 // loop for up to 31 seconds following a reset to allow 2033 // drives to come on line. Most devices take 50-100ms, a sleeping drive 2034 // may need to spin up and touch media to respond. This may take several seconds. 2035 for( int i = 0; i < 3100; i++) 2036 { 2037 2038 // read the status register - helps deal with devices which errantly 2039 // set interrupt pending states during resets. Reset operations are not 2040 // supposed to generate interrupts, but some devices do anyway. 2041 // interrupt handlers should be prepared to deal with errant interrupts on ATA busses. 2042 OSSynchronizeIO(); 2043 UInt8 status = *_tfStatusCmdReg; 2044 2045 // when drive is ready, break the loop 2046 if( ( status & readyMask )== readyOn) 2047 { 2048 // device reset completed in time 2049 resetFailed = false; 2050 break; 2051 } 2052 2053 IOSleep( 10 ); // sleep thread for another 10 ms 2054 2055 } 2056 2057 2058 if( resetFailed ) 2059 { 2060 // it is likely that this hardware is broken. 2061 // There's no recovery action if the drive fails 2062 // to reset. 2063 DLOG("IOATA device failed to reset.\n"); 2064 result = kATATimeoutErr; 2065 } 2066 2067 DLOG("IOATA reset complete.\n"); 2068 2069 return result; 2070 2071} 2072 2073 2074/*--------------------------------------------------------------------------- 2075 * 2076 * Subclasses should take necessary action to create DMA channel programs, 2077 * for the current memory descriptor in _currentCommand and activate the 2078 * the DMA hardware 2079 ---------------------------------------------------------------------------*/ 2080IOReturn 2081IOATAController::startDMA( void ) 2082{ 2083 2084 2085 DLOG("IOATA Bus controllers that offer DMA must provide implementation/n"); 2086 2087 return kATAModeNotSupported; 2088} 2089 2090 2091 2092 2093/*--------------------------------------------------------------------------- 2094 * Subclasses should take all actions necesary to safely shutdown DMA engines 2095 * in any state of activity, whether finished, pending or stopped. Calling 2096 * this function must be harmless reguardless of the state of the engine. 2097 * 2098 ---------------------------------------------------------------------------*/ 2099IOReturn 2100IOATAController::stopDMA( void ) 2101{ 2102 2103 DLOG("IOATA Bus controllers that offer DMA must provide implementation/n"); 2104 2105 return kATAModeNotSupported; 2106} 2107 2108 2109/*--------------------------------------------------------------------------- 2110// WaitForU8Status 2111// Will wait up to one millisecond for the value in the altStatus register & mask to equal the value 2112// passed in. Note that I always use the altStatus register so as not to have the side affect of clearing 2113// the interrupt if there is one. 2114 ---------------------------------------------------------------------------*/ 2115bool 2116IOATAController::waitForU8Status (UInt8 mask, UInt8 value) 2117{ 2118 int i; 2119 2120 // we will read the status from the alt status register so as not 2121 // to clear the interrupt accidentally 2122 2123 for (i=0; i < kStatusDelayLoopMS; i++) 2124 { 2125 OSSynchronizeIO(); 2126 2127 if ((*_tfAltSDevCReg & mask) == value) 2128 { 2129 return true; 2130 } 2131 2132 IODelay( kStatusDelayTime ); 2133 } 2134 return false; // time's up 2135} 2136 2137/*---------------------------------------------------------------------------------------------------- 2138** Routine ATAPISlaveExists 2139** 2140** Purpose: Determines whether an ATAPI device seen as a "slave" of a master ATAPI device 2141** is actually present, or the product of the master shadowing a not-present slave's registers 2142** Call this function when the master device shows EBh 14h, and the slave also shows the ATAPI 2143** protocol signature. 2144** Returns: False if a device is ruled out. True if a device is verified. Leaves device in a ready state, 2145** But no longer showing signatures. 2146 2147 NOTE: Device 1 (slave) is assumed already selected. 2148*/ 2149 2150 2151bool 2152IOATAController::ATAPISlaveExists( void ) 2153{ 2154 UInt8 scratchByte; 2155 UInt16 scratchWord; 2156 UInt32 dataCounter; 2157 UInt32 loopCounter; 2158 2159 // The only option is to issue a command and see what happens. 2160 OSSynchronizeIO(); 2161 *_tfAltSDevCReg = 0x02; // disable interrupts 2162 2163 //issue INDENTIFY PACKET DEVICE 2164 OSSynchronizeIO(); 2165 *_tfStatusCmdReg = 0xA1; 2166 2167 // reading and disreguarding a register provides the required 400ns delay time. 2168 OSSynchronizeIO(); 2169 scratchByte = *_tfAltSDevCReg; 2170 2171 OSSynchronizeIO(); 2172 scratchByte = *_tfAltSDevCReg; 2173 2174 // if the device returns status 00h, we declare it not present. A real device would probably be 2175 // status BSY (80h) now. An incredibly fast device might be ready to move data and show DRQ. 2176 // However, by ATA standards, a not present device is required to return 00h. 2177 // Lucky break, no device and we figured it out in a hurry. 2178 2179 if( scratchByte == 0x00 ) 2180 { 2181 // enable device interrupt 2182 *_tfAltSDevCReg = 0x00; 2183 OSSynchronizeIO(); 2184 return false; 2185 } 2186 2187 // OK we probably have a device now. We have to wait for drive to send data, and read it and clear it. 2188 // It is possible that the a misbehaving master has decided to respond to the command. So, we'll 2189 // break on error bit and say it's not a real slave should that happen. 2190 2191 // take a leisurely approach, this will take a while. 2192 2193 // give the device up to 10 seconds to respond with data. 2194 for( loopCounter = 0; loopCounter < 10000; loopCounter++) 2195 { 2196 OSSynchronizeIO(); 2197 scratchByte = *_tfAltSDevCReg; 2198 2199 // If drive sets error, clear status and return false. It's probably a misbehaving master 2200 if( scratchByte & 0x01 ) 2201 break; 2202 2203 // this means the drive is really there. Clear the data and return true. 2204 if( (scratchByte & 0x58) == 0x58) // RDY=1 DRQ=1 2205 { 2206 OSSynchronizeIO(); 2207 scratchByte = *_tfStatusCmdReg; // clear pending interrupt state 2208 2209 for( dataCounter = 0; dataCounter < 256; dataCounter++ ) 2210 { 2211 OSSynchronizeIO(); 2212 scratchWord = *_tfDataReg; 2213 } 2214 // enable device interrupt 2215 *_tfAltSDevCReg = 0x00; 2216 OSSynchronizeIO(); 2217 return true; 2218 } 2219 2220 // OK, sleep for 10 ms and try again. 2221 IOSleep(10); 2222 } 2223 2224 // In the ugly case, a drive set BSY, and didn't respond within 10 seconds with data. 2225 // Otherwise, this is the for loop terminating on seeing the error bit. 2226 // We'll read status and return false. 2227 2228 OSSynchronizeIO(); 2229 scratchByte = *_tfStatusCmdReg; // clear pending interrupt state 2230 2231 // enable device interrupt 2232 *_tfAltSDevCReg = 0x00; 2233 OSSynchronizeIO(); 2234 2235 return false; 2236 2237} 2238 2239 2240 2241/*--------------------------------------------------------------------------- 2242 * scan the bus to see if devices are attached. The assumption is that the 2243 * devices are in a cleanly-reset state, showing their protocol signatures, 2244 * and the bus is properly wired with a pull down resistor on DD:7. 2245 * If your bus controller does not meet these conditions, you should override 2246 * and supply your own function which meets your specific hardware needs. 2247 * Your controller may or may not require a reset, or it may require more 2248 * thorough scanning, or additional configuration prior to looking for drives, 2249 * or it may aquire information from firmware indicating the devices attached. 2250 * This function should be self contained and not rely upon work loop or 2251 * or anything other than the register pointers being setup and enabled for access 2252 ---------------------------------------------------------------------------*/ 2253 2254UInt32 2255IOATAController::scanForDrives( void ) 2256{ 2257 UInt32 unitsFound = 0; 2258 UInt8 status = 0x00; 2259 // count total time spent searching max time allowed = 31 secs 2260 // it RARELY takes this long. 2261 UInt32 milsSpent = 0; 2262 2263 // wait for a not busy bus 2264 // should be ready, but some devices may be slow to wake or spin up. 2265 for( int loopMils = 0; milsSpent < 3100; loopMils++ ) 2266 { 2267 OSSynchronizeIO(); 2268 status = *_tfStatusCmdReg; 2269 if( (status & mATABusy) == 0x00 ) 2270 break; 2271 2272 IOSleep( 10 ); 2273 milsSpent++; 2274 } 2275 2276 // spun on BSY for too long, declare bus empty 2277 if( ! (milsSpent < 3100) ) 2278 goto AllDone; 2279 2280 2281 // select each possible device on the bus, wait for BSY- 2282 // then check for protocol signatures. 2283 2284 for( int unit = 0; unit < 2; unit++ ) 2285 { 2286 2287 // wait for a not busy bus 2288 for( int loopMils = 0; milsSpent < 3100; loopMils++ ) 2289 { 2290 // write the selection bit 2291 OSSynchronizeIO(); 2292 *_tfSDHReg = ( unit << 4 ); 2293 IODelay( 10 ); 2294 // typically, devices respond quickly to selection 2295 // but we'll give it a chance in case it is slow for some reason. 2296 status = *_tfStatusCmdReg; 2297 if( (status & mATABusy) == 0x00 ) 2298 { 2299 break; 2300 } 2301 2302 IOSleep( 10 ); 2303 milsSpent++; 2304 } 2305 2306 // spun on BSY too long, probably bad device 2307 if( ! (milsSpent < 3100) ) 2308 goto AllDone; 2309 2310 // check for ATAPI device signature first 2311 if ( ( *_tfCylLoReg == 0x14) && ( *_tfCylHiReg == 0xEB) ) 2312 { 2313 if( (unit == 1 ) 2314 && ( _devInfo[0].type == kATAPIDeviceType ) ) 2315 { 2316 2317 // OK we've met the condition for an indeterminate bus, master is atapi and we see a slave atapi 2318 // signature. This is legal ATA, though we are fortunate enough that most devices don't do this. 2319 2320 if( ATAPISlaveExists( ) != true ) 2321 { 2322 _devInfo[unit].type = kUnknownATADeviceType; 2323 goto AllDone; 2324 2325 } 2326 2327 } 2328 2329 _devInfo[unit].type = kATAPIDeviceType; 2330 _devInfo[unit].packetSend = kATAPIDRQFast; // this is the safest default setting 2331 unitsFound++; 2332 2333 } // check for ATA signature, including status RDY=1 and ERR=0 2334 else if ( (*_tfCylLoReg == 0x00) && (*_tfCylHiReg == 0x00) && 2335 (*_tfSCountReg == 0x01) && (*_tfSectorNReg == 0x01) && 2336 ( (*_tfAltSDevCReg & 0x51) == 0x50) ) 2337 { 2338 2339 _devInfo[unit].type = kATADeviceType; 2340 _devInfo[unit].packetSend = kATAPIUnknown; 2341 unitsFound++; 2342 2343 }else{ 2344 2345 _devInfo[unit].type = kUnknownATADeviceType; 2346 _devInfo[unit].packetSend = kATAPIUnknown; 2347 } 2348 2349 } 2350 2351 2352AllDone: 2353 2354 // reselect device 0 2355 *_tfSDHReg = 0x00; 2356 // enable device interrupts 2357 *_tfAltSDevCReg = 0x00; 2358 OSSynchronizeIO(); 2359 2360 // enforce ATA device selection protocol 2361 // before issuing the next command. 2362 _selectedUnit = kATAInvalidDeviceID; 2363 2364 return unitsFound; 2365 2366} 2367 2368 2369 2370/*____________________________________________________________________________ 2371 Name: txDataIn 2372 Function: Reads data in from the data register of a selected device to 2373 the specified buffer. It is assumed that the DRQ bit has been 2374 checked in the status register. All data transfers are in 16-bit 2375 words. 2376 Output: The buffer contains the number of bytes specified by length 2377______________________________________________________________________________*/ 2378 2379IOReturn 2380IOATAController::txDataIn (IOLogicalAddress buf, IOByteCount length) 2381{ 2382 register UInt16 *buf16 = (UInt16*)buf; 2383 2384 // on reads, we expect an interrupt after we send the data except on the last block. 2385 // in the case of the last block, we will clear this bit when we return to the 2386 // AsyncData call 2387 while (length >= 32) // read in groups of 16 words at a time 2388 { 2389 OSSynchronizeIO(); 2390 *buf16++ = *_tfDataReg; 2391 OSSynchronizeIO(); 2392 *buf16++ = *_tfDataReg; 2393 OSSynchronizeIO(); 2394 *buf16++ = *_tfDataReg; 2395 OSSynchronizeIO(); 2396 *buf16++ = *_tfDataReg; 2397 OSSynchronizeIO(); 2398 *buf16++ = *_tfDataReg; 2399 OSSynchronizeIO(); 2400 *buf16++ = *_tfDataReg; 2401 OSSynchronizeIO(); 2402 *buf16++ = *_tfDataReg; 2403 OSSynchronizeIO(); 2404 *buf16++ = *_tfDataReg; 2405 OSSynchronizeIO(); 2406 *buf16++ = *_tfDataReg; 2407 OSSynchronizeIO(); 2408 *buf16++ = *_tfDataReg; 2409 OSSynchronizeIO(); 2410 *buf16++ = *_tfDataReg; 2411 OSSynchronizeIO(); 2412 *buf16++ = *_tfDataReg; 2413 OSSynchronizeIO(); 2414 *buf16++ = *_tfDataReg; 2415 OSSynchronizeIO(); 2416 *buf16++ = *_tfDataReg; 2417 OSSynchronizeIO(); 2418 *buf16++ = *_tfDataReg; 2419 OSSynchronizeIO(); 2420 *buf16++ = *_tfDataReg; 2421 length -= 32; // update the length count 2422 OSSynchronizeIO(); 2423 } 2424 2425 while (length >= 2) 2426 { 2427 *buf16++ = *_tfDataReg; 2428 OSSynchronizeIO(); 2429 length -= 2; // update the length count 2430 } 2431 2432 UInt8* buf8 = (UInt8*)buf16; 2433 2434 if (length) // This is needed to handle odd byte transfer 2435 { 2436 *buf8 = *(IOATARegPtr8Cast(_tfDataReg)); 2437 OSSynchronizeIO(); 2438 length--; 2439 } 2440 2441 return kATANoErr; 2442 2443} 2444 2445 2446 2447/*____________________________________________________________________________ 2448 Name: txDataOut 2449 Function: Writes data out to the data register of a selected device from 2450 the specified buffer. It is assumed that the DRQ bit has been 2451 checked in the status register. All transfers are in groups of 2452 16-bit words. 2453______________________________________________________________________________*/ 2454 2455IOReturn 2456IOATAController::txDataOut(IOLogicalAddress buf, IOByteCount length) 2457{ 2458 register UInt16 *buf16 = (UInt16*)buf; 2459 2460 while (length >= 32) // write in groups of 16 words at a time 2461 { 2462 *_tfDataReg = *buf16++; 2463 OSSynchronizeIO(); 2464 *_tfDataReg = *buf16++; 2465 OSSynchronizeIO(); 2466 *_tfDataReg = *buf16++; 2467 OSSynchronizeIO(); 2468 *_tfDataReg = *buf16++; 2469 OSSynchronizeIO(); 2470 *_tfDataReg = *buf16++; 2471 OSSynchronizeIO(); 2472 *_tfDataReg = *buf16++; 2473 OSSynchronizeIO(); 2474 *_tfDataReg = *buf16++; 2475 OSSynchronizeIO(); 2476 *_tfDataReg = *buf16++; 2477 OSSynchronizeIO(); 2478 *_tfDataReg = *buf16++; 2479 OSSynchronizeIO(); 2480 *_tfDataReg = *buf16++; 2481 OSSynchronizeIO(); 2482 *_tfDataReg = *buf16++; 2483 OSSynchronizeIO(); 2484 *_tfDataReg = *buf16++; 2485 OSSynchronizeIO(); 2486 *_tfDataReg = *buf16++; 2487 OSSynchronizeIO(); 2488 *_tfDataReg = *buf16++; 2489 OSSynchronizeIO(); 2490 *_tfDataReg = *buf16++; 2491 OSSynchronizeIO(); 2492 *_tfDataReg = *buf16++; 2493 OSSynchronizeIO(); 2494 length -= 32; 2495 } 2496 while (length >= 2) 2497 { 2498 *_tfDataReg = *buf16++; 2499 OSSynchronizeIO(); 2500 length -= 2; 2501 } 2502 2503 // Odd byte counts aren't really good on ATA, but we'll do it anyway. 2504 UInt8* buf8 = (UInt8*)buf16; 2505 2506 if (length) 2507 { 2508 *(IOATARegPtr8Cast(_tfDataReg)) = *buf8; 2509 OSSynchronizeIO(); 2510 length--; 2511 } 2512 2513 return kATANoErr; 2514} 2515 2516 2517/*____________________________________________________________________________ 2518 Name: ATAPIByteCountRegistersRead() 2519 Function: This function reads both the low and high byte count registers 2520 of the ATAPI task file and returns the read result to the caller. 2521 2522 Input: none 2523 Output: An UInt16 value from both the low and high byte count registers 2524 2525______________________________________________________________________________*/ 2526 2527IOByteCount 2528IOATAController::readATAPIByteCount (void) 2529{ 2530 UInt16 ByteCountValue; 2531 2532 ByteCountValue = (*_tfCylHiReg) << 8; 2533 OSSynchronizeIO(); 2534 ByteCountValue += *_tfCylLoReg; 2535 OSSynchronizeIO(); 2536 2537 return (IOByteCount) ByteCountValue; 2538} 2539 2540 2541//---------------------------------------------------------------------------------------- 2542// FUNCTION: DetermineATAPIState() 2543// Description: This function determines the next state based on the Interrupt reason 2544// register of the device. If the command hasn't been initiated, the 2545// function returns kATAStarted state. 2546// <Current State> <Interrupt Reason> <Next State> 2547// kATAStarted Don't care kATAStarted 2548// Don't care 0x00 kATADataTx (Write) 2549// Don't care 0x01 kATAPICmd 2550// Don't care 0x02 kATADataTx (Read) 2551// Don't care 0x03 kATAStatus (or Message - future) 2552// 2553// Input: Manager parameter block pointer: ATA_PB* 2554// Base address pointer: ATAtaskfile* 2555// Output: Next state value: UInt16 2556//---------------------------------------------------------------------------------------- 2557IOATAController::transState 2558IOATAController::determineATAPIState(void) 2559{ 2560 IOATAController::transState nextPhase; 2561 const IOATAController::transState NextState[4] = {kATADataTx, kATAPICmd, 2562 kATADataTx, kATAStatus}; 2563 2564 if (_currentCommand->state == kATAStarted) // the command hasn't started yet 2565 return (kATAStarted); // return the same state 2566 2567 /* Generate next phase from interrupt reason */ 2568 nextPhase = NextState[ *_tfSCountReg & 0x03]; 2569 2570 return nextPhase; 2571} 2572 2573 2574/*____________________________________________________________________________ 2575 Name: handleOverrun 2576 Function: This function provides handling of overrun data. This condition 2577 will occur if the device indicates more data than the host expects 2578 asked for. 2579 Input: IOByteCount length = number of bytes to do dummy read/write on 2580 device data register. 2581 Output: None 2582______________________________________________________________________________*/ 2583void 2584IOATAController::handleOverrun( IOByteCount length) 2585{ 2586 UInt16 dummy = 0; 2587 2588 if( _currentCommand->getFlags() & mATAFlagIORead ) 2589 { 2590 2591 while (length >= 2) 2592 { 2593 dummy = *_tfDataReg; 2594 OSSynchronizeIO(); 2595 length -= 2; 2596 } 2597 2598 while (length > 0) 2599 { 2600 dummy = *_tfDataReg; 2601 OSSynchronizeIO(); 2602 length--; 2603 } 2604 2605 } else { // write 2606 2607 2608 while (length >= 2) 2609 { 2610 *_tfDataReg = dummy; 2611 OSSynchronizeIO(); 2612 length -= 2; 2613 } 2614 2615 while (length > 0) 2616 { 2617 *_tfDataReg = dummy; 2618 OSSynchronizeIO(); 2619 length--; 2620 } 2621 2622 2623 2624 } 2625} 2626 2627UInt16 2628IOATAController::readExtRegister( IOATARegPtr8 inRegister ) 2629{ 2630 // read in the lsb of the 16 bit fifo register 2631 UInt16 result = (*inRegister); 2632 OSSynchronizeIO(); 2633 // select the HOB bit in the dev ctrl register 2634 *_tfAltSDevCReg = 0x80; 2635 OSSynchronizeIO(); 2636 result |= ((UInt16) (*inRegister)) << 8; 2637 OSSynchronizeIO(); 2638 *_tfAltSDevCReg = 0x00; 2639 OSSynchronizeIO(); 2640 return result; 2641} 2642 2643void 2644IOATAController::writeExtRegister( IOATARegPtr8 inRegister, UInt16 inValue ) 2645{ 2646 // read in the lsb of the 16 bit fifo register 2647 *inRegister = (UInt8)((inValue & 0xFF00) >> 8); 2648 OSSynchronizeIO(); 2649 *inRegister = (UInt8) (inValue & 0xFF); 2650 OSSynchronizeIO(); 2651} 2652 2653 2654/*--------------------------------------------------------------------------- 2655 * 2656 * registerAccess read or write the TF registers as indicated by the mask 2657 * in the current command. 2658 * input: bool isWrite = true means write the register(s), false = read 2659 * 2660 ---------------------------------------------------------------------------*/ 2661IOReturn 2662IOATAController::registerAccess(bool isWrite) 2663{ 2664 UInt32 RegAccessMask = _currentCommand->getRegMask(); 2665 IOReturn err = kATANoErr; 2666 bool isExtLBA = _currentCommand->getFlags() & mATAFlag48BitLBA; 2667 IOExtendedLBA* extLBA = _currentCommand->getExtendedLBA(); 2668 2669 ///////////////////////////////////////////////////////////////////////// 2670 if (RegAccessMask & mATAErrFeaturesValid) // error/features register 2671 { 2672 if(isWrite) 2673 { 2674 if(isExtLBA ) 2675 { 2676 writeExtRegister(_tfFeatureReg,extLBA->getFeatures16()); 2677 2678 } else { 2679 2680 *_tfFeatureReg = _currentCommand->getErrorReg(); 2681 } 2682 }else{ 2683 2684 if(isExtLBA ) 2685 { 2686 extLBA->setFeatures16( readExtRegister(_tfFeatureReg)); 2687 2688 } else { 2689 2690 _currentCommand->setFeatures( *_tfFeatureReg) ; 2691 } 2692 } 2693 } 2694 2695 ///////////////////////////////////////////////////////////////////////// 2696 if (RegAccessMask & mATASectorCntValid) // sector count register 2697 { 2698 if(isWrite) 2699 { 2700 if(isExtLBA ) 2701 { 2702 writeExtRegister( _tfSCountReg, extLBA->getSectorCount16()); 2703 2704 } else { 2705 2706 *_tfSCountReg = _currentCommand->getSectorCount(); 2707 2708 } 2709 }else{ 2710 2711 if(isExtLBA ) 2712 { 2713 extLBA->setSectorCount16( readExtRegister(_tfSCountReg) ); 2714 2715 } else { 2716 _currentCommand->setSectorCount( *_tfSCountReg ); 2717 } 2718 } 2719 } 2720 2721 ///////////////////////////////////////////////////////////////////////// 2722 if (RegAccessMask & mATASectorNumValid) // sector number register 2723 { 2724 if(isWrite) 2725 { 2726 if(isExtLBA ) 2727 { 2728 writeExtRegister( _tfSectorNReg, extLBA->getLBALow16()); 2729 2730 } else { 2731 *_tfSectorNReg = _currentCommand->getSectorNumber(); 2732 } 2733 2734 }else{ 2735 2736 if(isExtLBA ) 2737 { 2738 extLBA->setLBALow16(readExtRegister(_tfSectorNReg)); 2739 2740 } else { 2741 _currentCommand->setSectorNumber( *_tfSectorNReg ); 2742 } 2743 } 2744 } 2745 2746 ///////////////////////////////////////////////////////////////////////// 2747 if (RegAccessMask & mATACylinderLoValid) // cylinder low register 2748 { 2749 if(isWrite) 2750 { 2751 if(isExtLBA ) 2752 { 2753 writeExtRegister( _tfCylLoReg, extLBA->getLBAMid16()); 2754 2755 } else { 2756 2757 *_tfCylLoReg = _currentCommand->getCylLo(); 2758 } 2759 2760 }else{ 2761 2762 if(isExtLBA ) 2763 { 2764 extLBA->setLBAMid16(readExtRegister(_tfCylLoReg)); 2765 2766 } else { 2767 _currentCommand->setCylLo( *_tfCylLoReg ); 2768 } 2769 } 2770 } 2771 2772 ///////////////////////////////////////////////////////////////////////// 2773 if (RegAccessMask & mATACylinderHiValid) // cylinder high register 2774 { 2775 if(isWrite) 2776 { 2777 if(isExtLBA ) 2778 { 2779 writeExtRegister( _tfCylHiReg, extLBA->getLBAHigh16()); 2780 2781 } else { 2782 2783 *_tfCylHiReg = _currentCommand->getCylHi(); 2784 } 2785 }else{ 2786 2787 if(isExtLBA ) 2788 { 2789 extLBA->setLBAHigh16(readExtRegister(_tfCylHiReg)); 2790 2791 } else { 2792 _currentCommand->setCylHi( *_tfCylHiReg ); 2793 } 2794 } 2795 } 2796 2797 ///////////////////////////////////////////////////////////////////////// 2798 if (RegAccessMask & mATASDHValid) // ataTFSDH register 2799 { 2800 if(isWrite) 2801 { 2802 *_tfSDHReg = _currentCommand->getDevice_Head(); 2803 }else{ 2804 _currentCommand->setDevice_Head( *_tfSDHReg ); 2805 } 2806 } 2807 2808 2809 ///////////////////////////////////////////////////////////////////////// 2810 if (RegAccessMask & mATAAltSDevCValid) // alternate status/device control register 2811 { 2812 if(isWrite) 2813 { 2814 *_tfAltSDevCReg = _currentCommand->getAltStatus(); 2815 }else{ 2816 _currentCommand->setControl( *_tfAltSDevCReg ); 2817 } 2818 } 2819 2820 ///////////////////////////////////////////////////////////////////////// 2821 if (RegAccessMask & mATADataValid) // data register... 2822 { 2823 if(isWrite) 2824 { 2825 *_tfDataReg = _currentCommand->getDataReg(); 2826 2827 }else{ 2828 2829 _currentCommand->setDataReg( *_tfDataReg ); 2830 } 2831 } 2832 2833 ///////////////////////////////////////////////////////////////////////// 2834 if (RegAccessMask & mATAStatusCmdValid) // status/command register 2835 { 2836 if(isWrite) 2837 { 2838 *_tfStatusCmdReg = _currentCommand->getStatus(); 2839 }else{ 2840 _currentCommand->setCommand(*_tfStatusCmdReg ); 2841 } 2842 } 2843 2844 return err; 2845 2846 2847 2848 2849} 2850 2851#pragma mark -misc functions- 2852 2853/*--------------------------------------------------------------------------- 2854 * 2855// perform 2-byte endian swap. Only useful on PIO transfers and identify data 2856// 2857 ---------------------------------------------------------------------------*/ 2858void 2859IOATAController::swapBytes16( UInt8* dataBuffer, IOByteCount length) 2860{ 2861 2862 IOByteCount i; 2863 UInt8 c; 2864 unsigned char* firstBytePtr; 2865 2866 for (i = 0; i < length; i+=2) 2867 { 2868 firstBytePtr = dataBuffer; // save pointer 2869 c = *dataBuffer++; // Save Byte0, point to Byte1 2870 *firstBytePtr = *dataBuffer; // Byte0 = Byte1 2871 *dataBuffer++= c; // Byte1 = Byte0 2872 } 2873 2874 2875 2876} 2877 2878 2879/***************************************************************************** 2880** Function bitSigToNumeric 2881** This function converts a bit-significant value into an integer which 2882** corresponds to the highest-order bit which is active. For example, 2883** 0x0035 is converted to 5, which is the bit-number of the high bit of 0x0035. 2884** Input variable binary = zero is technically illegal; the routine does not check 2885** explicitly for this value, but rather returns 0xFFFF as a result of no 2886** bit being found, and the return value is decemented below zero. The 2887** loop terminates when i becomes zero because of binary = 0. 2888** Implicit maximum value of binary: 0x00FF. 2889** 2890** Explicit Inputs: 2891** binary - a non-zero binary number (0 has no corresponding bit number) 2892** Return Value: 2893** integer - the bit-number of the highest bit active in binary. 2894** 2895******************************************************************************/ 2896 2897UInt16 2898IOATAController::bitSigToNumeric(UInt16 binary) 2899{ 2900 UInt16 i, integer; 2901 2902 /* Test all bits from left to right, terminating at the first non-zero bit. */ 2903 for (i = 0x0080, integer = 7; ((i & binary) == 0 && i != 0) ; i >>= 1, integer-- ) 2904 {;} 2905 return (integer); 2906} /* end BitSigToNumeric() */ 2907 2908