1// SPDX-License-Identifier: GPL-2.0-only
2#define _GNU_SOURCE /* for program_invocation_short_name */
3#include <fcntl.h>
4#include <stdio.h>
5#include <stdlib.h>
6#include <string.h>
7#include <sys/ioctl.h>
8
9#include "apic.h"
10#include "kvm_util.h"
11#include "processor.h"
12#include "test_util.h"
13
14struct xapic_vcpu {
15	struct kvm_vcpu *vcpu;
16	bool is_x2apic;
17};
18
19static void xapic_guest_code(void)
20{
21	asm volatile("cli");
22
23	xapic_enable();
24
25	while (1) {
26		uint64_t val = (u64)xapic_read_reg(APIC_IRR) |
27			       (u64)xapic_read_reg(APIC_IRR + 0x10) << 32;
28
29		xapic_write_reg(APIC_ICR2, val >> 32);
30		xapic_write_reg(APIC_ICR, val);
31		GUEST_SYNC(val);
32	}
33}
34
35static void x2apic_guest_code(void)
36{
37	asm volatile("cli");
38
39	x2apic_enable();
40
41	do {
42		uint64_t val = x2apic_read_reg(APIC_IRR) |
43			       x2apic_read_reg(APIC_IRR + 0x10) << 32;
44
45		x2apic_write_reg(APIC_ICR, val);
46		GUEST_SYNC(val);
47	} while (1);
48}
49
50static void ____test_icr(struct xapic_vcpu *x, uint64_t val)
51{
52	struct kvm_vcpu *vcpu = x->vcpu;
53	struct kvm_lapic_state xapic;
54	struct ucall uc;
55	uint64_t icr;
56
57	/*
58	 * Tell the guest what ICR value to write.  Use the IRR to pass info,
59	 * all bits are valid and should not be modified by KVM (ignoring the
60	 * fact that vectors 0-15 are technically illegal).
61	 */
62	vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic);
63	*((u32 *)&xapic.regs[APIC_IRR]) = val;
64	*((u32 *)&xapic.regs[APIC_IRR + 0x10]) = val >> 32;
65	vcpu_ioctl(vcpu, KVM_SET_LAPIC, &xapic);
66
67	vcpu_run(vcpu);
68	TEST_ASSERT_EQ(get_ucall(vcpu, &uc), UCALL_SYNC);
69	TEST_ASSERT_EQ(uc.args[1], val);
70
71	vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic);
72	icr = (u64)(*((u32 *)&xapic.regs[APIC_ICR])) |
73	      (u64)(*((u32 *)&xapic.regs[APIC_ICR2])) << 32;
74	if (!x->is_x2apic) {
75		val &= (-1u | (0xffull << (32 + 24)));
76		TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY);
77	} else {
78		TEST_ASSERT_EQ(icr & ~APIC_ICR_BUSY, val & ~APIC_ICR_BUSY);
79	}
80}
81
82#define X2APIC_RSVED_BITS_MASK  (GENMASK_ULL(31,20) | \
83				 GENMASK_ULL(17,16) | \
84				 GENMASK_ULL(13,13))
85
86static void __test_icr(struct xapic_vcpu *x, uint64_t val)
87{
88	if (x->is_x2apic) {
89		/* Hardware writing vICR register requires reserved bits 31:20,
90		 * 17:16 and 13 kept as zero to avoid #GP exception. Data value
91		 * written to vICR should mask out those bits above.
92		 */
93		val &= ~X2APIC_RSVED_BITS_MASK;
94	}
95	____test_icr(x, val | APIC_ICR_BUSY);
96	____test_icr(x, val & ~(u64)APIC_ICR_BUSY);
97}
98
99static void test_icr(struct xapic_vcpu *x)
100{
101	struct kvm_vcpu *vcpu = x->vcpu;
102	uint64_t icr, i, j;
103
104	icr = APIC_DEST_SELF | APIC_INT_ASSERT | APIC_DM_FIXED;
105	for (i = 0; i <= 0xff; i++)
106		__test_icr(x, icr | i);
107
108	icr = APIC_INT_ASSERT | APIC_DM_FIXED;
109	for (i = 0; i <= 0xff; i++)
110		__test_icr(x, icr | i);
111
112	/*
113	 * Send all flavors of IPIs to non-existent vCPUs.  TODO: use number of
114	 * vCPUs, not vcpu.id + 1.  Arbitrarily use vector 0xff.
115	 */
116	icr = APIC_INT_ASSERT | 0xff;
117	for (i = 0; i < 0xff; i++) {
118		if (i == vcpu->id)
119			continue;
120		for (j = 0; j < 8; j++)
121			__test_icr(x, i << (32 + 24) | icr | (j << 8));
122	}
123
124	/* And again with a shorthand destination for all types of IPIs. */
125	icr = APIC_DEST_ALLBUT | APIC_INT_ASSERT;
126	for (i = 0; i < 8; i++)
127		__test_icr(x, icr | (i << 8));
128
129	/* And a few garbage value, just make sure it's an IRQ (blocked). */
130	__test_icr(x, 0xa5a5a5a5a5a5a5a5 & ~APIC_DM_FIXED_MASK);
131	__test_icr(x, 0x5a5a5a5a5a5a5a5a & ~APIC_DM_FIXED_MASK);
132	__test_icr(x, -1ull & ~APIC_DM_FIXED_MASK);
133}
134
135static void __test_apic_id(struct kvm_vcpu *vcpu, uint64_t apic_base)
136{
137	uint32_t apic_id, expected;
138	struct kvm_lapic_state xapic;
139
140	vcpu_set_msr(vcpu, MSR_IA32_APICBASE, apic_base);
141
142	vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic);
143
144	expected = apic_base & X2APIC_ENABLE ? vcpu->id : vcpu->id << 24;
145	apic_id = *((u32 *)&xapic.regs[APIC_ID]);
146
147	TEST_ASSERT(apic_id == expected,
148		    "APIC_ID not set back to %s format; wanted = %x, got = %x",
149		    (apic_base & X2APIC_ENABLE) ? "x2APIC" : "xAPIC",
150		    expected, apic_id);
151}
152
153/*
154 * Verify that KVM switches the APIC_ID between xAPIC and x2APIC when userspace
155 * stuffs MSR_IA32_APICBASE.  Setting the APIC_ID when x2APIC is enabled and
156 * when the APIC transitions for DISABLED to ENABLED is architectural behavior
157 * (on Intel), whereas the x2APIC => xAPIC transition behavior is KVM ABI since
158 * attempted to transition from x2APIC to xAPIC without disabling the APIC is
159 * architecturally disallowed.
160 */
161static void test_apic_id(void)
162{
163	const uint32_t NR_VCPUS = 3;
164	struct kvm_vcpu *vcpus[NR_VCPUS];
165	uint64_t apic_base;
166	struct kvm_vm *vm;
167	int i;
168
169	vm = vm_create_with_vcpus(NR_VCPUS, NULL, vcpus);
170	vm_enable_cap(vm, KVM_CAP_X2APIC_API, KVM_X2APIC_API_USE_32BIT_IDS);
171
172	for (i = 0; i < NR_VCPUS; i++) {
173		apic_base = vcpu_get_msr(vcpus[i], MSR_IA32_APICBASE);
174
175		TEST_ASSERT(apic_base & MSR_IA32_APICBASE_ENABLE,
176			    "APIC not in ENABLED state at vCPU RESET");
177		TEST_ASSERT(!(apic_base & X2APIC_ENABLE),
178			    "APIC not in xAPIC mode at vCPU RESET");
179
180		__test_apic_id(vcpus[i], apic_base);
181		__test_apic_id(vcpus[i], apic_base | X2APIC_ENABLE);
182		__test_apic_id(vcpus[i], apic_base);
183	}
184
185	kvm_vm_free(vm);
186}
187
188int main(int argc, char *argv[])
189{
190	struct xapic_vcpu x = {
191		.vcpu = NULL,
192		.is_x2apic = true,
193	};
194	struct kvm_vm *vm;
195
196	vm = vm_create_with_one_vcpu(&x.vcpu, x2apic_guest_code);
197	test_icr(&x);
198	kvm_vm_free(vm);
199
200	/*
201	 * Use a second VM for the xAPIC test so that x2APIC can be hidden from
202	 * the guest in order to test AVIC.  KVM disallows changing CPUID after
203	 * KVM_RUN and AVIC is disabled if _any_ vCPU is allowed to use x2APIC.
204	 */
205	vm = vm_create_with_one_vcpu(&x.vcpu, xapic_guest_code);
206	x.is_x2apic = false;
207
208	vcpu_clear_cpuid_feature(x.vcpu, X86_FEATURE_X2APIC);
209
210	virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
211	test_icr(&x);
212	kvm_vm_free(vm);
213
214	test_apic_id();
215}
216