1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * RISC-V SBI specific definitions 4 * 5 * Copyright (C) 2024 Rivos Inc. 6 */ 7 8#ifndef SELFTEST_KVM_SBI_H 9#define SELFTEST_KVM_SBI_H 10 11/* SBI spec version fields */ 12#define SBI_SPEC_VERSION_DEFAULT 0x1 13#define SBI_SPEC_VERSION_MAJOR_SHIFT 24 14#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f 15#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff 16 17/* SBI return error codes */ 18#define SBI_SUCCESS 0 19#define SBI_ERR_FAILURE -1 20#define SBI_ERR_NOT_SUPPORTED -2 21#define SBI_ERR_INVALID_PARAM -3 22#define SBI_ERR_DENIED -4 23#define SBI_ERR_INVALID_ADDRESS -5 24#define SBI_ERR_ALREADY_AVAILABLE -6 25#define SBI_ERR_ALREADY_STARTED -7 26#define SBI_ERR_ALREADY_STOPPED -8 27 28#define SBI_EXT_EXPERIMENTAL_START 0x08000000 29#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF 30 31#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END 32#define KVM_RISCV_SELFTESTS_SBI_UCALL 0 33#define KVM_RISCV_SELFTESTS_SBI_UNEXP 1 34 35enum sbi_ext_id { 36 SBI_EXT_BASE = 0x10, 37 SBI_EXT_STA = 0x535441, 38 SBI_EXT_PMU = 0x504D55, 39}; 40 41enum sbi_ext_base_fid { 42 SBI_EXT_BASE_GET_SPEC_VERSION = 0, 43 SBI_EXT_BASE_GET_IMP_ID, 44 SBI_EXT_BASE_GET_IMP_VERSION, 45 SBI_EXT_BASE_PROBE_EXT = 3, 46}; 47enum sbi_ext_pmu_fid { 48 SBI_EXT_PMU_NUM_COUNTERS = 0, 49 SBI_EXT_PMU_COUNTER_GET_INFO, 50 SBI_EXT_PMU_COUNTER_CFG_MATCH, 51 SBI_EXT_PMU_COUNTER_START, 52 SBI_EXT_PMU_COUNTER_STOP, 53 SBI_EXT_PMU_COUNTER_FW_READ, 54 SBI_EXT_PMU_COUNTER_FW_READ_HI, 55 SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, 56}; 57 58union sbi_pmu_ctr_info { 59 unsigned long value; 60 struct { 61 unsigned long csr:12; 62 unsigned long width:6; 63#if __riscv_xlen == 32 64 unsigned long reserved:13; 65#else 66 unsigned long reserved:45; 67#endif 68 unsigned long type:1; 69 }; 70}; 71 72struct riscv_pmu_snapshot_data { 73 u64 ctr_overflow_mask; 74 u64 ctr_values[64]; 75 u64 reserved[447]; 76}; 77 78struct sbiret { 79 long error; 80 long value; 81}; 82 83/** General pmu event codes specified in SBI PMU extension */ 84enum sbi_pmu_hw_generic_events_t { 85 SBI_PMU_HW_NO_EVENT = 0, 86 SBI_PMU_HW_CPU_CYCLES = 1, 87 SBI_PMU_HW_INSTRUCTIONS = 2, 88 SBI_PMU_HW_CACHE_REFERENCES = 3, 89 SBI_PMU_HW_CACHE_MISSES = 4, 90 SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5, 91 SBI_PMU_HW_BRANCH_MISSES = 6, 92 SBI_PMU_HW_BUS_CYCLES = 7, 93 SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8, 94 SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9, 95 SBI_PMU_HW_REF_CPU_CYCLES = 10, 96 97 SBI_PMU_HW_GENERAL_MAX, 98}; 99 100/* SBI PMU counter types */ 101enum sbi_pmu_ctr_type { 102 SBI_PMU_CTR_TYPE_HW = 0x0, 103 SBI_PMU_CTR_TYPE_FW, 104}; 105 106/* Flags defined for config matching function */ 107#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) 108#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) 109#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) 110#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) 111#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) 112#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) 113#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) 114#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) 115 116/* Flags defined for counter start function */ 117#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) 118#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1) 119 120/* Flags defined for counter stop function */ 121#define SBI_PMU_STOP_FLAG_RESET BIT(0) 122#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) 123 124struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, 125 unsigned long arg1, unsigned long arg2, 126 unsigned long arg3, unsigned long arg4, 127 unsigned long arg5); 128 129bool guest_sbi_probe_extension(int extid, long *out_val); 130 131/* Make SBI version */ 132static inline unsigned long sbi_mk_version(unsigned long major, 133 unsigned long minor) 134{ 135 return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT) 136 | (minor & SBI_SPEC_VERSION_MINOR_MASK); 137} 138 139unsigned long get_host_sbi_spec_version(void); 140 141#endif /* SELFTEST_KVM_SBI_H */ 142