1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * AArch64 processor specific defines
4 *
5 * Copyright (C) 2018, Red Hat, Inc.
6 */
7#ifndef SELFTEST_KVM_PROCESSOR_H
8#define SELFTEST_KVM_PROCESSOR_H
9
10#include "kvm_util.h"
11#include <linux/stringify.h>
12#include <linux/types.h>
13#include <asm/sysreg.h>
14
15
16#define ARM64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
17			   KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
18
19/*
20 * KVM_ARM64_SYS_REG(sys_reg_id): Helper macro to convert
21 * SYS_* register definitions in asm/sysreg.h to use in KVM
22 * calls such as vcpu_get_reg() and vcpu_set_reg().
23 */
24#define KVM_ARM64_SYS_REG(sys_reg_id)			\
25	ARM64_SYS_REG(sys_reg_Op0(sys_reg_id),		\
26			sys_reg_Op1(sys_reg_id),	\
27			sys_reg_CRn(sys_reg_id),	\
28			sys_reg_CRm(sys_reg_id),	\
29			sys_reg_Op2(sys_reg_id))
30
31/*
32 * Default MAIR
33 *                  index   attribute
34 * DEVICE_nGnRnE      0     0000:0000
35 * DEVICE_nGnRE       1     0000:0100
36 * DEVICE_GRE         2     0000:1100
37 * NORMAL_NC          3     0100:0100
38 * NORMAL             4     1111:1111
39 * NORMAL_WT          5     1011:1011
40 */
41#define DEFAULT_MAIR_EL1 ((0x00ul << (0 * 8)) | \
42			  (0x04ul << (1 * 8)) | \
43			  (0x0cul << (2 * 8)) | \
44			  (0x44ul << (3 * 8)) | \
45			  (0xfful << (4 * 8)) | \
46			  (0xbbul << (5 * 8)))
47
48#define MPIDR_HWID_BITMASK (0xff00fffffful)
49
50void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init);
51struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
52				  struct kvm_vcpu_init *init, void *guest_code);
53
54struct ex_regs {
55	u64 regs[31];
56	u64 sp;
57	u64 pc;
58	u64 pstate;
59};
60
61#define VECTOR_NUM	16
62
63enum {
64	VECTOR_SYNC_CURRENT_SP0,
65	VECTOR_IRQ_CURRENT_SP0,
66	VECTOR_FIQ_CURRENT_SP0,
67	VECTOR_ERROR_CURRENT_SP0,
68
69	VECTOR_SYNC_CURRENT,
70	VECTOR_IRQ_CURRENT,
71	VECTOR_FIQ_CURRENT,
72	VECTOR_ERROR_CURRENT,
73
74	VECTOR_SYNC_LOWER_64,
75	VECTOR_IRQ_LOWER_64,
76	VECTOR_FIQ_LOWER_64,
77	VECTOR_ERROR_LOWER_64,
78
79	VECTOR_SYNC_LOWER_32,
80	VECTOR_IRQ_LOWER_32,
81	VECTOR_FIQ_LOWER_32,
82	VECTOR_ERROR_LOWER_32,
83};
84
85#define VECTOR_IS_SYNC(v) ((v) == VECTOR_SYNC_CURRENT_SP0 || \
86			   (v) == VECTOR_SYNC_CURRENT     || \
87			   (v) == VECTOR_SYNC_LOWER_64    || \
88			   (v) == VECTOR_SYNC_LOWER_32)
89
90#define ESR_EC_NUM		64
91#define ESR_EC_SHIFT		26
92#define ESR_EC_MASK		(ESR_EC_NUM - 1)
93
94#define ESR_EC_SVC64		0x15
95#define ESR_EC_HW_BP_CURRENT	0x31
96#define ESR_EC_SSTEP_CURRENT	0x33
97#define ESR_EC_WP_CURRENT	0x35
98#define ESR_EC_BRK_INS		0x3c
99
100void aarch64_get_supported_page_sizes(uint32_t ipa,
101				      bool *ps4k, bool *ps16k, bool *ps64k);
102
103void vm_init_descriptor_tables(struct kvm_vm *vm);
104void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu);
105
106typedef void(*handler_fn)(struct ex_regs *);
107void vm_install_exception_handler(struct kvm_vm *vm,
108		int vector, handler_fn handler);
109void vm_install_sync_handler(struct kvm_vm *vm,
110		int vector, int ec, handler_fn handler);
111
112static inline void cpu_relax(void)
113{
114	asm volatile("yield" ::: "memory");
115}
116
117#define isb()		asm volatile("isb" : : : "memory")
118#define dsb(opt)	asm volatile("dsb " #opt : : : "memory")
119#define dmb(opt)	asm volatile("dmb " #opt : : : "memory")
120
121#define dma_wmb()	dmb(oshst)
122#define __iowmb()	dma_wmb()
123
124#define dma_rmb()	dmb(oshld)
125
126#define __iormb(v)							\
127({									\
128	unsigned long tmp;						\
129									\
130	dma_rmb();							\
131									\
132	/*								\
133	 * Courtesy of arch/arm64/include/asm/io.h:			\
134	 * Create a dummy control dependency from the IO read to any	\
135	 * later instructions. This ensures that a subsequent call	\
136	 * to udelay() will be ordered due to the ISB in __delay().	\
137	 */								\
138	asm volatile("eor	%0, %1, %1\n"				\
139		     "cbnz	%0, ."					\
140		     : "=r" (tmp) : "r" ((unsigned long)(v))		\
141		     : "memory");					\
142})
143
144static __always_inline void __raw_writel(u32 val, volatile void *addr)
145{
146	asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
147}
148
149static __always_inline u32 __raw_readl(const volatile void *addr)
150{
151	u32 val;
152	asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
153	return val;
154}
155
156#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
157#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
158
159#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c));})
160#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
161
162static inline void local_irq_enable(void)
163{
164	asm volatile("msr daifclr, #3" : : : "memory");
165}
166
167static inline void local_irq_disable(void)
168{
169	asm volatile("msr daifset, #3" : : : "memory");
170}
171
172/**
173 * struct arm_smccc_res - Result from SMC/HVC call
174 * @a0-a3 result values from registers 0 to 3
175 */
176struct arm_smccc_res {
177	unsigned long a0;
178	unsigned long a1;
179	unsigned long a2;
180	unsigned long a3;
181};
182
183/**
184 * smccc_hvc - Invoke a SMCCC function using the hvc conduit
185 * @function_id: the SMCCC function to be called
186 * @arg0-arg6: SMCCC function arguments, corresponding to registers x1-x7
187 * @res: pointer to write the return values from registers x0-x3
188 *
189 */
190void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
191	       uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
192	       uint64_t arg6, struct arm_smccc_res *res);
193
194uint32_t guest_get_vcpuid(void);
195
196#endif /* SELFTEST_KVM_PROCESSOR_H */
197