1[
2    {
3        "BriefDescription": "Memory accesses that missed the DTLB.",
4        "EventCode": "0x8",
5        "EventName": "DATA_TLB_MISSES.DTLB_MISS",
6        "SampleAfterValue": "200000",
7        "UMask": "0x7"
8    },
9    {
10        "BriefDescription": "DTLB misses due to load operations.",
11        "EventCode": "0x8",
12        "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
13        "SampleAfterValue": "200000",
14        "UMask": "0x5"
15    },
16    {
17        "BriefDescription": "DTLB misses due to store operations.",
18        "EventCode": "0x8",
19        "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
20        "SampleAfterValue": "200000",
21        "UMask": "0x6"
22    },
23    {
24        "BriefDescription": "L0 DTLB misses due to load operations.",
25        "EventCode": "0x8",
26        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
27        "SampleAfterValue": "200000",
28        "UMask": "0x9"
29    },
30    {
31        "BriefDescription": "L0 DTLB misses due to store operations",
32        "EventCode": "0x8",
33        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
34        "SampleAfterValue": "200000",
35        "UMask": "0xa"
36    },
37    {
38        "BriefDescription": "ITLB flushes.",
39        "EventCode": "0x82",
40        "EventName": "ITLB.FLUSH",
41        "SampleAfterValue": "200000",
42        "UMask": "0x4"
43    },
44    {
45        "BriefDescription": "ITLB hits.",
46        "EventCode": "0x82",
47        "EventName": "ITLB.HIT",
48        "SampleAfterValue": "200000",
49        "UMask": "0x1"
50    },
51    {
52        "BriefDescription": "ITLB misses.",
53        "EventCode": "0x82",
54        "EventName": "ITLB.MISSES",
55        "PEBS": "2",
56        "SampleAfterValue": "200000",
57        "UMask": "0x2"
58    },
59    {
60        "BriefDescription": "Retired loads that miss the DTLB (precise event).",
61        "EventCode": "0xCB",
62        "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
63        "PEBS": "1",
64        "SampleAfterValue": "200000",
65        "UMask": "0x4"
66    },
67    {
68        "BriefDescription": "Duration of page-walks in core cycles",
69        "EventCode": "0xC",
70        "EventName": "PAGE_WALKS.CYCLES",
71        "SampleAfterValue": "2000000",
72        "UMask": "0x3"
73    },
74    {
75        "BriefDescription": "Duration of D-side only page walks",
76        "EventCode": "0xC",
77        "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
78        "SampleAfterValue": "2000000",
79        "UMask": "0x1"
80    },
81    {
82        "BriefDescription": "Number of D-side only page walks",
83        "EventCode": "0xC",
84        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
85        "SampleAfterValue": "200000",
86        "UMask": "0x1"
87    },
88    {
89        "BriefDescription": "Duration of I-Side page walks",
90        "EventCode": "0xC",
91        "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
92        "SampleAfterValue": "2000000",
93        "UMask": "0x2"
94    },
95    {
96        "BriefDescription": "Number of I-Side page walks",
97        "EventCode": "0xC",
98        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
99        "SampleAfterValue": "200000",
100        "UMask": "0x2"
101    },
102    {
103        "BriefDescription": "Number of page-walks executed.",
104        "EventCode": "0xC",
105        "EventName": "PAGE_WALKS.WALKS",
106        "SampleAfterValue": "200000",
107        "UMask": "0x3"
108    }
109]
110