1[
2    {
3        "PublicDescription": "Level 2 prefetch requests, refilled to L2 cache",
4        "EventCode": "0x10A",
5        "EventName": "L2_PREFETCH_REFILL",
6        "BriefDescription": "Level 2 prefetch requests, refilled to L2 cache"
7    },
8    {
9        "PublicDescription": "Level 2 prefetch requests, late",
10        "EventCode": "0x10B",
11        "EventName": "L2_PREFETCH_UPGRADE",
12        "BriefDescription": "Level 2 prefetch requests, late"
13    },
14    {
15        "PublicDescription": "Predictable branch speculatively executed that hit any level of BTB",
16        "EventCode": "0x110",
17        "EventName": "BPU_HIT_BTB",
18        "BriefDescription": "Predictable branch speculatively executed that hit any level of BTB"
19    },
20    {
21        "PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB",
22        "EventCode": "0x111",
23        "EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB",
24        "BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB"
25    },
26    {
27        "PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor",
28        "EventCode": "0x112",
29        "EventName": "BPU_HIT_INDIRECT_PREDICTOR",
30        "BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor"
31    },
32    {
33        "PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor",
34        "EventCode": "0x113",
35        "EventName": "BPU_HIT_RSB",
36        "BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor"
37    },
38    {
39        "PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB",
40        "EventCode": "0x114",
41        "EventName": "BPU_UNCONDITIONAL_BRANCH_MISS_BTB",
42        "BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB"
43    },
44    {
45        "PublicDescription": "Predictable branch speculatively executed, unpredicted",
46        "EventCode": "0x115",
47        "EventName": "BPU_BRANCH_NO_HIT",
48        "BriefDescription": "Predictable branch speculatively executed, unpredicted"
49    },
50    {
51        "PublicDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict",
52        "EventCode": "0x116",
53        "EventName": "BPU_HIT_BTB_AND_MISPREDICT",
54        "BriefDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict"
55    },
56    {
57        "PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict",
58        "EventCode": "0x117",
59        "EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB_AND_MISPREDICT",
60        "BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict"
61    },
62    {
63        "PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict",
64        "EventCode": "0x118",
65        "EventName": "BPU_INDIRECT_BRANCH_HIT_BTB_AND_MISPREDICT",
66        "BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict"
67    },
68    {
69        "PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict",
70        "EventCode": "0x119",
71        "EventName": "BPU_HIT_RSB_AND_MISPREDICT",
72        "BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict"
73    },
74    {
75        "PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict",
76        "EventCode": "0x11a",
77        "EventName": "BPU_MISS_RSB_AND_MISPREDICT",
78        "BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict"
79    },
80    {
81        "PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
82        "EventCode": "0x11b",
83        "EventName": "BPU_NO_PREDICTION_MISPREDICT",
84        "BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
85    },
86    {
87        "PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
88        "EventCode": "0x11c",
89        "EventName": "BPU_BTB_UPDATE",
90        "BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
91    },
92    {
93        "PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
94        "EventCode": "0x11d",
95        "EventName": "BPU_RSB_FULL_STALL",
96        "BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
97    },
98    {
99        "PublicDescription": "Macro-ops speculatively decoded",
100        "EventCode": "0x11f",
101        "EventName": "ICF_INST_SPEC_DECODE",
102        "BriefDescription": "Macro-ops speculatively decoded"
103    },
104    {
105        "PublicDescription": "Flushes",
106        "EventCode": "0x120",
107        "EventName": "GPC_FLUSH",
108        "BriefDescription": "Flushes"
109    },
110    {
111        "PublicDescription": "Flushes due to memory hazards",
112        "EventCode": "0x121",
113        "EventName": "GPC_FLUSH_MEM_FAULT",
114        "BriefDescription": "Flushes due to memory hazards"
115    },
116    {
117        "PublicDescription": "ETM extout bit 0",
118        "EventCode": "0x141",
119        "EventName": "MSC_ETM_EXTOUT0",
120        "BriefDescription": "ETM extout bit 0"
121    },
122    {
123        "PublicDescription": "ETM extout bit 1",
124        "EventCode": "0x142",
125        "EventName": "MSC_ETM_EXTOUT1",
126        "BriefDescription": "ETM extout bit 1"
127    },
128    {
129        "PublicDescription": "ETM extout bit 2",
130        "EventCode": "0x143",
131        "EventName": "MSC_ETM_EXTOUT2",
132        "BriefDescription": "ETM extout bit 2"
133    },
134    {
135        "PublicDescription": "ETM extout bit 3",
136        "EventCode": "0x144",
137        "EventName": "MSC_ETM_EXTOUT3",
138        "BriefDescription": "ETM extout bit 3"
139    },
140    {
141        "PublicDescription": "Bus request sn",
142        "EventCode": "0x156",
143        "EventName": "L2C_SNOOP",
144        "BriefDescription": "Bus request sn"
145    },
146    {
147        "PublicDescription": "L2 TXDAT LCRD blocked",
148        "EventCode": "0x169",
149        "EventName": "L2C_DAT_CRD_STALL",
150        "BriefDescription": "L2 TXDAT LCRD blocked"
151    },
152    {
153        "PublicDescription": "L2 TXRSP LCRD blocked",
154        "EventCode": "0x16a",
155        "EventName": "L2C_RSP_CRD_STALL",
156        "BriefDescription": "L2 TXRSP LCRD blocked"
157    },
158    {
159        "PublicDescription": "L2 TXREQ LCRD blocked",
160        "EventCode": "0x16b",
161        "EventName": "L2C_REQ_CRD_STALL",
162        "BriefDescription": "L2 TXREQ LCRD blocked"
163    },
164    {
165        "PublicDescription": "Early mispredict",
166        "EventCode": "0xD100",
167        "EventName": "ICF_EARLY_MIS_PRED",
168        "BriefDescription": "Early mispredict"
169    },
170    {
171        "PublicDescription": "FEQ full cycles",
172        "EventCode": "0xD101",
173        "EventName": "ICF_FEQ_FULL",
174        "BriefDescription": "FEQ full cycles"
175    },
176    {
177        "PublicDescription": "Instruction FIFO Full",
178        "EventCode": "0xD102",
179        "EventName": "ICF_INST_FIFO_FULL",
180        "BriefDescription": "Instruction FIFO Full"
181    },
182    {
183        "PublicDescription": "L1I TLB miss",
184        "EventCode": "0xD103",
185        "EventName": "L1I_TLB_MISS",
186        "BriefDescription": "L1I TLB miss"
187    },
188    {
189        "PublicDescription": "ICF sent 0 instructions to IDR this cycle",
190        "EventCode": "0xD104",
191        "EventName": "ICF_STALL",
192        "BriefDescription": "ICF sent 0 instructions to IDR this cycle"
193    },
194    {
195        "PublicDescription": "PC FIFO Full",
196        "EventCode": "0xD105",
197        "EventName": "ICF_PC_FIFO_FULL",
198        "BriefDescription": "PC FIFO Full"
199    },
200    {
201        "PublicDescription": "Stall due to BOB ID",
202        "EventCode": "0xD200",
203        "EventName": "IDR_STALL_BOB_ID",
204        "BriefDescription": "Stall due to BOB ID"
205    },
206    {
207        "PublicDescription": "Dispatch stall due to LOB entries",
208        "EventCode": "0xD201",
209        "EventName": "IDR_STALL_LOB_ID",
210        "BriefDescription": "Dispatch stall due to LOB entries"
211    },
212    {
213        "PublicDescription": "Dispatch stall due to SOB entries",
214        "EventCode": "0xD202",
215        "EventName": "IDR_STALL_SOB_ID",
216        "BriefDescription": "Dispatch stall due to SOB entries"
217    },
218    {
219        "PublicDescription": "Dispatch stall due to IXU scheduler entries",
220        "EventCode": "0xD203",
221        "EventName": "IDR_STALL_IXU_SCHED",
222        "BriefDescription": "Dispatch stall due to IXU scheduler entries"
223    },
224    {
225        "PublicDescription": "Dispatch stall due to FSU scheduler entries",
226        "EventCode": "0xD204",
227        "EventName": "IDR_STALL_FSU_SCHED",
228        "BriefDescription": "Dispatch stall due to FSU scheduler entries"
229    },
230    {
231        "PublicDescription": "Dispatch stall due to ROB entries",
232        "EventCode": "0xD205",
233        "EventName": "IDR_STALL_ROB_ID",
234        "BriefDescription": "Dispatch stall due to ROB entries"
235    },
236    {
237        "PublicDescription": "Dispatch stall due to flush (6 cycles)",
238        "EventCode": "0xD206",
239        "EventName": "IDR_STALL_FLUSH",
240        "BriefDescription": "Dispatch stall due to flush (6 cycles)"
241    },
242    {
243        "PublicDescription": "Dispatch stall due to WFI",
244        "EventCode": "0xD207",
245        "EventName": "IDR_STALL_WFI",
246        "BriefDescription": "Dispatch stall due to WFI"
247    },
248    {
249        "PublicDescription": "Number of SWOB drains triggered by timeout",
250        "EventCode": "0xD208",
251        "EventName": "IDR_STALL_SWOB_TIMEOUT",
252        "BriefDescription": "Number of SWOB drains triggered by timeout"
253    },
254    {
255        "PublicDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain",
256        "EventCode": "0xD209",
257        "EventName": "IDR_STALL_SWOB_RAW",
258        "BriefDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain"
259    },
260    {
261        "PublicDescription": "Number of SWOB drains triggered by system register write when SWOB full",
262        "EventCode": "0xD20A",
263        "EventName": "IDR_STALL_SWOB_FULL",
264        "BriefDescription": "Number of SWOB drains triggered by system register write when SWOB full"
265    },
266    {
267        "PublicDescription": "Dispatch stall due to L1 instruction cache miss",
268        "EventCode": "0xD20B",
269        "EventName": "STALL_FRONTEND_CACHE",
270        "BriefDescription": "Dispatch stall due to L1 instruction cache miss"
271    },
272    {
273        "PublicDescription": "Dispatch stall due to L1 instruction TLB miss",
274        "EventCode": "0xD20C",
275        "EventName": "STALL_FRONTEND_TLB",
276        "BriefDescription": "Dispatch stall due to L1 instruction TLB miss"
277    },
278    {
279        "PublicDescription": "Dispatch stall due to L1 data cache miss",
280        "EventCode": "0xD20D",
281        "EventName": "STALL_BACKEND_CACHE",
282        "BriefDescription": "Dispatch stall due to L1 data cache miss"
283    },
284    {
285        "PublicDescription": "Dispatch stall due to L1 data TLB miss",
286        "EventCode": "0xD20E",
287        "EventName": "STALL_BACKEND_TLB",
288        "BriefDescription": "Dispatch stall due to L1 data TLB miss"
289    },
290    {
291        "PublicDescription": "Dispatch stall due to lack of any core resource",
292        "EventCode": "0xD20F",
293        "EventName": "STALL_BACKEND_RESOURCE",
294        "BriefDescription": "Dispatch stall due to lack of any core resource"
295    },
296    {
297        "PublicDescription": "Instructions issued by the scheduler",
298        "EventCode": "0xD300",
299        "EventName": "IXU_NUM_UOPS_ISSUED",
300        "BriefDescription": "Instructions issued by the scheduler"
301    },
302    {
303        "PublicDescription": "Any uop issued was canceled for any reason",
304        "EventCode": "0xD301",
305        "EventName": "IXU_ISSUE_CANCEL",
306        "BriefDescription": "Any uop issued was canceled for any reason"
307    },
308    {
309        "PublicDescription": "A load wakeup to the scheduler has been cancelled",
310        "EventCode": "0xD302",
311        "EventName": "IXU_LOAD_CANCEL",
312        "BriefDescription": "A load wakeup to the scheduler has been cancelled"
313    },
314    {
315        "PublicDescription": "The scheduler had to cancel one slow Uop due to resource conflict",
316        "EventCode": "0xD303",
317        "EventName": "IXU_SLOW_CANCEL",
318        "BriefDescription": "The scheduler had to cancel one slow Uop due to resource conflict"
319    },
320    {
321        "PublicDescription": "Uops issued by the scheduler on IXA",
322        "EventCode": "0xD304",
323        "EventName": "IXU_IXA_ISSUED",
324        "BriefDescription": "Uops issued by the scheduler on IXA"
325    },
326    {
327        "PublicDescription": "Uops issued by the scheduler on IXA Par 0",
328        "EventCode": "0xD305",
329        "EventName": "IXU_IXA_PAR0_ISSUED",
330        "BriefDescription": "Uops issued by the scheduler on IXA Par 0"
331    },
332    {
333        "PublicDescription": "Uops issued by the scheduler on IXA Par 1",
334        "EventCode": "0xD306",
335        "EventName": "IXU_IXA_PAR1_ISSUED",
336        "BriefDescription": "Uops issued by the scheduler on IXA Par 1"
337    },
338    {
339        "PublicDescription": "Uops issued by the scheduler on IXB",
340        "EventCode": "0xD307",
341        "EventName": "IXU_IXB_ISSUED",
342        "BriefDescription": "Uops issued by the scheduler on IXB"
343    },
344    {
345        "PublicDescription": "Uops issued by the scheduler on IXB Par 0",
346        "EventCode": "0xD308",
347        "EventName": "IXU_IXB_PAR0_ISSUED",
348        "BriefDescription": "Uops issued by the scheduler on IXB Par 0"
349    },
350    {
351        "PublicDescription": "Uops issued by the scheduler on IXB Par 1",
352        "EventCode": "0xD309",
353        "EventName": "IXU_IXB_PAR1_ISSUED",
354        "BriefDescription": "Uops issued by the scheduler on IXB Par 1"
355    },
356    {
357        "PublicDescription": "Uops issued by the scheduler on IXC",
358        "EventCode": "0xD30A",
359        "EventName": "IXU_IXC_ISSUED",
360        "BriefDescription": "Uops issued by the scheduler on IXC"
361    },
362    {
363        "PublicDescription": "Uops issued by the scheduler on IXC Par 0",
364        "EventCode": "0xD30B",
365        "EventName": "IXU_IXC_PAR0_ISSUED",
366        "BriefDescription": "Uops issued by the scheduler on IXC Par 0"
367    },
368    {
369        "PublicDescription": "Uops issued by the scheduler on IXC Par 1",
370        "EventCode": "0xD30C",
371        "EventName": "IXU_IXC_PAR1_ISSUED",
372        "BriefDescription": "Uops issued by the scheduler on IXC Par 1"
373    },
374    {
375        "PublicDescription": "Uops issued by the scheduler on IXD",
376        "EventCode": "0xD30D",
377        "EventName": "IXU_IXD_ISSUED",
378        "BriefDescription": "Uops issued by the scheduler on IXD"
379    },
380    {
381        "PublicDescription": "Uops issued by the scheduler on IXD Par 0",
382        "EventCode": "0xD30E",
383        "EventName": "IXU_IXD_PAR0_ISSUED",
384        "BriefDescription": "Uops issued by the scheduler on IXD Par 0"
385    },
386    {
387        "PublicDescription": "Uops issued by the scheduler on IXD Par 1",
388        "EventCode": "0xD30F",
389        "EventName": "IXU_IXD_PAR1_ISSUED",
390        "BriefDescription": "Uops issued by the scheduler on IXD Par 1"
391    },
392    {
393        "PublicDescription": "Uops issued by the FSU scheduler",
394        "EventCode": "0xD400",
395        "EventName": "FSU_ISSUED",
396        "BriefDescription": "Uops issued by the FSU scheduler"
397    },
398    {
399        "PublicDescription": "Uops issued by the scheduler on pipe X",
400        "EventCode": "0xD401",
401        "EventName": "FSU_FSX_ISSUED",
402        "BriefDescription": "Uops issued by the scheduler on pipe X"
403    },
404    {
405        "PublicDescription": "Uops issued by the scheduler on pipe Y",
406        "EventCode": "0xD402",
407        "EventName": "FSU_FSY_ISSUED",
408        "BriefDescription": "Uops issued by the scheduler on pipe Y"
409    },
410    {
411        "PublicDescription": "Uops issued by the scheduler on pipe Z",
412        "EventCode": "0xD403",
413        "EventName": "FSU_FSZ_ISSUED",
414        "BriefDescription": "Uops issued by the scheduler on pipe Z"
415    },
416    {
417        "PublicDescription": "Uops canceled (load cancels)",
418        "EventCode": "0xD404",
419        "EventName": "FSU_CANCEL",
420        "BriefDescription": "Uops canceled (load cancels)"
421    },
422    {
423        "PublicDescription": "Count scheduler stalls due to divide/sqrt",
424        "EventCode": "0xD405",
425        "EventName": "FSU_DIV_SQRT_STALL",
426        "BriefDescription": "Count scheduler stalls due to divide/sqrt"
427    },
428    {
429        "PublicDescription": "Number of SWOB drains",
430        "EventCode": "0xD500",
431        "EventName": "GPC_SWOB_DRAIN",
432        "BriefDescription": "Number of SWOB drains"
433    },
434    {
435        "PublicDescription": "GPC detected a Breakpoint instruction match",
436        "EventCode": "0xD501",
437        "EventName": "BREAKPOINT_MATCH",
438        "BriefDescription": "GPC detected a Breakpoint instruction match"
439    },
440    {
441        "PublicDescription": "L1D TLB miss",
442        "EventCode": "0xD600",
443        "EventName": "L1D_TLB_MISS",
444        "BriefDescription": "L1D TLB miss"
445    },
446    {
447        "PublicDescription": "OFB full cycles",
448        "EventCode": "0xD601",
449        "EventName": "OFB_FULL",
450        "BriefDescription": "OFB full cycles"
451    },
452    {
453        "PublicDescription": "Load satisified from store forwarded data",
454        "EventCode": "0xD605",
455        "EventName": "LD_FROM_ST_FWD",
456        "BriefDescription": "Load satisified from store forwarded data"
457    },
458    {
459        "PublicDescription": "L1 prefetcher, load prefetch requests generated",
460        "EventCode": "0xD606",
461        "EventName": "L1_PFETCH_LD_GEN",
462        "BriefDescription": "L1 prefetcher, load prefetch requests generated"
463    },
464    {
465        "PublicDescription": "L1 prefetcher, load prefetch fills into the L1 cache",
466        "EventCode": "0xD607",
467        "EventName": "L1_PFETCH_LD_FILL",
468        "BriefDescription": "L1 prefetcher, load prefetch fills into the L1 cache"
469    },
470    {
471        "PublicDescription": "L1 prefetcher, load prefetch to L2 generated",
472        "EventCode": "0xD608",
473        "EventName": "L1_PFETCH_L2_REQ",
474        "BriefDescription": "L1 prefetcher, load prefetch to L2 generated"
475    },
476    {
477        "PublicDescription": "L1 prefetcher, distance was reset",
478        "EventCode": "0xD609",
479        "EventName": "L1_PFETCH_DIST_RST",
480        "BriefDescription": "L1 prefetcher, distance was reset"
481    },
482    {
483        "PublicDescription": "L1 prefetcher, distance was increased",
484        "EventCode": "0xD60A",
485        "EventName": "L1_PFETCH_DIST_INC",
486        "BriefDescription": "L1 prefetcher, distance was increased"
487    },
488    {
489        "PublicDescription": "L1 prefetcher, table entry is trained",
490        "EventCode": "0xD60B",
491        "EventName": "L1_PFETCH_ENTRY_TRAINED",
492        "BriefDescription": "L1 prefetcher, table entry is trained"
493    },
494    {
495        "PublicDescription": "Store retirement pipe stall",
496        "EventCode": "0xD60C",
497        "EventName": "LSU_ST_RETIRE_STALL",
498        "BriefDescription": "Store retirement pipe stall"
499    },
500    {
501        "PublicDescription": "LSU detected a Watchpoint data match",
502        "EventCode": "0xD60D",
503        "EventName": "WATCHPOINT_MATCH",
504        "BriefDescription": "LSU detected a Watchpoint data match"
505    },
506    {
507        "PublicDescription": "L2 pipeline replay",
508        "EventCode": "0xD700",
509        "EventName": "L2C_PIPE_REPLAY",
510        "BriefDescription": "L2 pipeline replay"
511    },
512    {
513        "PublicDescription": "L2 refill from I-side miss",
514        "EventCode": "0xD701",
515        "EventName": "L2C_INST_REFILL",
516        "BriefDescription": "L2 refill from I-side miss"
517    },
518    {
519        "PublicDescription": "L2 refill from D-side miss",
520        "EventCode": "0xD702",
521        "EventName": "L2C_DATA_REFILL",
522        "BriefDescription": "L2 refill from D-side miss"
523    },
524    {
525        "PublicDescription": "L2 prefetcher, load prefetch requests generated",
526        "EventCode": "0xD703",
527        "EventName": "L2_PREFETCH_REQ",
528        "BriefDescription": "L2 prefetcher, load prefetch requests generated"
529    },
530    {
531        "PublicDescription": "L2D OTB allocate",
532        "EventCode": "0xD800",
533        "EventName": "MMU_D_OTB_ALLOC",
534        "BriefDescription": "L2D OTB allocate"
535    },
536    {
537        "PublicDescription": "D-side Stage1 tablewalk fault",
538        "EventCode": "0xD80B",
539        "EventName": "MMU_D_S1_WALK_FAULT",
540        "BriefDescription": "D-side Stage1 tablewalk fault"
541    },
542    {
543        "PublicDescription": "D-side Stage2 tablewalk fault",
544        "EventCode": "0xD80C",
545        "EventName": "MMU_D_S2_WALK_FAULT",
546        "BriefDescription": "D-side Stage2 tablewalk fault"
547    },
548    {
549        "PublicDescription": "D-side Tablewalk steps or descriptor fetches",
550        "EventCode": "0xD80D",
551        "EventName": "MMU_D_WALK_STEPS",
552        "BriefDescription": "D-side Tablewalk steps or descriptor fetches"
553    },
554    {
555        "PublicDescription": "L2I OTB allocate",
556        "EventCode": "0xD900",
557        "EventName": "MMU_I_OTB_ALLOC",
558        "BriefDescription": "L2I OTB allocate"
559    },
560    {
561        "PublicDescription": "I-side Stage1 tablewalk fault",
562        "EventCode": "0xD90B",
563        "EventName": "MMU_I_S1_WALK_FAULT",
564        "BriefDescription": "I-side Stage1 tablewalk fault"
565    },
566    {
567        "PublicDescription": "I-side Stage2 tablewalk fault",
568        "EventCode": "0xD90C",
569        "EventName": "MMU_I_S2_WALK_FAULT",
570        "BriefDescription": "I-side Stage2 tablewalk fault"
571    },
572    {
573        "PublicDescription": "I-side Tablewalk steps or descriptor fetches",
574        "EventCode": "0xD90D",
575        "EventName": "MMU_I_WALK_STEPS",
576        "BriefDescription": "I-side Tablewalk steps or descriptor fetches"
577    }
578]
579