1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * tegra210_ope.h - Definitions for Tegra210 OPE driver
4 *
5 * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
6 *
7 */
8
9#ifndef __TEGRA210_OPE_H__
10#define __TEGRA210_OPE_H__
11
12#include <linux/regmap.h>
13#include <sound/soc.h>
14
15#include "tegra210_peq.h"
16
17/*
18 * OPE_RX registers are with respect to XBAR.
19 * The data comes from XBAR to OPE
20 */
21#define TEGRA210_OPE_RX_STATUS			0xc
22#define TEGRA210_OPE_RX_INT_STATUS		0x10
23#define TEGRA210_OPE_RX_INT_MASK		0x14
24#define TEGRA210_OPE_RX_INT_SET			0x18
25#define TEGRA210_OPE_RX_INT_CLEAR		0x1c
26#define TEGRA210_OPE_RX_CIF_CTRL		0x20
27
28/*
29 * OPE_TX registers are with respect to XBAR.
30 * The data goes out from OPE to XBAR
31 */
32#define TEGRA210_OPE_TX_STATUS			0x4c
33#define TEGRA210_OPE_TX_INT_STATUS		0x50
34#define TEGRA210_OPE_TX_INT_MASK		0x54
35#define TEGRA210_OPE_TX_INT_SET			0x58
36#define TEGRA210_OPE_TX_INT_CLEAR		0x5c
37#define TEGRA210_OPE_TX_CIF_CTRL		0x60
38
39/* OPE Gloabal registers */
40#define TEGRA210_OPE_ENABLE			0x80
41#define TEGRA210_OPE_SOFT_RESET			0x84
42#define TEGRA210_OPE_CG				0x88
43#define TEGRA210_OPE_STATUS			0x8c
44#define TEGRA210_OPE_INT_STATUS			0x90
45#define TEGRA210_OPE_DIR			0x94
46
47/* Fields for TEGRA210_OPE_ENABLE */
48#define TEGRA210_OPE_EN_SHIFT			0
49#define TEGRA210_OPE_EN				(1 << TEGRA210_OPE_EN_SHIFT)
50
51/* Fields for TEGRA210_OPE_SOFT_RESET */
52#define TEGRA210_OPE_SOFT_RESET_SHIFT		0
53#define TEGRA210_OPE_SOFT_RESET_EN		(1 << TEGRA210_OPE_SOFT_RESET_SHIFT)
54
55#define TEGRA210_OPE_DIR_SHIFT			0
56
57struct tegra210_ope {
58	struct regmap *regmap;
59	struct regmap *peq_regmap;
60	struct regmap *mbdrc_regmap;
61	u32 peq_biquad_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH];
62	u32 peq_biquad_shifts[TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH];
63	unsigned int data_dir;
64};
65
66/* Extension of soc_bytes structure defined in sound/soc.h */
67struct tegra_soc_bytes {
68	struct soc_bytes soc;
69	u32 shift; /* Used as offset for AHUB RAM related programing */
70};
71
72/* Utility structures for using mixer control of type snd_soc_bytes */
73#define TEGRA_SOC_BYTES_EXT(xname, xbase, xregs, xshift, xmask,		\
74			    xhandler_get, xhandler_put, xinfo)		\
75{									\
76	.iface	= SNDRV_CTL_ELEM_IFACE_MIXER,				\
77	.name	= xname,						\
78	.info	= xinfo,						\
79	.get	= xhandler_get,						\
80	.put	= xhandler_put,						\
81	.private_value = ((unsigned long)&(struct tegra_soc_bytes)	\
82	{								\
83		.soc.base	= xbase,				\
84		.soc.num_regs	= xregs,				\
85		.soc.mask	= xmask,				\
86		.shift		= xshift				\
87	})								\
88}
89
90#endif
91