1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 *		http://www.samsung.com
5 *
6 * Samsung I2S driver's register header
7 */
8
9#ifndef __SND_SOC_SAMSUNG_I2S_REGS_H
10#define __SND_SOC_SAMSUNG_I2S_REGS_H
11
12#define I2SCON		0x0
13#define I2SMOD		0x4
14#define I2SFIC		0x8
15#define I2SPSR		0xc
16#define I2STXD		0x10
17#define I2SRXD		0x14
18#define I2SFICS		0x18
19#define I2STXDS		0x1c
20#define I2SAHB		0x20
21#define I2SSTR0		0x24
22#define I2SSIZE		0x28
23#define I2STRNCNT	0x2c
24#define I2SLVL0ADDR	0x30
25#define I2SLVL1ADDR	0x34
26#define I2SLVL2ADDR	0x38
27#define I2SLVL3ADDR	0x3c
28#define I2SSTR1		0x40
29#define I2SVER		0x44
30#define I2SFIC1		0x48
31#define I2STDM		0x4c
32#define I2SFSTA		0x50
33
34#define CON_RSTCLR		(1 << 31)
35#define CON_FRXOFSTATUS		(1 << 26)
36#define CON_FRXORINTEN		(1 << 25)
37#define CON_FTXSURSTAT		(1 << 24)
38#define CON_FTXSURINTEN		(1 << 23)
39#define CON_TXSDMA_PAUSE	(1 << 20)
40#define CON_TXSDMA_ACTIVE	(1 << 18)
41
42#define CON_FTXURSTATUS		(1 << 17)
43#define CON_FTXURINTEN		(1 << 16)
44#define CON_TXFIFO2_EMPTY	(1 << 15)
45#define CON_TXFIFO1_EMPTY	(1 << 14)
46#define CON_TXFIFO2_FULL	(1 << 13)
47#define CON_TXFIFO1_FULL	(1 << 12)
48
49#define CON_LRINDEX		(1 << 11)
50#define CON_TXFIFO_EMPTY	(1 << 10)
51#define CON_RXFIFO_EMPTY	(1 << 9)
52#define CON_TXFIFO_FULL		(1 << 8)
53#define CON_RXFIFO_FULL		(1 << 7)
54#define CON_TXDMA_PAUSE		(1 << 6)
55#define CON_RXDMA_PAUSE		(1 << 5)
56#define CON_TXCH_PAUSE		(1 << 4)
57#define CON_RXCH_PAUSE		(1 << 3)
58#define CON_TXDMA_ACTIVE	(1 << 2)
59#define CON_RXDMA_ACTIVE	(1 << 1)
60#define CON_ACTIVE		(1 << 0)
61
62#define MOD_OPCLK_SHIFT		30
63#define MOD_OPCLK_CDCLK_OUT	(0 << MOD_OPCLK_SHIFT)
64#define MOD_OPCLK_CDCLK_IN	(1 << MOD_OPCLK_SHIFT)
65#define MOD_OPCLK_BCLK_OUT	(2 << MOD_OPCLK_SHIFT)
66#define MOD_OPCLK_PCLK		(3 << MOD_OPCLK_SHIFT)
67#define MOD_OPCLK_MASK		(3 << MOD_OPCLK_SHIFT)
68#define MOD_TXS_IDMA		(1 << 28) /* Sec_TXFIFO use I-DMA */
69
70#define MOD_BLCS_SHIFT		26
71#define MOD_BLCS_16BIT		(0 << MOD_BLCS_SHIFT)
72#define MOD_BLCS_8BIT		(1 << MOD_BLCS_SHIFT)
73#define MOD_BLCS_24BIT		(2 << MOD_BLCS_SHIFT)
74#define MOD_BLCS_MASK		(3 << MOD_BLCS_SHIFT)
75#define MOD_BLCP_SHIFT		24
76#define MOD_BLCP_16BIT		(0 << MOD_BLCP_SHIFT)
77#define MOD_BLCP_8BIT		(1 << MOD_BLCP_SHIFT)
78#define MOD_BLCP_24BIT		(2 << MOD_BLCP_SHIFT)
79#define MOD_BLCP_MASK		(3 << MOD_BLCP_SHIFT)
80
81#define MOD_C2DD_HHALF		(1 << 21) /* Discard Higher-half */
82#define MOD_C2DD_LHALF		(1 << 20) /* Discard Lower-half */
83#define MOD_C1DD_HHALF		(1 << 19)
84#define MOD_C1DD_LHALF		(1 << 18)
85#define MOD_DC2_EN		(1 << 17)
86#define MOD_DC1_EN		(1 << 16)
87#define MOD_BLC_16BIT		(0 << 13)
88#define MOD_BLC_8BIT		(1 << 13)
89#define MOD_BLC_24BIT		(2 << 13)
90#define MOD_BLC_MASK		(3 << 13)
91
92#define MOD_TXONLY		(0 << 8)
93#define MOD_RXONLY		(1 << 8)
94#define MOD_TXRX		(2 << 8)
95#define MOD_MASK		(3 << 8)
96#define MOD_LRP_SHIFT		7
97#define MOD_LR_LLOW		0
98#define MOD_LR_RLOW		1
99#define MOD_SDF_SHIFT		5
100#define MOD_SDF_IIS		0
101#define MOD_SDF_MSB		1
102#define MOD_SDF_LSB		2
103#define MOD_SDF_MASK		3
104#define MOD_RCLK_SHIFT		3
105#define MOD_RCLK_256FS		0
106#define MOD_RCLK_512FS		1
107#define MOD_RCLK_384FS		2
108#define MOD_RCLK_768FS		3
109#define MOD_RCLK_MASK		3
110#define MOD_BCLK_SHIFT		1
111#define MOD_BCLK_32FS		0
112#define MOD_BCLK_48FS		1
113#define MOD_BCLK_16FS		2
114#define MOD_BCLK_24FS		3
115#define MOD_BCLK_MASK		3
116#define MOD_8BIT		(1 << 0)
117
118#define EXYNOS5420_MOD_LRP_SHIFT	15
119#define EXYNOS5420_MOD_SDF_SHIFT	6
120#define EXYNOS5420_MOD_RCLK_SHIFT	4
121#define EXYNOS5420_MOD_BCLK_SHIFT	0
122#define EXYNOS5420_MOD_BCLK_64FS	4
123#define EXYNOS5420_MOD_BCLK_96FS	5
124#define EXYNOS5420_MOD_BCLK_128FS	6
125#define EXYNOS5420_MOD_BCLK_192FS	7
126#define EXYNOS5420_MOD_BCLK_256FS	8
127#define EXYNOS5420_MOD_BCLK_MASK	0xf
128
129#define EXYNOS7_MOD_RCLK_64FS	4
130#define EXYNOS7_MOD_RCLK_128FS	5
131#define EXYNOS7_MOD_RCLK_96FS	6
132#define EXYNOS7_MOD_RCLK_192FS	7
133
134#define PSR_PSREN		(1 << 15)
135#define PSR_PSVAL(x)		((((x) - 1) << 8) & 0x3f00)
136
137#define FIC_TX2COUNT(x)		(((x) >>  24) & 0xf)
138#define FIC_TX1COUNT(x)		(((x) >>  16) & 0xf)
139
140#define FIC_TXFLUSH		(1 << 15)
141#define FIC_RXFLUSH		(1 << 7)
142
143#define FIC_TXCOUNT(x)		(((x) >>  8) & 0xf)
144#define FIC_RXCOUNT(x)		(((x) >>  0) & 0xf)
145#define FICS_TXCOUNT(x)		(((x) >>  8) & 0x7f)
146
147#define AHB_INTENLVL0		(1 << 24)
148#define AHB_LVL0INT		(1 << 20)
149#define AHB_CLRLVL0INT		(1 << 16)
150#define AHB_DMARLD		(1 << 5)
151#define AHB_INTMASK		(1 << 3)
152#define AHB_DMAEN		(1 << 0)
153#define AHB_LVLINTMASK		(0xf << 20)
154
155#define I2SSIZE_TRNMSK		(0xffff)
156#define I2SSIZE_SHIFT		(16)
157
158#endif /* __SND_SOC_SAMSUNG_I2S_REGS_H */
159