1275970Scy/* SPDX-License-Identifier: GPL-2.0 */ 2275970Scy/* 3275970Scy * Mediatek MT8192 audio driver interconnection definition 4275970Scy * 5275970Scy * Copyright (c) 2020 MediaTek Inc. 6275970Scy * Author: Shane Chien <shane.chien@mediatek.com> 7275970Scy */ 8275970Scy 9275970Scy#ifndef _MT8192_INTERCONNECTION_H_ 10275970Scy#define _MT8192_INTERCONNECTION_H_ 11275970Scy 12275970Scy/* in port define */ 13275970Scy#define I_I2S0_CH1 0 14275970Scy#define I_I2S0_CH2 1 15275970Scy#define I_ADDA_UL_CH1 3 16275970Scy#define I_ADDA_UL_CH2 4 17275970Scy#define I_DL1_CH1 5 18275970Scy#define I_DL1_CH2 6 19275970Scy#define I_DL2_CH1 7 20275970Scy#define I_DL2_CH2 8 21275970Scy#define I_PCM_1_CAP_CH1 9 22275970Scy#define I_GAIN1_OUT_CH1 10 23275970Scy#define I_GAIN1_OUT_CH2 11 24275970Scy#define I_GAIN2_OUT_CH1 12 25275970Scy#define I_GAIN2_OUT_CH2 13 26275970Scy#define I_PCM_2_CAP_CH1 14 27275970Scy#define I_ADDA_UL_CH3 17 28275970Scy#define I_ADDA_UL_CH4 18 29275970Scy#define I_DL12_CH1 19 30275970Scy#define I_DL12_CH2 20 31275970Scy#define I_PCM_2_CAP_CH2 21 32275970Scy#define I_PCM_1_CAP_CH2 22 33275970Scy#define I_DL3_CH1 23 34275970Scy#define I_DL3_CH2 24 35275970Scy#define I_I2S2_CH1 25 36310419Sdelphij#define I_I2S2_CH2 26 37275970Scy#define I_I2S2_CH3 27 38310419Sdelphij#define I_I2S2_CH4 28 39275970Scy 40275970Scy/* in port define >= 32 */ 41275970Scy#define I_32_OFFSET 32 42275970Scy#define I_CONNSYS_I2S_CH1 (34 - I_32_OFFSET) 43275970Scy#define I_CONNSYS_I2S_CH2 (35 - I_32_OFFSET) 44275970Scy#define I_SRC_1_OUT_CH1 (36 - I_32_OFFSET) 45275970Scy#define I_SRC_1_OUT_CH2 (37 - I_32_OFFSET) 46275970Scy#define I_SRC_2_OUT_CH1 (38 - I_32_OFFSET) 47275970Scy#define I_SRC_2_OUT_CH2 (39 - I_32_OFFSET) 48275970Scy#define I_DL4_CH1 (40 - I_32_OFFSET) 49275970Scy#define I_DL4_CH2 (41 - I_32_OFFSET) 50275970Scy#define I_DL5_CH1 (42 - I_32_OFFSET) 51275970Scy#define I_DL5_CH2 (43 - I_32_OFFSET) 52275970Scy#define I_DL6_CH1 (44 - I_32_OFFSET) 53275970Scy#define I_DL6_CH2 (45 - I_32_OFFSET) 54275970Scy#define I_DL7_CH1 (46 - I_32_OFFSET) 55275970Scy#define I_DL7_CH2 (47 - I_32_OFFSET) 56275970Scy#define I_DL8_CH1 (48 - I_32_OFFSET) 57275970Scy#define I_DL8_CH2 (49 - I_32_OFFSET) 58275970Scy#define I_DL9_CH1 (50 - I_32_OFFSET) 59275970Scy#define I_DL9_CH2 (51 - I_32_OFFSET) 60275970Scy#define I_I2S6_CH1 (52 - I_32_OFFSET) 61275970Scy#define I_I2S6_CH2 (53 - I_32_OFFSET) 62275970Scy#define I_I2S8_CH1 (54 - I_32_OFFSET) 63275970Scy#define I_I2S8_CH2 (55 - I_32_OFFSET) 64275970Scy 65275970Scy#endif 66275970Scy