1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * cht-bsw-rt5645.c - ASoc Machine driver for Intel Cherryview-based platforms 4 * Cherrytrail and Braswell, with RT5645 codec. 5 * 6 * Copyright (C) 2015 Intel Corp 7 * Author: Fang, Yang A <yang.a.fang@intel.com> 8 * N,Harshapriya <harshapriya.n@intel.com> 9 * This file is modified from cht_bsw_rt5672.c 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 */ 14 15#include <linux/module.h> 16#include <linux/platform_device.h> 17#include <linux/acpi.h> 18#include <linux/clk.h> 19#include <linux/dmi.h> 20#include <linux/slab.h> 21#include <sound/pcm.h> 22#include <sound/pcm_params.h> 23#include <sound/soc.h> 24#include <sound/jack.h> 25#include <sound/soc-acpi.h> 26#include "../../codecs/rt5645.h" 27#include "../atom/sst-atom-controls.h" 28#include "../common/soc-intel-quirks.h" 29 30#define CHT_PLAT_CLK_3_HZ 19200000 31#define CHT_CODEC_DAI1 "rt5645-aif1" 32#define CHT_CODEC_DAI2 "rt5645-aif2" 33 34struct cht_acpi_card { 35 char *codec_id; 36 int codec_type; 37 struct snd_soc_card *soc_card; 38}; 39 40struct cht_mc_private { 41 struct snd_soc_jack jack; 42 struct cht_acpi_card *acpi_card; 43 struct clk *mclk; 44}; 45 46#define CHT_RT5645_MAP(quirk) ((quirk) & GENMASK(7, 0)) 47#define CHT_RT5645_SSP2_AIF2 BIT(16) /* default is using AIF1 */ 48#define CHT_RT5645_SSP0_AIF1 BIT(17) 49#define CHT_RT5645_SSP0_AIF2 BIT(18) 50#define CHT_RT5645_PMC_PLT_CLK_0 BIT(19) 51 52static unsigned long cht_rt5645_quirk = 0; 53 54static void log_quirks(struct device *dev) 55{ 56 if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) 57 dev_info(dev, "quirk SSP2_AIF2 enabled"); 58 if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) 59 dev_info(dev, "quirk SSP0_AIF1 enabled"); 60 if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2) 61 dev_info(dev, "quirk SSP0_AIF2 enabled"); 62 if (cht_rt5645_quirk & CHT_RT5645_PMC_PLT_CLK_0) 63 dev_info(dev, "quirk PMC_PLT_CLK_0 enabled"); 64} 65 66static int platform_clock_control(struct snd_soc_dapm_widget *w, 67 struct snd_kcontrol *k, int event) 68{ 69 struct snd_soc_dapm_context *dapm = w->dapm; 70 struct snd_soc_card *card = dapm->card; 71 struct snd_soc_dai *codec_dai; 72 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 73 int ret; 74 75 codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI1); 76 if (!codec_dai) 77 codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI2); 78 79 if (!codec_dai) { 80 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); 81 return -EIO; 82 } 83 84 if (SND_SOC_DAPM_EVENT_ON(event)) { 85 ret = clk_prepare_enable(ctx->mclk); 86 if (ret < 0) { 87 dev_err(card->dev, 88 "could not configure MCLK state"); 89 return ret; 90 } 91 } else { 92 /* Set codec sysclk source to its internal clock because codec PLL will 93 * be off when idle and MCLK will also be off when codec is 94 * runtime suspended. Codec needs clock for jack detection and button 95 * press. MCLK is turned off with clock framework or ACPI. 96 */ 97 ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_RCCLK, 98 48000 * 512, SND_SOC_CLOCK_IN); 99 if (ret < 0) { 100 dev_err(card->dev, "can't set codec sysclk: %d\n", ret); 101 return ret; 102 } 103 104 clk_disable_unprepare(ctx->mclk); 105 } 106 107 return 0; 108} 109 110static const struct snd_soc_dapm_widget cht_dapm_widgets[] = { 111 SND_SOC_DAPM_HP("Headphone", NULL), 112 SND_SOC_DAPM_MIC("Headset Mic", NULL), 113 SND_SOC_DAPM_MIC("Int Mic", NULL), 114 SND_SOC_DAPM_MIC("Int Analog Mic", NULL), 115 SND_SOC_DAPM_SPK("Ext Spk", NULL), 116 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0, 117 platform_clock_control, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 118}; 119 120static const struct snd_soc_dapm_route cht_rt5645_audio_map[] = { 121 {"IN1P", NULL, "Headset Mic"}, 122 {"IN1N", NULL, "Headset Mic"}, 123 {"DMIC L1", NULL, "Int Mic"}, 124 {"DMIC R1", NULL, "Int Mic"}, 125 {"IN2P", NULL, "Int Analog Mic"}, 126 {"IN2N", NULL, "Int Analog Mic"}, 127 {"Headphone", NULL, "HPOL"}, 128 {"Headphone", NULL, "HPOR"}, 129 {"Ext Spk", NULL, "SPOL"}, 130 {"Ext Spk", NULL, "SPOR"}, 131 {"Headphone", NULL, "Platform Clock"}, 132 {"Headset Mic", NULL, "Platform Clock"}, 133 {"Int Mic", NULL, "Platform Clock"}, 134 {"Int Analog Mic", NULL, "Platform Clock"}, 135 {"Int Analog Mic", NULL, "micbias1"}, 136 {"Int Analog Mic", NULL, "micbias2"}, 137 {"Ext Spk", NULL, "Platform Clock"}, 138}; 139 140static const struct snd_soc_dapm_route cht_rt5650_audio_map[] = { 141 {"IN1P", NULL, "Headset Mic"}, 142 {"IN1N", NULL, "Headset Mic"}, 143 {"DMIC L2", NULL, "Int Mic"}, 144 {"DMIC R2", NULL, "Int Mic"}, 145 {"Headphone", NULL, "HPOL"}, 146 {"Headphone", NULL, "HPOR"}, 147 {"Ext Spk", NULL, "SPOL"}, 148 {"Ext Spk", NULL, "SPOR"}, 149 {"Headphone", NULL, "Platform Clock"}, 150 {"Headset Mic", NULL, "Platform Clock"}, 151 {"Int Mic", NULL, "Platform Clock"}, 152 {"Ext Spk", NULL, "Platform Clock"}, 153}; 154 155static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif1_map[] = { 156 {"AIF1 Playback", NULL, "ssp2 Tx"}, 157 {"ssp2 Tx", NULL, "codec_out0"}, 158 {"ssp2 Tx", NULL, "codec_out1"}, 159 {"codec_in0", NULL, "ssp2 Rx" }, 160 {"codec_in1", NULL, "ssp2 Rx" }, 161 {"ssp2 Rx", NULL, "AIF1 Capture"}, 162}; 163 164static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif2_map[] = { 165 {"AIF2 Playback", NULL, "ssp2 Tx"}, 166 {"ssp2 Tx", NULL, "codec_out0"}, 167 {"ssp2 Tx", NULL, "codec_out1"}, 168 {"codec_in0", NULL, "ssp2 Rx" }, 169 {"codec_in1", NULL, "ssp2 Rx" }, 170 {"ssp2 Rx", NULL, "AIF2 Capture"}, 171}; 172 173static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif1_map[] = { 174 {"AIF1 Playback", NULL, "ssp0 Tx"}, 175 {"ssp0 Tx", NULL, "modem_out"}, 176 {"modem_in", NULL, "ssp0 Rx" }, 177 {"ssp0 Rx", NULL, "AIF1 Capture"}, 178}; 179 180static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif2_map[] = { 181 {"AIF2 Playback", NULL, "ssp0 Tx"}, 182 {"ssp0 Tx", NULL, "modem_out"}, 183 {"modem_in", NULL, "ssp0 Rx" }, 184 {"ssp0 Rx", NULL, "AIF2 Capture"}, 185}; 186 187static const struct snd_kcontrol_new cht_mc_controls[] = { 188 SOC_DAPM_PIN_SWITCH("Headphone"), 189 SOC_DAPM_PIN_SWITCH("Headset Mic"), 190 SOC_DAPM_PIN_SWITCH("Int Mic"), 191 SOC_DAPM_PIN_SWITCH("Int Analog Mic"), 192 SOC_DAPM_PIN_SWITCH("Ext Spk"), 193}; 194 195static struct snd_soc_jack_pin cht_bsw_jack_pins[] = { 196 { 197 .pin = "Headphone", 198 .mask = SND_JACK_HEADPHONE, 199 }, 200 { 201 .pin = "Headset Mic", 202 .mask = SND_JACK_MICROPHONE, 203 }, 204}; 205 206static int cht_aif1_hw_params(struct snd_pcm_substream *substream, 207 struct snd_pcm_hw_params *params) 208{ 209 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 210 struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0); 211 int ret; 212 213 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ 214 ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK, 215 CHT_PLAT_CLK_3_HZ, params_rate(params) * 512); 216 if (ret < 0) { 217 dev_err(rtd->dev, "can't set codec pll: %d\n", ret); 218 return ret; 219 } 220 221 ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1, 222 params_rate(params) * 512, SND_SOC_CLOCK_IN); 223 if (ret < 0) { 224 dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret); 225 return ret; 226 } 227 228 return 0; 229} 230 231static int cht_rt5645_quirk_cb(const struct dmi_system_id *id) 232{ 233 cht_rt5645_quirk = (unsigned long)id->driver_data; 234 return 1; 235} 236 237static const struct dmi_system_id cht_rt5645_quirk_table[] = { 238 { 239 /* Strago family Chromebooks */ 240 .callback = cht_rt5645_quirk_cb, 241 .matches = { 242 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 243 }, 244 .driver_data = (void *)CHT_RT5645_PMC_PLT_CLK_0, 245 }, 246 { 247 }, 248}; 249 250static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) 251{ 252 struct snd_soc_card *card = runtime->card; 253 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card); 254 struct snd_soc_component *component = snd_soc_rtd_to_codec(runtime, 0)->component; 255 int jack_type; 256 int ret; 257 258 if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) || 259 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) { 260 /* Select clk_i2s2_asrc as ASRC clock source */ 261 rt5645_sel_asrc_clk_src(component, 262 RT5645_DA_STEREO_FILTER | 263 RT5645_DA_MONO_L_FILTER | 264 RT5645_DA_MONO_R_FILTER | 265 RT5645_AD_STEREO_FILTER, 266 RT5645_CLK_SEL_I2S2_ASRC); 267 } else { 268 /* Select clk_i2s1_asrc as ASRC clock source */ 269 rt5645_sel_asrc_clk_src(component, 270 RT5645_DA_STEREO_FILTER | 271 RT5645_DA_MONO_L_FILTER | 272 RT5645_DA_MONO_R_FILTER | 273 RT5645_AD_STEREO_FILTER, 274 RT5645_CLK_SEL_I2S1_ASRC); 275 } 276 277 if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) { 278 ret = snd_soc_dapm_add_routes(&card->dapm, 279 cht_rt5645_ssp2_aif2_map, 280 ARRAY_SIZE(cht_rt5645_ssp2_aif2_map)); 281 } else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) { 282 ret = snd_soc_dapm_add_routes(&card->dapm, 283 cht_rt5645_ssp0_aif1_map, 284 ARRAY_SIZE(cht_rt5645_ssp0_aif1_map)); 285 } else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2) { 286 ret = snd_soc_dapm_add_routes(&card->dapm, 287 cht_rt5645_ssp0_aif2_map, 288 ARRAY_SIZE(cht_rt5645_ssp0_aif2_map)); 289 } else { 290 ret = snd_soc_dapm_add_routes(&card->dapm, 291 cht_rt5645_ssp2_aif1_map, 292 ARRAY_SIZE(cht_rt5645_ssp2_aif1_map)); 293 } 294 if (ret) 295 return ret; 296 297 if (ctx->acpi_card->codec_type == CODEC_TYPE_RT5650) 298 jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE | 299 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 300 SND_JACK_BTN_2 | SND_JACK_BTN_3; 301 else 302 jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE; 303 304 ret = snd_soc_card_jack_new_pins(runtime->card, "Headset", jack_type, 305 &ctx->jack, cht_bsw_jack_pins, 306 ARRAY_SIZE(cht_bsw_jack_pins)); 307 if (ret) { 308 dev_err(runtime->dev, "Headset jack creation failed %d\n", ret); 309 return ret; 310 } 311 312 rt5645_set_jack_detect(component, &ctx->jack, &ctx->jack, &ctx->jack); 313 314 315 /* 316 * The firmware might enable the clock at 317 * boot (this information may or may not 318 * be reflected in the enable clock register). 319 * To change the rate we must disable the clock 320 * first to cover these cases. Due to common 321 * clock framework restrictions that do not allow 322 * to disable a clock that has not been enabled, 323 * we need to enable the clock first. 324 */ 325 ret = clk_prepare_enable(ctx->mclk); 326 if (!ret) 327 clk_disable_unprepare(ctx->mclk); 328 329 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); 330 331 if (ret) 332 dev_err(runtime->dev, "unable to set MCLK rate\n"); 333 334 return ret; 335} 336 337static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd, 338 struct snd_pcm_hw_params *params) 339{ 340 int ret; 341 struct snd_interval *rate = hw_param_interval(params, 342 SNDRV_PCM_HW_PARAM_RATE); 343 struct snd_interval *channels = hw_param_interval(params, 344 SNDRV_PCM_HW_PARAM_CHANNELS); 345 346 /* The DSP will convert the FE rate to 48k, stereo, 24bits */ 347 rate->min = rate->max = 48000; 348 channels->min = channels->max = 2; 349 350 if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) || 351 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) { 352 353 /* set SSP0 to 16-bit */ 354 params_set_format(params, SNDRV_PCM_FORMAT_S16_LE); 355 356 /* 357 * Default mode for SSP configuration is TDM 4 slot, override config 358 * with explicit setting to I2S 2ch 16-bit. The word length is set with 359 * dai_set_tdm_slot() since there is no other API exposed 360 */ 361 ret = snd_soc_dai_set_fmt(snd_soc_rtd_to_cpu(rtd, 0), 362 SND_SOC_DAIFMT_I2S | 363 SND_SOC_DAIFMT_NB_NF | 364 SND_SOC_DAIFMT_BP_FP 365 ); 366 if (ret < 0) { 367 dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret); 368 return ret; 369 } 370 371 ret = snd_soc_dai_set_fmt(snd_soc_rtd_to_codec(rtd, 0), 372 SND_SOC_DAIFMT_I2S | 373 SND_SOC_DAIFMT_NB_NF | 374 SND_SOC_DAIFMT_BC_FC 375 ); 376 if (ret < 0) { 377 dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret); 378 return ret; 379 } 380 381 ret = snd_soc_dai_set_tdm_slot(snd_soc_rtd_to_cpu(rtd, 0), 0x3, 0x3, 2, 16); 382 if (ret < 0) { 383 dev_err(rtd->dev, "can't set I2S config, err %d\n", ret); 384 return ret; 385 } 386 387 } else { 388 389 /* set SSP2 to 24-bit */ 390 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE); 391 392 /* 393 * Default mode for SSP configuration is TDM 4 slot 394 */ 395 ret = snd_soc_dai_set_fmt(snd_soc_rtd_to_codec(rtd, 0), 396 SND_SOC_DAIFMT_DSP_B | 397 SND_SOC_DAIFMT_IB_NF | 398 SND_SOC_DAIFMT_BC_FC); 399 if (ret < 0) { 400 dev_err(rtd->dev, "can't set format to TDM %d\n", ret); 401 return ret; 402 } 403 404 /* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */ 405 ret = snd_soc_dai_set_tdm_slot(snd_soc_rtd_to_codec(rtd, 0), 0xF, 0xF, 4, 24); 406 if (ret < 0) { 407 dev_err(rtd->dev, "can't set codec TDM slot %d\n", ret); 408 return ret; 409 } 410 } 411 return 0; 412} 413 414static int cht_aif1_startup(struct snd_pcm_substream *substream) 415{ 416 return snd_pcm_hw_constraint_single(substream->runtime, 417 SNDRV_PCM_HW_PARAM_RATE, 48000); 418} 419 420static const struct snd_soc_ops cht_aif1_ops = { 421 .startup = cht_aif1_startup, 422}; 423 424static const struct snd_soc_ops cht_be_ssp2_ops = { 425 .hw_params = cht_aif1_hw_params, 426}; 427 428SND_SOC_DAILINK_DEF(dummy, 429 DAILINK_COMP_ARRAY(COMP_DUMMY())); 430 431SND_SOC_DAILINK_DEF(media, 432 DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai"))); 433 434SND_SOC_DAILINK_DEF(deepbuffer, 435 DAILINK_COMP_ARRAY(COMP_CPU("deepbuffer-cpu-dai"))); 436 437SND_SOC_DAILINK_DEF(ssp2_port, 438 DAILINK_COMP_ARRAY(COMP_CPU("ssp2-port"))); 439SND_SOC_DAILINK_DEF(ssp2_codec, 440 DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5645:00", "rt5645-aif1"))); 441 442SND_SOC_DAILINK_DEF(platform, 443 DAILINK_COMP_ARRAY(COMP_PLATFORM("sst-mfld-platform"))); 444 445static struct snd_soc_dai_link cht_dailink[] = { 446 [MERR_DPCM_AUDIO] = { 447 .name = "Audio Port", 448 .stream_name = "Audio", 449 .nonatomic = true, 450 .dynamic = 1, 451 .dpcm_playback = 1, 452 .dpcm_capture = 1, 453 .ops = &cht_aif1_ops, 454 SND_SOC_DAILINK_REG(media, dummy, platform), 455 }, 456 [MERR_DPCM_DEEP_BUFFER] = { 457 .name = "Deep-Buffer Audio Port", 458 .stream_name = "Deep-Buffer Audio", 459 .nonatomic = true, 460 .dynamic = 1, 461 .dpcm_playback = 1, 462 .ops = &cht_aif1_ops, 463 SND_SOC_DAILINK_REG(deepbuffer, dummy, platform), 464 }, 465 /* CODEC<->CODEC link */ 466 /* back ends */ 467 { 468 .name = "SSP2-Codec", 469 .id = 0, 470 .no_pcm = 1, 471 .init = cht_codec_init, 472 .be_hw_params_fixup = cht_codec_fixup, 473 .dpcm_playback = 1, 474 .dpcm_capture = 1, 475 .ops = &cht_be_ssp2_ops, 476 SND_SOC_DAILINK_REG(ssp2_port, ssp2_codec, platform), 477 }, 478}; 479 480/* use space before codec name to simplify card ID, and simplify driver name */ 481#define SOF_CARD_RT5645_NAME "bytcht rt5645" /* card name 'sof-bytcht rt5645' */ 482#define SOF_CARD_RT5650_NAME "bytcht rt5650" /* card name 'sof-bytcht rt5650' */ 483#define SOF_DRIVER_NAME "SOF" 484 485#define CARD_RT5645_NAME "chtrt5645" 486#define CARD_RT5650_NAME "chtrt5650" 487#define DRIVER_NAME NULL /* card name will be used for driver name */ 488 489/* SoC card */ 490static struct snd_soc_card snd_soc_card_chtrt5645 = { 491 .owner = THIS_MODULE, 492 .dai_link = cht_dailink, 493 .num_links = ARRAY_SIZE(cht_dailink), 494 .dapm_widgets = cht_dapm_widgets, 495 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets), 496 .dapm_routes = cht_rt5645_audio_map, 497 .num_dapm_routes = ARRAY_SIZE(cht_rt5645_audio_map), 498 .controls = cht_mc_controls, 499 .num_controls = ARRAY_SIZE(cht_mc_controls), 500}; 501 502static struct snd_soc_card snd_soc_card_chtrt5650 = { 503 .owner = THIS_MODULE, 504 .dai_link = cht_dailink, 505 .num_links = ARRAY_SIZE(cht_dailink), 506 .dapm_widgets = cht_dapm_widgets, 507 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets), 508 .dapm_routes = cht_rt5650_audio_map, 509 .num_dapm_routes = ARRAY_SIZE(cht_rt5650_audio_map), 510 .controls = cht_mc_controls, 511 .num_controls = ARRAY_SIZE(cht_mc_controls), 512}; 513 514static struct cht_acpi_card snd_soc_cards[] = { 515 {"10EC5640", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645}, 516 {"10EC5645", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645}, 517 {"10EC5648", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645}, 518 {"10EC3270", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645}, 519 {"10EC5650", CODEC_TYPE_RT5650, &snd_soc_card_chtrt5650}, 520}; 521 522static char cht_rt5645_codec_name[SND_ACPI_I2C_ID_LEN]; 523 524struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */ 525 u64 aif_value; /* 1: AIF1, 2: AIF2 */ 526 u64 mclock_value; /* usually 25MHz (0x17d7940), ignored */ 527}; 528 529static int snd_cht_mc_probe(struct platform_device *pdev) 530{ 531 struct snd_soc_card *card = snd_soc_cards[0].soc_card; 532 struct snd_soc_acpi_mach *mach; 533 const char *platform_name; 534 struct cht_mc_private *drv; 535 struct acpi_device *adev; 536 struct device *codec_dev; 537 bool sof_parent; 538 bool found = false; 539 bool is_bytcr = false; 540 int dai_index = 0; 541 int ret_val = 0; 542 int i; 543 const char *mclk_name; 544 545 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); 546 if (!drv) 547 return -ENOMEM; 548 549 mach = pdev->dev.platform_data; 550 551 for (i = 0; i < ARRAY_SIZE(snd_soc_cards); i++) { 552 if (acpi_dev_found(snd_soc_cards[i].codec_id) && 553 (!strncmp(snd_soc_cards[i].codec_id, mach->id, 8))) { 554 dev_dbg(&pdev->dev, 555 "found codec %s\n", snd_soc_cards[i].codec_id); 556 card = snd_soc_cards[i].soc_card; 557 drv->acpi_card = &snd_soc_cards[i]; 558 found = true; 559 break; 560 } 561 } 562 563 if (!found) { 564 dev_err(&pdev->dev, "No matching HID found in supported list\n"); 565 return -ENODEV; 566 } 567 568 card->dev = &pdev->dev; 569 570 /* set correct codec name */ 571 for (i = 0; i < ARRAY_SIZE(cht_dailink); i++) 572 if (cht_dailink[i].codecs->name && 573 !strcmp(cht_dailink[i].codecs->name, 574 "i2c-10EC5645:00")) { 575 dai_index = i; 576 break; 577 } 578 579 /* fixup codec name based on HID */ 580 adev = acpi_dev_get_first_match_dev(mach->id, NULL, -1); 581 if (adev) { 582 snprintf(cht_rt5645_codec_name, sizeof(cht_rt5645_codec_name), 583 "i2c-%s", acpi_dev_name(adev)); 584 cht_dailink[dai_index].codecs->name = cht_rt5645_codec_name; 585 } 586 /* acpi_get_first_physical_node() returns a borrowed ref, no need to deref */ 587 codec_dev = acpi_get_first_physical_node(adev); 588 acpi_dev_put(adev); 589 if (!codec_dev) 590 return -EPROBE_DEFER; 591 592 snd_soc_card_chtrt5645.components = rt5645_components(codec_dev); 593 snd_soc_card_chtrt5650.components = rt5645_components(codec_dev); 594 595 /* 596 * swap SSP0 if bytcr is detected 597 * (will be overridden if DMI quirk is detected) 598 */ 599 if (soc_intel_is_byt()) { 600 if (mach->mach_params.acpi_ipc_irq_index == 0) 601 is_bytcr = true; 602 } 603 604 if (is_bytcr) { 605 /* 606 * Baytrail CR platforms may have CHAN package in BIOS, try 607 * to find relevant routing quirk based as done on Windows 608 * platforms. We have to read the information directly from the 609 * BIOS, at this stage the card is not created and the links 610 * with the codec driver/pdata are non-existent 611 */ 612 613 struct acpi_chan_package chan_package = { 0 }; 614 615 /* format specified: 2 64-bit integers */ 616 struct acpi_buffer format = {sizeof("NN"), "NN"}; 617 struct acpi_buffer state = {0, NULL}; 618 struct snd_soc_acpi_package_context pkg_ctx; 619 bool pkg_found = false; 620 621 state.length = sizeof(chan_package); 622 state.pointer = &chan_package; 623 624 pkg_ctx.name = "CHAN"; 625 pkg_ctx.length = 2; 626 pkg_ctx.format = &format; 627 pkg_ctx.state = &state; 628 pkg_ctx.data_valid = false; 629 630 pkg_found = snd_soc_acpi_find_package_from_hid(mach->id, 631 &pkg_ctx); 632 if (pkg_found) { 633 if (chan_package.aif_value == 1) { 634 dev_info(&pdev->dev, "BIOS Routing: AIF1 connected\n"); 635 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF1; 636 } else if (chan_package.aif_value == 2) { 637 dev_info(&pdev->dev, "BIOS Routing: AIF2 connected\n"); 638 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2; 639 } else { 640 dev_info(&pdev->dev, "BIOS Routing isn't valid, ignored\n"); 641 pkg_found = false; 642 } 643 } 644 645 if (!pkg_found) { 646 /* no BIOS indications, assume SSP0-AIF2 connection */ 647 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2; 648 } 649 } 650 651 /* check quirks before creating card */ 652 dmi_check_system(cht_rt5645_quirk_table); 653 log_quirks(&pdev->dev); 654 655 if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) || 656 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) 657 cht_dailink[dai_index].codecs->dai_name = "rt5645-aif2"; 658 659 if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) || 660 (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) 661 cht_dailink[dai_index].cpus->dai_name = "ssp0-port"; 662 663 /* override platform name, if required */ 664 platform_name = mach->mach_params.platform; 665 666 ret_val = snd_soc_fixup_dai_links_platform_name(card, 667 platform_name); 668 if (ret_val) 669 return ret_val; 670 671 if (cht_rt5645_quirk & CHT_RT5645_PMC_PLT_CLK_0) 672 mclk_name = "pmc_plt_clk_0"; 673 else 674 mclk_name = "pmc_plt_clk_3"; 675 676 drv->mclk = devm_clk_get(&pdev->dev, mclk_name); 677 if (IS_ERR(drv->mclk)) { 678 dev_err(&pdev->dev, "Failed to get MCLK from %s: %ld\n", 679 mclk_name, PTR_ERR(drv->mclk)); 680 return PTR_ERR(drv->mclk); 681 } 682 683 snd_soc_card_set_drvdata(card, drv); 684 685 sof_parent = snd_soc_acpi_sof_parent(&pdev->dev); 686 687 /* set card and driver name */ 688 if (sof_parent) { 689 snd_soc_card_chtrt5645.name = SOF_CARD_RT5645_NAME; 690 snd_soc_card_chtrt5645.driver_name = SOF_DRIVER_NAME; 691 snd_soc_card_chtrt5650.name = SOF_CARD_RT5650_NAME; 692 snd_soc_card_chtrt5650.driver_name = SOF_DRIVER_NAME; 693 } else { 694 snd_soc_card_chtrt5645.name = CARD_RT5645_NAME; 695 snd_soc_card_chtrt5645.driver_name = DRIVER_NAME; 696 snd_soc_card_chtrt5650.name = CARD_RT5650_NAME; 697 snd_soc_card_chtrt5650.driver_name = DRIVER_NAME; 698 } 699 700 /* set pm ops */ 701 if (sof_parent) 702 pdev->dev.driver->pm = &snd_soc_pm_ops; 703 704 ret_val = devm_snd_soc_register_card(&pdev->dev, card); 705 if (ret_val) { 706 dev_err(&pdev->dev, 707 "snd_soc_register_card failed %d\n", ret_val); 708 return ret_val; 709 } 710 platform_set_drvdata(pdev, card); 711 return ret_val; 712} 713 714static struct platform_driver snd_cht_mc_driver = { 715 .driver = { 716 .name = "cht-bsw-rt5645", 717 }, 718 .probe = snd_cht_mc_probe, 719}; 720 721module_platform_driver(snd_cht_mc_driver) 722 723MODULE_DESCRIPTION("ASoC Intel(R) Braswell Machine driver"); 724MODULE_AUTHOR("Fang, Yang A,N,Harshapriya"); 725MODULE_LICENSE("GPL v2"); 726MODULE_ALIAS("platform:cht-bsw-rt5645"); 727