1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright(c) 2021-2022 Intel Corporation. All rights reserved. 4 * 5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com> 6 * Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com> 7 */ 8 9#ifndef __SOUND_SOC_INTEL_AVS_REGS_H 10#define __SOUND_SOC_INTEL_AVS_REGS_H 11 12#include <linux/sizes.h> 13 14#define AZX_PCIREG_PGCTL 0x44 15#define AZX_PCIREG_CGCTL 0x48 16#define AZX_PGCTL_LSRMD_MASK BIT(4) 17#define AZX_CGCTL_MISCBDCGE_MASK BIT(6) 18#define AZX_VS_EM2_L1SEN BIT(13) 19#define AZX_VS_EM2_DUM BIT(23) 20 21/* Intel HD Audio General DSP Registers */ 22#define AVS_ADSP_GEN_BASE 0x0 23#define AVS_ADSP_REG_ADSPCS (AVS_ADSP_GEN_BASE + 0x04) 24#define AVS_ADSP_REG_ADSPIC (AVS_ADSP_GEN_BASE + 0x08) 25#define AVS_ADSP_REG_ADSPIS (AVS_ADSP_GEN_BASE + 0x0C) 26 27#define AVS_ADSP_ADSPIC_IPC BIT(0) 28#define AVS_ADSP_ADSPIC_CLDMA BIT(1) 29#define AVS_ADSP_ADSPIS_IPC BIT(0) 30#define AVS_ADSP_ADSPIS_CLDMA BIT(1) 31 32#define AVS_ADSPCS_CRST_MASK(cm) (cm) 33#define AVS_ADSPCS_CSTALL_MASK(cm) ((cm) << 8) 34#define AVS_ADSPCS_SPA_MASK(cm) ((cm) << 16) 35#define AVS_ADSPCS_CPA_MASK(cm) ((cm) << 24) 36#define AVS_MAIN_CORE_MASK BIT(0) 37 38#define AVS_ADSP_HIPCCTL_BUSY BIT(0) 39#define AVS_ADSP_HIPCCTL_DONE BIT(1) 40 41/* SKL Intel HD Audio Inter-Processor Communication Registers */ 42#define SKL_ADSP_IPC_BASE 0x40 43#define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) 44#define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) 45#define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) 46#define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) 47#define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) 48 49#define SKL_ADSP_HIPCI_BUSY BIT(31) 50#define SKL_ADSP_HIPCIE_DONE BIT(30) 51#define SKL_ADSP_HIPCT_BUSY BIT(31) 52 53/* CNL Intel HD Audio Inter-Processor Communication Registers */ 54#define CNL_ADSP_IPC_BASE 0xC0 55#define CNL_ADSP_REG_HIPCTDR (CNL_ADSP_IPC_BASE + 0x00) 56#define CNL_ADSP_REG_HIPCTDA (CNL_ADSP_IPC_BASE + 0x04) 57#define CNL_ADSP_REG_HIPCTDD (CNL_ADSP_IPC_BASE + 0x08) 58#define CNL_ADSP_REG_HIPCIDR (CNL_ADSP_IPC_BASE + 0x10) 59#define CNL_ADSP_REG_HIPCIDA (CNL_ADSP_IPC_BASE + 0x14) 60#define CNL_ADSP_REG_HIPCIDD (CNL_ADSP_IPC_BASE + 0x18) 61#define CNL_ADSP_REG_HIPCCTL (CNL_ADSP_IPC_BASE + 0x28) 62 63#define CNL_ADSP_HIPCTDR_BUSY BIT(31) 64#define CNL_ADSP_HIPCTDA_DONE BIT(31) 65#define CNL_ADSP_HIPCIDR_BUSY BIT(31) 66#define CNL_ADSP_HIPCIDA_DONE BIT(31) 67 68/* Intel HD Audio SRAM windows base addresses */ 69#define SKL_ADSP_SRAM_BASE_OFFSET 0x8000 70#define SKL_ADSP_SRAM_WINDOW_SIZE 0x2000 71#define APL_ADSP_SRAM_BASE_OFFSET 0x80000 72#define APL_ADSP_SRAM_WINDOW_SIZE 0x20000 73 74/* Constants used when accessing SRAM, space shared with firmware */ 75#define AVS_FW_REG_BASE(adev) ((adev)->spec->sram->base_offset) 76#define AVS_FW_REG_STATUS(adev) (AVS_FW_REG_BASE(adev) + 0x0) 77#define AVS_FW_REG_ERROR_CODE(adev) (AVS_FW_REG_BASE(adev) + 0x4) 78 79#define AVS_WINDOW_CHUNK_SIZE SZ_4K 80#define AVS_FW_REGS_SIZE AVS_WINDOW_CHUNK_SIZE 81#define AVS_FW_REGS_WINDOW 0 82/* DSP -> HOST communication window */ 83#define AVS_UPLINK_WINDOW AVS_FW_REGS_WINDOW 84/* HOST -> DSP communication window */ 85#define AVS_DOWNLINK_WINDOW 1 86#define AVS_DEBUG_WINDOW 2 87 88/* registry I/O helpers */ 89#define avs_sram_offset(adev, window_idx) \ 90 ((adev)->spec->sram->base_offset + \ 91 (adev)->spec->sram->window_size * (window_idx)) 92 93#define avs_sram_addr(adev, window_idx) \ 94 ((adev)->dsp_ba + avs_sram_offset(adev, window_idx)) 95 96#define avs_uplink_addr(adev) \ 97 (avs_sram_addr(adev, AVS_UPLINK_WINDOW) + AVS_FW_REGS_SIZE) 98#define avs_downlink_addr(adev) \ 99 avs_sram_addr(adev, AVS_DOWNLINK_WINDOW) 100 101#endif /* __SOUND_SOC_INTEL_AVS_REGS_H */ 102