1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/sound/soc/hisilicon/hi6210-i2s.h
4 *
5 * Copyright (C) 2015 Linaro, Ltd
6 * Author: Andy Green <andy.green@linaro.org>
7 *
8 * Note at least on 6220, S2 == BT, S1 == Digital FM Radio IF
9 */
10
11#ifndef _HI6210_I2S_H
12#define _HI6210_I2S_H
13
14#define HII2S_SW_RST_N				0
15
16#define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_SHIFT			28
17#define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_MASK			3
18#define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_SHIFT			26
19#define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_MASK			3
20#define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_SHIFT			24
21#define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_MASK			3
22#define HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT				20
23#define HII2S_SW_RST_N__ST_DL_WORDLEN_MASK				3
24#define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_SHIFT			18
25#define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_MASK			3
26#define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_SHIFT			16
27#define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_MASK			3
28
29#define HII2S_SW_RST_N__SW_RST_N					BIT(0)
30
31enum hi6210_bits {
32	HII2S_BITS_16,
33	HII2S_BITS_18,
34	HII2S_BITS_20,
35	HII2S_BITS_24,
36};
37
38
39#define HII2S_IF_CLK_EN_CFG			4
40
41#define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN				BIT(25)
42#define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN				BIT(24)
43#define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN				BIT(20)
44#define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN				BIT(16)
45#define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN				BIT(15)
46#define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN				BIT(14)
47#define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN				BIT(13)
48#define HII2S_IF_CLK_EN_CFG__S2_IL_PGA_EN				BIT(12)
49#define HII2S_IF_CLK_EN_CFG__S1_IR_PGA_EN				BIT(10)
50#define HII2S_IF_CLK_EN_CFG__S1_IL_PGA_EN				BIT(9)
51#define HII2S_IF_CLK_EN_CFG__S1_IF_CLK_EN				BIT(8)
52#define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_SRC_EN				BIT(7)
53#define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_EN				BIT(6)
54#define HII2S_IF_CLK_EN_CFG__ST_DL_R_EN					BIT(5)
55#define HII2S_IF_CLK_EN_CFG__ST_DL_L_EN					BIT(4)
56#define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_R_EN				BIT(3)
57#define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_L_EN				BIT(2)
58#define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_R_EN				BIT(1)
59#define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_L_EN				BIT(0)
60
61#define HII2S_DIG_FILTER_CLK_EN_CFG		8
62#define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN			BIT(30)
63#define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN			BIT(28)
64#define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN			BIT(25)
65#define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN			BIT(24)
66#define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN			BIT(22)
67#define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN			BIT(20)
68#define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN			BIT(17)
69#define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN			BIT(16)
70
71#define HII2S_FS_CFG				0xc
72
73#define HII2S_FS_CFG__FS_S2_SHIFT					28
74#define HII2S_FS_CFG__FS_S2_MASK					7
75#define HII2S_FS_CFG__FS_S1_SHIFT					24
76#define HII2S_FS_CFG__FS_S1_MASK					7
77#define HII2S_FS_CFG__FS_ADCLR_SHIFT					20
78#define HII2S_FS_CFG__FS_ADCLR_MASK					7
79#define HII2S_FS_CFG__FS_DACLR_SHIFT					16
80#define HII2S_FS_CFG__FS_DACLR_MASK					7
81#define HII2S_FS_CFG__FS_ST_DL_R_SHIFT					8
82#define HII2S_FS_CFG__FS_ST_DL_R_MASK					7
83#define HII2S_FS_CFG__FS_ST_DL_L_SHIFT					4
84#define HII2S_FS_CFG__FS_ST_DL_L_MASK					7
85#define HII2S_FS_CFG__FS_VOICE_DLINK_SHIFT				0
86#define HII2S_FS_CFG__FS_VOICE_DLINK_MASK				7
87
88enum hi6210_i2s_rates {
89	HII2S_FS_RATE_8KHZ = 0,
90	HII2S_FS_RATE_16KHZ = 1,
91	HII2S_FS_RATE_32KHZ = 2,
92	HII2S_FS_RATE_48KHZ = 4,
93	HII2S_FS_RATE_96KHZ = 5,
94	HII2S_FS_RATE_192KHZ = 6,
95};
96
97#define HII2S_I2S_CFG				0x10
98
99#define HII2S_I2S_CFG__S2_IF_TX_EN					BIT(31)
100#define HII2S_I2S_CFG__S2_IF_RX_EN					BIT(30)
101#define HII2S_I2S_CFG__S2_FRAME_MODE					BIT(29)
102#define HII2S_I2S_CFG__S2_MST_SLV					BIT(28)
103#define HII2S_I2S_CFG__S2_LRCK_MODE					BIT(27)
104#define HII2S_I2S_CFG__S2_CHNNL_MODE					BIT(26)
105#define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT			24
106#define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK			3
107#define HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT				22
108#define HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK				3
109#define HII2S_I2S_CFG__S2_TX_CLK_SEL					BIT(21)
110#define HII2S_I2S_CFG__S2_RX_CLK_SEL					BIT(20)
111#define HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT				BIT(19)
112#define HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT				16
113#define HII2S_I2S_CFG__S2_FUNC_MODE_MASK				7
114#define HII2S_I2S_CFG__S1_IF_TX_EN					BIT(15)
115#define HII2S_I2S_CFG__S1_IF_RX_EN					BIT(14)
116#define HII2S_I2S_CFG__S1_FRAME_MODE					BIT(13)
117#define HII2S_I2S_CFG__S1_MST_SLV					BIT(12)
118#define HII2S_I2S_CFG__S1_LRCK_MODE					BIT(11)
119#define HII2S_I2S_CFG__S1_CHNNL_MODE					BIT(10)
120#define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_SHIFT			8
121#define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_MASK			3
122#define HII2S_I2S_CFG__S1_DIRECT_LOOP_SHIFT				6
123#define HII2S_I2S_CFG__S1_DIRECT_LOOP_MASK				3
124#define HII2S_I2S_CFG__S1_TX_CLK_SEL					BIT(5)
125#define HII2S_I2S_CFG__S1_RX_CLK_SEL					BIT(4)
126#define HII2S_I2S_CFG__S1_CODEC_DATA_FORMAT				BIT(3)
127#define HII2S_I2S_CFG__S1_FUNC_MODE_SHIFT				0
128#define HII2S_I2S_CFG__S1_FUNC_MODE_MASK				7
129
130enum hi6210_i2s_formats {
131	HII2S_FORMAT_I2S,
132	HII2S_FORMAT_PCM_STD,
133	HII2S_FORMAT_PCM_USER,
134	HII2S_FORMAT_LEFT_JUST,
135	HII2S_FORMAT_RIGHT_JUST,
136};
137
138#define HII2S_DIG_FILTER_MODULE_CFG		0x14
139
140#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_SHIFT		28
141#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_MASK		3
142#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN4_MUTE		BIT(27)
143#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN3_MUTE		BIT(26)
144#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE		BIT(25)
145#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN1_MUTE		BIT(24)
146#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_SHIFT		20
147#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_MASK		3
148#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN4_MUTE		BIT(19)
149#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN3_MUTE		BIT(18)
150#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE		BIT(17)
151#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN1_MUTE		BIT(16)
152#define HII2S_DIG_FILTER_MODULE_CFG__SW_DACR_SDM_DITHER			BIT(9)
153#define HII2S_DIG_FILTER_MODULE_CFG__SW_DACL_SDM_DITHER			BIT(8)
154#define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_SHIFT		4
155#define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_MASK		7
156#define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_SHIFT		0
157#define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_MASK		7
158
159enum hi6210_gains {
160	HII2S_GAIN_100PC,
161	HII2S_GAIN_50PC,
162	HII2S_GAIN_25PC,
163};
164
165#define HII2S_MUX_TOP_MODULE_CFG		0x18
166
167#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_SHIFT		14
168#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_MASK		3
169#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE		BIT(13)
170#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE		BIT(12)
171#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_SHIFT		10
172#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_MASK			3
173#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE			BIT(9)
174#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE			BIT(8)
175#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_RDY				BIT(6)
176#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_SHIFT			4
177#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_MASK			3
178#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_RDY			BIT(3)
179#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_SHIFT		0
180#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_MASK		7
181
182enum hi6210_s2_src_mode {
183	HII2S_S2_SRC_MODE_3,
184	HII2S_S2_SRC_MODE_12,
185	HII2S_S2_SRC_MODE_6,
186	HII2S_S2_SRC_MODE_2,
187};
188
189enum hi6210_voice_dlink_src_mode {
190	HII2S_VOICE_DL_SRC_MODE_12 = 1,
191	HII2S_VOICE_DL_SRC_MODE_6,
192	HII2S_VOICE_DL_SRC_MODE_2,
193	HII2S_VOICE_DL_SRC_MODE_3,
194};
195
196#define HII2S_ADC_PGA_CFG			0x1c
197#define HII2S_S1_INPUT_PGA_CFG			0x20
198#define HII2S_S2_INPUT_PGA_CFG			0x24
199#define HII2S_ST_DL_PGA_CFG			0x28
200#define HII2S_VOICE_SIDETONE_DLINK_PGA_CFG	0x2c
201#define HII2S_APB_AFIFO_CFG_1			0x30
202#define HII2S_APB_AFIFO_CFG_2			0x34
203#define HII2S_ST_DL_FIFO_TH_CFG			0x38
204
205#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT			24
206#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK			0x1f
207#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT			16
208#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK			0x1f
209#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT			8
210#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK			0x1f
211#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT			0
212#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK			0x1f
213
214#define HII2S_STEREO_UPLINK_FIFO_TH_CFG		0x3c
215#define HII2S_VOICE_UPLINK_FIFO_TH_CFG		0x40
216#define HII2S_CODEC_IRQ_MASK			0x44
217#define HII2S_CODEC_IRQ				0x48
218#define HII2S_DACL_AGC_CFG_1			0x4c
219#define HII2S_DACL_AGC_CFG_2			0x50
220#define HII2S_DACR_AGC_CFG_1			0x54
221#define HII2S_DACR_AGC_CFG_2			0x58
222#define HII2S_DMIC_SIF_CFG			0x5c
223#define HII2S_MISC_CFG				0x60
224
225#define HII2S_MISC_CFG__THIRDMD_DLINK_TEST_SEL				BIT(17)
226#define HII2S_MISC_CFG__THIRDMD_DLINK_DIN_SEL				BIT(16)
227#define HII2S_MISC_CFG__S3_DOUT_RIGHT_SEL				BIT(14)
228#define HII2S_MISC_CFG__S3_DOUT_LEFT_SEL				BIT(13)
229#define HII2S_MISC_CFG__S3_DIN_TEST_SEL					BIT(12)
230#define HII2S_MISC_CFG__VOICE_DLINK_SRC_UP_DOUT_VLD_SEL			BIT(8)
231#define HII2S_MISC_CFG__VOICE_DLINK_TEST_SEL				BIT(7)
232#define HII2S_MISC_CFG__VOICE_DLINK_DIN_SEL				BIT(6)
233#define HII2S_MISC_CFG__ST_DL_TEST_SEL					BIT(4)
234#define HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL				BIT(3)
235#define HII2S_MISC_CFG__S2_DOUT_TEST_SEL				BIT(2)
236#define HII2S_MISC_CFG__S1_DOUT_TEST_SEL				BIT(1)
237#define HII2S_MISC_CFG__S2_DOUT_LEFT_SEL				BIT(0)
238
239#define HII2S_S2_SRC_CFG			0x64
240#define HII2S_MEM_CFG				0x68
241#define HII2S_THIRDMD_PCM_PGA_CFG		0x6c
242#define HII2S_THIRD_MODEM_FIFO_TH		0x70
243#define HII2S_S3_ANTI_FREQ_JITTER_TX_INC_CNT	0x74
244#define HII2S_S3_ANTI_FREQ_JITTER_TX_DEC_CNT	0x78
245#define HII2S_S3_ANTI_FREQ_JITTER_RX_INC_CNT	0x7c
246#define HII2S_S3_ANTI_FREQ_JITTER_RX_DEC_CNT	0x80
247#define HII2S_ANTI_FREQ_JITTER_EN		0x84
248#define HII2S_CLK_SEL				0x88
249
250/* 0 = BT owns the i2s */
251#define HII2S_CLK_SEL__I2S_BT_FM_SEL					BIT(0)
252/* 0 = internal source, 1 = ext */
253#define HII2S_CLK_SEL__EXT_12_288MHZ_SEL				BIT(1)
254
255
256#define HII2S_THIRDMD_DLINK_CHANNEL		0xe8
257#define HII2S_THIRDMD_ULINK_CHANNEL		0xec
258#define HII2S_VOICE_DLINK_CHANNEL		0xf0
259
260/* shovel data in here for playback */
261#define HII2S_ST_DL_CHANNEL			0xf4
262#define HII2S_STEREO_UPLINK_CHANNEL		0xf8
263#define HII2S_VOICE_UPLINK_CHANNEL		0xfc
264
265#endif/* _HI6210_I2S_H */
266