1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023, Linaro Ltd. 5 */ 6 7#include <linux/bitfield.h> 8#include <linux/device.h> 9#include <linux/gpio/consumer.h> 10#include <linux/init.h> 11#include <linux/kernel.h> 12#include <linux/module.h> 13#include <linux/pm_runtime.h> 14#include <linux/regmap.h> 15#include <linux/regulator/consumer.h> 16#include <linux/reset.h> 17#include <linux/slab.h> 18#include <linux/soundwire/sdw.h> 19#include <linux/soundwire/sdw_registers.h> 20#include <linux/soundwire/sdw_type.h> 21#include <sound/pcm.h> 22#include <sound/pcm_params.h> 23#include <sound/soc-dapm.h> 24#include <sound/soc.h> 25#include <sound/tlv.h> 26 27#define WSA884X_BASE 0x3000 28#define WSA884X_ANA_BG_TSADC_BASE (WSA884X_BASE + 0x0001) 29#define WSA884X_BG_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x00) 30#define WSA884X_ADC_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x01) 31#define WSA884X_BOP1_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x02) 32#define WSA884X_BOP2_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x03) 33#define WSA884X_BOP2_PROG_BOP2_VTH_MASK 0xf0 34#define WSA884X_BOP2_PROG_BOP2_VTH_SHIFT 4 35#define WSA884X_BOP2_PROG_BOP2_HYST_MASK 0x0f 36#define WSA884X_BOP2_PROG_BOP2_HYST_SHIFT 0 37#define WSA884X_UVLO_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x04) 38#define WSA884X_UVLO_PROG1 (WSA884X_ANA_BG_TSADC_BASE + 0x05) 39#define WSA884X_SPARE_CTRL_0 (WSA884X_ANA_BG_TSADC_BASE + 0x06) 40#define WSA884X_SPARE_CTRL_1 (WSA884X_ANA_BG_TSADC_BASE + 0x07) 41#define WSA884X_SPARE_CTRL_2 (WSA884X_ANA_BG_TSADC_BASE + 0x08) 42#define WSA884X_SPARE_CTRL_3 (WSA884X_ANA_BG_TSADC_BASE + 0x09) 43#define WSA884X_REF_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x0a) 44#define WSA884X_REF_CTRL_BG_RDY_SEL_MASK 0x03 45#define WSA884X_REF_CTRL_BG_RDY_SEL_SHIFT 0 46#define WSA884X_BG_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0b) 47#define WSA884X_BG_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x0c) 48#define WSA884X_ADC_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x0d) 49#define WSA884X_ADC_IREF_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0e) 50#define WSA884X_ADC_ISENS_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0f) 51#define WSA884X_ADC_CLK_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x10) 52#define WSA884X_ADC_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x11) 53#define WSA884X_ADC_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x12) 54#define WSA884X_VBAT_SNS (WSA884X_ANA_BG_TSADC_BASE + 0x13) 55#define WSA884X_DOUT_MSB (WSA884X_ANA_BG_TSADC_BASE + 0x14) 56#define WSA884X_DOUT_LSB (WSA884X_ANA_BG_TSADC_BASE + 0x15) 57#define WSA884X_BOP_ATEST_SEL (WSA884X_ANA_BG_TSADC_BASE + 0x16) 58#define WSA884X_MISC0 (WSA884X_ANA_BG_TSADC_BASE + 0x17) 59#define WSA884X_MISC1 (WSA884X_ANA_BG_TSADC_BASE + 0x18) 60#define WSA884X_MISC2 (WSA884X_ANA_BG_TSADC_BASE + 0x19) 61#define WSA884X_MISC3 (WSA884X_ANA_BG_TSADC_BASE + 0x1a) 62#define WSA884X_SPARE_TSBG_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1b) 63#define WSA884X_SPARE_TUNE_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1c) 64#define WSA884X_SPARE_TUNE_1 (WSA884X_ANA_BG_TSADC_BASE + 0x1d) 65 66#define WSA884X_ANA_IVSENSE_BASE (WSA884X_BASE + 0x0020) 67#define WSA884X_VSENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x00) 68#define WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK 0xe0 69#define WSA884X_VSENSE1_GAIN_VSENSE_FE_SHIFT 5 70#define WSA884X_ISENSE2 (WSA884X_ANA_IVSENSE_BASE + 0x01) 71#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK 0xe0 72#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_SHIFT 5 73 74#define WSA884X_SPARE_CTL_1 (WSA884X_ANA_IVSENSE_BASE + 0x02) 75#define WSA884X_SPARE_CTL_2 (WSA884X_ANA_IVSENSE_BASE + 0x03) 76#define WSA884X_SPARE_CTL_3 (WSA884X_ANA_IVSENSE_BASE + 0x04) 77#define WSA884X_SPARE_CTL_4 (WSA884X_ANA_IVSENSE_BASE + 0x05) 78#define WSA884X_EN (WSA884X_ANA_IVSENSE_BASE + 0x06) 79#define WSA884X_OVERRIDE1 (WSA884X_ANA_IVSENSE_BASE + 0x07) 80#define WSA884X_OVERRIDE2 (WSA884X_ANA_IVSENSE_BASE + 0x08) 81#define WSA884X_ISENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x09) 82#define WSA884X_ISENSE_CAL (WSA884X_ANA_IVSENSE_BASE + 0x0a) 83#define WSA884X_MISC (WSA884X_ANA_IVSENSE_BASE + 0x0b) 84#define WSA884X_ADC_0 (WSA884X_ANA_IVSENSE_BASE + 0x0c) 85#define WSA884X_ADC_1 (WSA884X_ANA_IVSENSE_BASE + 0x0d) 86#define WSA884X_ADC_2 (WSA884X_ANA_IVSENSE_BASE + 0x0e) 87#define WSA884X_ADC_3 (WSA884X_ANA_IVSENSE_BASE + 0x0f) 88#define WSA884X_ADC_4 (WSA884X_ANA_IVSENSE_BASE + 0x10) 89#define WSA884X_ADC_5 (WSA884X_ANA_IVSENSE_BASE + 0x11) 90#define WSA884X_ADC_6 (WSA884X_ANA_IVSENSE_BASE + 0x12) 91#define WSA884X_ADC_7 (WSA884X_ANA_IVSENSE_BASE + 0x13) 92#define WSA884X_STATUS (WSA884X_ANA_IVSENSE_BASE + 0x14) 93#define WSA884X_IVSENSE_SPARE_TUNE_1 (WSA884X_ANA_IVSENSE_BASE + 0x15) 94#define WSA884X_SPARE_TUNE_2 (WSA884X_ANA_IVSENSE_BASE + 0x16) 95#define WSA884X_SPARE_TUNE_3 (WSA884X_ANA_IVSENSE_BASE + 0x17) 96#define WSA884X_SPARE_TUNE_4 (WSA884X_ANA_IVSENSE_BASE + 0x18) 97 98#define WSA884X_ANA_SPK_TOP_BASE (WSA884X_BASE + 0x0040) 99#define WSA884X_TOP_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x00) 100#define WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK 0x01 101#define WSA884X_CLIP_DET_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x01) 102#define WSA884X_CLIP_DET_CTRL2 (WSA884X_ANA_SPK_TOP_BASE + 0x02) 103#define WSA884X_DAC_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x03) 104#define WSA884X_DAC_VCM_CTRL_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x04) 105#define WSA884X_DAC_VCM_CTRL_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x05) 106#define WSA884X_DAC_VCM_CTRL_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x06) 107#define WSA884X_DAC_VCM_CTRL_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x07) 108#define WSA884X_DAC_VCM_CTRL_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x08) 109#define WSA884X_DAC_VCM_CTRL_REG6 (WSA884X_ANA_SPK_TOP_BASE + 0x09) 110#define WSA884X_PWM_CLK_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0a) 111#define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_MASK 0x80 112#define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_SHIFT 7 113#define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_MASK 0x40 114#define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_SHIFT 6 115#define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_MASK 0x30 116#define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_SHIFT 4 117#define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK 0x08 118#define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_SHIFT 3 119#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_MASK 0x06 120#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_SHIFT 1 121#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_MASK 0x01 122#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_SHIFT 0 123#define WSA884X_DRV_LF_LDO_SEL (WSA884X_ANA_SPK_TOP_BASE + 0x0b) 124#define WSA884X_OCP_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0c) 125#define WSA884X_PDRV_HS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0d) 126#define WSA884X_PDRV_LS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0e) 127#define WSA884X_SPK_TOP_SPARE_CTL_1 (WSA884X_ANA_SPK_TOP_BASE + 0x0f) 128#define WSA884X_SPK_TOP_SPARE_CTL_2 (WSA884X_ANA_SPK_TOP_BASE + 0x10) 129#define WSA884X_SPK_TOP_SPARE_CTL_3 (WSA884X_ANA_SPK_TOP_BASE + 0x11) 130#define WSA884X_SPK_TOP_SPARE_CTL_4 (WSA884X_ANA_SPK_TOP_BASE + 0x12) 131#define WSA884X_SPARE_CTL_5 (WSA884X_ANA_SPK_TOP_BASE + 0x13) 132#define WSA884X_DAC_EN_DEBUG_REG (WSA884X_ANA_SPK_TOP_BASE + 0x14) 133#define WSA884X_DAC_OPAMP_BIAS1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x15) 134#define WSA884X_DAC_OPAMP_BIAS2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x16) 135#define WSA884X_DAC_TUNE1 (WSA884X_ANA_SPK_TOP_BASE + 0x17) 136#define WSA884X_DAC_VOLTAGE_CTRL_REG (WSA884X_ANA_SPK_TOP_BASE + 0x18) 137#define WSA884X_ATEST1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x19) 138#define WSA884X_ATEST2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x1a) 139#define WSA884X_TOP_BIAS_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x1b) 140#define WSA884X_TOP_BIAS_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1c) 141#define WSA884X_TOP_BIAS_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x1d) 142#define WSA884X_TOP_BIAS_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x1e) 143#define WSA884X_PWRSTG_DBG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1f) 144#define WSA884X_DRV_LF_BLK_EN (WSA884X_ANA_SPK_TOP_BASE + 0x20) 145#define WSA884X_DRV_LF_EN (WSA884X_ANA_SPK_TOP_BASE + 0x21) 146#define WSA884X_DRV_LF_MASK_DCC_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x22) 147#define WSA884X_DRV_LF_MISC_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x23) 148#define WSA884X_DRV_LF_REG_GAIN (WSA884X_ANA_SPK_TOP_BASE + 0x24) 149#define WSA884X_DRV_OS_CAL_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x25) 150#define WSA884X_DRV_OS_CAL_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x26) 151#define WSA884X_PWRSTG_DBG (WSA884X_ANA_SPK_TOP_BASE + 0x27) 152#define WSA884X_BBM_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x28) 153#define WSA884X_TOP_MISC1 (WSA884X_ANA_SPK_TOP_BASE + 0x29) 154#define WSA884X_DAC_VCM_CTRL_REG7 (WSA884X_ANA_SPK_TOP_BASE + 0x2a) 155#define WSA884X_TOP_BIAS_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x2b) 156#define WSA884X_DRV_LF_MISC_CTL2 (WSA884X_ANA_SPK_TOP_BASE + 0x2c) 157#define WSA884X_SPK_TOP_SPARE_TUNE_2 (WSA884X_ANA_SPK_TOP_BASE + 0x2d) 158#define WSA884X_SPK_TOP_SPARE_TUNE_3 (WSA884X_ANA_SPK_TOP_BASE + 0x2e) 159#define WSA884X_SPK_TOP_SPARE_TUNE_4 (WSA884X_ANA_SPK_TOP_BASE + 0x2f) 160#define WSA884X_SPARE_TUNE_5 (WSA884X_ANA_SPK_TOP_BASE + 0x30) 161#define WSA884X_SPARE_TUNE_6 (WSA884X_ANA_SPK_TOP_BASE + 0x31) 162#define WSA884X_SPARE_TUNE_7 (WSA884X_ANA_SPK_TOP_BASE + 0x32) 163#define WSA884X_SPARE_TUNE_8 (WSA884X_ANA_SPK_TOP_BASE + 0x33) 164#define WSA884X_SPARE_TUNE_9 (WSA884X_ANA_SPK_TOP_BASE + 0x34) 165#define WSA884X_SPARE_TUNE_10 (WSA884X_ANA_SPK_TOP_BASE + 0x35) 166#define WSA884X_PA_STATUS0 (WSA884X_ANA_SPK_TOP_BASE + 0x36) 167#define WSA884X_PA_STATUS1 (WSA884X_ANA_SPK_TOP_BASE + 0x37) 168#define WSA884X_PA_STATUS2 (WSA884X_ANA_SPK_TOP_BASE + 0x38) 169#define WSA884X_PA_STATUS3 (WSA884X_ANA_SPK_TOP_BASE + 0x39) 170#define WSA884X_PA_STATUS4 (WSA884X_ANA_SPK_TOP_BASE + 0x3a) 171#define WSA884X_PA_STATUS5 (WSA884X_ANA_SPK_TOP_BASE + 0x3b) 172#define WSA884X_SPARE_RO_1 (WSA884X_ANA_SPK_TOP_BASE + 0x3c) 173#define WSA884X_SPARE_RO_2 (WSA884X_ANA_SPK_TOP_BASE + 0x3d) 174#define WSA884X_SPARE_RO_3 (WSA884X_ANA_SPK_TOP_BASE + 0x3e) 175 176#define WSA884X_ANA_BOOST_BASE (WSA884X_BASE + 0x0090) 177#define WSA884X_STB_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x00) 178#define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK 0xf8 179#define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_SHIFT 3 180#define WSA884X_STB_CTRL1_VOUT_FS_MASK 0x07 181#define WSA884X_STB_CTRL1_VOUT_FS_SHIFT 0 182#define WSA884X_CURRENT_LIMIT (WSA884X_ANA_BOOST_BASE + 0x01) 183#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK 0x80 184#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_SHIFT 7 185#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK 0x7c 186#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_SHIFT 2 187#define WSA884X_CURRENT_LIMIT_CLK_PHASE_SHIFT 0 188#define WSA884X_BYP_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x02) 189#define WSA884X_SPARE_CTL_0 (WSA884X_ANA_BOOST_BASE + 0x03) 190#define WSA884X_BOOST_SPARE_CTL_1 (WSA884X_ANA_BOOST_BASE + 0x04) 191#define WSA884X_SPARE_RO_0 (WSA884X_ANA_BOOST_BASE + 0x05) 192#define WSA884X_BOOST_SPARE_RO_1 (WSA884X_ANA_BOOST_BASE + 0x06) 193#define WSA884X_IBIAS1 (WSA884X_ANA_BOOST_BASE + 0x07) 194#define WSA884X_IBIAS2 (WSA884X_ANA_BOOST_BASE + 0x08) 195#define WSA884X_IBIAS3 (WSA884X_ANA_BOOST_BASE + 0x09) 196#define WSA884X_EN_CTRL (WSA884X_ANA_BOOST_BASE + 0x0a) 197#define WSA884X_STB_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0b) 198#define WSA884X_STB_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0c) 199#define WSA884X_STB_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x0d) 200#define WSA884X_BYP_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0e) 201#define WSA884X_BYP_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0f) 202#define WSA884X_ZX_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x10) 203#define WSA884X_ZX_CTRL1_ZX_DET_EN_MASK 0x80 204#define WSA884X_ZX_CTRL1_ZX_DET_EN_SHIFT 7 205#define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_MASK 0x40 206#define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_SHIFT 6 207#define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_MASK 0x20 208#define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_SHIFT 5 209#define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK 0x18 210#define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_SHIFT 3 211#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_MASK 0x04 212#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_SHIFT 2 213#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_MASK 0x02 214#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_SHIFT 1 215#define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_MASK 0x01 216#define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_SHIFT 0 217#define WSA884X_ZX_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x11) 218#define WSA884X_BLEEDER_CTRL (WSA884X_ANA_BOOST_BASE + 0x12) 219#define WSA884X_BOOST_MISC (WSA884X_ANA_BOOST_BASE + 0x13) 220#define WSA884X_PWRSTAGE_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x14) 221#define WSA884X_PWRSTAGE_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x15) 222#define WSA884X_PWRSTAGE_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x16) 223#define WSA884X_PWRSTAGE_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x17) 224#define WSA884X_MAXD_REG1 (WSA884X_ANA_BOOST_BASE + 0x18) 225#define WSA884X_MAXD_REG2 (WSA884X_ANA_BOOST_BASE + 0x19) 226#define WSA884X_ILIM_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1a) 227#define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_MASK 0x80 228#define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_SHIFT 0x07 229#define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_MASK 0x40 230#define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_SHIFT 0x06 231#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_MASK 0x38 232#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_SHIFT 0x03 233#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK 0x07 234#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_SHIFT 0x00 235#define WSA884X_ILIM_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1b) 236#define WSA884X_TEST_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1c) 237#define WSA884X_TEST_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1d) 238#define WSA884X_SPARE1 (WSA884X_ANA_BOOST_BASE + 0x1e) 239#define WSA884X_BOOT_CAP_CHECK (WSA884X_ANA_BOOST_BASE + 0x1f) 240 241#define WSA884X_ANA_PON_LDOL_BASE (WSA884X_BASE + 0x00b0) 242#define WSA884X_PON_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x00) 243#define WSA884X_PWRSAV_CTL (WSA884X_ANA_PON_LDOL_BASE + 0x01) 244#define WSA884X_PON_LDOL_SPARE_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x02) 245#define WSA884X_PON_LDOL_SPARE_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x03) 246#define WSA884X_PON_LDOL_SPARE_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x04) 247#define WSA884X_PON_LDOL_SPARE_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x05) 248#define WSA884X_PON_CLT_1 (WSA884X_ANA_PON_LDOL_BASE + 0x06) 249#define WSA884X_PON_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x07) 250#define WSA884X_PON_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x08) 251#define WSA884X_CKWD_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x09) 252#define WSA884X_CKWD_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0a) 253#define WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK 0x20 254#define WSA884X_CKWD_CTL_1_VPP_SW_CTL_SHIFT 5 255#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK 0x1f 256#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_SHIFT 0 257#define WSA884X_CKWD_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x0b) 258#define WSA884X_CKSK_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0c) 259#define WSA884X_PADSW_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0d) 260#define WSA884X_TEST_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0e) 261#define WSA884X_TEST_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0f) 262#define WSA884X_STATUS_0 (WSA884X_ANA_PON_LDOL_BASE + 0x10) 263#define WSA884X_STATUS_1 (WSA884X_ANA_PON_LDOL_BASE + 0x11) 264#define WSA884X_PON_LDOL_SPARE_TUNE_0 (WSA884X_ANA_PON_LDOL_BASE + 0x12) 265#define WSA884X_PON_LDOL_SPARE_TUNE_1 (WSA884X_ANA_PON_LDOL_BASE + 0x13) 266#define WSA884X_PON_LDOL_SPARE_TUNE_2 (WSA884X_ANA_PON_LDOL_BASE + 0x14) 267#define WSA884X_PON_LDOL_SPARE_TUNE_3 (WSA884X_ANA_PON_LDOL_BASE + 0x15) 268#define WSA884X_PON_LDOL_SPARE_TUNE_4 (WSA884X_ANA_PON_LDOL_BASE + 0x16) 269 270#define WSA884X_DIG_CTRL0_BASE (WSA884X_BASE + 0x0400) 271#define WSA884X_DIG_CTRL0_PAGE (WSA884X_DIG_CTRL0_BASE + 0x00) 272#define WSA884X_CHIP_ID0 (WSA884X_DIG_CTRL0_BASE + 0x01) 273#define WSA884X_CHIP_ID1 (WSA884X_DIG_CTRL0_BASE + 0x02) 274#define WSA884X_CHIP_ID2 (WSA884X_DIG_CTRL0_BASE + 0x03) 275#define WSA884X_CHIP_ID3 (WSA884X_DIG_CTRL0_BASE + 0x04) 276#define WSA884X_BUS_ID (WSA884X_DIG_CTRL0_BASE + 0x05) 277#define WSA884X_CDC_RST_CTL (WSA884X_DIG_CTRL0_BASE + 0x10) 278#define WSA884X_SWR_RESET_EN (WSA884X_DIG_CTRL0_BASE + 0x14) 279#define WSA884X_TOP_CLK_CFG (WSA884X_DIG_CTRL0_BASE + 0x18) 280#define WSA884X_SWR_CLK_RATE (WSA884X_DIG_CTRL0_BASE + 0x19) 281#define WSA884X_CDC_PATH_MODE (WSA884X_DIG_CTRL0_BASE + 0x1a) 282#define WSA884X_CDC_PATH_MODE_RXD_MODE_MASK 0x02 283#define WSA884X_CDC_PATH_MODE_RXD_MODE_SHIFT 0 284#define WSA884X_CDC_PATH_MODE_TXD_MODE_MASK 0x01 285#define WSA884X_CDC_PATH_MODE_TXD_MODE_SHIFT 0 286#define WSA884X_CDC_CLK_CTL (WSA884X_DIG_CTRL0_BASE + 0x1c) 287#define WSA884X_PA_FSM_EN (WSA884X_DIG_CTRL0_BASE + 0x30) 288#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK 0x01 289#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0 290#define WSA884X_PA_FSM_CTL0 (WSA884X_DIG_CTRL0_BASE + 0x31) 291#define WSA884X_PA_FSM_CTL1 (WSA884X_DIG_CTRL0_BASE + 0x32) 292#define WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK 0x38 293#define WSA884X_PA_FSM_TIMER0 (WSA884X_DIG_CTRL0_BASE + 0x33) 294#define WSA884X_PA_FSM_TIMER1 (WSA884X_DIG_CTRL0_BASE + 0x34) 295#define WSA884X_PA_FSM_STA0 (WSA884X_DIG_CTRL0_BASE + 0x35) 296#define WSA884X_PA_FSM_STA1 (WSA884X_DIG_CTRL0_BASE + 0x36) 297#define WSA884X_PA_FSM_ERR_CTL (WSA884X_DIG_CTRL0_BASE + 0x37) 298#define WSA884X_PA_FSM_ERR_COND0 (WSA884X_DIG_CTRL0_BASE + 0x38) 299#define WSA884X_PA_FSM_ERR_COND1 (WSA884X_DIG_CTRL0_BASE + 0x39) 300#define WSA884X_PA_FSM_MSK0 (WSA884X_DIG_CTRL0_BASE + 0x3a) 301#define WSA884X_PA_FSM_MSK1 (WSA884X_DIG_CTRL0_BASE + 0x3b) 302#define WSA884X_PA_FSM_BYP_CTL (WSA884X_DIG_CTRL0_BASE + 0x3c) 303#define WSA884X_PA_FSM_BYP0 (WSA884X_DIG_CTRL0_BASE + 0x3d) 304#define WSA884X_PA_FSM_BYP1 (WSA884X_DIG_CTRL0_BASE + 0x3e) 305#define WSA884X_TADC_VALUE_CTL (WSA884X_DIG_CTRL0_BASE + 0x50) 306#define WSA884X_TEMP_DETECT_CTL (WSA884X_DIG_CTRL0_BASE + 0x51) 307#define WSA884X_TEMP_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x52) 308#define WSA884X_TEMP_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x53) 309#define WSA884X_TEMP_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x54) 310#define WSA884X_TEMP_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x55) 311#define WSA884X_TEMP_CONFIG0 (WSA884X_DIG_CTRL0_BASE + 0x56) 312#define WSA884X_TEMP_CONFIG1 (WSA884X_DIG_CTRL0_BASE + 0x57) 313#define WSA884X_VBAT_THRM_FLT_CTL (WSA884X_DIG_CTRL0_BASE + 0x58) 314#define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_MASK 0xe0 315#define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_SHIFT 5 316#define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_SHIFT 4 317#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK 0x0e 318#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 1 319#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0 320#define WSA884X_VBAT_CAL_CTL (WSA884X_DIG_CTRL0_BASE + 0x59) 321#define WSA884X_VBAT_CAL_CTL_RESERVE_MASK 0x0e 322#define WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK 0x01 323#define WSA884X_VBAT_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x5a) 324#define WSA884X_VBAT_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x5b) 325#define WSA884X_VBAT_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x5c) 326#define WSA884X_VBAT_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x5d) 327#define WSA884X_VBAT_CAL_MSB (WSA884X_DIG_CTRL0_BASE + 0x5e) 328#define WSA884X_VBAT_CAL_LSB (WSA884X_DIG_CTRL0_BASE + 0x5f) 329#define WSA884X_UVLO_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x60) 330#define WSA884X_BOP_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x61) 331#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK 0x1e 332#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_SHIFT 1 333#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK 0x1 334#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_SHIFT 0 335#define WSA884X_VBAT_ZONE_DETC_CTL (WSA884X_DIG_CTRL0_BASE + 0x64) 336#define WSA884X_CPS_CTL (WSA884X_DIG_CTRL0_BASE + 0x68) 337#define WSA884X_CDC_RX_CTL (WSA884X_DIG_CTRL0_BASE + 0x70) 338#define WSA884X_CDC_SPK_DSM_A1_0 (WSA884X_DIG_CTRL0_BASE + 0x71) 339#define WSA884X_CDC_SPK_DSM_A1_1 (WSA884X_DIG_CTRL0_BASE + 0x72) 340#define WSA884X_CDC_SPK_DSM_A2_0 (WSA884X_DIG_CTRL0_BASE + 0x73) 341#define WSA884X_CDC_SPK_DSM_A2_1 (WSA884X_DIG_CTRL0_BASE + 0x74) 342#define WSA884X_CDC_SPK_DSM_A3_0 (WSA884X_DIG_CTRL0_BASE + 0x75) 343#define WSA884X_CDC_SPK_DSM_A3_1 (WSA884X_DIG_CTRL0_BASE + 0x76) 344#define WSA884X_CDC_SPK_DSM_A4_0 (WSA884X_DIG_CTRL0_BASE + 0x77) 345#define WSA884X_CDC_SPK_DSM_A4_1 (WSA884X_DIG_CTRL0_BASE + 0x78) 346#define WSA884X_CDC_SPK_DSM_A5_0 (WSA884X_DIG_CTRL0_BASE + 0x79) 347#define WSA884X_CDC_SPK_DSM_A5_1 (WSA884X_DIG_CTRL0_BASE + 0x7a) 348#define WSA884X_CDC_SPK_DSM_A6_0 (WSA884X_DIG_CTRL0_BASE + 0x7b) 349#define WSA884X_CDC_SPK_DSM_A7_0 (WSA884X_DIG_CTRL0_BASE + 0x7c) 350#define WSA884X_CDC_SPK_DSM_C_0 (WSA884X_DIG_CTRL0_BASE + 0x7d) 351#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK 0xf0 352#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 4 353#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK 0x0f 354#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0 355#define WSA884X_CDC_SPK_DSM_C_1 (WSA884X_DIG_CTRL0_BASE + 0x7e) 356#define WSA884X_CDC_SPK_DSM_C_2 (WSA884X_DIG_CTRL0_BASE + 0x7f) 357#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK 0xf0 358#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 4 359#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK 0x0f 360#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0 361#define WSA884X_CDC_SPK_DSM_C_3 (WSA884X_DIG_CTRL0_BASE + 0x80) 362#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK 0x3f 363#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0 364#define WSA884X_CDC_SPK_DSM_R1 (WSA884X_DIG_CTRL0_BASE + 0x81) 365#define WSA884X_CDC_SPK_DSM_R2 (WSA884X_DIG_CTRL0_BASE + 0x82) 366#define WSA884X_CDC_SPK_DSM_R3 (WSA884X_DIG_CTRL0_BASE + 0x83) 367#define WSA884X_CDC_SPK_DSM_R4 (WSA884X_DIG_CTRL0_BASE + 0x84) 368#define WSA884X_CDC_SPK_DSM_R5 (WSA884X_DIG_CTRL0_BASE + 0x85) 369#define WSA884X_CDC_SPK_DSM_R6 (WSA884X_DIG_CTRL0_BASE + 0x86) 370#define WSA884X_CDC_SPK_DSM_R7 (WSA884X_DIG_CTRL0_BASE + 0x87) 371#define WSA884X_CDC_SPK_GAIN_PDM_0 (WSA884X_DIG_CTRL0_BASE + 0x88) 372#define WSA884X_CDC_SPK_GAIN_PDM_1 (WSA884X_DIG_CTRL0_BASE + 0x89) 373#define WSA884X_CDC_SPK_GAIN_PDM_2 (WSA884X_DIG_CTRL0_BASE + 0x8a) 374#define WSA884X_PDM_WD_CTL (WSA884X_DIG_CTRL0_BASE + 0x8b) 375#define WSA884X_PDM_WD_CTL_HOLD_OFF_MASK 0x04 376#define WSA884X_PDM_WD_CTL_HOLD_OFF_SHIFT 2 377#define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_MASK 0x02 378#define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_SHIFT 1 379#define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK 0x01 380#define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0 381#define WSA884X_DEM_BYPASS_DATA0 (WSA884X_DIG_CTRL0_BASE + 0x90) 382#define WSA884X_DEM_BYPASS_DATA1 (WSA884X_DIG_CTRL0_BASE + 0x91) 383#define WSA884X_DEM_BYPASS_DATA2 (WSA884X_DIG_CTRL0_BASE + 0x92) 384#define WSA884X_DEM_BYPASS_DATA3 (WSA884X_DIG_CTRL0_BASE + 0x93) 385#define WSA884X_DRE_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xb0) 386#define WSA884X_DRE_CTL_0_PROG_DELAY_MASK 0xf0 387#define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 4 388#define WSA884X_DRE_CTL_0_OFFSET_MASK 0x07 389#define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0 390#define WSA884X_DRE_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xb1) 391#define WSA884X_DRE_CTL_1_CSR_GAIN_MASK 0x3e 392#define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 1 393#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK 0x01 394#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0 395#define WSA884X_DRE_IDLE_DET_CTL (WSA884X_DIG_CTRL0_BASE + 0xb2) 396#define WSA884X_GAIN_RAMPING_CTL (WSA884X_DIG_CTRL0_BASE + 0xb8) 397#define WSA884X_GAIN_RAMPING_MIN (WSA884X_DIG_CTRL0_BASE + 0xb9) 398#define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK 0x1f 399#define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_SHIFT 0 400#define WSA884X_TAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc0) 401#define WSA884X_TAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc1) 402#define WSA884X_TAGC_FORCE_VAL (WSA884X_DIG_CTRL0_BASE + 0xc2) 403#define WSA884X_VAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc8) 404#define WSA884X_VAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc9) 405#define WSA884X_VAGC_ATTN_LVL_1 (WSA884X_DIG_CTRL0_BASE + 0xca) 406#define WSA884X_VAGC_ATTN_LVL_2 (WSA884X_DIG_CTRL0_BASE + 0xcb) 407#define WSA884X_VAGC_ATTN_LVL_3 (WSA884X_DIG_CTRL0_BASE + 0xcc) 408#define WSA884X_CLSH_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xd0) 409#define WSA884X_CLSH_CTL_0_CSR_GAIN_EN_SHIFT 7 410#define WSA884X_CLSH_CTL_0_DLY_CODE_MASK 0x70 411#define WSA884X_CLSH_CTL_0_DLY_CODE_SHIFT 4 412#define WSA884X_CLSH_CTL_0_DLY_RST_SHIFT 3 413#define WSA884X_CLSH_CTL_0_DLY_EN_SHIFT 2 414#define WSA884X_CLSH_CTL_0_INPUT_EN_SHIFT 1 415#define WSA884X_CLSH_CTL_0_CLSH_EN_SHIFT 0 416#define WSA884X_CLSH_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xd1) 417#define WSA884X_CLSH_V_HD_PA (WSA884X_DIG_CTRL0_BASE + 0xd2) 418#define WSA884X_CLSH_V_PA_MIN (WSA884X_DIG_CTRL0_BASE + 0xd3) 419#define WSA884X_CLSH_OVRD_VAL (WSA884X_DIG_CTRL0_BASE + 0xd4) 420#define WSA884X_CLSH_HARD_MAX (WSA884X_DIG_CTRL0_BASE + 0xd5) 421#define WSA884X_CLSH_SOFT_MAX (WSA884X_DIG_CTRL0_BASE + 0xd6) 422#define WSA884X_CLSH_SIG_DP (WSA884X_DIG_CTRL0_BASE + 0xd7) 423#define WSA884X_PBR_DELAY_CTL (WSA884X_DIG_CTRL0_BASE + 0xd8) 424#define WSA884X_CLSH_SRL_MAX_PBR (WSA884X_DIG_CTRL0_BASE + 0xe0) 425#define WSA884X_PBR_MAX_VOLTAGE 20 426#define WSA884X_PBR_MAX_CODE 255 427#define WSA884X_VTH_TO_REG(vth) \ 428 ((vth) != 0 ? (((vth) - 150) * WSA884X_PBR_MAX_CODE / (WSA884X_PBR_MAX_VOLTAGE * 100) + 1) : 0) 429#define WSA884X_CLSH_VTH1 (WSA884X_DIG_CTRL0_BASE + 0xe1) 430#define WSA884X_CLSH_VTH2 (WSA884X_DIG_CTRL0_BASE + 0xe2) 431#define WSA884X_CLSH_VTH3 (WSA884X_DIG_CTRL0_BASE + 0xe3) 432#define WSA884X_CLSH_VTH4 (WSA884X_DIG_CTRL0_BASE + 0xe4) 433#define WSA884X_CLSH_VTH5 (WSA884X_DIG_CTRL0_BASE + 0xe5) 434#define WSA884X_CLSH_VTH6 (WSA884X_DIG_CTRL0_BASE + 0xe6) 435#define WSA884X_CLSH_VTH7 (WSA884X_DIG_CTRL0_BASE + 0xe7) 436#define WSA884X_CLSH_VTH8 (WSA884X_DIG_CTRL0_BASE + 0xe8) 437#define WSA884X_CLSH_VTH9 (WSA884X_DIG_CTRL0_BASE + 0xe9) 438#define WSA884X_CLSH_VTH10 (WSA884X_DIG_CTRL0_BASE + 0xea) 439#define WSA884X_CLSH_VTH11 (WSA884X_DIG_CTRL0_BASE + 0xeb) 440#define WSA884X_CLSH_VTH12 (WSA884X_DIG_CTRL0_BASE + 0xec) 441#define WSA884X_CLSH_VTH13 (WSA884X_DIG_CTRL0_BASE + 0xed) 442#define WSA884X_CLSH_VTH14 (WSA884X_DIG_CTRL0_BASE + 0xee) 443#define WSA884X_CLSH_VTH15 (WSA884X_DIG_CTRL0_BASE + 0xef) 444 445#define WSA884X_DIG_CTRL1_BASE (WSA884X_BASE + 0x0500) 446#define WSA884X_DIG_CTRL1_PAGE (WSA884X_DIG_CTRL1_BASE + 0x00) 447#define WSA884X_VPHX_SYS_EN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x01) 448#define WSA884X_ANA_WO_CTL_0 (WSA884X_DIG_CTRL1_BASE + 0x04) 449#define WSA884X_ANA_WO_CTL_0_MODE_SHIFT 0 450#define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_MASK 0xc0 451#define WSA884X_ANA_WO_CTL_0_PA_AUX_DISABLE 0x0 452#define WSA884X_ANA_WO_CTL_0_PA_AUX_18_DB 0xa 453#define WSA884X_ANA_WO_CTL_0_PA_AUX_0_DB 0x7 454#define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK 0x3c 455#define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_MASK 0x02 456#define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER 0x1 457#define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK 0x01 458#define WSA884X_ANA_WO_CTL_1 (WSA884X_DIG_CTRL1_BASE + 0x05) 459#define WSA884X_PIN_CTL (WSA884X_DIG_CTRL1_BASE + 0x10) 460#define WSA884X_PIN_CTL_OE (WSA884X_DIG_CTRL1_BASE + 0x11) 461#define WSA884X_PIN_WDATA_IOPAD (WSA884X_DIG_CTRL1_BASE + 0x12) 462#define WSA884X_PIN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x13) 463#define WSA884X_I2C_SLAVE_CTL (WSA884X_DIG_CTRL1_BASE + 0x14) 464#define WSA884X_SPMI_PAD_CTL0 (WSA884X_DIG_CTRL1_BASE + 0x15) 465#define WSA884X_SPMI_PAD_CTL1 (WSA884X_DIG_CTRL1_BASE + 0x16) 466#define WSA884X_SPMI_PAD_CTL2 (WSA884X_DIG_CTRL1_BASE + 0x17) 467#define WSA884X_MEM_CTL (WSA884X_DIG_CTRL1_BASE + 0x18) 468#define WSA884X_SWR_HM_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x19) 469#define WSA884X_SWR_HM_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x1a) 470#define WSA884X_OTP_CTRL0 (WSA884X_DIG_CTRL1_BASE + 0x30) 471#define WSA884X_OTP_CTRL1 (WSA884X_DIG_CTRL1_BASE + 0x31) 472#define WSA884X_OTP_CTRL2 (WSA884X_DIG_CTRL1_BASE + 0x32) 473#define WSA884X_OTP_STAT (WSA884X_DIG_CTRL1_BASE + 0x33) 474#define WSA884X_OTP_PRG_TCSP0 (WSA884X_DIG_CTRL1_BASE + 0x34) 475#define WSA884X_OTP_PRG_TCSP1 (WSA884X_DIG_CTRL1_BASE + 0x35) 476#define WSA884X_OTP_PRG_TPPS (WSA884X_DIG_CTRL1_BASE + 0x36) 477#define WSA884X_OTP_PRG_TVPS (WSA884X_DIG_CTRL1_BASE + 0x37) 478#define WSA884X_OTP_PRG_TVPH (WSA884X_DIG_CTRL1_BASE + 0x38) 479#define WSA884X_OTP_PRG_TPPR0 (WSA884X_DIG_CTRL1_BASE + 0x39) 480#define WSA884X_OTP_PRG_TPPR1 (WSA884X_DIG_CTRL1_BASE + 0x3a) 481#define WSA884X_OTP_PRG_TPPH (WSA884X_DIG_CTRL1_BASE + 0x3b) 482#define WSA884X_OTP_PRG_END (WSA884X_DIG_CTRL1_BASE + 0x3c) 483#define WSA884X_WAVG_PLAY (WSA884X_DIG_CTRL1_BASE + 0x40) 484#define WSA884X_WAVG_CTL (WSA884X_DIG_CTRL1_BASE + 0x41) 485#define WSA884X_WAVG_LRA_PER_0 (WSA884X_DIG_CTRL1_BASE + 0x43) 486#define WSA884X_WAVG_LRA_PER_1 (WSA884X_DIG_CTRL1_BASE + 0x44) 487#define WSA884X_WAVG_DELTA_THETA_0 (WSA884X_DIG_CTRL1_BASE + 0x45) 488#define WSA884X_WAVG_DELTA_THETA_1 (WSA884X_DIG_CTRL1_BASE + 0x46) 489#define WSA884X_WAVG_DIRECT_AMP_0 (WSA884X_DIG_CTRL1_BASE + 0x47) 490#define WSA884X_WAVG_DIRECT_AMP_1 (WSA884X_DIG_CTRL1_BASE + 0x48) 491#define WSA884X_WAVG_PTRN_AMP0_0 (WSA884X_DIG_CTRL1_BASE + 0x49) 492#define WSA884X_WAVG_PTRN_AMP0_1 (WSA884X_DIG_CTRL1_BASE + 0x4a) 493#define WSA884X_WAVG_PTRN_AMP1_0 (WSA884X_DIG_CTRL1_BASE + 0x4b) 494#define WSA884X_WAVG_PTRN_AMP1_1 (WSA884X_DIG_CTRL1_BASE + 0x4c) 495#define WSA884X_WAVG_PTRN_AMP2_0 (WSA884X_DIG_CTRL1_BASE + 0x4d) 496#define WSA884X_WAVG_PTRN_AMP2_1 (WSA884X_DIG_CTRL1_BASE + 0x4e) 497#define WSA884X_WAVG_PTRN_AMP3_0 (WSA884X_DIG_CTRL1_BASE + 0x4f) 498#define WSA884X_WAVG_PTRN_AMP3_1 (WSA884X_DIG_CTRL1_BASE + 0x50) 499#define WSA884X_WAVG_PTRN_AMP4_0 (WSA884X_DIG_CTRL1_BASE + 0x51) 500#define WSA884X_WAVG_PTRN_AMP4_1 (WSA884X_DIG_CTRL1_BASE + 0x52) 501#define WSA884X_WAVG_PTRN_AMP5_0 (WSA884X_DIG_CTRL1_BASE + 0x53) 502#define WSA884X_WAVG_PTRN_AMP5_1 (WSA884X_DIG_CTRL1_BASE + 0x54) 503#define WSA884X_WAVG_PTRN_AMP6_0 (WSA884X_DIG_CTRL1_BASE + 0x55) 504#define WSA884X_WAVG_PTRN_AMP6_1 (WSA884X_DIG_CTRL1_BASE + 0x56) 505#define WSA884X_WAVG_PTRN_AMP7_0 (WSA884X_DIG_CTRL1_BASE + 0x57) 506#define WSA884X_WAVG_PTRN_AMP7_1 (WSA884X_DIG_CTRL1_BASE + 0x58) 507#define WSA884X_WAVG_PER_0_1 (WSA884X_DIG_CTRL1_BASE + 0x59) 508#define WSA884X_WAVG_PER_2_3 (WSA884X_DIG_CTRL1_BASE + 0x5a) 509#define WSA884X_WAVG_PER_4_5 (WSA884X_DIG_CTRL1_BASE + 0x5b) 510#define WSA884X_WAVG_PER_6_7 (WSA884X_DIG_CTRL1_BASE + 0x5c) 511#define WSA884X_WAVG_STA (WSA884X_DIG_CTRL1_BASE + 0x5d) 512#define WSA884X_INTR_MODE (WSA884X_DIG_CTRL1_BASE + 0x80) 513#define WSA884X_INTR_MASK0 (WSA884X_DIG_CTRL1_BASE + 0x81) 514#define WSA884X_INTR_MASK1 (WSA884X_DIG_CTRL1_BASE + 0x82) 515#define WSA884X_INTR_STATUS0 (WSA884X_DIG_CTRL1_BASE + 0x83) 516#define WSA884X_INTR_STATUS1 (WSA884X_DIG_CTRL1_BASE + 0x84) 517#define WSA884X_INTR_CLEAR0 (WSA884X_DIG_CTRL1_BASE + 0x85) 518#define WSA884X_INTR_CLEAR1 (WSA884X_DIG_CTRL1_BASE + 0x86) 519#define WSA884X_INTR_LEVEL0 (WSA884X_DIG_CTRL1_BASE + 0x87) 520#define WSA884X_INTR_LEVEL1 (WSA884X_DIG_CTRL1_BASE + 0x88) 521#define WSA884X_INTR_SET0 (WSA884X_DIG_CTRL1_BASE + 0x89) 522#define WSA884X_INTR_SET1 (WSA884X_DIG_CTRL1_BASE + 0x8a) 523#define WSA884X_INTR_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x8b) 524#define WSA884X_INTR_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x8c) 525#define WSA884X_PDM_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc0) 526#define WSA884X_ATE_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc1) 527#define WSA884X_PA_FSM_DBG (WSA884X_DIG_CTRL1_BASE + 0xc2) 528#define WSA884X_DIG_DEBUG_MODE (WSA884X_DIG_CTRL1_BASE + 0xc3) 529#define WSA884X_DIG_DEBUG_SEL (WSA884X_DIG_CTRL1_BASE + 0xc4) 530#define WSA884X_DIG_DEBUG_EN (WSA884X_DIG_CTRL1_BASE + 0xc5) 531#define WSA884X_TADC_DETECT_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xc9) 532#define WSA884X_TADC_DEBUG_MSB (WSA884X_DIG_CTRL1_BASE + 0xca) 533#define WSA884X_TADC_DEBUG_LSB (WSA884X_DIG_CTRL1_BASE + 0xcb) 534#define WSA884X_SAMPLE_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcc) 535#define WSA884X_SWR_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcd) 536#define WSA884X_TEST_MODE_CTL (WSA884X_DIG_CTRL1_BASE + 0xce) 537#define WSA884X_IOPAD_CTL (WSA884X_DIG_CTRL1_BASE + 0xcf) 538#define WSA884X_ANA_CSR_DBG_ADD (WSA884X_DIG_CTRL1_BASE + 0xd0) 539#define WSA884X_ANA_CSR_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd1) 540#define WSA884X_CLK_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd2) 541#define WSA884X_SPARE_R (WSA884X_DIG_CTRL1_BASE + 0xf0) 542#define WSA884X_SPARE_0 (WSA884X_DIG_CTRL1_BASE + 0xf1) 543#define WSA884X_SPARE_1 (WSA884X_DIG_CTRL1_BASE + 0xf2) 544#define WSA884X_SPARE_2 (WSA884X_DIG_CTRL1_BASE + 0xf3) 545#define WSA884X_SCODE (WSA884X_DIG_CTRL1_BASE + 0xff) 546 547#define WSA884X_DIG_TRIM_BASE (WSA884X_BASE + 0x0800) 548#define WSA884X_DIG_TRIM_PAGE (WSA884X_DIG_TRIM_BASE + 0x00) 549#define WSA884X_OTP_REG_0 (WSA884X_DIG_TRIM_BASE + 0x80) 550#define WSA884X_OTP_ID_WSA8840 0x0 551#define WSA884X_OTP_ID_WSA8845 0x5 552#define WSA884X_OTP_ID_WSA8845H 0xc 553#define WSA884X_OTP_REG_0_ID_MASK 0x0f 554#define WSA884X_OTP_REG_1 (WSA884X_DIG_TRIM_BASE + 0x81) 555#define WSA884X_OTP_REG_2 (WSA884X_DIG_TRIM_BASE + 0x82) 556#define WSA884X_OTP_REG_3 (WSA884X_DIG_TRIM_BASE + 0x83) 557#define WSA884X_OTP_REG_4 (WSA884X_DIG_TRIM_BASE + 0x84) 558#define WSA884X_OTP_REG_5 (WSA884X_DIG_TRIM_BASE + 0x85) 559#define WSA884X_OTP_REG_6 (WSA884X_DIG_TRIM_BASE + 0x86) 560#define WSA884X_OTP_REG_7 (WSA884X_DIG_TRIM_BASE + 0x87) 561#define WSA884X_OTP_REG_8 (WSA884X_DIG_TRIM_BASE + 0x88) 562#define WSA884X_OTP_REG_9 (WSA884X_DIG_TRIM_BASE + 0x89) 563#define WSA884X_OTP_REG_10 (WSA884X_DIG_TRIM_BASE + 0x8a) 564#define WSA884X_OTP_REG_11 (WSA884X_DIG_TRIM_BASE + 0x8b) 565#define WSA884X_OTP_REG_12 (WSA884X_DIG_TRIM_BASE + 0x8c) 566#define WSA884X_OTP_REG_13 (WSA884X_DIG_TRIM_BASE + 0x8d) 567#define WSA884X_OTP_REG_14 (WSA884X_DIG_TRIM_BASE + 0x8e) 568#define WSA884X_OTP_REG_15 (WSA884X_DIG_TRIM_BASE + 0x8f) 569#define WSA884X_OTP_REG_16 (WSA884X_DIG_TRIM_BASE + 0x90) 570#define WSA884X_OTP_REG_17 (WSA884X_DIG_TRIM_BASE + 0x91) 571#define WSA884X_OTP_REG_18 (WSA884X_DIG_TRIM_BASE + 0x92) 572#define WSA884X_OTP_REG_19 (WSA884X_DIG_TRIM_BASE + 0x93) 573#define WSA884X_OTP_REG_20 (WSA884X_DIG_TRIM_BASE + 0x94) 574#define WSA884X_OTP_REG_21 (WSA884X_DIG_TRIM_BASE + 0x95) 575#define WSA884X_OTP_REG_22 (WSA884X_DIG_TRIM_BASE + 0x96) 576#define WSA884X_OTP_REG_23 (WSA884X_DIG_TRIM_BASE + 0x97) 577#define WSA884X_OTP_REG_24 (WSA884X_DIG_TRIM_BASE + 0x98) 578#define WSA884X_OTP_REG_25 (WSA884X_DIG_TRIM_BASE + 0x99) 579#define WSA884X_OTP_REG_26 (WSA884X_DIG_TRIM_BASE + 0x9a) 580#define WSA884X_OTP_REG_27 (WSA884X_DIG_TRIM_BASE + 0x9b) 581#define WSA884X_OTP_REG_28 (WSA884X_DIG_TRIM_BASE + 0x9c) 582#define WSA884X_OTP_REG_29 (WSA884X_DIG_TRIM_BASE + 0x9d) 583#define WSA884X_OTP_REG_30 (WSA884X_DIG_TRIM_BASE + 0x9e) 584#define WSA884X_OTP_REG_31 (WSA884X_DIG_TRIM_BASE + 0x9f) 585#define WSA884X_OTP_REG_32 (WSA884X_DIG_TRIM_BASE + 0xa0) 586#define WSA884X_OTP_REG_33 (WSA884X_DIG_TRIM_BASE + 0xa1) 587#define WSA884X_OTP_REG_34 (WSA884X_DIG_TRIM_BASE + 0xa2) 588#define WSA884X_OTP_REG_35 (WSA884X_DIG_TRIM_BASE + 0xa3) 589#define WSA884X_OTP_REG_36 (WSA884X_DIG_TRIM_BASE + 0xa4) 590#define WSA884X_OTP_REG_37 (WSA884X_DIG_TRIM_BASE + 0xa5) 591#define WSA884X_OTP_REG_38 (WSA884X_DIG_TRIM_BASE + 0xa6) 592#define WSA884X_OTP_REG_38_RESERVER_MASK 0xf0 593#define WSA884X_OTP_REG_38_RESERVER_SHIFT 4 594#define WSA884X_OTP_REG_38_BST_CFG_SEL_MASK 0x08 595#define WSA884X_OTP_REG_38_BST_CFG_SEL_SHIFT 3 596#define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_MASK 0x07 597#define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_SHIFT 0 598#define WSA884X_OTP_REG_39 (WSA884X_DIG_TRIM_BASE + 0xa7) 599#define WSA884X_OTP_REG_40 (WSA884X_DIG_TRIM_BASE + 0xa8) 600#define WSA884X_OTP_REG_40_SPARE_TYPE2_MASK 0xc0 601#define WSA884X_OTP_REG_40_SPARE_TYPE2_SHIFT 6 602#define WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK 0x3c 603#define WSA884X_OTP_REG_40_ISENSE_RESCAL_SHIFT 2 604#define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_MASK 0x2 605#define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_SHIFT 1 606#define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_MASK 0x1 607#define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_SHIFT 0 608#define WSA884X_OTP_REG_41 (WSA884X_DIG_TRIM_BASE + 0xa9) 609#define WSA884X_OTP_REG_63 (WSA884X_DIG_TRIM_BASE + 0xbf) 610 611#define WSA884X_DIG_EMEM_BASE (WSA884X_BASE + 0x08C0) 612#define WSA884X_EMEM_0 (WSA884X_DIG_EMEM_BASE + 0x00) 613#define WSA884X_EMEM_1 (WSA884X_DIG_EMEM_BASE + 0x01) 614#define WSA884X_EMEM_2 (WSA884X_DIG_EMEM_BASE + 0x02) 615#define WSA884X_EMEM_3 (WSA884X_DIG_EMEM_BASE + 0x03) 616#define WSA884X_EMEM_4 (WSA884X_DIG_EMEM_BASE + 0x04) 617#define WSA884X_EMEM_5 (WSA884X_DIG_EMEM_BASE + 0x05) 618#define WSA884X_EMEM_6 (WSA884X_DIG_EMEM_BASE + 0x06) 619#define WSA884X_EMEM_7 (WSA884X_DIG_EMEM_BASE + 0x07) 620#define WSA884X_EMEM_8 (WSA884X_DIG_EMEM_BASE + 0x08) 621#define WSA884X_EMEM_9 (WSA884X_DIG_EMEM_BASE + 0x09) 622#define WSA884X_EMEM_10 (WSA884X_DIG_EMEM_BASE + 0x0a) 623#define WSA884X_EMEM_11 (WSA884X_DIG_EMEM_BASE + 0x0b) 624#define WSA884X_EMEM_12 (WSA884X_DIG_EMEM_BASE + 0x0c) 625#define WSA884X_EMEM_13 (WSA884X_DIG_EMEM_BASE + 0x0d) 626#define WSA884X_EMEM_14 (WSA884X_DIG_EMEM_BASE + 0x0e) 627#define WSA884X_EMEM_15 (WSA884X_DIG_EMEM_BASE + 0x0f) 628#define WSA884X_EMEM_16 (WSA884X_DIG_EMEM_BASE + 0x10) 629#define WSA884X_EMEM_17 (WSA884X_DIG_EMEM_BASE + 0x11) 630#define WSA884X_EMEM_18 (WSA884X_DIG_EMEM_BASE + 0x12) 631#define WSA884X_EMEM_19 (WSA884X_DIG_EMEM_BASE + 0x13) 632#define WSA884X_EMEM_20 (WSA884X_DIG_EMEM_BASE + 0x14) 633#define WSA884X_EMEM_21 (WSA884X_DIG_EMEM_BASE + 0x15) 634#define WSA884X_EMEM_22 (WSA884X_DIG_EMEM_BASE + 0x16) 635#define WSA884X_EMEM_23 (WSA884X_DIG_EMEM_BASE + 0x17) 636#define WSA884X_EMEM_24 (WSA884X_DIG_EMEM_BASE + 0x18) 637#define WSA884X_EMEM_25 (WSA884X_DIG_EMEM_BASE + 0x19) 638#define WSA884X_EMEM_26 (WSA884X_DIG_EMEM_BASE + 0x1a) 639#define WSA884X_EMEM_27 (WSA884X_DIG_EMEM_BASE + 0x1b) 640#define WSA884X_EMEM_28 (WSA884X_DIG_EMEM_BASE + 0x1c) 641#define WSA884X_EMEM_29 (WSA884X_DIG_EMEM_BASE + 0x1d) 642#define WSA884X_EMEM_30 (WSA884X_DIG_EMEM_BASE + 0x1e) 643#define WSA884X_EMEM_31 (WSA884X_DIG_EMEM_BASE + 0x1f) 644#define WSA884X_EMEM_32 (WSA884X_DIG_EMEM_BASE + 0x20) 645#define WSA884X_EMEM_33 (WSA884X_DIG_EMEM_BASE + 0x21) 646#define WSA884X_EMEM_34 (WSA884X_DIG_EMEM_BASE + 0x22) 647#define WSA884X_EMEM_35 (WSA884X_DIG_EMEM_BASE + 0x23) 648#define WSA884X_EMEM_36 (WSA884X_DIG_EMEM_BASE + 0x24) 649#define WSA884X_EMEM_37 (WSA884X_DIG_EMEM_BASE + 0x25) 650#define WSA884X_EMEM_38 (WSA884X_DIG_EMEM_BASE + 0x26) 651#define WSA884X_EMEM_39 (WSA884X_DIG_EMEM_BASE + 0x27) 652#define WSA884X_EMEM_40 (WSA884X_DIG_EMEM_BASE + 0x28) 653#define WSA884X_EMEM_41 (WSA884X_DIG_EMEM_BASE + 0x29) 654#define WSA884X_EMEM_42 (WSA884X_DIG_EMEM_BASE + 0x2a) 655#define WSA884X_EMEM_43 (WSA884X_DIG_EMEM_BASE + 0x2b) 656#define WSA884X_EMEM_44 (WSA884X_DIG_EMEM_BASE + 0x2c) 657#define WSA884X_EMEM_45 (WSA884X_DIG_EMEM_BASE + 0x2d) 658#define WSA884X_EMEM_46 (WSA884X_DIG_EMEM_BASE + 0x2e) 659#define WSA884X_EMEM_47 (WSA884X_DIG_EMEM_BASE + 0x2f) 660#define WSA884X_EMEM_48 (WSA884X_DIG_EMEM_BASE + 0x30) 661#define WSA884X_EMEM_49 (WSA884X_DIG_EMEM_BASE + 0x31) 662#define WSA884X_EMEM_50 (WSA884X_DIG_EMEM_BASE + 0x32) 663#define WSA884X_EMEM_51 (WSA884X_DIG_EMEM_BASE + 0x33) 664#define WSA884X_EMEM_52 (WSA884X_DIG_EMEM_BASE + 0x34) 665#define WSA884X_EMEM_53 (WSA884X_DIG_EMEM_BASE + 0x35) 666#define WSA884X_EMEM_54 (WSA884X_DIG_EMEM_BASE + 0x36) 667#define WSA884X_EMEM_55 (WSA884X_DIG_EMEM_BASE + 0x37) 668#define WSA884X_EMEM_56 (WSA884X_DIG_EMEM_BASE + 0x38) 669#define WSA884X_EMEM_57 (WSA884X_DIG_EMEM_BASE + 0x39) 670#define WSA884X_EMEM_58 (WSA884X_DIG_EMEM_BASE + 0x3a) 671#define WSA884X_EMEM_59 (WSA884X_DIG_EMEM_BASE + 0x3b) 672#define WSA884X_EMEM_60 (WSA884X_DIG_EMEM_BASE + 0x3c) 673#define WSA884X_EMEM_61 (WSA884X_DIG_EMEM_BASE + 0x3d) 674#define WSA884X_EMEM_62 (WSA884X_DIG_EMEM_BASE + 0x3e) 675#define WSA884X_EMEM_63 (WSA884X_DIG_EMEM_BASE + 0x3f) 676 677#define WSA884X_NUM_REGISTERS (WSA884X_EMEM_63 + 1) 678#define WSA884X_MAX_REGISTER (WSA884X_NUM_REGISTERS - 1) 679 680#define WSA884X_SUPPLIES_NUM 2 681#define WSA884X_MAX_SWR_PORTS 6 682#define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 683 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 684 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 685 SNDRV_PCM_RATE_384000) 686/* Fractional Rates */ 687#define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 688 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 689 690#define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 691 SNDRV_PCM_FMTBIT_S24_LE |\ 692 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 693 694struct wsa884x_priv { 695 struct regmap *regmap; 696 struct device *dev; 697 struct regulator_bulk_data supplies[WSA884X_SUPPLIES_NUM]; 698 struct sdw_slave *slave; 699 struct sdw_stream_config sconfig; 700 struct sdw_stream_runtime *sruntime; 701 struct sdw_port_config port_config[WSA884X_MAX_SWR_PORTS]; 702 struct gpio_desc *sd_n; 703 struct reset_control *sd_reset; 704 bool port_prepared[WSA884X_MAX_SWR_PORTS]; 705 bool port_enable[WSA884X_MAX_SWR_PORTS]; 706 unsigned int variant; 707 int active_ports; 708 int dev_mode; 709 bool hw_init; 710}; 711 712enum { 713 COMP_OFFSET0, 714 COMP_OFFSET1, 715 COMP_OFFSET2, 716 COMP_OFFSET3, 717 COMP_OFFSET4, 718}; 719 720enum wsa884x_gain { 721 G_21_DB = 0, 722 G_19P5_DB, 723 G_18_DB, 724 G_16P5_DB, 725 G_15_DB, 726 G_13P5_DB, 727 G_12_DB, 728 G_10P5_DB, 729 G_9_DB, 730 G_7P5_DB, 731 G_6_DB, 732 G_4P5_DB, 733 G_3_DB, 734 G_1P5_DB, 735 G_0_DB, 736 G_M1P5_DB, 737 G_M3_DB, 738 G_M4P5_DB, 739 G_M6_DB, 740 G_MAX_DB, 741}; 742 743enum wsa884x_isense { 744 ISENSE_6_DB = 0, 745 ISENSE_12_DB, 746 ISENSE_15_DB, 747 ISENSE_18_DB, 748}; 749 750enum wsa884x_vsense { 751 VSENSE_M12_DB = 0, 752 VSENSE_M15_DB, 753 VSENSE_M18_DB, 754 VSENSE_M21_DB, 755 VSENSE_M24_DB, 756}; 757 758enum wsa884x_port_ids { 759 WSA884X_PORT_DAC, 760 WSA884X_PORT_COMP, 761 WSA884X_PORT_BOOST, 762 WSA884X_PORT_PBR, 763 WSA884X_PORT_VISENSE, 764 WSA884X_PORT_CPS, 765}; 766 767static const char * const wsa884x_supply_name[] = { 768 "vdd-io", 769 "vdd-1p8", 770}; 771 772static const char * const wsa884x_dev_mode_text[] = { 773 "Speaker", "Receiver" 774}; 775 776enum wsa884x_mode { 777 WSA884X_SPEAKER, 778 WSA884X_RECEIVER, 779}; 780 781static const struct soc_enum wsa884x_dev_mode_enum = 782 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa884x_dev_mode_text), wsa884x_dev_mode_text); 783 784static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = { 785 { 786 .num = WSA884X_PORT_DAC + 1, 787 .type = SDW_DPN_SIMPLE, 788 .min_ch = 1, 789 .max_ch = 1, 790 .simple_ch_prep_sm = true, 791 .read_only_wordlength = true, 792 }, { 793 .num = WSA884X_PORT_COMP + 1, 794 .type = SDW_DPN_SIMPLE, 795 .min_ch = 1, 796 .max_ch = 1, 797 .simple_ch_prep_sm = true, 798 .read_only_wordlength = true, 799 }, { 800 .num = WSA884X_PORT_BOOST + 1, 801 .type = SDW_DPN_SIMPLE, 802 .min_ch = 1, 803 .max_ch = 1, 804 .simple_ch_prep_sm = true, 805 .read_only_wordlength = true, 806 }, { 807 .num = WSA884X_PORT_PBR + 1, 808 .type = SDW_DPN_SIMPLE, 809 .min_ch = 1, 810 .max_ch = 1, 811 .simple_ch_prep_sm = true, 812 .read_only_wordlength = true, 813 }, { 814 .num = WSA884X_PORT_VISENSE + 1, 815 .type = SDW_DPN_SIMPLE, 816 .min_ch = 1, 817 .max_ch = 1, 818 .simple_ch_prep_sm = true, 819 .read_only_wordlength = true, 820 }, { 821 .num = WSA884X_PORT_CPS + 1, 822 .type = SDW_DPN_SIMPLE, 823 .min_ch = 1, 824 .max_ch = 1, 825 .simple_ch_prep_sm = true, 826 .read_only_wordlength = true, 827 } 828}; 829 830static const struct sdw_port_config wsa884x_pconfig[WSA884X_MAX_SWR_PORTS] = { 831 { 832 .num = WSA884X_PORT_DAC + 1, 833 .ch_mask = 0x1, 834 }, { 835 .num = WSA884X_PORT_COMP + 1, 836 .ch_mask = 0xf, 837 }, { 838 .num = WSA884X_PORT_BOOST + 1, 839 .ch_mask = 0x3, 840 }, { 841 .num = WSA884X_PORT_PBR + 1, 842 .ch_mask = 0x1, 843 }, { 844 .num = WSA884X_PORT_VISENSE + 1, 845 .ch_mask = 0x3, 846 }, { 847 .num = WSA884X_PORT_CPS + 1, 848 .ch_mask = 0x3, 849 }, 850}; 851 852static struct reg_default wsa884x_defaults[] = { 853 { WSA884X_BG_CTRL, 0xa5 }, 854 { WSA884X_ADC_CTRL, 0x00 }, 855 { WSA884X_BOP1_PROG, 0x22 }, 856 { WSA884X_BOP2_PROG, 0x44 }, 857 { WSA884X_UVLO_PROG, 0x99 }, 858 { WSA884X_UVLO_PROG1, 0x70 }, 859 { WSA884X_SPARE_CTRL_0, 0x00 }, 860 { WSA884X_SPARE_CTRL_1, 0x00 }, 861 { WSA884X_SPARE_CTRL_2, 0x00 }, 862 { WSA884X_SPARE_CTRL_3, 0x00 }, 863 { WSA884X_REF_CTRL, 0xd2 }, 864 { WSA884X_BG_TEST_CTL, 0x06 }, 865 { WSA884X_BG_BIAS, 0xd7 }, 866 { WSA884X_ADC_PROG, 0x08 }, 867 { WSA884X_ADC_IREF_CTL, 0x57 }, 868 { WSA884X_ADC_ISENS_CTL, 0x47 }, 869 { WSA884X_ADC_CLK_CTL, 0x87 }, 870 { WSA884X_ADC_TEST_CTL, 0x00 }, 871 { WSA884X_ADC_BIAS, 0x51 }, 872 { WSA884X_VBAT_SNS, 0xa0 }, 873 { WSA884X_BOP_ATEST_SEL, 0x00 }, 874 { WSA884X_MISC0, 0x04 }, 875 { WSA884X_MISC1, 0x75 }, 876 { WSA884X_MISC2, 0x00 }, 877 { WSA884X_MISC3, 0x10 }, 878 { WSA884X_SPARE_TSBG_0, 0x00 }, 879 { WSA884X_SPARE_TUNE_0, 0x00 }, 880 { WSA884X_SPARE_TUNE_1, 0x00 }, 881 { WSA884X_VSENSE1, 0xe7 }, 882 { WSA884X_ISENSE2, 0x27 }, 883 { WSA884X_SPARE_CTL_1, 0x00 }, 884 { WSA884X_SPARE_CTL_2, 0x00 }, 885 { WSA884X_SPARE_CTL_3, 0x00 }, 886 { WSA884X_SPARE_CTL_4, 0x00 }, 887 { WSA884X_EN, 0x10 }, 888 { WSA884X_OVERRIDE1, 0x00 }, 889 { WSA884X_OVERRIDE2, 0x08 }, 890 { WSA884X_ISENSE1, 0xd4 }, 891 { WSA884X_ISENSE_CAL, 0x00 }, 892 { WSA884X_MISC, 0x00 }, 893 { WSA884X_ADC_0, 0x00 }, 894 { WSA884X_ADC_1, 0x00 }, 895 { WSA884X_ADC_2, 0x40 }, 896 { WSA884X_ADC_3, 0x80 }, 897 { WSA884X_ADC_4, 0x25 }, 898 { WSA884X_ADC_5, 0x24 }, 899 { WSA884X_ADC_6, 0x0a }, 900 { WSA884X_ADC_7, 0x81 }, 901 { WSA884X_IVSENSE_SPARE_TUNE_1, 0x00 }, 902 { WSA884X_SPARE_TUNE_2, 0x00 }, 903 { WSA884X_SPARE_TUNE_3, 0x00 }, 904 { WSA884X_SPARE_TUNE_4, 0x00 }, 905 { WSA884X_TOP_CTRL1, 0xd3 }, 906 { WSA884X_CLIP_DET_CTRL1, 0x7e }, 907 { WSA884X_CLIP_DET_CTRL2, 0x4c }, 908 { WSA884X_DAC_CTRL1, 0xa4 }, 909 { WSA884X_DAC_VCM_CTRL_REG1, 0x02 }, 910 { WSA884X_DAC_VCM_CTRL_REG2, 0x00 }, 911 { WSA884X_DAC_VCM_CTRL_REG3, 0x00 }, 912 { WSA884X_DAC_VCM_CTRL_REG4, 0x00 }, 913 { WSA884X_DAC_VCM_CTRL_REG5, 0x00 }, 914 { WSA884X_DAC_VCM_CTRL_REG6, 0x00 }, 915 { WSA884X_PWM_CLK_CTL, 0x20 }, 916 { WSA884X_DRV_LF_LDO_SEL, 0xaa }, 917 { WSA884X_OCP_CTL, 0xc6 }, 918 { WSA884X_PDRV_HS_CTL, 0x52 }, 919 { WSA884X_PDRV_LS_CTL, 0x4a }, 920 { WSA884X_SPK_TOP_SPARE_CTL_1, 0x00 }, 921 { WSA884X_SPK_TOP_SPARE_CTL_2, 0x00 }, 922 { WSA884X_SPK_TOP_SPARE_CTL_3, 0x00 }, 923 { WSA884X_SPK_TOP_SPARE_CTL_4, 0x00 }, 924 { WSA884X_SPARE_CTL_5, 0x00 }, 925 { WSA884X_DAC_EN_DEBUG_REG, 0x00 }, 926 { WSA884X_DAC_OPAMP_BIAS1_REG, 0x48 }, 927 { WSA884X_DAC_OPAMP_BIAS2_REG, 0x48 }, 928 { WSA884X_DAC_TUNE1, 0x02 }, 929 { WSA884X_DAC_VOLTAGE_CTRL_REG, 0x05 }, 930 { WSA884X_ATEST1_REG, 0x00 }, 931 { WSA884X_ATEST2_REG, 0x00 }, 932 { WSA884X_TOP_BIAS_REG1, 0x6a }, 933 { WSA884X_TOP_BIAS_REG2, 0x65 }, 934 { WSA884X_TOP_BIAS_REG3, 0x55 }, 935 { WSA884X_TOP_BIAS_REG4, 0xa9 }, 936 { WSA884X_PWRSTG_DBG2, 0x21 }, 937 { WSA884X_DRV_LF_BLK_EN, 0x0f }, 938 { WSA884X_DRV_LF_EN, 0x0a }, 939 { WSA884X_DRV_LF_MASK_DCC_CTL, 0x08 }, 940 { WSA884X_DRV_LF_MISC_CTL1, 0x30 }, 941 { WSA884X_DRV_LF_REG_GAIN, 0x00 }, 942 { WSA884X_DRV_OS_CAL_CTL, 0x00 }, 943 { WSA884X_DRV_OS_CAL_CTL1, 0x90 }, 944 { WSA884X_PWRSTG_DBG, 0x08 }, 945 { WSA884X_BBM_CTL, 0x92 }, 946 { WSA884X_TOP_MISC1, 0x00 }, 947 { WSA884X_DAC_VCM_CTRL_REG7, 0x00 }, 948 { WSA884X_TOP_BIAS_REG5, 0x15 }, 949 { WSA884X_DRV_LF_MISC_CTL2, 0x00 }, 950 { WSA884X_STB_CTRL1, 0x42 }, 951 { WSA884X_CURRENT_LIMIT, 0x54 }, 952 { WSA884X_BYP_CTRL1, 0x01 }, 953 { WSA884X_SPARE_CTL_0, 0x00 }, 954 { WSA884X_BOOST_SPARE_CTL_1, 0x00 }, 955 { WSA884X_IBIAS1, 0x00 }, 956 { WSA884X_IBIAS2, 0x00 }, 957 { WSA884X_IBIAS3, 0x00 }, 958 { WSA884X_EN_CTRL, 0x42 }, 959 { WSA884X_STB_CTRL2, 0x03 }, 960 { WSA884X_STB_CTRL3, 0x3c }, 961 { WSA884X_STB_CTRL4, 0x30 }, 962 { WSA884X_BYP_CTRL2, 0x97 }, 963 { WSA884X_BYP_CTRL3, 0x11 }, 964 { WSA884X_ZX_CTRL1, 0xf0 }, 965 { WSA884X_ZX_CTRL2, 0x04 }, 966 { WSA884X_BLEEDER_CTRL, 0x04 }, 967 { WSA884X_BOOST_MISC, 0x62 }, 968 { WSA884X_PWRSTAGE_CTRL1, 0x00 }, 969 { WSA884X_PWRSTAGE_CTRL2, 0x31 }, 970 { WSA884X_PWRSTAGE_CTRL3, 0x81 }, 971 { WSA884X_PWRSTAGE_CTRL4, 0x5f }, 972 { WSA884X_MAXD_REG1, 0x00 }, 973 { WSA884X_MAXD_REG2, 0x5b }, 974 { WSA884X_ILIM_CTRL1, 0xe2 }, 975 { WSA884X_ILIM_CTRL2, 0x90 }, 976 { WSA884X_TEST_CTRL1, 0x00 }, 977 { WSA884X_TEST_CTRL2, 0x00 }, 978 { WSA884X_SPARE1, 0x00 }, 979 { WSA884X_BOOT_CAP_CHECK, 0x01 }, 980 { WSA884X_PON_CTL_0, 0x12 }, 981 { WSA884X_PWRSAV_CTL, 0xaa }, 982 { WSA884X_PON_LDOL_SPARE_CTL_0, 0x00 }, 983 { WSA884X_PON_LDOL_SPARE_CTL_1, 0x00 }, 984 { WSA884X_PON_LDOL_SPARE_CTL_2, 0x00 }, 985 { WSA884X_PON_LDOL_SPARE_CTL_3, 0x00 }, 986 { WSA884X_PON_CLT_1, 0xe1 }, 987 { WSA884X_PON_CTL_2, 0x00 }, 988 { WSA884X_PON_CTL_3, 0x70 }, 989 { WSA884X_CKWD_CTL_0, 0x14 }, 990 { WSA884X_CKWD_CTL_1, 0x3b }, 991 { WSA884X_CKWD_CTL_2, 0x00 }, 992 { WSA884X_CKSK_CTL_0, 0x00 }, 993 { WSA884X_PADSW_CTL_0, 0x00 }, 994 { WSA884X_TEST_0, 0x00 }, 995 { WSA884X_TEST_1, 0x00 }, 996 { WSA884X_PON_LDOL_SPARE_TUNE_0, 0x00 }, 997 { WSA884X_PON_LDOL_SPARE_TUNE_1, 0x00 }, 998 { WSA884X_PON_LDOL_SPARE_TUNE_2, 0x00 }, 999 { WSA884X_PON_LDOL_SPARE_TUNE_3, 0x00 }, 1000 { WSA884X_PON_LDOL_SPARE_TUNE_4, 0x00 }, 1001 { WSA884X_DIG_CTRL0_PAGE, 0x00 }, 1002 { WSA884X_CDC_RST_CTL, 0x01 }, 1003 { WSA884X_SWR_RESET_EN, 0x00 }, 1004 { WSA884X_TOP_CLK_CFG, 0x00 }, 1005 { WSA884X_SWR_CLK_RATE, 0x00 }, 1006 { WSA884X_CDC_PATH_MODE, 0x00 }, 1007 { WSA884X_CDC_CLK_CTL, 0x1f }, 1008 { WSA884X_PA_FSM_EN, 0x00 }, 1009 { WSA884X_PA_FSM_CTL0, 0x00 }, 1010 { WSA884X_PA_FSM_CTL1, 0xfe }, 1011 { WSA884X_PA_FSM_TIMER0, 0x80 }, 1012 { WSA884X_PA_FSM_TIMER1, 0x80 }, 1013 { WSA884X_PA_FSM_ERR_CTL, 0x00 }, 1014 { WSA884X_PA_FSM_MSK0, 0x00 }, 1015 { WSA884X_PA_FSM_MSK1, 0x00 }, 1016 { WSA884X_PA_FSM_BYP_CTL, 0x00 }, 1017 { WSA884X_PA_FSM_BYP0, 0x00 }, 1018 { WSA884X_PA_FSM_BYP1, 0x00 }, 1019 { WSA884X_TADC_VALUE_CTL, 0x03 }, 1020 { WSA884X_TEMP_DETECT_CTL, 0x01 }, 1021 { WSA884X_TEMP_CONFIG0, 0x00 }, 1022 { WSA884X_TEMP_CONFIG1, 0x00 }, 1023 { WSA884X_VBAT_THRM_FLT_CTL, 0x7f }, 1024 { WSA884X_VBAT_CAL_CTL, 0x01 }, 1025 { WSA884X_UVLO_DEGLITCH_CTL, 0x05 }, 1026 { WSA884X_BOP_DEGLITCH_CTL, 0x05 }, 1027 { WSA884X_VBAT_ZONE_DETC_CTL, 0x31 }, 1028 { WSA884X_CPS_CTL, 0x00 }, 1029 { WSA884X_CDC_RX_CTL, 0xfe }, 1030 { WSA884X_CDC_SPK_DSM_A1_0, 0x00 }, 1031 { WSA884X_CDC_SPK_DSM_A1_1, 0x01 }, 1032 { WSA884X_CDC_SPK_DSM_A2_0, 0x96 }, 1033 { WSA884X_CDC_SPK_DSM_A2_1, 0x09 }, 1034 { WSA884X_CDC_SPK_DSM_A3_0, 0xab }, 1035 { WSA884X_CDC_SPK_DSM_A3_1, 0x05 }, 1036 { WSA884X_CDC_SPK_DSM_A4_0, 0x1c }, 1037 { WSA884X_CDC_SPK_DSM_A4_1, 0x02 }, 1038 { WSA884X_CDC_SPK_DSM_A5_0, 0x17 }, 1039 { WSA884X_CDC_SPK_DSM_A5_1, 0x02 }, 1040 { WSA884X_CDC_SPK_DSM_A6_0, 0xaa }, 1041 { WSA884X_CDC_SPK_DSM_A7_0, 0xe3 }, 1042 { WSA884X_CDC_SPK_DSM_C_0, 0x69 }, 1043 { WSA884X_CDC_SPK_DSM_C_1, 0x54 }, 1044 { WSA884X_CDC_SPK_DSM_C_2, 0x02 }, 1045 { WSA884X_CDC_SPK_DSM_C_3, 0x15 }, 1046 { WSA884X_CDC_SPK_DSM_R1, 0xa4 }, 1047 { WSA884X_CDC_SPK_DSM_R2, 0xb5 }, 1048 { WSA884X_CDC_SPK_DSM_R3, 0x86 }, 1049 { WSA884X_CDC_SPK_DSM_R4, 0x85 }, 1050 { WSA884X_CDC_SPK_DSM_R5, 0xaa }, 1051 { WSA884X_CDC_SPK_DSM_R6, 0xe2 }, 1052 { WSA884X_CDC_SPK_DSM_R7, 0x62 }, 1053 { WSA884X_CDC_SPK_GAIN_PDM_0, 0x00 }, 1054 { WSA884X_CDC_SPK_GAIN_PDM_1, 0xfc }, 1055 { WSA884X_CDC_SPK_GAIN_PDM_2, 0x05 }, 1056 { WSA884X_PDM_WD_CTL, 0x00 }, 1057 { WSA884X_DEM_BYPASS_DATA0, 0x00 }, 1058 { WSA884X_DEM_BYPASS_DATA1, 0x00 }, 1059 { WSA884X_DEM_BYPASS_DATA2, 0x00 }, 1060 { WSA884X_DEM_BYPASS_DATA3, 0x00 }, 1061 { WSA884X_DRE_CTL_0, 0x70 }, 1062 { WSA884X_DRE_CTL_1, 0x04 }, 1063 { WSA884X_DRE_IDLE_DET_CTL, 0x2f }, 1064 { WSA884X_GAIN_RAMPING_CTL, 0x50 }, 1065 { WSA884X_GAIN_RAMPING_MIN, 0x12 }, 1066 { WSA884X_TAGC_CTL, 0x15 }, 1067 { WSA884X_TAGC_TIME, 0xbc }, 1068 { WSA884X_TAGC_FORCE_VAL, 0x00 }, 1069 { WSA884X_VAGC_CTL, 0x01 }, 1070 { WSA884X_VAGC_TIME, 0x0f }, 1071 { WSA884X_VAGC_ATTN_LVL_1, 0x03 }, 1072 { WSA884X_VAGC_ATTN_LVL_2, 0x06 }, 1073 { WSA884X_VAGC_ATTN_LVL_3, 0x09 }, 1074 { WSA884X_CLSH_CTL_0, 0x37 }, 1075 { WSA884X_CLSH_CTL_1, 0x81 }, 1076 { WSA884X_CLSH_V_HD_PA, 0x0c }, 1077 { WSA884X_CLSH_V_PA_MIN, 0x00 }, 1078 { WSA884X_CLSH_OVRD_VAL, 0x00 }, 1079 { WSA884X_CLSH_HARD_MAX, 0xff }, 1080 { WSA884X_CLSH_SOFT_MAX, 0xf5 }, 1081 { WSA884X_CLSH_SIG_DP, 0x00 }, 1082 { WSA884X_PBR_DELAY_CTL, 0x07 }, 1083 { WSA884X_CLSH_SRL_MAX_PBR, 0x02 }, 1084 { WSA884X_CLSH_VTH1, 0x00 }, 1085 { WSA884X_CLSH_VTH2, 0x00 }, 1086 { WSA884X_CLSH_VTH3, 0x00 }, 1087 { WSA884X_CLSH_VTH4, 0x00 }, 1088 { WSA884X_CLSH_VTH5, 0x00 }, 1089 { WSA884X_CLSH_VTH6, 0x00 }, 1090 { WSA884X_CLSH_VTH7, 0x00 }, 1091 { WSA884X_CLSH_VTH8, 0x00 }, 1092 { WSA884X_CLSH_VTH9, 0x00 }, 1093 { WSA884X_CLSH_VTH10, 0x00 }, 1094 { WSA884X_CLSH_VTH11, 0x00 }, 1095 { WSA884X_CLSH_VTH12, 0x00 }, 1096 { WSA884X_CLSH_VTH13, 0x00 }, 1097 { WSA884X_CLSH_VTH14, 0x00 }, 1098 { WSA884X_CLSH_VTH15, 0x00 }, 1099 { WSA884X_DIG_CTRL1_PAGE, 0x00 }, 1100 { WSA884X_PIN_CTL, 0x04 }, 1101 { WSA884X_PIN_CTL_OE, 0x00 }, 1102 { WSA884X_PIN_WDATA_IOPAD, 0x00 }, 1103 { WSA884X_I2C_SLAVE_CTL, 0x00 }, 1104 { WSA884X_SPMI_PAD_CTL0, 0x2f }, 1105 { WSA884X_SPMI_PAD_CTL1, 0x2f }, 1106 { WSA884X_SPMI_PAD_CTL2, 0x2f }, 1107 { WSA884X_MEM_CTL, 0x00 }, 1108 { WSA884X_SWR_HM_TEST0, 0x08 }, 1109 { WSA884X_OTP_CTRL0, 0x00 }, 1110 { WSA884X_OTP_CTRL2, 0x00 }, 1111 { WSA884X_OTP_PRG_TCSP0, 0x77 }, 1112 { WSA884X_OTP_PRG_TCSP1, 0x00 }, 1113 { WSA884X_OTP_PRG_TPPS, 0x47 }, 1114 { WSA884X_OTP_PRG_TVPS, 0x3b }, 1115 { WSA884X_OTP_PRG_TVPH, 0x47 }, 1116 { WSA884X_OTP_PRG_TPPR0, 0x47 }, 1117 { WSA884X_OTP_PRG_TPPR1, 0x00 }, 1118 { WSA884X_OTP_PRG_TPPH, 0x47 }, 1119 { WSA884X_OTP_PRG_END, 0x47 }, 1120 { WSA884X_WAVG_PLAY, 0x00 }, 1121 { WSA884X_WAVG_CTL, 0x06 }, 1122 { WSA884X_WAVG_LRA_PER_0, 0xd1 }, 1123 { WSA884X_WAVG_LRA_PER_1, 0x00 }, 1124 { WSA884X_WAVG_DELTA_THETA_0, 0xe6 }, 1125 { WSA884X_WAVG_DELTA_THETA_1, 0x04 }, 1126 { WSA884X_WAVG_DIRECT_AMP_0, 0x50 }, 1127 { WSA884X_WAVG_DIRECT_AMP_1, 0x00 }, 1128 { WSA884X_WAVG_PTRN_AMP0_0, 0x50 }, 1129 { WSA884X_WAVG_PTRN_AMP0_1, 0x00 }, 1130 { WSA884X_WAVG_PTRN_AMP1_0, 0x50 }, 1131 { WSA884X_WAVG_PTRN_AMP1_1, 0x00 }, 1132 { WSA884X_WAVG_PTRN_AMP2_0, 0x50 }, 1133 { WSA884X_WAVG_PTRN_AMP2_1, 0x00 }, 1134 { WSA884X_WAVG_PTRN_AMP3_0, 0x50 }, 1135 { WSA884X_WAVG_PTRN_AMP3_1, 0x00 }, 1136 { WSA884X_WAVG_PTRN_AMP4_0, 0x50 }, 1137 { WSA884X_WAVG_PTRN_AMP4_1, 0x00 }, 1138 { WSA884X_WAVG_PTRN_AMP5_0, 0x50 }, 1139 { WSA884X_WAVG_PTRN_AMP5_1, 0x00 }, 1140 { WSA884X_WAVG_PTRN_AMP6_0, 0x50 }, 1141 { WSA884X_WAVG_PTRN_AMP6_1, 0x00 }, 1142 { WSA884X_WAVG_PTRN_AMP7_0, 0x50 }, 1143 { WSA884X_WAVG_PTRN_AMP7_1, 0x00 }, 1144 { WSA884X_WAVG_PER_0_1, 0x88 }, 1145 { WSA884X_WAVG_PER_2_3, 0x88 }, 1146 { WSA884X_WAVG_PER_4_5, 0x88 }, 1147 { WSA884X_WAVG_PER_6_7, 0x88 }, 1148 { WSA884X_INTR_MODE, 0x00 }, 1149 { WSA884X_INTR_MASK0, 0x90 }, 1150 { WSA884X_INTR_MASK1, 0x00 }, 1151 { WSA884X_INTR_CLEAR0, 0x00 }, 1152 { WSA884X_INTR_CLEAR1, 0x00 }, 1153 { WSA884X_INTR_LEVEL0, 0x04 }, 1154 { WSA884X_INTR_LEVEL1, 0x00 }, 1155 { WSA884X_INTR_SET0, 0x00 }, 1156 { WSA884X_INTR_SET1, 0x00 }, 1157 { WSA884X_INTR_TEST0, 0x00 }, 1158 { WSA884X_INTR_TEST1, 0x00 }, 1159 { WSA884X_PDM_TEST_MODE, 0x00 }, 1160 { WSA884X_PA_FSM_DBG, 0x00 }, 1161 { WSA884X_DIG_DEBUG_MODE, 0x00 }, 1162 { WSA884X_DIG_DEBUG_SEL, 0x00 }, 1163 { WSA884X_DIG_DEBUG_EN, 0x00 }, 1164 { WSA884X_TADC_DETECT_DBG_CTL, 0x00 }, 1165 { WSA884X_TADC_DEBUG_MSB, 0x00 }, 1166 { WSA884X_TADC_DEBUG_LSB, 0x00 }, 1167 { WSA884X_SAMPLE_EDGE_SEL, 0x7f }, 1168 { WSA884X_SWR_EDGE_SEL, 0x00 }, 1169 { WSA884X_TEST_MODE_CTL, 0x05 }, 1170 { WSA884X_IOPAD_CTL, 0x00 }, 1171 { WSA884X_ANA_CSR_DBG_ADD, 0x00 }, 1172 { WSA884X_ANA_CSR_DBG_CTL, 0x12 }, 1173 { WSA884X_CLK_DBG_CTL, 0x00 }, 1174 { WSA884X_SPARE_0, 0x00 }, 1175 { WSA884X_SPARE_1, 0x00 }, 1176 { WSA884X_SPARE_2, 0x00 }, 1177 { WSA884X_SCODE, 0x00 }, 1178 { WSA884X_DIG_TRIM_PAGE, 0x00 }, 1179 { WSA884X_EMEM_0, 0x00 }, 1180 { WSA884X_EMEM_1, 0x00 }, 1181 { WSA884X_EMEM_2, 0x00 }, 1182 { WSA884X_EMEM_3, 0x00 }, 1183 { WSA884X_EMEM_4, 0x00 }, 1184 { WSA884X_EMEM_5, 0x00 }, 1185 { WSA884X_EMEM_6, 0x00 }, 1186 { WSA884X_EMEM_7, 0x00 }, 1187 { WSA884X_EMEM_8, 0x00 }, 1188 { WSA884X_EMEM_9, 0x00 }, 1189 { WSA884X_EMEM_10, 0x00 }, 1190 { WSA884X_EMEM_11, 0x00 }, 1191 { WSA884X_EMEM_12, 0x00 }, 1192 { WSA884X_EMEM_13, 0x00 }, 1193 { WSA884X_EMEM_14, 0x00 }, 1194 { WSA884X_EMEM_15, 0x00 }, 1195 { WSA884X_EMEM_16, 0x00 }, 1196 { WSA884X_EMEM_17, 0x00 }, 1197 { WSA884X_EMEM_18, 0x00 }, 1198 { WSA884X_EMEM_19, 0x00 }, 1199 { WSA884X_EMEM_20, 0x00 }, 1200 { WSA884X_EMEM_21, 0x00 }, 1201 { WSA884X_EMEM_22, 0x00 }, 1202 { WSA884X_EMEM_23, 0x00 }, 1203 { WSA884X_EMEM_24, 0x00 }, 1204 { WSA884X_EMEM_25, 0x00 }, 1205 { WSA884X_EMEM_26, 0x00 }, 1206 { WSA884X_EMEM_27, 0x00 }, 1207 { WSA884X_EMEM_28, 0x00 }, 1208 { WSA884X_EMEM_29, 0x00 }, 1209 { WSA884X_EMEM_30, 0x00 }, 1210 { WSA884X_EMEM_31, 0x00 }, 1211 { WSA884X_EMEM_32, 0x00 }, 1212 { WSA884X_EMEM_33, 0x00 }, 1213 { WSA884X_EMEM_34, 0x00 }, 1214 { WSA884X_EMEM_35, 0x00 }, 1215 { WSA884X_EMEM_36, 0x00 }, 1216 { WSA884X_EMEM_37, 0x00 }, 1217 { WSA884X_EMEM_38, 0x00 }, 1218 { WSA884X_EMEM_39, 0x00 }, 1219 { WSA884X_EMEM_40, 0x00 }, 1220 { WSA884X_EMEM_41, 0x00 }, 1221 { WSA884X_EMEM_42, 0x00 }, 1222 { WSA884X_EMEM_43, 0x00 }, 1223 { WSA884X_EMEM_44, 0x00 }, 1224 { WSA884X_EMEM_45, 0x00 }, 1225 { WSA884X_EMEM_46, 0x00 }, 1226 { WSA884X_EMEM_47, 0x00 }, 1227 { WSA884X_EMEM_48, 0x00 }, 1228 { WSA884X_EMEM_49, 0x00 }, 1229 { WSA884X_EMEM_50, 0x00 }, 1230 { WSA884X_EMEM_51, 0x00 }, 1231 { WSA884X_EMEM_52, 0x00 }, 1232 { WSA884X_EMEM_53, 0x00 }, 1233 { WSA884X_EMEM_54, 0x00 }, 1234 { WSA884X_EMEM_55, 0x00 }, 1235 { WSA884X_EMEM_56, 0x00 }, 1236 { WSA884X_EMEM_57, 0x00 }, 1237 { WSA884X_EMEM_58, 0x00 }, 1238 { WSA884X_EMEM_59, 0x00 }, 1239 { WSA884X_EMEM_60, 0x00 }, 1240 { WSA884X_EMEM_61, 0x00 }, 1241 { WSA884X_EMEM_62, 0x00 }, 1242 { WSA884X_EMEM_63, 0x00 }, 1243}; 1244 1245static bool wsa884x_readonly_register(struct device *dev, unsigned int reg) 1246{ 1247 switch (reg) { 1248 case WSA884X_DOUT_MSB: 1249 case WSA884X_DOUT_LSB: 1250 case WSA884X_STATUS: 1251 case WSA884X_SPK_TOP_SPARE_TUNE_2: 1252 case WSA884X_SPK_TOP_SPARE_TUNE_3: 1253 case WSA884X_SPK_TOP_SPARE_TUNE_4: 1254 case WSA884X_SPARE_TUNE_5: 1255 case WSA884X_SPARE_TUNE_6: 1256 case WSA884X_SPARE_TUNE_7: 1257 case WSA884X_SPARE_TUNE_8: 1258 case WSA884X_SPARE_TUNE_9: 1259 case WSA884X_SPARE_TUNE_10: 1260 case WSA884X_PA_STATUS0: 1261 case WSA884X_PA_STATUS1: 1262 case WSA884X_PA_STATUS2: 1263 case WSA884X_PA_STATUS3: 1264 case WSA884X_PA_STATUS4: 1265 case WSA884X_PA_STATUS5: 1266 case WSA884X_SPARE_RO_1: 1267 case WSA884X_SPARE_RO_2: 1268 case WSA884X_SPARE_RO_3: 1269 case WSA884X_SPARE_RO_0: 1270 case WSA884X_BOOST_SPARE_RO_1: 1271 case WSA884X_STATUS_0: 1272 case WSA884X_STATUS_1: 1273 case WSA884X_CHIP_ID0: 1274 case WSA884X_CHIP_ID1: 1275 case WSA884X_CHIP_ID2: 1276 case WSA884X_CHIP_ID3: 1277 case WSA884X_BUS_ID: 1278 case WSA884X_PA_FSM_STA0: 1279 case WSA884X_PA_FSM_STA1: 1280 case WSA884X_PA_FSM_ERR_COND0: 1281 case WSA884X_PA_FSM_ERR_COND1: 1282 case WSA884X_TEMP_DIN_MSB: 1283 case WSA884X_TEMP_DIN_LSB: 1284 case WSA884X_TEMP_DOUT_MSB: 1285 case WSA884X_TEMP_DOUT_LSB: 1286 case WSA884X_VBAT_DIN_MSB: 1287 case WSA884X_VBAT_DIN_LSB: 1288 case WSA884X_VBAT_DOUT_MSB: 1289 case WSA884X_VBAT_DOUT_LSB: 1290 case WSA884X_VBAT_CAL_MSB: 1291 case WSA884X_VBAT_CAL_LSB: 1292 case WSA884X_VPHX_SYS_EN_STATUS: 1293 case WSA884X_PIN_STATUS: 1294 case WSA884X_SWR_HM_TEST1: 1295 case WSA884X_OTP_CTRL1: 1296 case WSA884X_OTP_STAT: 1297 case WSA884X_WAVG_STA: 1298 case WSA884X_INTR_STATUS0: 1299 case WSA884X_INTR_STATUS1: 1300 case WSA884X_ATE_TEST_MODE: 1301 case WSA884X_SPARE_R: 1302 return true; 1303 } 1304 return false; 1305} 1306 1307static bool wsa884x_writeable_register(struct device *dev, unsigned int reg) 1308{ 1309 return !wsa884x_readonly_register(dev, reg); 1310} 1311 1312static bool wsa884x_volatile_register(struct device *dev, unsigned int reg) 1313{ 1314 switch (reg) { 1315 case WSA884X_ANA_WO_CTL_0: 1316 case WSA884X_ANA_WO_CTL_1: 1317 return true; 1318 } 1319 return wsa884x_readonly_register(dev, reg); 1320} 1321 1322static struct regmap_config wsa884x_regmap_config = { 1323 .reg_bits = 32, 1324 .val_bits = 8, 1325 .cache_type = REGCACHE_MAPLE, 1326 .reg_defaults = wsa884x_defaults, 1327 .max_register = WSA884X_MAX_REGISTER, 1328 .num_reg_defaults = ARRAY_SIZE(wsa884x_defaults), 1329 .volatile_reg = wsa884x_volatile_register, 1330 .writeable_reg = wsa884x_writeable_register, 1331 .reg_format_endian = REGMAP_ENDIAN_NATIVE, 1332 .val_format_endian = REGMAP_ENDIAN_NATIVE, 1333 .use_single_read = true, 1334}; 1335 1336static const struct reg_sequence wsa884x_reg_init[] = { 1337 { WSA884X_BOP2_PROG, FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_VTH_MASK, 0x6) | 1338 FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_HYST_MASK, 0x6) }, 1339 { WSA884X_REF_CTRL, (0xd2 & ~WSA884X_REF_CTRL_BG_RDY_SEL_MASK) | 1340 FIELD_PREP_CONST(WSA884X_REF_CTRL_BG_RDY_SEL_MASK, 0x1) }, 1341 /* 1342 * Downstream suggests for batteries different than 1-Stacked (1S): 1343 * { WSA884X_TOP_CTRL1, 0xd3 & ~WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK }, 1344 */ 1345 { WSA884X_STB_CTRL1, (0x42 & ~WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK) | 1346 FIELD_PREP_CONST(WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK, 0xd) }, 1347 { WSA884X_CURRENT_LIMIT, (0x54 & ~WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK) | 1348 FIELD_PREP_CONST(WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK, 0x9) }, 1349 { WSA884X_ZX_CTRL1, (0xf0 & ~WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK) | 1350 FIELD_PREP_CONST(WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK, 0x3) }, 1351 { WSA884X_ILIM_CTRL1, (0xe2 & ~WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK) | 1352 FIELD_PREP_CONST(WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK, 0x3) }, 1353 { WSA884X_CKWD_CTL_1, FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK, 0x0) | 1354 FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK, 0x13) }, 1355 { WSA884X_PA_FSM_CTL1, (0xfe & ~WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK) | 1356 FIELD_PREP_CONST(WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK, 0x4) }, /* == 0xfe */ 1357 { WSA884X_VBAT_THRM_FLT_CTL, (0x7f & ~WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK) | 1358 FIELD_PREP_CONST(WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK, 0x4) }, 1359 { WSA884X_VBAT_CAL_CTL, FIELD_PREP_CONST(WSA884X_VBAT_CAL_CTL_RESERVE_MASK, 0x2) | 1360 FIELD_PREP_CONST(WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK, 0x1) }, 1361 { WSA884X_BOP_DEGLITCH_CTL, FIELD_PREP_CONST(WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK, 0x8) | 1362 FIELD_PREP_CONST(WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK, 0x1) }, 1363 { WSA884X_CDC_SPK_DSM_A2_0, 0x0a }, 1364 { WSA884X_CDC_SPK_DSM_A2_1, 0x08 }, 1365 { WSA884X_CDC_SPK_DSM_A3_0, 0xf3 }, 1366 { WSA884X_CDC_SPK_DSM_A3_1, 0x07 }, 1367 { WSA884X_CDC_SPK_DSM_A4_0, 0x79 }, 1368 { WSA884X_CDC_SPK_DSM_A5_0, 0x0b }, 1369 { WSA884X_CDC_SPK_DSM_A6_0, 0x8a }, 1370 { WSA884X_CDC_SPK_DSM_A7_0, 0x9b }, 1371 { WSA884X_CDC_SPK_DSM_C_0, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK, 0x6) | 1372 FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK, 0x8) }, 1373 { WSA884X_CDC_SPK_DSM_C_2, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK, 0xf) }, 1374 { WSA884X_CDC_SPK_DSM_C_3, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK, 0x20) }, 1375 { WSA884X_CDC_SPK_DSM_R1, 0x83 }, 1376 { WSA884X_CDC_SPK_DSM_R2, 0x7f }, 1377 { WSA884X_CDC_SPK_DSM_R3, 0x9d }, 1378 { WSA884X_CDC_SPK_DSM_R4, 0x82 }, 1379 { WSA884X_CDC_SPK_DSM_R5, 0x8b }, 1380 { WSA884X_CDC_SPK_DSM_R6, 0x9b }, 1381 { WSA884X_CDC_SPK_DSM_R7, 0x3f }, 1382 /* Speaker mode by default */ 1383 { WSA884X_DRE_CTL_0, FIELD_PREP_CONST(WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0x7) }, 1384 { WSA884X_CLSH_CTL_0, (0x37 & ~WSA884X_CLSH_CTL_0_DLY_CODE_MASK) | 1385 FIELD_PREP_CONST(WSA884X_CLSH_CTL_0_DLY_CODE_MASK, 0x6) }, 1386 /* 1387 * WSA884X_CLSH_VTH values for speaker mode with G_21_DB system gain, 1388 * battery 1S and rload 8 Ohms. 1389 */ 1390 { WSA884X_CLSH_VTH1, WSA884X_VTH_TO_REG(863), }, 1391 { WSA884X_CLSH_VTH2, WSA884X_VTH_TO_REG(918), }, 1392 { WSA884X_CLSH_VTH3, WSA884X_VTH_TO_REG(980), }, 1393 { WSA884X_CLSH_VTH4, WSA884X_VTH_TO_REG(1043), }, 1394 { WSA884X_CLSH_VTH5, WSA884X_VTH_TO_REG(1098), }, 1395 { WSA884X_CLSH_VTH6, WSA884X_VTH_TO_REG(1137), }, 1396 { WSA884X_CLSH_VTH7, WSA884X_VTH_TO_REG(1184), }, 1397 { WSA884X_CLSH_VTH8, WSA884X_VTH_TO_REG(1239), }, 1398 { WSA884X_CLSH_VTH9, WSA884X_VTH_TO_REG(1278), }, 1399 { WSA884X_CLSH_VTH10, WSA884X_VTH_TO_REG(1380), }, 1400 { WSA884X_CLSH_VTH11, WSA884X_VTH_TO_REG(1482), }, 1401 { WSA884X_CLSH_VTH12, WSA884X_VTH_TO_REG(1584), }, 1402 { WSA884X_CLSH_VTH13, WSA884X_VTH_TO_REG(1663), }, 1403 { WSA884X_CLSH_VTH14, WSA884X_VTH_TO_REG(1780), }, 1404 { WSA884X_CLSH_VTH15, WSA884X_VTH_TO_REG(2000), }, 1405 { WSA884X_ANA_WO_CTL_1, 0x00 }, 1406 { WSA884X_OTP_REG_38, 0x00 }, 1407 { WSA884X_OTP_REG_40, FIELD_PREP_CONST(WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK, 0x8) }, 1408}; 1409 1410static void wsa884x_set_gain_parameters(struct wsa884x_priv *wsa884x) 1411{ 1412 struct regmap *regmap = wsa884x->regmap; 1413 unsigned int min_gain, igain, vgain, comp_offset; 1414 1415 /* 1416 * Downstream sets gain parameters customized per boards per use-case. 1417 * Choose here some sane values matching knowon users, like QRD8550 1418 * board:. 1419 * 1420 * Values match here downstream: 1421 * For WSA884X_RECEIVER - G_7P5_DB system gain 1422 * For WSA884X_SPEAKER - G_21_DB system gain 1423 */ 1424 if (wsa884x->dev_mode == WSA884X_RECEIVER) { 1425 comp_offset = COMP_OFFSET4; 1426 min_gain = G_M6_DB; 1427 igain = ISENSE_18_DB; 1428 vgain = VSENSE_M12_DB; 1429 } else { 1430 /* WSA884X_SPEAKER */ 1431 comp_offset = COMP_OFFSET0; 1432 min_gain = G_0_DB; 1433 igain = ISENSE_12_DB; 1434 vgain = VSENSE_M24_DB; 1435 } 1436 1437 regmap_update_bits(regmap, WSA884X_ISENSE2, 1438 WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK, 1439 FIELD_PREP(WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK, igain)); 1440 regmap_update_bits(regmap, WSA884X_VSENSE1, 1441 WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK, 1442 FIELD_PREP(WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK, vgain)); 1443 regmap_update_bits(regmap, WSA884X_GAIN_RAMPING_MIN, 1444 WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK, 1445 FIELD_PREP(WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK, min_gain)); 1446 1447 if (wsa884x->port_enable[WSA884X_PORT_COMP]) { 1448 regmap_update_bits(regmap, WSA884X_DRE_CTL_0, 1449 WSA884X_DRE_CTL_0_OFFSET_MASK, 1450 FIELD_PREP(WSA884X_DRE_CTL_0_OFFSET_MASK, comp_offset)); 1451 1452 regmap_update_bits(regmap, WSA884X_DRE_CTL_1, 1453 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 1454 FIELD_PREP(WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 0x0)); 1455 } else { 1456 regmap_update_bits(regmap, WSA884X_DRE_CTL_1, 1457 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 1458 FIELD_PREP(WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 0x1)); 1459 } 1460} 1461 1462static void wsa884x_init(struct wsa884x_priv *wsa884x) 1463{ 1464 unsigned int wo_ctl_0; 1465 unsigned int variant = 0; 1466 1467 if (!regmap_read(wsa884x->regmap, WSA884X_OTP_REG_0, &variant)) 1468 wsa884x->variant = variant & WSA884X_OTP_REG_0_ID_MASK; 1469 1470 regmap_multi_reg_write(wsa884x->regmap, wsa884x_reg_init, 1471 ARRAY_SIZE(wsa884x_reg_init)); 1472 1473 wo_ctl_0 = 0xc; 1474 wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK, 1475 WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER); 1476 /* Assume that compander is enabled by default unless it is haptics sku */ 1477 if (wsa884x->variant == WSA884X_OTP_ID_WSA8845H) 1478 wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK, 1479 WSA884X_ANA_WO_CTL_0_PA_AUX_18_DB); 1480 else 1481 wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK, 1482 WSA884X_ANA_WO_CTL_0_PA_AUX_0_DB); 1483 regmap_write(wsa884x->regmap, WSA884X_ANA_WO_CTL_0, wo_ctl_0); 1484 1485 wsa884x_set_gain_parameters(wsa884x); 1486 1487 wsa884x->hw_init = false; 1488} 1489 1490static int wsa884x_update_status(struct sdw_slave *slave, 1491 enum sdw_slave_status status) 1492{ 1493 struct wsa884x_priv *wsa884x = dev_get_drvdata(&slave->dev); 1494 int ret; 1495 1496 if (status == SDW_SLAVE_UNATTACHED) { 1497 wsa884x->hw_init = false; 1498 regcache_cache_only(wsa884x->regmap, true); 1499 regcache_mark_dirty(wsa884x->regmap); 1500 return 0; 1501 } 1502 1503 if (wsa884x->hw_init || status != SDW_SLAVE_ATTACHED) 1504 return 0; 1505 1506 regcache_cache_only(wsa884x->regmap, false); 1507 ret = regcache_sync(wsa884x->regmap); 1508 if (ret < 0) { 1509 dev_err(&slave->dev, "Cannot sync regmap cache\n"); 1510 return ret; 1511 } 1512 1513 wsa884x_init(wsa884x); 1514 1515 return 0; 1516} 1517 1518static int wsa884x_port_prep(struct sdw_slave *slave, 1519 struct sdw_prepare_ch *prepare_ch, 1520 enum sdw_port_prep_ops state) 1521{ 1522 struct wsa884x_priv *wsa884x = dev_get_drvdata(&slave->dev); 1523 1524 if (state == SDW_OPS_PORT_POST_PREP) 1525 wsa884x->port_prepared[prepare_ch->num - 1] = true; 1526 else 1527 wsa884x->port_prepared[prepare_ch->num - 1] = false; 1528 1529 return 0; 1530} 1531 1532static const struct sdw_slave_ops wsa884x_slave_ops = { 1533 .update_status = wsa884x_update_status, 1534 .port_prep = wsa884x_port_prep, 1535}; 1536 1537static int wsa884x_dev_mode_get(struct snd_kcontrol *kcontrol, 1538 struct snd_ctl_elem_value *ucontrol) 1539{ 1540 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1541 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component); 1542 1543 ucontrol->value.enumerated.item[0] = wsa884x->dev_mode; 1544 1545 return 0; 1546} 1547 1548static int wsa884x_dev_mode_put(struct snd_kcontrol *kcontrol, 1549 struct snd_ctl_elem_value *ucontrol) 1550{ 1551 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1552 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component); 1553 1554 if (wsa884x->dev_mode == ucontrol->value.enumerated.item[0]) 1555 return 0; 1556 1557 wsa884x->dev_mode = ucontrol->value.enumerated.item[0]; 1558 1559 return 1; 1560} 1561 1562static int wsa884x_get_swr_port(struct snd_kcontrol *kcontrol, 1563 struct snd_ctl_elem_value *ucontrol) 1564{ 1565 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1566 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp); 1567 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1568 int portidx = mixer->reg; 1569 1570 ucontrol->value.integer.value[0] = wsa884x->port_enable[portidx]; 1571 1572 return 0; 1573} 1574 1575static int wsa884x_set_swr_port(struct snd_kcontrol *kcontrol, 1576 struct snd_ctl_elem_value *ucontrol) 1577{ 1578 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1579 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp); 1580 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1581 int portidx = mixer->reg; 1582 1583 if (ucontrol->value.integer.value[0]) { 1584 if (wsa884x->port_enable[portidx]) 1585 return 0; 1586 1587 wsa884x->port_enable[portidx] = true; 1588 } else { 1589 if (!wsa884x->port_enable[portidx]) 1590 return 0; 1591 1592 wsa884x->port_enable[portidx] = false; 1593 } 1594 1595 return 1; 1596} 1597 1598static int wsa884x_codec_probe(struct snd_soc_component *comp) 1599{ 1600 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp); 1601 1602 snd_soc_component_init_regmap(comp, wsa884x->regmap); 1603 1604 return 0; 1605} 1606 1607static void wsa884x_spkr_post_pmu(struct snd_soc_component *component, 1608 struct wsa884x_priv *wsa884x) 1609{ 1610 unsigned int curr_limit, curr_ovrd_en; 1611 1612 wsa884x_set_gain_parameters(wsa884x); 1613 if (wsa884x->dev_mode == WSA884X_RECEIVER) { 1614 snd_soc_component_write_field(component, WSA884X_DRE_CTL_0, 1615 WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0x3); 1616 snd_soc_component_write_field(component, WSA884X_CDC_PATH_MODE, 1617 WSA884X_CDC_PATH_MODE_RXD_MODE_MASK, 1618 0x1); 1619 snd_soc_component_write_field(component, WSA884X_PWM_CLK_CTL, 1620 WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK, 1621 0x1); 1622 } else { 1623 /* WSA884X_SPEAKER */ 1624 snd_soc_component_write_field(component, WSA884X_DRE_CTL_0, 1625 WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0xf); 1626 } 1627 1628 if (wsa884x->port_enable[WSA884X_PORT_PBR]) { 1629 curr_ovrd_en = 0x0; 1630 curr_limit = 0x15; 1631 } else { 1632 curr_ovrd_en = 0x1; 1633 if (wsa884x->dev_mode == WSA884X_RECEIVER) 1634 curr_limit = 0x9; 1635 else 1636 curr_limit = 0x15; 1637 } 1638 snd_soc_component_write_field(component, WSA884X_CURRENT_LIMIT, 1639 WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK, 1640 curr_ovrd_en); 1641 snd_soc_component_write_field(component, WSA884X_CURRENT_LIMIT, 1642 WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK, 1643 curr_limit); 1644} 1645 1646static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w, 1647 struct snd_kcontrol *kcontrol, int event) 1648{ 1649 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1650 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component); 1651 1652 switch (event) { 1653 case SND_SOC_DAPM_POST_PMU: 1654 wsa884x_spkr_post_pmu(component, wsa884x); 1655 1656 snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL, 1657 WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK, 1658 0x1); 1659 1660 break; 1661 case SND_SOC_DAPM_PRE_PMD: 1662 snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL, 1663 WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK, 1664 0x0); 1665 break; 1666 } 1667 1668 return 0; 1669} 1670 1671static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = { 1672 SND_SOC_DAPM_INPUT("IN"), 1673 SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event), 1674}; 1675 1676static const DECLARE_TLV_DB_SCALE(pa_gain, -900, 150, -900); 1677 1678static const struct snd_kcontrol_new wsa884x_snd_controls[] = { 1679 SOC_SINGLE_RANGE_TLV("PA Volume", WSA884X_DRE_CTL_1, 1680 WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT, 1681 0x0, 0x1f, 1, pa_gain), 1682 SOC_ENUM_EXT("WSA MODE", wsa884x_dev_mode_enum, 1683 wsa884x_dev_mode_get, wsa884x_dev_mode_put), 1684 SOC_SINGLE_EXT("DAC Switch", WSA884X_PORT_DAC, 0, 1, 0, 1685 wsa884x_get_swr_port, wsa884x_set_swr_port), 1686 SOC_SINGLE_EXT("COMP Switch", WSA884X_PORT_COMP, 0, 1, 0, 1687 wsa884x_get_swr_port, wsa884x_set_swr_port), 1688 SOC_SINGLE_EXT("BOOST Switch", WSA884X_PORT_BOOST, 0, 1, 0, 1689 wsa884x_get_swr_port, wsa884x_set_swr_port), 1690 SOC_SINGLE_EXT("PBR Switch", WSA884X_PORT_PBR, 0, 1, 0, 1691 wsa884x_get_swr_port, wsa884x_set_swr_port), 1692 SOC_SINGLE_EXT("VISENSE Switch", WSA884X_PORT_VISENSE, 0, 1, 0, 1693 wsa884x_get_swr_port, wsa884x_set_swr_port), 1694 SOC_SINGLE_EXT("CPS Switch", WSA884X_PORT_CPS, 0, 1, 0, 1695 wsa884x_get_swr_port, wsa884x_set_swr_port), 1696}; 1697 1698static const struct snd_soc_dapm_route wsa884x_audio_map[] = { 1699 {"SPKR", NULL, "IN"}, 1700}; 1701 1702static const struct snd_soc_component_driver wsa884x_component_drv = { 1703 .name = "WSA884x", 1704 .probe = wsa884x_codec_probe, 1705 .controls = wsa884x_snd_controls, 1706 .num_controls = ARRAY_SIZE(wsa884x_snd_controls), 1707 .dapm_widgets = wsa884x_dapm_widgets, 1708 .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets), 1709 .dapm_routes = wsa884x_audio_map, 1710 .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map), 1711}; 1712 1713static int wsa884x_hw_params(struct snd_pcm_substream *substream, 1714 struct snd_pcm_hw_params *params, 1715 struct snd_soc_dai *dai) 1716{ 1717 struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev); 1718 int i; 1719 1720 wsa884x->active_ports = 0; 1721 for (i = 0; i < WSA884X_MAX_SWR_PORTS; i++) { 1722 if (!wsa884x->port_enable[i]) 1723 continue; 1724 1725 wsa884x->port_config[wsa884x->active_ports] = wsa884x_pconfig[i]; 1726 wsa884x->active_ports++; 1727 } 1728 1729 wsa884x->sconfig.frame_rate = params_rate(params); 1730 1731 return sdw_stream_add_slave(wsa884x->slave, &wsa884x->sconfig, 1732 wsa884x->port_config, wsa884x->active_ports, 1733 wsa884x->sruntime); 1734} 1735 1736static int wsa884x_hw_free(struct snd_pcm_substream *substream, 1737 struct snd_soc_dai *dai) 1738{ 1739 struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev); 1740 1741 sdw_stream_remove_slave(wsa884x->slave, wsa884x->sruntime); 1742 1743 return 0; 1744} 1745 1746static int wsa884x_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 1747{ 1748 struct snd_soc_component *component = dai->component; 1749 1750 if (mute) { 1751 snd_soc_component_write_field(component, WSA884X_DRE_CTL_1, 1752 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 1753 0x0); 1754 snd_soc_component_write_field(component, WSA884X_PA_FSM_EN, 1755 WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK, 1756 0x0); 1757 1758 } else { 1759 snd_soc_component_write_field(component, WSA884X_DRE_CTL_1, 1760 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 1761 0x1); 1762 snd_soc_component_write_field(component, WSA884X_PA_FSM_EN, 1763 WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK, 1764 0x1); 1765 } 1766 1767 return 0; 1768} 1769 1770static int wsa884x_set_stream(struct snd_soc_dai *dai, 1771 void *stream, int direction) 1772{ 1773 struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev); 1774 1775 wsa884x->sruntime = stream; 1776 1777 return 0; 1778} 1779 1780static const struct snd_soc_dai_ops wsa884x_dai_ops = { 1781 .hw_params = wsa884x_hw_params, 1782 .hw_free = wsa884x_hw_free, 1783 .mute_stream = wsa884x_mute_stream, 1784 .set_stream = wsa884x_set_stream, 1785 .mute_unmute_on_trigger = true, 1786}; 1787 1788static struct snd_soc_dai_driver wsa884x_dais[] = { 1789 { 1790 .name = "SPKR", 1791 .playback = { 1792 .stream_name = "SPKR Playback", 1793 .rates = WSA884X_RATES | WSA884X_FRAC_RATES, 1794 .formats = WSA884X_FORMATS, 1795 .rate_min = 8000, 1796 .rate_max = 384000, 1797 .channels_min = 1, 1798 .channels_max = 1, 1799 }, 1800 .ops = &wsa884x_dai_ops, 1801 }, 1802}; 1803 1804static void wsa884x_reset_powerdown(void *data) 1805{ 1806 struct wsa884x_priv *wsa884x = data; 1807 1808 if (wsa884x->sd_reset) 1809 reset_control_assert(wsa884x->sd_reset); 1810 else 1811 gpiod_direction_output(wsa884x->sd_n, 1); 1812} 1813 1814static void wsa884x_reset_deassert(struct wsa884x_priv *wsa884x) 1815{ 1816 if (wsa884x->sd_reset) 1817 reset_control_deassert(wsa884x->sd_reset); 1818 else 1819 gpiod_direction_output(wsa884x->sd_n, 0); 1820} 1821 1822static void wsa884x_regulator_disable(void *data) 1823{ 1824 regulator_bulk_disable(WSA884X_SUPPLIES_NUM, data); 1825} 1826 1827static int wsa884x_get_reset(struct device *dev, struct wsa884x_priv *wsa884x) 1828{ 1829 wsa884x->sd_reset = devm_reset_control_get_optional_shared(dev, NULL); 1830 if (IS_ERR(wsa884x->sd_reset)) 1831 return dev_err_probe(dev, PTR_ERR(wsa884x->sd_reset), 1832 "Failed to get reset\n"); 1833 else if (wsa884x->sd_reset) 1834 return 0; 1835 /* 1836 * else: NULL, so use the backwards compatible way for powerdown-gpios, 1837 * which does not handle sharing GPIO properly. 1838 */ 1839 wsa884x->sd_n = devm_gpiod_get_optional(dev, "powerdown", 1840 GPIOD_OUT_HIGH); 1841 if (IS_ERR(wsa884x->sd_n)) 1842 return dev_err_probe(dev, PTR_ERR(wsa884x->sd_n), 1843 "Shutdown Control GPIO not found\n"); 1844 1845 return 0; 1846} 1847 1848static int wsa884x_probe(struct sdw_slave *pdev, 1849 const struct sdw_device_id *id) 1850{ 1851 struct device *dev = &pdev->dev; 1852 struct wsa884x_priv *wsa884x; 1853 unsigned int i; 1854 int ret; 1855 1856 wsa884x = devm_kzalloc(dev, sizeof(*wsa884x), GFP_KERNEL); 1857 if (!wsa884x) 1858 return -ENOMEM; 1859 1860 for (i = 0; i < WSA884X_SUPPLIES_NUM; i++) 1861 wsa884x->supplies[i].supply = wsa884x_supply_name[i]; 1862 1863 ret = devm_regulator_bulk_get(dev, WSA884X_SUPPLIES_NUM, 1864 wsa884x->supplies); 1865 if (ret) 1866 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1867 1868 ret = regulator_bulk_enable(WSA884X_SUPPLIES_NUM, wsa884x->supplies); 1869 if (ret) 1870 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1871 1872 ret = devm_add_action_or_reset(dev, wsa884x_regulator_disable, 1873 wsa884x->supplies); 1874 if (ret) 1875 return ret; 1876 1877 ret = wsa884x_get_reset(dev, wsa884x); 1878 if (ret) 1879 return ret; 1880 1881 dev_set_drvdata(dev, wsa884x); 1882 wsa884x->slave = pdev; 1883 wsa884x->dev = dev; 1884 wsa884x->dev_mode = WSA884X_SPEAKER; 1885 wsa884x->sconfig.ch_count = 1; 1886 wsa884x->sconfig.bps = 1; 1887 wsa884x->sconfig.direction = SDW_DATA_DIR_RX; 1888 wsa884x->sconfig.type = SDW_STREAM_PDM; 1889 1890 pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS, 0); 1891 pdev->prop.simple_clk_stop_capable = true; 1892 pdev->prop.sink_dpn_prop = wsa884x_sink_dpn_prop; 1893 pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 1894 1895 wsa884x_reset_deassert(wsa884x); 1896 ret = devm_add_action_or_reset(dev, wsa884x_reset_powerdown, wsa884x); 1897 if (ret) 1898 return ret; 1899 1900 wsa884x->regmap = devm_regmap_init_sdw(pdev, &wsa884x_regmap_config); 1901 if (IS_ERR(wsa884x->regmap)) 1902 return dev_err_probe(dev, PTR_ERR(wsa884x->regmap), 1903 "regmap_init failed\n"); 1904 1905 /* Start in cache-only until device is enumerated */ 1906 regcache_cache_only(wsa884x->regmap, true); 1907 wsa884x->hw_init = true; 1908 1909 pm_runtime_set_autosuspend_delay(dev, 3000); 1910 pm_runtime_use_autosuspend(dev); 1911 pm_runtime_mark_last_busy(dev); 1912 pm_runtime_set_active(dev); 1913 pm_runtime_enable(dev); 1914 1915 return devm_snd_soc_register_component(dev, 1916 &wsa884x_component_drv, 1917 wsa884x_dais, 1918 ARRAY_SIZE(wsa884x_dais)); 1919} 1920 1921static int __maybe_unused wsa884x_runtime_suspend(struct device *dev) 1922{ 1923 struct regmap *regmap = dev_get_regmap(dev, NULL); 1924 1925 regcache_cache_only(regmap, true); 1926 regcache_mark_dirty(regmap); 1927 1928 return 0; 1929} 1930 1931static int __maybe_unused wsa884x_runtime_resume(struct device *dev) 1932{ 1933 struct regmap *regmap = dev_get_regmap(dev, NULL); 1934 1935 regcache_cache_only(regmap, false); 1936 regcache_sync(regmap); 1937 1938 return 0; 1939} 1940 1941static const struct dev_pm_ops wsa884x_pm_ops = { 1942 SET_RUNTIME_PM_OPS(wsa884x_runtime_suspend, wsa884x_runtime_resume, NULL) 1943}; 1944 1945static const struct sdw_device_id wsa884x_swr_id[] = { 1946 SDW_SLAVE_ENTRY(0x0217, 0x204, 0), 1947 {}, 1948}; 1949MODULE_DEVICE_TABLE(sdw, wsa884x_swr_id); 1950 1951static struct sdw_driver wsa884x_codec_driver = { 1952 .driver = { 1953 .name = "wsa884x-codec", 1954 .pm = &wsa884x_pm_ops, 1955 }, 1956 .probe = wsa884x_probe, 1957 .ops = &wsa884x_slave_ops, 1958 .id_table = wsa884x_swr_id, 1959}; 1960module_sdw_driver(wsa884x_codec_driver); 1961 1962MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>"); 1963MODULE_DESCRIPTION("WSA884x codec driver"); 1964MODULE_LICENSE("GPL"); 1965