1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * wm8985.h -- WM8985 ASoC driver 4 * 5 * Copyright 2010 Wolfson Microelectronics plc 6 * 7 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 8 */ 9 10#ifndef _WM8985_H 11#define _WM8985_H 12 13#define WM8985_SOFTWARE_RESET 0x00 14#define WM8985_POWER_MANAGEMENT_1 0x01 15#define WM8985_POWER_MANAGEMENT_2 0x02 16#define WM8985_POWER_MANAGEMENT_3 0x03 17#define WM8985_AUDIO_INTERFACE 0x04 18#define WM8985_COMPANDING_CONTROL 0x05 19#define WM8985_CLOCK_GEN_CONTROL 0x06 20#define WM8985_ADDITIONAL_CONTROL 0x07 21#define WM8985_GPIO_CONTROL 0x08 22#define WM8985_JACK_DETECT_CONTROL_1 0x09 23#define WM8985_DAC_CONTROL 0x0A 24#define WM8985_LEFT_DAC_DIGITAL_VOL 0x0B 25#define WM8985_RIGHT_DAC_DIGITAL_VOL 0x0C 26#define WM8985_JACK_DETECT_CONTROL_2 0x0D 27#define WM8985_ADC_CONTROL 0x0E 28#define WM8985_LEFT_ADC_DIGITAL_VOL 0x0F 29#define WM8985_RIGHT_ADC_DIGITAL_VOL 0x10 30#define WM8985_EQ1_LOW_SHELF 0x12 31#define WM8985_EQ2_PEAK_1 0x13 32#define WM8985_EQ3_PEAK_2 0x14 33#define WM8985_EQ4_PEAK_3 0x15 34#define WM8985_EQ5_HIGH_SHELF 0x16 35#define WM8985_DAC_LIMITER_1 0x18 36#define WM8985_DAC_LIMITER_2 0x19 37#define WM8985_NOTCH_FILTER_1 0x1B 38#define WM8985_NOTCH_FILTER_2 0x1C 39#define WM8985_NOTCH_FILTER_3 0x1D 40#define WM8985_NOTCH_FILTER_4 0x1E 41#define WM8985_ALC_CONTROL_1 0x20 42#define WM8985_ALC_CONTROL_2 0x21 43#define WM8985_ALC_CONTROL_3 0x22 44#define WM8985_NOISE_GATE 0x23 45#define WM8985_PLL_N 0x24 46#define WM8985_PLL_K_1 0x25 47#define WM8985_PLL_K_2 0x26 48#define WM8985_PLL_K_3 0x27 49#define WM8985_3D_CONTROL 0x29 50#define WM8985_OUT4_TO_ADC 0x2A 51#define WM8985_BEEP_CONTROL 0x2B 52#define WM8985_INPUT_CTRL 0x2C 53#define WM8985_LEFT_INP_PGA_GAIN_CTRL 0x2D 54#define WM8985_RIGHT_INP_PGA_GAIN_CTRL 0x2E 55#define WM8985_LEFT_ADC_BOOST_CTRL 0x2F 56#define WM8985_RIGHT_ADC_BOOST_CTRL 0x30 57#define WM8985_OUTPUT_CTRL0 0x31 58#define WM8985_LEFT_MIXER_CTRL 0x32 59#define WM8985_RIGHT_MIXER_CTRL 0x33 60#define WM8985_LOUT1_HP_VOLUME_CTRL 0x34 61#define WM8985_ROUT1_HP_VOLUME_CTRL 0x35 62#define WM8985_LOUT2_SPK_VOLUME_CTRL 0x36 63#define WM8985_ROUT2_SPK_VOLUME_CTRL 0x37 64#define WM8985_OUT3_MIXER_CTRL 0x38 65#define WM8985_OUT4_MONO_MIX_CTRL 0x39 66#define WM8985_OUTPUT_CTRL1 0x3C 67#define WM8985_BIAS_CTRL 0x3D 68 69#define WM8985_REGISTER_COUNT 59 70#define WM8985_MAX_REGISTER 0x3F 71 72/* 73 * Field Definitions. 74 */ 75 76/* 77 * R0 (0x00) - Software Reset 78 */ 79#define WM8985_SOFTWARE_RESET_MASK 0x01FF /* SOFTWARE_RESET - [8:0] */ 80#define WM8985_SOFTWARE_RESET_SHIFT 0 /* SOFTWARE_RESET - [8:0] */ 81#define WM8985_SOFTWARE_RESET_WIDTH 9 /* SOFTWARE_RESET - [8:0] */ 82 83/* 84 * R1 (0x01) - Power management 1 85 */ 86#define WM8985_OUT4MIXEN 0x0080 /* OUT4MIXEN */ 87#define WM8985_OUT4MIXEN_MASK 0x0080 /* OUT4MIXEN */ 88#define WM8985_OUT4MIXEN_SHIFT 7 /* OUT4MIXEN */ 89#define WM8985_OUT4MIXEN_WIDTH 1 /* OUT4MIXEN */ 90#define WM8985_OUT3MIXEN 0x0040 /* OUT3MIXEN */ 91#define WM8985_OUT3MIXEN_MASK 0x0040 /* OUT3MIXEN */ 92#define WM8985_OUT3MIXEN_SHIFT 6 /* OUT3MIXEN */ 93#define WM8985_OUT3MIXEN_WIDTH 1 /* OUT3MIXEN */ 94#define WM8985_PLLEN 0x0020 /* PLLEN */ 95#define WM8985_PLLEN_MASK 0x0020 /* PLLEN */ 96#define WM8985_PLLEN_SHIFT 5 /* PLLEN */ 97#define WM8985_PLLEN_WIDTH 1 /* PLLEN */ 98#define WM8985_MICBEN 0x0010 /* MICBEN */ 99#define WM8985_MICBEN_MASK 0x0010 /* MICBEN */ 100#define WM8985_MICBEN_SHIFT 4 /* MICBEN */ 101#define WM8985_MICBEN_WIDTH 1 /* MICBEN */ 102#define WM8985_BIASEN 0x0008 /* BIASEN */ 103#define WM8985_BIASEN_MASK 0x0008 /* BIASEN */ 104#define WM8985_BIASEN_SHIFT 3 /* BIASEN */ 105#define WM8985_BIASEN_WIDTH 1 /* BIASEN */ 106#define WM8985_BUFIOEN 0x0004 /* BUFIOEN */ 107#define WM8985_BUFIOEN_MASK 0x0004 /* BUFIOEN */ 108#define WM8985_BUFIOEN_SHIFT 2 /* BUFIOEN */ 109#define WM8985_BUFIOEN_WIDTH 1 /* BUFIOEN */ 110#define WM8985_VMIDSEL 0x0003 /* VMIDSEL */ 111#define WM8985_VMIDSEL_MASK 0x0003 /* VMIDSEL - [1:0] */ 112#define WM8985_VMIDSEL_SHIFT 0 /* VMIDSEL - [1:0] */ 113#define WM8985_VMIDSEL_WIDTH 2 /* VMIDSEL - [1:0] */ 114 115/* 116 * R2 (0x02) - Power management 2 117 */ 118#define WM8985_ROUT1EN 0x0100 /* ROUT1EN */ 119#define WM8985_ROUT1EN_MASK 0x0100 /* ROUT1EN */ 120#define WM8985_ROUT1EN_SHIFT 8 /* ROUT1EN */ 121#define WM8985_ROUT1EN_WIDTH 1 /* ROUT1EN */ 122#define WM8985_LOUT1EN 0x0080 /* LOUT1EN */ 123#define WM8985_LOUT1EN_MASK 0x0080 /* LOUT1EN */ 124#define WM8985_LOUT1EN_SHIFT 7 /* LOUT1EN */ 125#define WM8985_LOUT1EN_WIDTH 1 /* LOUT1EN */ 126#define WM8985_SLEEP 0x0040 /* SLEEP */ 127#define WM8985_SLEEP_MASK 0x0040 /* SLEEP */ 128#define WM8985_SLEEP_SHIFT 6 /* SLEEP */ 129#define WM8985_SLEEP_WIDTH 1 /* SLEEP */ 130#define WM8985_BOOSTENR 0x0020 /* BOOSTENR */ 131#define WM8985_BOOSTENR_MASK 0x0020 /* BOOSTENR */ 132#define WM8985_BOOSTENR_SHIFT 5 /* BOOSTENR */ 133#define WM8985_BOOSTENR_WIDTH 1 /* BOOSTENR */ 134#define WM8985_BOOSTENL 0x0010 /* BOOSTENL */ 135#define WM8985_BOOSTENL_MASK 0x0010 /* BOOSTENL */ 136#define WM8985_BOOSTENL_SHIFT 4 /* BOOSTENL */ 137#define WM8985_BOOSTENL_WIDTH 1 /* BOOSTENL */ 138#define WM8985_INPGAENR 0x0008 /* INPGAENR */ 139#define WM8985_INPGAENR_MASK 0x0008 /* INPGAENR */ 140#define WM8985_INPGAENR_SHIFT 3 /* INPGAENR */ 141#define WM8985_INPGAENR_WIDTH 1 /* INPGAENR */ 142#define WM8985_INPPGAENL 0x0004 /* INPPGAENL */ 143#define WM8985_INPPGAENL_MASK 0x0004 /* INPPGAENL */ 144#define WM8985_INPPGAENL_SHIFT 2 /* INPPGAENL */ 145#define WM8985_INPPGAENL_WIDTH 1 /* INPPGAENL */ 146#define WM8985_ADCENR 0x0002 /* ADCENR */ 147#define WM8985_ADCENR_MASK 0x0002 /* ADCENR */ 148#define WM8985_ADCENR_SHIFT 1 /* ADCENR */ 149#define WM8985_ADCENR_WIDTH 1 /* ADCENR */ 150#define WM8985_ADCENL 0x0001 /* ADCENL */ 151#define WM8985_ADCENL_MASK 0x0001 /* ADCENL */ 152#define WM8985_ADCENL_SHIFT 0 /* ADCENL */ 153#define WM8985_ADCENL_WIDTH 1 /* ADCENL */ 154 155/* 156 * R3 (0x03) - Power management 3 157 */ 158#define WM8985_OUT4EN 0x0100 /* OUT4EN */ 159#define WM8985_OUT4EN_MASK 0x0100 /* OUT4EN */ 160#define WM8985_OUT4EN_SHIFT 8 /* OUT4EN */ 161#define WM8985_OUT4EN_WIDTH 1 /* OUT4EN */ 162#define WM8985_OUT3EN 0x0080 /* OUT3EN */ 163#define WM8985_OUT3EN_MASK 0x0080 /* OUT3EN */ 164#define WM8985_OUT3EN_SHIFT 7 /* OUT3EN */ 165#define WM8985_OUT3EN_WIDTH 1 /* OUT3EN */ 166#define WM8985_ROUT2EN 0x0040 /* ROUT2EN */ 167#define WM8985_ROUT2EN_MASK 0x0040 /* ROUT2EN */ 168#define WM8985_ROUT2EN_SHIFT 6 /* ROUT2EN */ 169#define WM8985_ROUT2EN_WIDTH 1 /* ROUT2EN */ 170#define WM8985_LOUT2EN 0x0020 /* LOUT2EN */ 171#define WM8985_LOUT2EN_MASK 0x0020 /* LOUT2EN */ 172#define WM8985_LOUT2EN_SHIFT 5 /* LOUT2EN */ 173#define WM8985_LOUT2EN_WIDTH 1 /* LOUT2EN */ 174#define WM8985_RMIXEN 0x0008 /* RMIXEN */ 175#define WM8985_RMIXEN_MASK 0x0008 /* RMIXEN */ 176#define WM8985_RMIXEN_SHIFT 3 /* RMIXEN */ 177#define WM8985_RMIXEN_WIDTH 1 /* RMIXEN */ 178#define WM8985_LMIXEN 0x0004 /* LMIXEN */ 179#define WM8985_LMIXEN_MASK 0x0004 /* LMIXEN */ 180#define WM8985_LMIXEN_SHIFT 2 /* LMIXEN */ 181#define WM8985_LMIXEN_WIDTH 1 /* LMIXEN */ 182#define WM8985_DACENR 0x0002 /* DACENR */ 183#define WM8985_DACENR_MASK 0x0002 /* DACENR */ 184#define WM8985_DACENR_SHIFT 1 /* DACENR */ 185#define WM8985_DACENR_WIDTH 1 /* DACENR */ 186#define WM8985_DACENL 0x0001 /* DACENL */ 187#define WM8985_DACENL_MASK 0x0001 /* DACENL */ 188#define WM8985_DACENL_SHIFT 0 /* DACENL */ 189#define WM8985_DACENL_WIDTH 1 /* DACENL */ 190 191/* 192 * R4 (0x04) - Audio Interface 193 */ 194#define WM8985_BCP 0x0100 /* BCP */ 195#define WM8985_BCP_MASK 0x0100 /* BCP */ 196#define WM8985_BCP_SHIFT 8 /* BCP */ 197#define WM8985_BCP_WIDTH 1 /* BCP */ 198#define WM8985_LRP 0x0080 /* LRP */ 199#define WM8985_LRP_MASK 0x0080 /* LRP */ 200#define WM8985_LRP_SHIFT 7 /* LRP */ 201#define WM8985_LRP_WIDTH 1 /* LRP */ 202#define WM8985_WL_MASK 0x0060 /* WL - [6:5] */ 203#define WM8985_WL_SHIFT 5 /* WL - [6:5] */ 204#define WM8985_WL_WIDTH 2 /* WL - [6:5] */ 205#define WM8985_FMT_MASK 0x0018 /* FMT - [4:3] */ 206#define WM8985_FMT_SHIFT 3 /* FMT - [4:3] */ 207#define WM8985_FMT_WIDTH 2 /* FMT - [4:3] */ 208#define WM8985_DLRSWAP 0x0004 /* DLRSWAP */ 209#define WM8985_DLRSWAP_MASK 0x0004 /* DLRSWAP */ 210#define WM8985_DLRSWAP_SHIFT 2 /* DLRSWAP */ 211#define WM8985_DLRSWAP_WIDTH 1 /* DLRSWAP */ 212#define WM8985_ALRSWAP 0x0002 /* ALRSWAP */ 213#define WM8985_ALRSWAP_MASK 0x0002 /* ALRSWAP */ 214#define WM8985_ALRSWAP_SHIFT 1 /* ALRSWAP */ 215#define WM8985_ALRSWAP_WIDTH 1 /* ALRSWAP */ 216#define WM8985_MONO 0x0001 /* MONO */ 217#define WM8985_MONO_MASK 0x0001 /* MONO */ 218#define WM8985_MONO_SHIFT 0 /* MONO */ 219#define WM8985_MONO_WIDTH 1 /* MONO */ 220 221/* 222 * R5 (0x05) - Companding control 223 */ 224#define WM8985_WL8 0x0020 /* WL8 */ 225#define WM8985_WL8_MASK 0x0020 /* WL8 */ 226#define WM8985_WL8_SHIFT 5 /* WL8 */ 227#define WM8985_WL8_WIDTH 1 /* WL8 */ 228#define WM8985_DAC_COMP_MASK 0x0018 /* DAC_COMP - [4:3] */ 229#define WM8985_DAC_COMP_SHIFT 3 /* DAC_COMP - [4:3] */ 230#define WM8985_DAC_COMP_WIDTH 2 /* DAC_COMP - [4:3] */ 231#define WM8985_ADC_COMP_MASK 0x0006 /* ADC_COMP - [2:1] */ 232#define WM8985_ADC_COMP_SHIFT 1 /* ADC_COMP - [2:1] */ 233#define WM8985_ADC_COMP_WIDTH 2 /* ADC_COMP - [2:1] */ 234#define WM8985_LOOPBACK 0x0001 /* LOOPBACK */ 235#define WM8985_LOOPBACK_MASK 0x0001 /* LOOPBACK */ 236#define WM8985_LOOPBACK_SHIFT 0 /* LOOPBACK */ 237#define WM8985_LOOPBACK_WIDTH 1 /* LOOPBACK */ 238 239/* 240 * R6 (0x06) - Clock Gen control 241 */ 242#define WM8985_CLKSEL 0x0100 /* CLKSEL */ 243#define WM8985_CLKSEL_MASK 0x0100 /* CLKSEL */ 244#define WM8985_CLKSEL_SHIFT 8 /* CLKSEL */ 245#define WM8985_CLKSEL_WIDTH 1 /* CLKSEL */ 246#define WM8985_MCLKDIV_MASK 0x00E0 /* MCLKDIV - [7:5] */ 247#define WM8985_MCLKDIV_SHIFT 5 /* MCLKDIV - [7:5] */ 248#define WM8985_MCLKDIV_WIDTH 3 /* MCLKDIV - [7:5] */ 249#define WM8985_BCLKDIV_MASK 0x001C /* BCLKDIV - [4:2] */ 250#define WM8985_BCLKDIV_SHIFT 2 /* BCLKDIV - [4:2] */ 251#define WM8985_BCLKDIV_WIDTH 3 /* BCLKDIV - [4:2] */ 252#define WM8985_MS 0x0001 /* MS */ 253#define WM8985_MS_MASK 0x0001 /* MS */ 254#define WM8985_MS_SHIFT 0 /* MS */ 255#define WM8985_MS_WIDTH 1 /* MS */ 256 257/* 258 * R7 (0x07) - Additional control 259 */ 260#define WM8985_M128ENB 0x0100 /* M128ENB */ 261#define WM8985_M128ENB_MASK 0x0100 /* M128ENB */ 262#define WM8985_M128ENB_SHIFT 8 /* M128ENB */ 263#define WM8985_M128ENB_WIDTH 1 /* M128ENB */ 264#define WM8985_DCLKDIV_MASK 0x00F0 /* DCLKDIV - [7:4] */ 265#define WM8985_DCLKDIV_SHIFT 4 /* DCLKDIV - [7:4] */ 266#define WM8985_DCLKDIV_WIDTH 4 /* DCLKDIV - [7:4] */ 267#define WM8985_SR_MASK 0x000E /* SR - [3:1] */ 268#define WM8985_SR_SHIFT 1 /* SR - [3:1] */ 269#define WM8985_SR_WIDTH 3 /* SR - [3:1] */ 270#define WM8985_SLOWCLKEN 0x0001 /* SLOWCLKEN */ 271#define WM8985_SLOWCLKEN_MASK 0x0001 /* SLOWCLKEN */ 272#define WM8985_SLOWCLKEN_SHIFT 0 /* SLOWCLKEN */ 273#define WM8985_SLOWCLKEN_WIDTH 1 /* SLOWCLKEN */ 274 275/* 276 * R8 (0x08) - GPIO Control 277 */ 278#define WM8985_GPIO1GP 0x0100 /* GPIO1GP */ 279#define WM8985_GPIO1GP_MASK 0x0100 /* GPIO1GP */ 280#define WM8985_GPIO1GP_SHIFT 8 /* GPIO1GP */ 281#define WM8985_GPIO1GP_WIDTH 1 /* GPIO1GP */ 282#define WM8985_GPIO1GPU 0x0080 /* GPIO1GPU */ 283#define WM8985_GPIO1GPU_MASK 0x0080 /* GPIO1GPU */ 284#define WM8985_GPIO1GPU_SHIFT 7 /* GPIO1GPU */ 285#define WM8985_GPIO1GPU_WIDTH 1 /* GPIO1GPU */ 286#define WM8985_GPIO1GPD 0x0040 /* GPIO1GPD */ 287#define WM8985_GPIO1GPD_MASK 0x0040 /* GPIO1GPD */ 288#define WM8985_GPIO1GPD_SHIFT 6 /* GPIO1GPD */ 289#define WM8985_GPIO1GPD_WIDTH 1 /* GPIO1GPD */ 290#define WM8758_OPCLKDIV_MASK 0x0030 /* OPCLKDIV - [1:0] */ 291#define WM8758_OPCLKDIV_SHIFT 4 /* OPCLKDIV - [1:0] */ 292#define WM8758_OPCLKDIV_WIDTH 2 /* OPCLKDIV - [1:0] */ 293#define WM8985_GPIO1POL 0x0008 /* GPIO1POL */ 294#define WM8985_GPIO1POL_MASK 0x0008 /* GPIO1POL */ 295#define WM8985_GPIO1POL_SHIFT 3 /* GPIO1POL */ 296#define WM8985_GPIO1POL_WIDTH 1 /* GPIO1POL */ 297#define WM8985_GPIO1SEL_MASK 0x0007 /* GPIO1SEL - [2:0] */ 298#define WM8985_GPIO1SEL_SHIFT 0 /* GPIO1SEL - [2:0] */ 299#define WM8985_GPIO1SEL_WIDTH 3 /* GPIO1SEL - [2:0] */ 300 301/* 302 * R9 (0x09) - Jack Detect Control 1 303 */ 304#define WM8758_JD_VMID1_MASK 0x0100 /* JD_VMID1 */ 305#define WM8758_JD_VMID1_SHIFT 8 /* JD_VMID1 */ 306#define WM8758_JD_VMID1_WIDTH 1 /* JD_VMID1 */ 307#define WM8758_JD_VMID0_MASK 0x0080 /* JD_VMID0 */ 308#define WM8758_JD_VMID0_SHIFT 7 /* JD_VMID0 */ 309#define WM8758_JD_VMID0_WIDTH 1 /* JD_VMID0 */ 310#define WM8985_JD_EN 0x0040 /* JD_EN */ 311#define WM8985_JD_EN_MASK 0x0040 /* JD_EN */ 312#define WM8985_JD_EN_SHIFT 6 /* JD_EN */ 313#define WM8985_JD_EN_WIDTH 1 /* JD_EN */ 314#define WM8985_JD_SEL_MASK 0x0030 /* JD_SEL - [5:4] */ 315#define WM8985_JD_SEL_SHIFT 4 /* JD_SEL - [5:4] */ 316#define WM8985_JD_SEL_WIDTH 2 /* JD_SEL - [5:4] */ 317 318/* 319 * R10 (0x0A) - DAC Control 320 */ 321#define WM8985_SOFTMUTE 0x0040 /* SOFTMUTE */ 322#define WM8985_SOFTMUTE_MASK 0x0040 /* SOFTMUTE */ 323#define WM8985_SOFTMUTE_SHIFT 6 /* SOFTMUTE */ 324#define WM8985_SOFTMUTE_WIDTH 1 /* SOFTMUTE */ 325#define WM8985_DACOSR128 0x0008 /* DACOSR128 */ 326#define WM8985_DACOSR128_MASK 0x0008 /* DACOSR128 */ 327#define WM8985_DACOSR128_SHIFT 3 /* DACOSR128 */ 328#define WM8985_DACOSR128_WIDTH 1 /* DACOSR128 */ 329#define WM8985_AMUTE 0x0004 /* AMUTE */ 330#define WM8985_AMUTE_MASK 0x0004 /* AMUTE */ 331#define WM8985_AMUTE_SHIFT 2 /* AMUTE */ 332#define WM8985_AMUTE_WIDTH 1 /* AMUTE */ 333#define WM8985_DACPOLR 0x0002 /* DACPOLR */ 334#define WM8985_DACPOLR_MASK 0x0002 /* DACPOLR */ 335#define WM8985_DACPOLR_SHIFT 1 /* DACPOLR */ 336#define WM8985_DACPOLR_WIDTH 1 /* DACPOLR */ 337#define WM8985_DACPOLL 0x0001 /* DACPOLL */ 338#define WM8985_DACPOLL_MASK 0x0001 /* DACPOLL */ 339#define WM8985_DACPOLL_SHIFT 0 /* DACPOLL */ 340#define WM8985_DACPOLL_WIDTH 1 /* DACPOLL */ 341 342/* 343 * R11 (0x0B) - Left DAC digital Vol 344 */ 345#define WM8985_DACVU 0x0100 /* DACVU */ 346#define WM8985_DACVU_MASK 0x0100 /* DACVU */ 347#define WM8985_DACVU_SHIFT 8 /* DACVU */ 348#define WM8985_DACVU_WIDTH 1 /* DACVU */ 349#define WM8985_DACVOLL_MASK 0x00FF /* DACVOLL - [7:0] */ 350#define WM8985_DACVOLL_SHIFT 0 /* DACVOLL - [7:0] */ 351#define WM8985_DACVOLL_WIDTH 8 /* DACVOLL - [7:0] */ 352 353/* 354 * R12 (0x0C) - Right DAC digital vol 355 */ 356#define WM8985_DACVU 0x0100 /* DACVU */ 357#define WM8985_DACVU_MASK 0x0100 /* DACVU */ 358#define WM8985_DACVU_SHIFT 8 /* DACVU */ 359#define WM8985_DACVU_WIDTH 1 /* DACVU */ 360#define WM8985_DACVOLR_MASK 0x00FF /* DACVOLR - [7:0] */ 361#define WM8985_DACVOLR_SHIFT 0 /* DACVOLR - [7:0] */ 362#define WM8985_DACVOLR_WIDTH 8 /* DACVOLR - [7:0] */ 363 364/* 365 * R13 (0x0D) - Jack Detect Control 2 366 */ 367#define WM8985_JD_EN1_MASK 0x00F0 /* JD_EN1 - [7:4] */ 368#define WM8985_JD_EN1_SHIFT 4 /* JD_EN1 - [7:4] */ 369#define WM8985_JD_EN1_WIDTH 4 /* JD_EN1 - [7:4] */ 370#define WM8985_JD_EN0_MASK 0x000F /* JD_EN0 - [3:0] */ 371#define WM8985_JD_EN0_SHIFT 0 /* JD_EN0 - [3:0] */ 372#define WM8985_JD_EN0_WIDTH 4 /* JD_EN0 - [3:0] */ 373 374/* 375 * R14 (0x0E) - ADC Control 376 */ 377#define WM8985_HPFEN 0x0100 /* HPFEN */ 378#define WM8985_HPFEN_MASK 0x0100 /* HPFEN */ 379#define WM8985_HPFEN_SHIFT 8 /* HPFEN */ 380#define WM8985_HPFEN_WIDTH 1 /* HPFEN */ 381#define WM8985_HPFAPP 0x0080 /* HPFAPP */ 382#define WM8985_HPFAPP_MASK 0x0080 /* HPFAPP */ 383#define WM8985_HPFAPP_SHIFT 7 /* HPFAPP */ 384#define WM8985_HPFAPP_WIDTH 1 /* HPFAPP */ 385#define WM8985_HPFCUT_MASK 0x0070 /* HPFCUT - [6:4] */ 386#define WM8985_HPFCUT_SHIFT 4 /* HPFCUT - [6:4] */ 387#define WM8985_HPFCUT_WIDTH 3 /* HPFCUT - [6:4] */ 388#define WM8985_ADCOSR128 0x0008 /* ADCOSR128 */ 389#define WM8985_ADCOSR128_MASK 0x0008 /* ADCOSR128 */ 390#define WM8985_ADCOSR128_SHIFT 3 /* ADCOSR128 */ 391#define WM8985_ADCOSR128_WIDTH 1 /* ADCOSR128 */ 392#define WM8985_ADCRPOL 0x0002 /* ADCRPOL */ 393#define WM8985_ADCRPOL_MASK 0x0002 /* ADCRPOL */ 394#define WM8985_ADCRPOL_SHIFT 1 /* ADCRPOL */ 395#define WM8985_ADCRPOL_WIDTH 1 /* ADCRPOL */ 396#define WM8985_ADCLPOL 0x0001 /* ADCLPOL */ 397#define WM8985_ADCLPOL_MASK 0x0001 /* ADCLPOL */ 398#define WM8985_ADCLPOL_SHIFT 0 /* ADCLPOL */ 399#define WM8985_ADCLPOL_WIDTH 1 /* ADCLPOL */ 400 401/* 402 * R15 (0x0F) - Left ADC Digital Vol 403 */ 404#define WM8985_ADCVU 0x0100 /* ADCVU */ 405#define WM8985_ADCVU_MASK 0x0100 /* ADCVU */ 406#define WM8985_ADCVU_SHIFT 8 /* ADCVU */ 407#define WM8985_ADCVU_WIDTH 1 /* ADCVU */ 408#define WM8985_ADCVOLL_MASK 0x00FF /* ADCVOLL - [7:0] */ 409#define WM8985_ADCVOLL_SHIFT 0 /* ADCVOLL - [7:0] */ 410#define WM8985_ADCVOLL_WIDTH 8 /* ADCVOLL - [7:0] */ 411 412/* 413 * R16 (0x10) - Right ADC Digital Vol 414 */ 415#define WM8985_ADCVU 0x0100 /* ADCVU */ 416#define WM8985_ADCVU_MASK 0x0100 /* ADCVU */ 417#define WM8985_ADCVU_SHIFT 8 /* ADCVU */ 418#define WM8985_ADCVU_WIDTH 1 /* ADCVU */ 419#define WM8985_ADCVOLR_MASK 0x00FF /* ADCVOLR - [7:0] */ 420#define WM8985_ADCVOLR_SHIFT 0 /* ADCVOLR - [7:0] */ 421#define WM8985_ADCVOLR_WIDTH 8 /* ADCVOLR - [7:0] */ 422 423/* 424 * R18 (0x12) - EQ1 - low shelf 425 */ 426#define WM8985_EQ3DMODE 0x0100 /* EQ3DMODE */ 427#define WM8985_EQ3DMODE_MASK 0x0100 /* EQ3DMODE */ 428#define WM8985_EQ3DMODE_SHIFT 8 /* EQ3DMODE */ 429#define WM8985_EQ3DMODE_WIDTH 1 /* EQ3DMODE */ 430#define WM8985_EQ1C_MASK 0x0060 /* EQ1C - [6:5] */ 431#define WM8985_EQ1C_SHIFT 5 /* EQ1C - [6:5] */ 432#define WM8985_EQ1C_WIDTH 2 /* EQ1C - [6:5] */ 433#define WM8985_EQ1G_MASK 0x001F /* EQ1G - [4:0] */ 434#define WM8985_EQ1G_SHIFT 0 /* EQ1G - [4:0] */ 435#define WM8985_EQ1G_WIDTH 5 /* EQ1G - [4:0] */ 436 437/* 438 * R19 (0x13) - EQ2 - peak 1 439 */ 440#define WM8985_EQ2BW 0x0100 /* EQ2BW */ 441#define WM8985_EQ2BW_MASK 0x0100 /* EQ2BW */ 442#define WM8985_EQ2BW_SHIFT 8 /* EQ2BW */ 443#define WM8985_EQ2BW_WIDTH 1 /* EQ2BW */ 444#define WM8985_EQ2C_MASK 0x0060 /* EQ2C - [6:5] */ 445#define WM8985_EQ2C_SHIFT 5 /* EQ2C - [6:5] */ 446#define WM8985_EQ2C_WIDTH 2 /* EQ2C - [6:5] */ 447#define WM8985_EQ2G_MASK 0x001F /* EQ2G - [4:0] */ 448#define WM8985_EQ2G_SHIFT 0 /* EQ2G - [4:0] */ 449#define WM8985_EQ2G_WIDTH 5 /* EQ2G - [4:0] */ 450 451/* 452 * R20 (0x14) - EQ3 - peak 2 453 */ 454#define WM8985_EQ3BW 0x0100 /* EQ3BW */ 455#define WM8985_EQ3BW_MASK 0x0100 /* EQ3BW */ 456#define WM8985_EQ3BW_SHIFT 8 /* EQ3BW */ 457#define WM8985_EQ3BW_WIDTH 1 /* EQ3BW */ 458#define WM8985_EQ3C_MASK 0x0060 /* EQ3C - [6:5] */ 459#define WM8985_EQ3C_SHIFT 5 /* EQ3C - [6:5] */ 460#define WM8985_EQ3C_WIDTH 2 /* EQ3C - [6:5] */ 461#define WM8985_EQ3G_MASK 0x001F /* EQ3G - [4:0] */ 462#define WM8985_EQ3G_SHIFT 0 /* EQ3G - [4:0] */ 463#define WM8985_EQ3G_WIDTH 5 /* EQ3G - [4:0] */ 464 465/* 466 * R21 (0x15) - EQ4 - peak 3 467 */ 468#define WM8985_EQ4BW 0x0100 /* EQ4BW */ 469#define WM8985_EQ4BW_MASK 0x0100 /* EQ4BW */ 470#define WM8985_EQ4BW_SHIFT 8 /* EQ4BW */ 471#define WM8985_EQ4BW_WIDTH 1 /* EQ4BW */ 472#define WM8985_EQ4C_MASK 0x0060 /* EQ4C - [6:5] */ 473#define WM8985_EQ4C_SHIFT 5 /* EQ4C - [6:5] */ 474#define WM8985_EQ4C_WIDTH 2 /* EQ4C - [6:5] */ 475#define WM8985_EQ4G_MASK 0x001F /* EQ4G - [4:0] */ 476#define WM8985_EQ4G_SHIFT 0 /* EQ4G - [4:0] */ 477#define WM8985_EQ4G_WIDTH 5 /* EQ4G - [4:0] */ 478 479/* 480 * R22 (0x16) - EQ5 - high shelf 481 */ 482#define WM8985_EQ5C_MASK 0x0060 /* EQ5C - [6:5] */ 483#define WM8985_EQ5C_SHIFT 5 /* EQ5C - [6:5] */ 484#define WM8985_EQ5C_WIDTH 2 /* EQ5C - [6:5] */ 485#define WM8985_EQ5G_MASK 0x001F /* EQ5G - [4:0] */ 486#define WM8985_EQ5G_SHIFT 0 /* EQ5G - [4:0] */ 487#define WM8985_EQ5G_WIDTH 5 /* EQ5G - [4:0] */ 488 489/* 490 * R24 (0x18) - DAC Limiter 1 491 */ 492#define WM8985_LIMEN 0x0100 /* LIMEN */ 493#define WM8985_LIMEN_MASK 0x0100 /* LIMEN */ 494#define WM8985_LIMEN_SHIFT 8 /* LIMEN */ 495#define WM8985_LIMEN_WIDTH 1 /* LIMEN */ 496#define WM8985_LIMDCY_MASK 0x00F0 /* LIMDCY - [7:4] */ 497#define WM8985_LIMDCY_SHIFT 4 /* LIMDCY - [7:4] */ 498#define WM8985_LIMDCY_WIDTH 4 /* LIMDCY - [7:4] */ 499#define WM8985_LIMATK_MASK 0x000F /* LIMATK - [3:0] */ 500#define WM8985_LIMATK_SHIFT 0 /* LIMATK - [3:0] */ 501#define WM8985_LIMATK_WIDTH 4 /* LIMATK - [3:0] */ 502 503/* 504 * R25 (0x19) - DAC Limiter 2 505 */ 506#define WM8985_LIMLVL_MASK 0x0070 /* LIMLVL - [6:4] */ 507#define WM8985_LIMLVL_SHIFT 4 /* LIMLVL - [6:4] */ 508#define WM8985_LIMLVL_WIDTH 3 /* LIMLVL - [6:4] */ 509#define WM8985_LIMBOOST_MASK 0x000F /* LIMBOOST - [3:0] */ 510#define WM8985_LIMBOOST_SHIFT 0 /* LIMBOOST - [3:0] */ 511#define WM8985_LIMBOOST_WIDTH 4 /* LIMBOOST - [3:0] */ 512 513/* 514 * R27 (0x1B) - Notch Filter 1 515 */ 516#define WM8985_NFU 0x0100 /* NFU */ 517#define WM8985_NFU_MASK 0x0100 /* NFU */ 518#define WM8985_NFU_SHIFT 8 /* NFU */ 519#define WM8985_NFU_WIDTH 1 /* NFU */ 520#define WM8985_NFEN 0x0080 /* NFEN */ 521#define WM8985_NFEN_MASK 0x0080 /* NFEN */ 522#define WM8985_NFEN_SHIFT 7 /* NFEN */ 523#define WM8985_NFEN_WIDTH 1 /* NFEN */ 524#define WM8985_NFA0_13_7_MASK 0x007F /* NFA0(13:7) - [6:0] */ 525#define WM8985_NFA0_13_7_SHIFT 0 /* NFA0(13:7) - [6:0] */ 526#define WM8985_NFA0_13_7_WIDTH 7 /* NFA0(13:7) - [6:0] */ 527 528/* 529 * R28 (0x1C) - Notch Filter 2 530 */ 531#define WM8985_NFU 0x0100 /* NFU */ 532#define WM8985_NFU_MASK 0x0100 /* NFU */ 533#define WM8985_NFU_SHIFT 8 /* NFU */ 534#define WM8985_NFU_WIDTH 1 /* NFU */ 535#define WM8985_NFA0_6_0_MASK 0x007F /* NFA0(6:0) - [6:0] */ 536#define WM8985_NFA0_6_0_SHIFT 0 /* NFA0(6:0) - [6:0] */ 537#define WM8985_NFA0_6_0_WIDTH 7 /* NFA0(6:0) - [6:0] */ 538 539/* 540 * R29 (0x1D) - Notch Filter 3 541 */ 542#define WM8985_NFU 0x0100 /* NFU */ 543#define WM8985_NFU_MASK 0x0100 /* NFU */ 544#define WM8985_NFU_SHIFT 8 /* NFU */ 545#define WM8985_NFU_WIDTH 1 /* NFU */ 546#define WM8985_NFA1_13_7_MASK 0x007F /* NFA1(13:7) - [6:0] */ 547#define WM8985_NFA1_13_7_SHIFT 0 /* NFA1(13:7) - [6:0] */ 548#define WM8985_NFA1_13_7_WIDTH 7 /* NFA1(13:7) - [6:0] */ 549 550/* 551 * R30 (0x1E) - Notch Filter 4 552 */ 553#define WM8985_NFU 0x0100 /* NFU */ 554#define WM8985_NFU_MASK 0x0100 /* NFU */ 555#define WM8985_NFU_SHIFT 8 /* NFU */ 556#define WM8985_NFU_WIDTH 1 /* NFU */ 557#define WM8985_NFA1_6_0_MASK 0x007F /* NFA1(6:0) - [6:0] */ 558#define WM8985_NFA1_6_0_SHIFT 0 /* NFA1(6:0) - [6:0] */ 559#define WM8985_NFA1_6_0_WIDTH 7 /* NFA1(6:0) - [6:0] */ 560 561/* 562 * R32 (0x20) - ALC control 1 563 */ 564#define WM8985_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */ 565#define WM8985_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */ 566#define WM8985_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */ 567#define WM8985_ALCMAX_MASK 0x0038 /* ALCMAX - [5:3] */ 568#define WM8985_ALCMAX_SHIFT 3 /* ALCMAX - [5:3] */ 569#define WM8985_ALCMAX_WIDTH 3 /* ALCMAX - [5:3] */ 570#define WM8985_ALCMIN_MASK 0x0007 /* ALCMIN - [2:0] */ 571#define WM8985_ALCMIN_SHIFT 0 /* ALCMIN - [2:0] */ 572#define WM8985_ALCMIN_WIDTH 3 /* ALCMIN - [2:0] */ 573 574/* 575 * R33 (0x21) - ALC control 2 576 */ 577#define WM8985_ALCHLD_MASK 0x00F0 /* ALCHLD - [7:4] */ 578#define WM8985_ALCHLD_SHIFT 4 /* ALCHLD - [7:4] */ 579#define WM8985_ALCHLD_WIDTH 4 /* ALCHLD - [7:4] */ 580#define WM8985_ALCLVL_MASK 0x000F /* ALCLVL - [3:0] */ 581#define WM8985_ALCLVL_SHIFT 0 /* ALCLVL - [3:0] */ 582#define WM8985_ALCLVL_WIDTH 4 /* ALCLVL - [3:0] */ 583 584/* 585 * R34 (0x22) - ALC control 3 586 */ 587#define WM8985_ALCMODE 0x0100 /* ALCMODE */ 588#define WM8985_ALCMODE_MASK 0x0100 /* ALCMODE */ 589#define WM8985_ALCMODE_SHIFT 8 /* ALCMODE */ 590#define WM8985_ALCMODE_WIDTH 1 /* ALCMODE */ 591#define WM8985_ALCDCY_MASK 0x00F0 /* ALCDCY - [7:4] */ 592#define WM8985_ALCDCY_SHIFT 4 /* ALCDCY - [7:4] */ 593#define WM8985_ALCDCY_WIDTH 4 /* ALCDCY - [7:4] */ 594#define WM8985_ALCATK_MASK 0x000F /* ALCATK - [3:0] */ 595#define WM8985_ALCATK_SHIFT 0 /* ALCATK - [3:0] */ 596#define WM8985_ALCATK_WIDTH 4 /* ALCATK - [3:0] */ 597 598/* 599 * R35 (0x23) - Noise Gate 600 */ 601#define WM8985_NGEN 0x0008 /* NGEN */ 602#define WM8985_NGEN_MASK 0x0008 /* NGEN */ 603#define WM8985_NGEN_SHIFT 3 /* NGEN */ 604#define WM8985_NGEN_WIDTH 1 /* NGEN */ 605#define WM8985_NGTH_MASK 0x0007 /* NGTH - [2:0] */ 606#define WM8985_NGTH_SHIFT 0 /* NGTH - [2:0] */ 607#define WM8985_NGTH_WIDTH 3 /* NGTH - [2:0] */ 608 609/* 610 * R36 (0x24) - PLL N 611 */ 612#define WM8985_PLL_PRESCALE 0x0010 /* PLL_PRESCALE */ 613#define WM8985_PLL_PRESCALE_MASK 0x0010 /* PLL_PRESCALE */ 614#define WM8985_PLL_PRESCALE_SHIFT 4 /* PLL_PRESCALE */ 615#define WM8985_PLL_PRESCALE_WIDTH 1 /* PLL_PRESCALE */ 616#define WM8985_PLLN_MASK 0x000F /* PLLN - [3:0] */ 617#define WM8985_PLLN_SHIFT 0 /* PLLN - [3:0] */ 618#define WM8985_PLLN_WIDTH 4 /* PLLN - [3:0] */ 619 620/* 621 * R37 (0x25) - PLL K 1 622 */ 623#define WM8985_PLLK_23_18_MASK 0x003F /* PLLK(23:18) - [5:0] */ 624#define WM8985_PLLK_23_18_SHIFT 0 /* PLLK(23:18) - [5:0] */ 625#define WM8985_PLLK_23_18_WIDTH 6 /* PLLK(23:18) - [5:0] */ 626 627/* 628 * R38 (0x26) - PLL K 2 629 */ 630#define WM8985_PLLK_17_9_MASK 0x01FF /* PLLK(17:9) - [8:0] */ 631#define WM8985_PLLK_17_9_SHIFT 0 /* PLLK(17:9) - [8:0] */ 632#define WM8985_PLLK_17_9_WIDTH 9 /* PLLK(17:9) - [8:0] */ 633 634/* 635 * R39 (0x27) - PLL K 3 636 */ 637#define WM8985_PLLK_8_0_MASK 0x01FF /* PLLK(8:0) - [8:0] */ 638#define WM8985_PLLK_8_0_SHIFT 0 /* PLLK(8:0) - [8:0] */ 639#define WM8985_PLLK_8_0_WIDTH 9 /* PLLK(8:0) - [8:0] */ 640 641/* 642 * R41 (0x29) - 3D control 643 */ 644#define WM8985_DEPTH3D_MASK 0x000F /* DEPTH3D - [3:0] */ 645#define WM8985_DEPTH3D_SHIFT 0 /* DEPTH3D - [3:0] */ 646#define WM8985_DEPTH3D_WIDTH 4 /* DEPTH3D - [3:0] */ 647 648/* 649 * R42 (0x2A) - OUT4 to ADC 650 */ 651#define WM8985_OUT4_2ADCVOL_MASK 0x01C0 /* OUT4_2ADCVOL - [8:6] */ 652#define WM8985_OUT4_2ADCVOL_SHIFT 6 /* OUT4_2ADCVOL - [8:6] */ 653#define WM8985_OUT4_2ADCVOL_WIDTH 3 /* OUT4_2ADCVOL - [8:6] */ 654#define WM8985_OUT4_2LNR 0x0020 /* OUT4_2LNR */ 655#define WM8985_OUT4_2LNR_MASK 0x0020 /* OUT4_2LNR */ 656#define WM8985_OUT4_2LNR_SHIFT 5 /* OUT4_2LNR */ 657#define WM8985_OUT4_2LNR_WIDTH 1 /* OUT4_2LNR */ 658#define WM8758_VMIDTOG_MASK 0x0010 /* VMIDTOG */ 659#define WM8758_VMIDTOG_SHIFT 4 /* VMIDTOG */ 660#define WM8758_VMIDTOG_WIDTH 1 /* VMIDTOG */ 661#define WM8758_OUT2DEL_MASK 0x0008 /* OUT2DEL */ 662#define WM8758_OUT2DEL_SHIFT 3 /* OUT2DEL */ 663#define WM8758_OUT2DEL_WIDTH 1 /* OUT2DEL */ 664#define WM8985_POBCTRL 0x0004 /* POBCTRL */ 665#define WM8985_POBCTRL_MASK 0x0004 /* POBCTRL */ 666#define WM8985_POBCTRL_SHIFT 2 /* POBCTRL */ 667#define WM8985_POBCTRL_WIDTH 1 /* POBCTRL */ 668#define WM8985_DELEN 0x0002 /* DELEN */ 669#define WM8985_DELEN_MASK 0x0002 /* DELEN */ 670#define WM8985_DELEN_SHIFT 1 /* DELEN */ 671#define WM8985_DELEN_WIDTH 1 /* DELEN */ 672#define WM8985_OUT1DEL 0x0001 /* OUT1DEL */ 673#define WM8985_OUT1DEL_MASK 0x0001 /* OUT1DEL */ 674#define WM8985_OUT1DEL_SHIFT 0 /* OUT1DEL */ 675#define WM8985_OUT1DEL_WIDTH 1 /* OUT1DEL */ 676 677/* 678 * R43 (0x2B) - Beep control 679 */ 680#define WM8985_BYPL2RMIX 0x0100 /* BYPL2RMIX */ 681#define WM8985_BYPL2RMIX_MASK 0x0100 /* BYPL2RMIX */ 682#define WM8985_BYPL2RMIX_SHIFT 8 /* BYPL2RMIX */ 683#define WM8985_BYPL2RMIX_WIDTH 1 /* BYPL2RMIX */ 684#define WM8985_BYPR2LMIX 0x0080 /* BYPR2LMIX */ 685#define WM8985_BYPR2LMIX_MASK 0x0080 /* BYPR2LMIX */ 686#define WM8985_BYPR2LMIX_SHIFT 7 /* BYPR2LMIX */ 687#define WM8985_BYPR2LMIX_WIDTH 1 /* BYPR2LMIX */ 688#define WM8985_MUTERPGA2INV 0x0020 /* MUTERPGA2INV */ 689#define WM8985_MUTERPGA2INV_MASK 0x0020 /* MUTERPGA2INV */ 690#define WM8985_MUTERPGA2INV_SHIFT 5 /* MUTERPGA2INV */ 691#define WM8985_MUTERPGA2INV_WIDTH 1 /* MUTERPGA2INV */ 692#define WM8985_INVROUT2 0x0010 /* INVROUT2 */ 693#define WM8985_INVROUT2_MASK 0x0010 /* INVROUT2 */ 694#define WM8985_INVROUT2_SHIFT 4 /* INVROUT2 */ 695#define WM8985_INVROUT2_WIDTH 1 /* INVROUT2 */ 696#define WM8985_BEEPVOL_MASK 0x000E /* BEEPVOL - [3:1] */ 697#define WM8985_BEEPVOL_SHIFT 1 /* BEEPVOL - [3:1] */ 698#define WM8985_BEEPVOL_WIDTH 3 /* BEEPVOL - [3:1] */ 699#define WM8758_DELEN2_MASK 0x0004 /* DELEN2 */ 700#define WM8758_DELEN2_SHIFT 2 /* DELEN2 */ 701#define WM8758_DELEN2_WIDTH 1 /* DELEN2 */ 702#define WM8985_BEEPEN 0x0001 /* BEEPEN */ 703#define WM8985_BEEPEN_MASK 0x0001 /* BEEPEN */ 704#define WM8985_BEEPEN_SHIFT 0 /* BEEPEN */ 705#define WM8985_BEEPEN_WIDTH 1 /* BEEPEN */ 706 707/* 708 * R44 (0x2C) - Input ctrl 709 */ 710#define WM8985_MBVSEL 0x0100 /* MBVSEL */ 711#define WM8985_MBVSEL_MASK 0x0100 /* MBVSEL */ 712#define WM8985_MBVSEL_SHIFT 8 /* MBVSEL */ 713#define WM8985_MBVSEL_WIDTH 1 /* MBVSEL */ 714#define WM8985_R2_2INPPGA 0x0040 /* R2_2INPPGA */ 715#define WM8985_R2_2INPPGA_MASK 0x0040 /* R2_2INPPGA */ 716#define WM8985_R2_2INPPGA_SHIFT 6 /* R2_2INPPGA */ 717#define WM8985_R2_2INPPGA_WIDTH 1 /* R2_2INPPGA */ 718#define WM8985_RIN2INPPGA 0x0020 /* RIN2INPPGA */ 719#define WM8985_RIN2INPPGA_MASK 0x0020 /* RIN2INPPGA */ 720#define WM8985_RIN2INPPGA_SHIFT 5 /* RIN2INPPGA */ 721#define WM8985_RIN2INPPGA_WIDTH 1 /* RIN2INPPGA */ 722#define WM8985_RIP2INPPGA 0x0010 /* RIP2INPPGA */ 723#define WM8985_RIP2INPPGA_MASK 0x0010 /* RIP2INPPGA */ 724#define WM8985_RIP2INPPGA_SHIFT 4 /* RIP2INPPGA */ 725#define WM8985_RIP2INPPGA_WIDTH 1 /* RIP2INPPGA */ 726#define WM8985_L2_2INPPGA 0x0004 /* L2_2INPPGA */ 727#define WM8985_L2_2INPPGA_MASK 0x0004 /* L2_2INPPGA */ 728#define WM8985_L2_2INPPGA_SHIFT 2 /* L2_2INPPGA */ 729#define WM8985_L2_2INPPGA_WIDTH 1 /* L2_2INPPGA */ 730#define WM8985_LIN2INPPGA 0x0002 /* LIN2INPPGA */ 731#define WM8985_LIN2INPPGA_MASK 0x0002 /* LIN2INPPGA */ 732#define WM8985_LIN2INPPGA_SHIFT 1 /* LIN2INPPGA */ 733#define WM8985_LIN2INPPGA_WIDTH 1 /* LIN2INPPGA */ 734#define WM8985_LIP2INPPGA 0x0001 /* LIP2INPPGA */ 735#define WM8985_LIP2INPPGA_MASK 0x0001 /* LIP2INPPGA */ 736#define WM8985_LIP2INPPGA_SHIFT 0 /* LIP2INPPGA */ 737#define WM8985_LIP2INPPGA_WIDTH 1 /* LIP2INPPGA */ 738 739/* 740 * R45 (0x2D) - Left INP PGA gain ctrl 741 */ 742#define WM8985_INPGAVU 0x0100 /* INPGAVU */ 743#define WM8985_INPGAVU_MASK 0x0100 /* INPGAVU */ 744#define WM8985_INPGAVU_SHIFT 8 /* INPGAVU */ 745#define WM8985_INPGAVU_WIDTH 1 /* INPGAVU */ 746#define WM8985_INPPGAZCL 0x0080 /* INPPGAZCL */ 747#define WM8985_INPPGAZCL_MASK 0x0080 /* INPPGAZCL */ 748#define WM8985_INPPGAZCL_SHIFT 7 /* INPPGAZCL */ 749#define WM8985_INPPGAZCL_WIDTH 1 /* INPPGAZCL */ 750#define WM8985_INPPGAMUTEL 0x0040 /* INPPGAMUTEL */ 751#define WM8985_INPPGAMUTEL_MASK 0x0040 /* INPPGAMUTEL */ 752#define WM8985_INPPGAMUTEL_SHIFT 6 /* INPPGAMUTEL */ 753#define WM8985_INPPGAMUTEL_WIDTH 1 /* INPPGAMUTEL */ 754#define WM8985_INPPGAVOLL_MASK 0x003F /* INPPGAVOLL - [5:0] */ 755#define WM8985_INPPGAVOLL_SHIFT 0 /* INPPGAVOLL - [5:0] */ 756#define WM8985_INPPGAVOLL_WIDTH 6 /* INPPGAVOLL - [5:0] */ 757 758/* 759 * R46 (0x2E) - Right INP PGA gain ctrl 760 */ 761#define WM8985_INPGAVU 0x0100 /* INPGAVU */ 762#define WM8985_INPGAVU_MASK 0x0100 /* INPGAVU */ 763#define WM8985_INPGAVU_SHIFT 8 /* INPGAVU */ 764#define WM8985_INPGAVU_WIDTH 1 /* INPGAVU */ 765#define WM8985_INPPGAZCR 0x0080 /* INPPGAZCR */ 766#define WM8985_INPPGAZCR_MASK 0x0080 /* INPPGAZCR */ 767#define WM8985_INPPGAZCR_SHIFT 7 /* INPPGAZCR */ 768#define WM8985_INPPGAZCR_WIDTH 1 /* INPPGAZCR */ 769#define WM8985_INPPGAMUTER 0x0040 /* INPPGAMUTER */ 770#define WM8985_INPPGAMUTER_MASK 0x0040 /* INPPGAMUTER */ 771#define WM8985_INPPGAMUTER_SHIFT 6 /* INPPGAMUTER */ 772#define WM8985_INPPGAMUTER_WIDTH 1 /* INPPGAMUTER */ 773#define WM8985_INPPGAVOLR_MASK 0x003F /* INPPGAVOLR - [5:0] */ 774#define WM8985_INPPGAVOLR_SHIFT 0 /* INPPGAVOLR - [5:0] */ 775#define WM8985_INPPGAVOLR_WIDTH 6 /* INPPGAVOLR - [5:0] */ 776 777/* 778 * R47 (0x2F) - Left ADC BOOST ctrl 779 */ 780#define WM8985_PGABOOSTL 0x0100 /* PGABOOSTL */ 781#define WM8985_PGABOOSTL_MASK 0x0100 /* PGABOOSTL */ 782#define WM8985_PGABOOSTL_SHIFT 8 /* PGABOOSTL */ 783#define WM8985_PGABOOSTL_WIDTH 1 /* PGABOOSTL */ 784#define WM8985_L2_2BOOSTVOL_MASK 0x0070 /* L2_2BOOSTVOL - [6:4] */ 785#define WM8985_L2_2BOOSTVOL_SHIFT 4 /* L2_2BOOSTVOL - [6:4] */ 786#define WM8985_L2_2BOOSTVOL_WIDTH 3 /* L2_2BOOSTVOL - [6:4] */ 787#define WM8985_AUXL2BOOSTVOL_MASK 0x0007 /* AUXL2BOOSTVOL - [2:0] */ 788#define WM8985_AUXL2BOOSTVOL_SHIFT 0 /* AUXL2BOOSTVOL - [2:0] */ 789#define WM8985_AUXL2BOOSTVOL_WIDTH 3 /* AUXL2BOOSTVOL - [2:0] */ 790 791/* 792 * R48 (0x30) - Right ADC BOOST ctrl 793 */ 794#define WM8985_PGABOOSTR 0x0100 /* PGABOOSTR */ 795#define WM8985_PGABOOSTR_MASK 0x0100 /* PGABOOSTR */ 796#define WM8985_PGABOOSTR_SHIFT 8 /* PGABOOSTR */ 797#define WM8985_PGABOOSTR_WIDTH 1 /* PGABOOSTR */ 798#define WM8985_R2_2BOOSTVOL_MASK 0x0070 /* R2_2BOOSTVOL - [6:4] */ 799#define WM8985_R2_2BOOSTVOL_SHIFT 4 /* R2_2BOOSTVOL - [6:4] */ 800#define WM8985_R2_2BOOSTVOL_WIDTH 3 /* R2_2BOOSTVOL - [6:4] */ 801#define WM8985_AUXR2BOOSTVOL_MASK 0x0007 /* AUXR2BOOSTVOL - [2:0] */ 802#define WM8985_AUXR2BOOSTVOL_SHIFT 0 /* AUXR2BOOSTVOL - [2:0] */ 803#define WM8985_AUXR2BOOSTVOL_WIDTH 3 /* AUXR2BOOSTVOL - [2:0] */ 804 805/* 806 * R49 (0x31) - Output ctrl 807 */ 808#define WM8758_HP_COM 0x0100 /* HP_COM */ 809#define WM8758_HP_COM_MASK 0x0100 /* HP_COM */ 810#define WM8758_HP_COM_SHIFT 8 /* HP_COM */ 811#define WM8758_HP_COM_WIDTH 1 /* HP_COM */ 812#define WM8758_LINE_COM 0x0080 /* LINE_COM */ 813#define WM8758_LINE_COM_MASK 0x0080 /* LINE_COM */ 814#define WM8758_LINE_COM_SHIFT 7 /* LINE_COM */ 815#define WM8758_LINE_COM_WIDTH 1 /* LINE_COM */ 816#define WM8985_DACL2RMIX 0x0040 /* DACL2RMIX */ 817#define WM8985_DACL2RMIX_MASK 0x0040 /* DACL2RMIX */ 818#define WM8985_DACL2RMIX_SHIFT 6 /* DACL2RMIX */ 819#define WM8985_DACL2RMIX_WIDTH 1 /* DACL2RMIX */ 820#define WM8985_DACR2LMIX 0x0020 /* DACR2LMIX */ 821#define WM8985_DACR2LMIX_MASK 0x0020 /* DACR2LMIX */ 822#define WM8985_DACR2LMIX_SHIFT 5 /* DACR2LMIX */ 823#define WM8985_DACR2LMIX_WIDTH 1 /* DACR2LMIX */ 824#define WM8985_OUT4BOOST 0x0010 /* OUT4BOOST */ 825#define WM8985_OUT4BOOST_MASK 0x0010 /* OUT4BOOST */ 826#define WM8985_OUT4BOOST_SHIFT 4 /* OUT4BOOST */ 827#define WM8985_OUT4BOOST_WIDTH 1 /* OUT4BOOST */ 828#define WM8985_OUT3BOOST 0x0008 /* OUT3BOOST */ 829#define WM8985_OUT3BOOST_MASK 0x0008 /* OUT3BOOST */ 830#define WM8985_OUT3BOOST_SHIFT 3 /* OUT3BOOST */ 831#define WM8985_OUT3BOOST_WIDTH 1 /* OUT3BOOST */ 832#define WM8758_OUT4ENDEL 0x0010 /* OUT4ENDEL */ 833#define WM8758_OUT4ENDEL_MASK 0x0010 /* OUT4ENDEL */ 834#define WM8758_OUT4ENDEL_SHIFT 4 /* OUT4ENDEL */ 835#define WM8758_OUT4ENDEL_WIDTH 1 /* OUT4ENDEL */ 836#define WM8758_OUT3ENDEL 0x0008 /* OUT3ENDEL */ 837#define WM8758_OUT3ENDEL_MASK 0x0008 /* OUT3ENDEL */ 838#define WM8758_OUT3ENDEL_SHIFT 3 /* OUT3ENDEL */ 839#define WM8758_OUT3ENDEL_WIDTH 1 /* OUT3ENDEL */ 840#define WM8985_TSOPCTRL 0x0004 /* TSOPCTRL */ 841#define WM8985_TSOPCTRL_MASK 0x0004 /* TSOPCTRL */ 842#define WM8985_TSOPCTRL_SHIFT 2 /* TSOPCTRL */ 843#define WM8985_TSOPCTRL_WIDTH 1 /* TSOPCTRL */ 844#define WM8985_TSDEN 0x0002 /* TSDEN */ 845#define WM8985_TSDEN_MASK 0x0002 /* TSDEN */ 846#define WM8985_TSDEN_SHIFT 1 /* TSDEN */ 847#define WM8985_TSDEN_WIDTH 1 /* TSDEN */ 848#define WM8985_VROI 0x0001 /* VROI */ 849#define WM8985_VROI_MASK 0x0001 /* VROI */ 850#define WM8985_VROI_SHIFT 0 /* VROI */ 851#define WM8985_VROI_WIDTH 1 /* VROI */ 852 853/* 854 * R50 (0x32) - Left mixer ctrl 855 */ 856#define WM8985_AUXLMIXVOL_MASK 0x01C0 /* AUXLMIXVOL - [8:6] */ 857#define WM8985_AUXLMIXVOL_SHIFT 6 /* AUXLMIXVOL - [8:6] */ 858#define WM8985_AUXLMIXVOL_WIDTH 3 /* AUXLMIXVOL - [8:6] */ 859#define WM8985_AUXL2LMIX 0x0020 /* AUXL2LMIX */ 860#define WM8985_AUXL2LMIX_MASK 0x0020 /* AUXL2LMIX */ 861#define WM8985_AUXL2LMIX_SHIFT 5 /* AUXL2LMIX */ 862#define WM8985_AUXL2LMIX_WIDTH 1 /* AUXL2LMIX */ 863#define WM8985_BYPLMIXVOL_MASK 0x001C /* BYPLMIXVOL - [4:2] */ 864#define WM8985_BYPLMIXVOL_SHIFT 2 /* BYPLMIXVOL - [4:2] */ 865#define WM8985_BYPLMIXVOL_WIDTH 3 /* BYPLMIXVOL - [4:2] */ 866#define WM8985_BYPL2LMIX 0x0002 /* BYPL2LMIX */ 867#define WM8985_BYPL2LMIX_MASK 0x0002 /* BYPL2LMIX */ 868#define WM8985_BYPL2LMIX_SHIFT 1 /* BYPL2LMIX */ 869#define WM8985_BYPL2LMIX_WIDTH 1 /* BYPL2LMIX */ 870#define WM8985_DACL2LMIX 0x0001 /* DACL2LMIX */ 871#define WM8985_DACL2LMIX_MASK 0x0001 /* DACL2LMIX */ 872#define WM8985_DACL2LMIX_SHIFT 0 /* DACL2LMIX */ 873#define WM8985_DACL2LMIX_WIDTH 1 /* DACL2LMIX */ 874 875/* 876 * R51 (0x33) - Right mixer ctrl 877 */ 878#define WM8985_AUXRMIXVOL_MASK 0x01C0 /* AUXRMIXVOL - [8:6] */ 879#define WM8985_AUXRMIXVOL_SHIFT 6 /* AUXRMIXVOL - [8:6] */ 880#define WM8985_AUXRMIXVOL_WIDTH 3 /* AUXRMIXVOL - [8:6] */ 881#define WM8985_AUXR2RMIX 0x0020 /* AUXR2RMIX */ 882#define WM8985_AUXR2RMIX_MASK 0x0020 /* AUXR2RMIX */ 883#define WM8985_AUXR2RMIX_SHIFT 5 /* AUXR2RMIX */ 884#define WM8985_AUXR2RMIX_WIDTH 1 /* AUXR2RMIX */ 885#define WM8985_BYPRMIXVOL_MASK 0x001C /* BYPRMIXVOL - [4:2] */ 886#define WM8985_BYPRMIXVOL_SHIFT 2 /* BYPRMIXVOL - [4:2] */ 887#define WM8985_BYPRMIXVOL_WIDTH 3 /* BYPRMIXVOL - [4:2] */ 888#define WM8985_BYPR2RMIX 0x0002 /* BYPR2RMIX */ 889#define WM8985_BYPR2RMIX_MASK 0x0002 /* BYPR2RMIX */ 890#define WM8985_BYPR2RMIX_SHIFT 1 /* BYPR2RMIX */ 891#define WM8985_BYPR2RMIX_WIDTH 1 /* BYPR2RMIX */ 892#define WM8985_DACR2RMIX 0x0001 /* DACR2RMIX */ 893#define WM8985_DACR2RMIX_MASK 0x0001 /* DACR2RMIX */ 894#define WM8985_DACR2RMIX_SHIFT 0 /* DACR2RMIX */ 895#define WM8985_DACR2RMIX_WIDTH 1 /* DACR2RMIX */ 896 897/* 898 * R52 (0x34) - LOUT1 (HP) volume ctrl 899 */ 900#define WM8985_OUT1VU 0x0100 /* OUT1VU */ 901#define WM8985_OUT1VU_MASK 0x0100 /* OUT1VU */ 902#define WM8985_OUT1VU_SHIFT 8 /* OUT1VU */ 903#define WM8985_OUT1VU_WIDTH 1 /* OUT1VU */ 904#define WM8985_LOUT1ZC 0x0080 /* LOUT1ZC */ 905#define WM8985_LOUT1ZC_MASK 0x0080 /* LOUT1ZC */ 906#define WM8985_LOUT1ZC_SHIFT 7 /* LOUT1ZC */ 907#define WM8985_LOUT1ZC_WIDTH 1 /* LOUT1ZC */ 908#define WM8985_LOUT1MUTE 0x0040 /* LOUT1MUTE */ 909#define WM8985_LOUT1MUTE_MASK 0x0040 /* LOUT1MUTE */ 910#define WM8985_LOUT1MUTE_SHIFT 6 /* LOUT1MUTE */ 911#define WM8985_LOUT1MUTE_WIDTH 1 /* LOUT1MUTE */ 912#define WM8985_LOUT1VOL_MASK 0x003F /* LOUT1VOL - [5:0] */ 913#define WM8985_LOUT1VOL_SHIFT 0 /* LOUT1VOL - [5:0] */ 914#define WM8985_LOUT1VOL_WIDTH 6 /* LOUT1VOL - [5:0] */ 915 916/* 917 * R53 (0x35) - ROUT1 (HP) volume ctrl 918 */ 919#define WM8985_OUT1VU 0x0100 /* OUT1VU */ 920#define WM8985_OUT1VU_MASK 0x0100 /* OUT1VU */ 921#define WM8985_OUT1VU_SHIFT 8 /* OUT1VU */ 922#define WM8985_OUT1VU_WIDTH 1 /* OUT1VU */ 923#define WM8985_ROUT1ZC 0x0080 /* ROUT1ZC */ 924#define WM8985_ROUT1ZC_MASK 0x0080 /* ROUT1ZC */ 925#define WM8985_ROUT1ZC_SHIFT 7 /* ROUT1ZC */ 926#define WM8985_ROUT1ZC_WIDTH 1 /* ROUT1ZC */ 927#define WM8985_ROUT1MUTE 0x0040 /* ROUT1MUTE */ 928#define WM8985_ROUT1MUTE_MASK 0x0040 /* ROUT1MUTE */ 929#define WM8985_ROUT1MUTE_SHIFT 6 /* ROUT1MUTE */ 930#define WM8985_ROUT1MUTE_WIDTH 1 /* ROUT1MUTE */ 931#define WM8985_ROUT1VOL_MASK 0x003F /* ROUT1VOL - [5:0] */ 932#define WM8985_ROUT1VOL_SHIFT 0 /* ROUT1VOL - [5:0] */ 933#define WM8985_ROUT1VOL_WIDTH 6 /* ROUT1VOL - [5:0] */ 934 935/* 936 * R54 (0x36) - LOUT2 (SPK) volume ctrl 937 */ 938#define WM8985_OUT2VU 0x0100 /* OUT2VU */ 939#define WM8985_OUT2VU_MASK 0x0100 /* OUT2VU */ 940#define WM8985_OUT2VU_SHIFT 8 /* OUT2VU */ 941#define WM8985_OUT2VU_WIDTH 1 /* OUT2VU */ 942#define WM8985_LOUT2ZC 0x0080 /* LOUT2ZC */ 943#define WM8985_LOUT2ZC_MASK 0x0080 /* LOUT2ZC */ 944#define WM8985_LOUT2ZC_SHIFT 7 /* LOUT2ZC */ 945#define WM8985_LOUT2ZC_WIDTH 1 /* LOUT2ZC */ 946#define WM8985_LOUT2MUTE 0x0040 /* LOUT2MUTE */ 947#define WM8985_LOUT2MUTE_MASK 0x0040 /* LOUT2MUTE */ 948#define WM8985_LOUT2MUTE_SHIFT 6 /* LOUT2MUTE */ 949#define WM8985_LOUT2MUTE_WIDTH 1 /* LOUT2MUTE */ 950#define WM8985_LOUT2VOL_MASK 0x003F /* LOUT2VOL - [5:0] */ 951#define WM8985_LOUT2VOL_SHIFT 0 /* LOUT2VOL - [5:0] */ 952#define WM8985_LOUT2VOL_WIDTH 6 /* LOUT2VOL - [5:0] */ 953 954/* 955 * R55 (0x37) - ROUT2 (SPK) volume ctrl 956 */ 957#define WM8985_OUT2VU 0x0100 /* OUT2VU */ 958#define WM8985_OUT2VU_MASK 0x0100 /* OUT2VU */ 959#define WM8985_OUT2VU_SHIFT 8 /* OUT2VU */ 960#define WM8985_OUT2VU_WIDTH 1 /* OUT2VU */ 961#define WM8985_ROUT2ZC 0x0080 /* ROUT2ZC */ 962#define WM8985_ROUT2ZC_MASK 0x0080 /* ROUT2ZC */ 963#define WM8985_ROUT2ZC_SHIFT 7 /* ROUT2ZC */ 964#define WM8985_ROUT2ZC_WIDTH 1 /* ROUT2ZC */ 965#define WM8985_ROUT2MUTE 0x0040 /* ROUT2MUTE */ 966#define WM8985_ROUT2MUTE_MASK 0x0040 /* ROUT2MUTE */ 967#define WM8985_ROUT2MUTE_SHIFT 6 /* ROUT2MUTE */ 968#define WM8985_ROUT2MUTE_WIDTH 1 /* ROUT2MUTE */ 969#define WM8985_ROUT2VOL_MASK 0x003F /* ROUT2VOL - [5:0] */ 970#define WM8985_ROUT2VOL_SHIFT 0 /* ROUT2VOL - [5:0] */ 971#define WM8985_ROUT2VOL_WIDTH 6 /* ROUT2VOL - [5:0] */ 972 973/* 974 * R56 (0x38) - OUT3 mixer ctrl 975 */ 976#define WM8985_OUT3MUTE 0x0040 /* OUT3MUTE */ 977#define WM8985_OUT3MUTE_MASK 0x0040 /* OUT3MUTE */ 978#define WM8985_OUT3MUTE_SHIFT 6 /* OUT3MUTE */ 979#define WM8985_OUT3MUTE_WIDTH 1 /* OUT3MUTE */ 980#define WM8985_OUT4_2OUT3 0x0008 /* OUT4_2OUT3 */ 981#define WM8985_OUT4_2OUT3_MASK 0x0008 /* OUT4_2OUT3 */ 982#define WM8985_OUT4_2OUT3_SHIFT 3 /* OUT4_2OUT3 */ 983#define WM8985_OUT4_2OUT3_WIDTH 1 /* OUT4_2OUT3 */ 984#define WM8985_BYPL2OUT3 0x0004 /* BYPL2OUT3 */ 985#define WM8985_BYPL2OUT3_MASK 0x0004 /* BYPL2OUT3 */ 986#define WM8985_BYPL2OUT3_SHIFT 2 /* BYPL2OUT3 */ 987#define WM8985_BYPL2OUT3_WIDTH 1 /* BYPL2OUT3 */ 988#define WM8985_LMIX2OUT3 0x0002 /* LMIX2OUT3 */ 989#define WM8985_LMIX2OUT3_MASK 0x0002 /* LMIX2OUT3 */ 990#define WM8985_LMIX2OUT3_SHIFT 1 /* LMIX2OUT3 */ 991#define WM8985_LMIX2OUT3_WIDTH 1 /* LMIX2OUT3 */ 992#define WM8985_LDAC2OUT3 0x0001 /* LDAC2OUT3 */ 993#define WM8985_LDAC2OUT3_MASK 0x0001 /* LDAC2OUT3 */ 994#define WM8985_LDAC2OUT3_SHIFT 0 /* LDAC2OUT3 */ 995#define WM8985_LDAC2OUT3_WIDTH 1 /* LDAC2OUT3 */ 996 997/* 998 * R57 (0x39) - OUT4 (MONO) mix ctrl 999 */ 1000#define WM8985_OUT3_2OUT4 0x0080 /* OUT3_2OUT4 */ 1001#define WM8985_OUT3_2OUT4_MASK 0x0080 /* OUT3_2OUT4 */ 1002#define WM8985_OUT3_2OUT4_SHIFT 7 /* OUT3_2OUT4 */ 1003#define WM8985_OUT3_2OUT4_WIDTH 1 /* OUT3_2OUT4 */ 1004#define WM8985_OUT4MUTE 0x0040 /* OUT4MUTE */ 1005#define WM8985_OUT4MUTE_MASK 0x0040 /* OUT4MUTE */ 1006#define WM8985_OUT4MUTE_SHIFT 6 /* OUT4MUTE */ 1007#define WM8985_OUT4MUTE_WIDTH 1 /* OUT4MUTE */ 1008#define WM8985_OUT4ATTN 0x0020 /* OUT4ATTN */ 1009#define WM8985_OUT4ATTN_MASK 0x0020 /* OUT4ATTN */ 1010#define WM8985_OUT4ATTN_SHIFT 5 /* OUT4ATTN */ 1011#define WM8985_OUT4ATTN_WIDTH 1 /* OUT4ATTN */ 1012#define WM8985_LMIX2OUT4 0x0010 /* LMIX2OUT4 */ 1013#define WM8985_LMIX2OUT4_MASK 0x0010 /* LMIX2OUT4 */ 1014#define WM8985_LMIX2OUT4_SHIFT 4 /* LMIX2OUT4 */ 1015#define WM8985_LMIX2OUT4_WIDTH 1 /* LMIX2OUT4 */ 1016#define WM8985_LDAC2OUT4 0x0008 /* LDAC2OUT4 */ 1017#define WM8985_LDAC2OUT4_MASK 0x0008 /* LDAC2OUT4 */ 1018#define WM8985_LDAC2OUT4_SHIFT 3 /* LDAC2OUT4 */ 1019#define WM8985_LDAC2OUT4_WIDTH 1 /* LDAC2OUT4 */ 1020#define WM8985_BYPR2OUT4 0x0004 /* BYPR2OUT4 */ 1021#define WM8985_BYPR2OUT4_MASK 0x0004 /* BYPR2OUT4 */ 1022#define WM8985_BYPR2OUT4_SHIFT 2 /* BYPR2OUT4 */ 1023#define WM8985_BYPR2OUT4_WIDTH 1 /* BYPR2OUT4 */ 1024#define WM8985_RMIX2OUT4 0x0002 /* RMIX2OUT4 */ 1025#define WM8985_RMIX2OUT4_MASK 0x0002 /* RMIX2OUT4 */ 1026#define WM8985_RMIX2OUT4_SHIFT 1 /* RMIX2OUT4 */ 1027#define WM8985_RMIX2OUT4_WIDTH 1 /* RMIX2OUT4 */ 1028#define WM8985_RDAC2OUT4 0x0001 /* RDAC2OUT4 */ 1029#define WM8985_RDAC2OUT4_MASK 0x0001 /* RDAC2OUT4 */ 1030#define WM8985_RDAC2OUT4_SHIFT 0 /* RDAC2OUT4 */ 1031#define WM8985_RDAC2OUT4_WIDTH 1 /* RDAC2OUT4 */ 1032 1033/* 1034 * R60 (0x3C) - OUTPUT ctrl 1035 */ 1036#define WM8985_VIDBUFFTST_MASK 0x01E0 /* VIDBUFFTST - [8:5] */ 1037#define WM8985_VIDBUFFTST_SHIFT 5 /* VIDBUFFTST - [8:5] */ 1038#define WM8985_VIDBUFFTST_WIDTH 4 /* VIDBUFFTST - [8:5] */ 1039#define WM8985_HPTOG 0x0008 /* HPTOG */ 1040#define WM8985_HPTOG_MASK 0x0008 /* HPTOG */ 1041#define WM8985_HPTOG_SHIFT 3 /* HPTOG */ 1042#define WM8985_HPTOG_WIDTH 1 /* HPTOG */ 1043 1044/* 1045 * R61 (0x3D) - BIAS CTRL 1046 */ 1047#define WM8985_BIASCUT 0x0100 /* BIASCUT */ 1048#define WM8985_BIASCUT_MASK 0x0100 /* BIASCUT */ 1049#define WM8985_BIASCUT_SHIFT 8 /* BIASCUT */ 1050#define WM8985_BIASCUT_WIDTH 1 /* BIASCUT */ 1051#define WM8985_HALFIPBIAS 0x0080 /* HALFIPBIAS */ 1052#define WM8985_HALFIPBIAS_MASK 0x0080 /* HALFIPBIAS */ 1053#define WM8985_HALFIPBIAS_SHIFT 7 /* HALFIPBIAS */ 1054#define WM8985_HALFIPBIAS_WIDTH 1 /* HALFIPBIAS */ 1055#define WM8758_HALFIPBIAS 0x0040 /* HALFI_IPGA */ 1056#define WM8758_HALFI_IPGA_MASK 0x0040 /* HALFI_IPGA */ 1057#define WM8758_HALFI_IPGA_SHIFT 6 /* HALFI_IPGA */ 1058#define WM8758_HALFI_IPGA_WIDTH 1 /* HALFI_IPGA */ 1059#define WM8985_VBBIASTST_MASK 0x0060 /* VBBIASTST - [6:5] */ 1060#define WM8985_VBBIASTST_SHIFT 5 /* VBBIASTST - [6:5] */ 1061#define WM8985_VBBIASTST_WIDTH 2 /* VBBIASTST - [6:5] */ 1062#define WM8985_BUFBIAS_MASK 0x0018 /* BUFBIAS - [4:3] */ 1063#define WM8985_BUFBIAS_SHIFT 3 /* BUFBIAS - [4:3] */ 1064#define WM8985_BUFBIAS_WIDTH 2 /* BUFBIAS - [4:3] */ 1065#define WM8985_ADCBIAS_MASK 0x0006 /* ADCBIAS - [2:1] */ 1066#define WM8985_ADCBIAS_SHIFT 1 /* ADCBIAS - [2:1] */ 1067#define WM8985_ADCBIAS_WIDTH 2 /* ADCBIAS - [2:1] */ 1068#define WM8985_HALFOPBIAS 0x0001 /* HALFOPBIAS */ 1069#define WM8985_HALFOPBIAS_MASK 0x0001 /* HALFOPBIAS */ 1070#define WM8985_HALFOPBIAS_SHIFT 0 /* HALFOPBIAS */ 1071#define WM8985_HALFOPBIAS_WIDTH 1 /* HALFOPBIAS */ 1072 1073enum clk_src { 1074 WM8985_CLKSRC_MCLK, 1075 WM8985_CLKSRC_PLL 1076}; 1077 1078#define WM8985_PLL 0 1079 1080#endif 1081